Re: [U-Boot] Problem with sf write on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek,

>> Just check if the mainline SPL generated from this branch works on your
>> platform please.

I tested U-boot generated from the branch you specified:
U-Boot 2016.03-11349-g5d09125-dirty (Apr 09 2016 - 00:42:24 +0200)

Works pretty well.

All needed functionality works for me. I tested:
1. Mounting ubi partition.
2. Booting kernel from ubi partition.
3. Fpga configuration.
4. Ethernet.

For two more weeks I will have access to the hardware so you can ask for 
another test if you wish.
But in the end of April I will move to another project, so I'm afraid I will 
not be able to help then.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with sf write on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

> Just check if the mainline SPL generated from this branch works on your
> platform please.

Ok. I will test it but probably during the weekend.
Because it requires me to merge my configuration to it.
I will write back once I will have some results.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with sf write on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek,

> you mentioned you have problems with DRAM init on your AV, right ?
> Try this u-boot-socfpga/ddr branch [1] , see if it works for you and
> please let me know. The more testing the better.
> 
> [1]
> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr

Are you asking me to test problem with writing to the flash without "dcache 
off", right?

Best regards,
Denis Bakhvalov

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Re: [U-Boot] Problem with sf write on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek,

> Do "dcache off" and then update the flash again, it will work. That's
> the cache issue which we cannot track down.

Thank you for you quick support!

Maybe it's worth to invent a temporary solution?
Because in other way users will face problems which are hard to find (I've been 
chasing this problem for 2 days).
For example execute "dcache off" internally when sf write is called?

Best regards,
Denis Bakhvalov
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[U-Boot] Problem with sf write on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Dear U-Boot support,

I'm migrating to new U-Boot version from 2013 and now have problem with writing 
to the flash.

I have custom board with Altera Arria 5 SocFpga.
U-Boot version: 2016.03-rc1
My flash:
SF: Detected S25FL512S_256K with page size 512 Bytes, erase size 256 KiB, total 
64 MiB

I'm rewriting the flash with the image that I downloaded from tftp.
#> tftp 0x1B00 flash.bin
Then I'm trying to write it to the flash:
#> sf erase ...
#> sf write ...
After that if I try to mount Ubi partition (this is read operation) I receive 
failures (usually checksum errors).
So, the problem is that when I'm writing some data to flash and reading it back 
the data is corrupted.
I'm almost sure that there is no issue with reading, because previously I was 
able to read big amount of data successfully (for example, reading OS image and 
booting it).

With previous version (2013) there is no such issue.
With the same sequence of commands I was able to update entire flash.

I was able to reduce this problem to a smaller one.
I'm checking consistency of write operation by writing zipped file (3 KB):
#> tftp 0x1B00 file.zip
#> sf erase  
#> sf write   
#> sf read   
#> unzip  

And sometimes I can see:
Uncompressed size: 524288 = 0x8 (success)
but more often:
Error: inflate() returned -3 (data was corrupted)

So, the problem appears to be occasional.

When I'm comparing the original data with the data that I've read from flash I 
can see the blocks of 256 bytes were not written (0x).
For example:
Original data:
1b000200: c62e214e 0e48a4c9 19038ec8 37531cfdN!H...S7
1b000210: 8f1c7048 f60b861f e9482d5c 857404e8Hp..\-H...t.
1b000220: ef3996c1 fd02b093 2ee8d1f6 679ab03d..9.=..g
1b000230: e6c739f4 194eaec7 383ddca8 6f90a2ad.9N...=8...o
... and so on until (1b000300)
Stored data:
1f000200:    
1f000210:    
1f000220:    
1f000230:    
... and so on until (1f000300)

I already checked difference in QSPI registers (base address: 0xFF705000) 
between two versions of U-Boot, but haven't found any clue yet.
If needed I can provide this diff.

All hints are welcome.

Best regards,
Denis Bakhvalov

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[U-Boot] [PATCH] arm: socfpga: migration of CONFIG_SPI_FLASH_BAR

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

CONFIG_SPI_FLASH_BAR was deleted from socfpga_common.h
and placed in socfpga_*_defconfig where it makes sense.

Signed-off-by: Denis Bakhvalov 
Reported-by: Denis Bakhvalov 
Cc: Marek Vasut 
---
 configs/socfpga_arria5_defconfig   | 1 +
 configs/socfpga_cyclone5_defconfig | 1 +
 configs/socfpga_de0_nano_soc_defconfig | 1 +
 configs/socfpga_mcvevk_defconfig   | 1 +
 configs/socfpga_sockit_defconfig   | 1 +
 configs/socfpga_socrates_defconfig | 1 +
 configs/socfpga_sr1500_defconfig   | 1 +
 include/configs/socfpga_common.h   | 2 --
 8 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 7b60d95..505a68d 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/socfpga_cyclone5_defconfig 
b/configs/socfpga_cyclone5_defconfig
index 6a487f4..df19a95 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig 
b/configs/socfpga_de0_nano_soc_defconfig
index cfcae5d..bb37825 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -19,5 +19,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index b6f6a65..8a76aa1 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -19,5 +19,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index f45c3ed..36bb1e1 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/socfpga_socrates_defconfig 
b/configs/socfpga_socrates_defconfig
index e25d09b..937f14f 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -23,5 +23,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index d499a14..83eada3 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -17,6 +17,7 @@ CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 56d32e6..2ad0287 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -93,7 +93,6 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED3000
-#define CONFIG_SPI_FLASH_BAR
 /*
  * The base address is configurable in QSys, each board must specify the
  * base address based on it's particular FPGA configuration. Please note
@@ -219,7 +218,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #endif
 #define CONFIG_CQSPI_DECODER   0
 #define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_BAR

 /*
  * Designware SPI support
--
2.5.3.windows.1



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Re: [U-Boot] Problem with attaching UBI partition

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi

> > It's I belive in socfpga_common.h and it should be migrated to
> > socfpga_*_defconfig where it makes sense. Do you want to submit
> > a patch for this ?
> 
> I put it in my todo list.
> Once I will finish with u-boot bringup I will submit the patch.
> Currently I have Ethernet not working :(  

Patch was submitted:
http://lists.denx.de/pipermail/u-boot/2016-March/249392.html

Best regards,
Denis Bakhvalov
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[U-Boot] [PATCH] arm: socfpga: migration of CONFIG_SPI_FLASH_BAR

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

CONFIG_SPI_FLASH_BAR was deleted from socfpga_common.h
and placed in socfpga_*_defconfig where it makes sense.

Signed-off-by: Denis Bakhvalov 
Reported-by: Marek Vasut 
Cc: Dinh Nguyen 
---
 configs/socfpga_arria5_defconfig   | 1 +
 configs/socfpga_cyclone5_defconfig | 1 +
 configs/socfpga_de0_nano_soc_defconfig | 1 +
 configs/socfpga_mcvevk_defconfig   | 1 +
 configs/socfpga_sockit_defconfig   | 1 +
 configs/socfpga_socrates_defconfig | 1 +
 configs/socfpga_sr1500_defconfig   | 1 +
 include/configs/socfpga_common.h   | 2 --
 8 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 7b60d95..505a68d 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/socfpga_cyclone5_defconfig 
b/configs/socfpga_cyclone5_defconfig
index 6a487f4..df19a95 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig 
b/configs/socfpga_de0_nano_soc_defconfig
index cfcae5d..5e18844 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -18,6 +18,7 @@ CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index b6f6a65..8a76aa1 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -19,5 +19,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index f45c3ed..36bb1e1 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/socfpga_socrates_defconfig 
b/configs/socfpga_socrates_defconfig
index e25d09b..0aaef76 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -22,6 +22,7 @@ CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index d499a14..83eada3 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -17,6 +17,7 @@ CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 56d32e6..2ad0287 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -93,7 +93,6 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED3000
-#define CONFIG_SPI_FLASH_BAR
 /*
  * The base address is configurable in QSys, each board must specify the
  * base address based on it's particular FPGA configuration. Please note
@@ -219,7 +218,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #endif
 #define CONFIG_CQSPI_DECODER   0
 #define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_BAR

 /*
  * Designware SPI support
--
2.7.0




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Re: [U-Boot] Ethernet not found on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi,

Working perfectly!
Thanks for helping me remove this nasty workaround.

> We should parse the OF node phy-mode, which describes which mode your
> PHY uses. 

Right!

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Ethernet not found on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hello Dear U-Boot support,

Please comment on this also.

I have custom board with Altera Arria 5 SocFpga onboard.
U-Boot version: 2016.03-rc1

I had probems with configuring fpga from u-boot:

U-Boot > bridge disable
U-Boot > run config_fpga
FPGA: Could not configure
Command failed, result=-2

So, fpga did not reached configuration state in certain timeout 
(FPGAMGRREGS_MODE_CFGPHASE).
My workaround was based on U-Boot 2013 version were I had no such problem.

I fixed it like this:

diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 431e159..423ee23 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -269,7 +269,11 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
/* Prior programming the FPGA, all bridges need to be shut off */

/* Disable all signals from hps peripheral controller to fpga */
+#ifdef CONFIG_WORKAROUND
+   writel(0, _regs->fpgaintfgrp_module);
+#else
writel(0, _regs->fpgaintfgrp_gbl);
+#endif

Please evaluate my workaround.
Maybe I had to make some additional step before configuring fpga?

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Ethernet not found on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi,

I solved the Ethernet problem on our board.

The problem was in the register below:

Link: 
http://wl.altera.com/literature/hb/arria-v/hps.html#topic/sfo1410067853518.html
Registers used by the EMACs. All fields are reset by a cold or warm reset.
Module Instance Base AddressRegister Address
sysmgr  0xFFD08000  0xFFD08060

I found that difference while comparing the dumps between OK and NOK cases.

In new U-Boot (2016) the values of 
ctrl :: physel_0
ctrl :: physel_1
were always set to 
0x1 Select RGMII PHY interface

I changed this value to 
0x0 Select GMII/MII PHY interface

And it start working:

Using ethernet@ff702000 device
TFTP from server 192.168.1.126; our IP address is 192.168.1.130
Filename 'os.bin'.
Load address: 0x1b00
Loading: #
 #
 #
 #
 #
 #
 #
 #
 #
 #
 #
 #
 #
 #
 #
 #
 #
 #
 856.4 KiB/s
done
Bytes transferred = 5949368 (5ac7b8 hex)

I knew about that requirement about MII interface between EMAC and PHY but it 
took me so long to find it.

But still I have this sort of question:
Why those two registers are always assigned to RGMII PHY interface (and default 
value is 0x2Select RMII PHY interface)?
In current code there is no way to change this value.

I changed it like this:

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
old mode 100644
new mode 100755
index 9b43b92..295ed5a
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -23,6 +23,8 @@

@@ -97,14 +99,19 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id)
 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);

/* configure to PHY interface select choosed */
+#ifdef CONFIG_WORKAROUND
+   setbits_le32(_regs->emacgrp_ctrl,
+SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII << physhift);
+#else
setbits_le32(_regs->emacgrp_ctrl,
SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
+#endif

/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
 }

Please evaluate my correction.
Maybe we can assign ctrl :: physel_0 and ctrl :: physel_1 based on some switch 
in config?

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Ethernet not found on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi,

> Why are you constantly hung on this FPGA part ? The ethernet is not
> routed through the FPGA, it is connected directly to the HPS. Thus,
> you don't have to care about the FPGA at all, you only care about the
> configuration of the HPS.

Please excuse me for my small experience in this topic.
I'm just trying to find the way how to solve this issue. Maybe then take HPS 
dumps and compare them?

What I have for now:

OK case (U-Boot 2013):
ARP packets are sent from board to PC and back.
ICMP packets are sent from board to PC and back.
Ping is successful.

NOK case(U-Boot 2016):
ARP packets are sent from board to PC.
PC sends ARP reply but it is not recognized by the board.
Ping fails.
However when the board is "waiting" for ARP reply from the PC it can process 
ICMP packets from the PC and send reply to them.

I started thinking about: "What is that special in those ARP packets?"

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Ethernet not found on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek, Dinh,

> Are you booting using mainline U-Boot SPL ? :-)

No, we use SPL from U-Boot 2013.
I can quess what you will say now, but it somehow worked before (combination 
SPL + U-Boot from 2013).

Is there a way to capture fpga dumps?
I can then compare them to working case. 
I can assume that there will be lots of differences and I would have to check 
them manually, but it's better than nothing I think.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Ethernet not found on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek,

> Perform usual test, disable cache (dcache off) .

I tried and result is still the same.

UPD: I did a little trick:
1. I started ping from the board side. That made the board listen to incoming 
packets (calling in infinite loop eth_rx() ).
2. Started ping from PC side.
3. In this case board receive ICMP packets from PC:

packet received
Receive from protocol 0x800
Got IP
len=60, v=45
Got ICMP ECHO REQUEST, return 74 bytes 

So, ICMP packets are handled by the board, but ARP packets not.

In my understanding it tells me that at least interface on the board side is 
alive.

I'm now doing some low-level debugging, however I think this is not the best 
idea. :)
Now dw_eth_recv (designware.c) always returns 0 length of the packet.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Ethernet not found on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi,

> However there is still no ping in U-Boot.
> After power reset I did:
>
> ># bridge disable
> ># fpga load 0  
> ># bridge enable
>
> ># md 0xff706000 1
> ff706000: 0074  <-- this means fpga is in user mode
>
> ># setenv ethaddr ...
> ># setenv ipaddr ...
> ># setenv netmask ...
> ># setenv gatewayip ...
>
> => ping 192.168.1.126
> Speed: 100, full duplex
> Using ethernet@ff702000 device
> ping failed; host 192.168.1.126 is not alive
>
> With similar commands on previous U-Boot version I had ping.

Also using wireshark I found that board sends correct ARP packets to PC.
PC in it's turn send valid ARP response to the board.
But for some reason ARP reply is not handled by the board.
And board doesn't send ICMP packets to the PC.

I already checked ip addresses, they should be fine.
Also the same IP works fine for previous U-Boot version (2013).

What could be the reason for that?

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Ethernet not found on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek,

> What do you mean by this ? Is your ethernet controller synthesised in
> the FPGA ? The arriaV socdk u-boot uses the top-side ethernet port,
> which is connected to the ethernet controller in the HPS.

I managed to get it working.
Right after configuring fpga from Linux I made a soft reset and PHY chip was 
successfully found.

Net: eth0: ethernet@ff702000

However there is still no ping in U-Boot.
After power reset I did:

># bridge disable
># fpga load 0  
># bridge enable

># md 0xff706000 1
ff706000: 0074  <-- this means fpga is in user mode

># setenv ethaddr ...
># setenv ipaddr ...
># setenv netmask ...
># setenv gatewayip ...

=> ping 192.168.1.126
Speed: 100, full duplex
Using ethernet@ff702000 device
ping failed; host 192.168.1.126 is not alive

With similar commands on previous U-Boot version I had ping.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Ethernet not found on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi,

> It seems like your PHY is not recongnised. Could there be some reset
> line which is left asserted ?

I'm afraid I don't know how to check that.

But I have previous version of U-Boot (2013) where Ethernet is working.
Maybe I can check it there?
I already tried to go that path, but code is quite different there.

With U-Boot 2013 it is enough to config fpga and set env variables to have ping 
in both directions.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with attaching UBI partition

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek,

> > Currently I have Ethernet not working :(  
>
> OK. Do you use the same ethernet controller as ArriaV SoCDK? There are two.

Yes. I didn't changed that.
It is gmac1: ethernet@ff702000.

I already started new topic for that problem here:
http://lists.denx.de/pipermail/u-boot/2016-March/247290.html
Let's continue discussion there. :)

Best regards,
Denis Bakhvalov

MBB Radio Platforms, RFSW


-Original Message-
From: EXT Marek Vasut [mailto:ma...@denx.de] 
Sent: Friday, March 04, 2016 13:20
To: Bakhvalov, Denis (Nokia - PL/Wroclaw) <denis.bakhva...@nokia.com>; EXT 
Jagan Teki <jt...@openedev.com>
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] Problem with attaching UBI partition

On 03/04/2016 10:03 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
> Hi Marek,

Hi,

>> It's I belive in socfpga_common.h and it should be migrated to
>> socfpga_*_defconfig where it makes sense. Do you want to submit
>> a patch for this ?
> 
> I put it in my todo list.
> Once I will finish with u-boot bringup I will submit the patch.
> Currently I have Ethernet not working :(  

OK. Do you use the same ethernet controller as ArriaV SoCDK? There are two.

-- 
Best regards,
Marek Vasut
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[U-Boot] Ethernet not found on Arria 5.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Dear U-Boot support,

I'm migrating to new U-Boot version from 2013 and now have Ethernet not working 
both in U-Boot and in Linux (after booting).

I have custom board with Altera Arria 5 SocFpga onboard.
U-Boot version: 2016.03-rc1

In logs I can see:

 Net:   No ethernet found.

With more verbose:

 designware_eth_probe, iobase=ff702000, priv=1eb286a0
 ethernet@ff702000 PHY: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 
22 23 24 25 26 27 28 29 30 31 not found
 designware_eth_probe, ret=-19
 No ethernet found.

Ethernet connection inside my board is following:
   [CPU] - [EMAC1] - [ FPGA ]  [ PHY(KSZ8081MNXIA) ]

I already tried to configure FPGA from Linux environment but it didn't solved 
the problem.
My U-Boot configuration was cloned from socfpga dev kit board with some 
modifications.
But Ethernet configuration I didn't touched yet.

So far I tried to debug it with no success. Also I played with env variables 
(ethact, ethaddr) and CONFIG_PHY_ADDR with no success as well.
Something tells me that I have incorrect EMAC configuration but I don't know 
how to tackle it.

Please help me identify the problem or at least give me some hints where to 
look to solve my issue.

Best regards,
Denis Bakhvalov

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Re: [U-Boot] Problem with attaching UBI partition

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek,

> It's I belive in socfpga_common.h and it should be migrated to
> socfpga_*_defconfig where it makes sense. Do you want to submit
> a patch for this ?

I put it in my todo list.
Once I will finish with u-boot bringup I will submit the patch.
Currently I have Ethernet not working :(  

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with attaching UBI partition

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Jagan,

> Sorry, I couldn't understand the issue nor what you solved? because,
> socfpga_arria5_defconfig by default have CONFIG_SPI_FLASH_BAR enabled
> and even sf probe looks no warning for enabling the same. If you
> haven't enable CONFIG_SPI_FLASH_BAR then spi_flash core will give
> warning while doing 'sf probe'

I can see that for 2016.03-rc1 CONFIG_SPI_FLASH_BAR is not present in 
socfpga_arria5_defconfig.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with attaching UBI partition

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek,

>Try enabling CONFIG_SPI_FLASH_BAR in your board config ;-)

That solved my issue.
Thank you very much.
I removed workaround from the code.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with attaching UBI partition

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Jagan, Heiko,

> Did you enable CONFIG_SPI_FLASH_SPANSION on your config, becuase
> S25FL512S is already been added u-boot. Pls- check the same and let me
> know if you find any issues while detecting the flash.

> Whether the driver detecting flash or not with RDID, please define
> DEBUG on drivers/mtd/spi/spi_flash.c

I had no problems with detecting the flash. It was detected like this:
SF: Detected S25FL512S_256K with page size 512 Bytes, erase size 256 KiB, total 
64 MiB

Yes, I have CONFIG_SPI_FLASH_SPANSION enabled in 
configs/socfpga_arria5_dbrrh_defconfig (dbrrh - is my custom board).

Actually, today I solved the problem, although in not very clean way, I think.

As I mentioned in previous mail I had problems with reading from the flash. 
Some bytes were read incorrectly.
I'm migrating from U-Boot 2013 to mainline U-Boot. And on previous version 
there were no such issue.
I found out that there was some workaround introduced in order to fix this.

So, I just apply some part of that workaround to mainline U-Boot and now it 
works.

Here is the problem in more detail:

On previous version (2013):
U-BOOT # sf read 0x1B00 0x0380 4
 cadence_qspi_apb_indirect_read_setup. addr_value = 0x380
 cadence_qspi_apb_indirect_read_setup. rd_reg = 0x80b
 cadence_qspi_apb_indirect_read_setup. device size = 0x101003

U-BOOT # md 0x1B00 1
1b00: 55424923

But on mainline U-Boot(2016.03-rc1) I had:
U-BOOT # sf read 0x1B00 0x0380 4
 cadence_qspi_apb_indirect_read_setup. addr_value = 0x80
 cadence_qspi_apb_indirect_read_setup. rd_reg = 0x0b
 cadence_qspi_apb_indirect_read_setup. device size = 0x101002

U-BOOT # md 0x1B00 1
1b00: 554249ff

You can see the difference in the register values that were written in QSPI 
registers.
In case with mainline U-Boot I had address value not properly set.

Here is the workaround that I've made:

Index: drivers/mtd/spi/spi_flash.c
===
--- drivers/mtd/spi/spi_flash.c (revision 608)
+++ drivers/mtd/spi/spi_flash.c (revision 609)
@@ -29,6 +29,17 @@
cmd[3] = addr >> 0;
 }
 
+#ifdef CONFIG_DBRRH_WORKAROUND
+static void spi_flash_addr32(u32 addr, u8 *cmd)
+{
+   /* cmd[0] is actual command */
+   cmd[1] = (addr >> 24) & 0xFF;
+   cmd[2] = (addr >> 16) & 0xFF;
+   cmd[3] = (addr >> 8) & 0xFF;
+   cmd[4] = (addr >> 0) & 0xFF;
+}
+#endif
+
 static int read_sr(struct spi_flash *flash, u8 *rs)
 {
int ret;
@@ -510,8 +521,14 @@
else
read_len = remain_len;
 
+#ifdef CONFIG_DBRRH_WORKAROUND
+   spi_flash_addr32(read_addr, cmd);
+#else
spi_flash_addr(read_addr, cmd);
+#endif
 
ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
if (ret < 0) {
debug("SF: read failed\n");

Index: drivers/spi/cadence_qspi_apb.c
===
--- drivers/spi/cadence_qspi_apb.c  (revision 608)
+++ drivers/spi/cadence_qspi_apb.c  (revision 609)
@@ -30,6 +30,10 @@
 #include 
 #include "cadence_qspi.h"
 
+#ifdef CONFIG_DBRRH_WORKAROUND
+   #define CMD_OPTION_DUMMY_CYCLES 0x7F/* Dummy Cycles for 
Read Command */
+#endif
+
@@ -706,9 +710,25 @@
 #endif
 
/* Get address */
+#ifdef CONFIG_DBRRH_WORKAROUND
+   addr_value = cadence_qspi_apb_cmd2addr([1], 4);
+#else
addr_value = cadence_qspi_apb_cmd2addr([1], addr_bytes);
+#endif

+#ifdef CONFIG_DBRRH_WORKAROUND
+   /* Setting Dummy Clock Cycle */
+   dummy_clk = (0x08 & CMD_OPTION_DUMMY_CYCLES);
+   if (dummy_clk) 
+   {
+   rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
+   << CQSPI_REG_RD_INSTR_DUMMY_LSB;
+   }
+#else
+
/* The remaining lenght is dummy bytes. */
dummy_bytes = cmdlen - addr_bytes - 1;
if (dummy_bytes) {
@@ -731,7 +751,9 @@
rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
<< CQSPI_REG_RD_INSTR_DUMMY_LSB;
}
+#endif


With this correction I can read contents of the flash properly.
However, I'm a bit surprised that I was forced to make such correction like 
storing 4 bytes of address (see spi_flash_addr32() above).
On the other hand I haven't found any switch that could be turned on to fix my 
problem in a clean and nice way.

With 24 bytes we can address only 16 MB. How cadence driver is supposed to work 
for larger spaces?
Is this 4th byte comes from somewhere else?

Jagan, Heiko, please evaluate my correction.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with attaching UBI partition

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hello Heiko,

> Which U-Boot version? Which board?

This is U-Boot v2016.03-rc1.
I have custom board with socfpga Arria5 onboard.

> Where does this leading 0xff come from? There seems a problem
> with your spi nor flash driver?

Yes, you're right. I have problems with the driver.
As I mentioned in previous mail when I read the contents from the flash some 
data is corrupted.

How to find out if the problem is because U-Boot has no support for my flash 
(Spansion S25FL512S NOR flash with SPI) or I have not proper configured SPI in 
U-Boot?

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with attaching UBI partition

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi,

I found that I have problem with reading flash contents:

When dumping the flash from Linux env:

$ cat /dev/mtd5 > /tmp/flash.bin

: 55424923 0100  0003

But when I dump the flash contents from U-Boot I see this:

=> sf read 0x1B00 0x01B0 0x1000
=> md 0x1B00

1b00: 494255ff 0123  

So, that's why I see this print:

ubi0 warning: ubi_io_read_ec_hdr: bad magic number at PEB 0: ff554249 instead 
of 55424923

I will investigate why data was read from flash incorrectly.

Best regards,
Denis Bakhvalov

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[U-Boot] Problem with attaching UBI partition

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Dear U-Boot support,

I have problems while running following commands in U-Boot:

U-Boot => sf probe 0 0 0
SF: Detected S25FL512S with page size 512, total: 67108864

U-Boot => mtdparts
device nor0 , # parts = 4
 #: namesizeoffset  mask_flags
 0: boot0x0010  0x  0
 1: bootenv 0x0008  0x0010  0
 2: SomeInfo0x0198  0x0018  0
 3: ubifspart   0x0250  0x01b0  0

U-Boot => ubi part ubifspart
mtd: Giving out device 1 to mtd=3
ubi0: attaching mtd1
UBI DBG gen (pid 1): sizeof(struct ubi_ainf_peb) 48
UBI DBG gen (pid 1): sizeof(struct ubi_wl_entry) 20
UBI DBG gen (pid 1): min_io_size  1
UBI DBG gen (pid 1): max_write_size   512
UBI DBG gen (pid 1): hdrs_min_io_size 1
UBI DBG gen (pid 1): ec_hdr_alsize64
UBI DBG gen (pid 1): vid_hdr_alsize   64
UBI DBG gen (pid 1): vid_hdr_offset   64
UBI DBG gen (pid 1): vid_hdr_aloffset 64
UBI DBG gen (pid 1): vid_hdr_shift0
UBI DBG gen (pid 1): leb_start128
UBI DBG gen (pid 1): max_erroneous16
UBI DBG gen (pid 1): process PEB 0
UBI DBG bld (pid 1): scan PEB 0
UBI DBG io (pid 1): read EC header from PEB 0
UBI DBG io (pid 1): read 64 bytes from PEB 0:0
ubi0 warning: ubi_io_read_ec_hdr: bad magic number at PEB 0: ff554249 instead 
of 55424923
Erase counter header dump:
magic  0xff554249
version35
ec 0
vid_hdr_offset 16777216
data_offset1073741824
image_seq  -2142856561
hdr_crc0xe046ed
erase counter header hexdump:
UBI DBG bld (pid 1): bad magic number at PEB 0: ff554249 instead of 55424923
UBI DBG io (pid 1): read VID header from PEB 0
UBI DBG io (pid 1): read 64 bytes from PEB 0:64
UBI DBG bld (pid 1): no VID header found at PEB 0, only 0xFF bytes
UBI DBG bld (pid 1): add to erase: PEB 0, EC -1

... // this warning goes for all PEBs from 1 to 147

ubi0: scanning is finished
UBI DBG gen (pid 1): max. sequence number:   0
ubi0 error: ubi_read_volume_table: the layout volume was not found
ubi0 error: ubi_attach_mtd_dev: failed to attach mtd1, error -22
UBI error: cannot attach mtd1
UBI error: cannot initialize UBI, error -22
UBI init error 22
UBI init error 22

For me it looks like this magic number is shifted one byte right, although I 
can't understand why.

Here is how I create UBI partition in Linux env:

Linux Env #> mtdinfo -a

mtd5
Name:   data
Type:   nor
Eraseblock size:262144 bytes, 256.0 KiB
Amount of eraseblocks:  148 (38797312 bytes, 37.0 MiB)
Minimum input/output unit size: 1 byte
Sub-page size:  1 byte
Character device major/minor:   90:10
Bad blocks are allowed: false
Device is writable: true

Linux Env #> ubiformat /dev/mtd5

ubiformat: mtd5 (nor), size 38797312 bytes (37.0 MiB), 148 eraseblocks of 
262144 bytes (256.0 KiB), min. I/O size 1 bytes
libscan: scanning eraseblock 147 -- 100 % complete
ubiformat: 148 eraseblocks are supposedly empty
ubiformat: formatting eraseblock 147 -- 100 % complete  797312

Linux Env #> ubiattach -m 5 /dev/ubi_ctrl

UBI: attaching mtd5 to ubi0
UBI: scanning is finished
UBI: attached mtd5 (name "part5", size 37 MiB) to ubi0
UBI: PEB size: 262144 bytes (256 KiB), LEB size: 262016 bytes
UBI: min./max. I/O unit sizes: 1/256, sub-page size 1
UBI: VID header offset: 64 (aligned 64), data offset: 128
UBI: good PEBs: 148, bad PEBs: 0, corrupted PEBs: 0
UBI: user volume: 0, internal volumes: 1, max. volumes count: 128
UBI: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 
1371523162
UBI: available PEBs: 144, total reserved PEBs: 4, PEBs reserved for bad PEB 
handling: 0
UBI: background thread "ubi_bgt0d" started, PID 1003

Linux Env #> ubimkvol -N data -m /dev/ubi0

Linux Env #> mount -t ubifs ubi0:data /mnt

Linux Env #>  mount -t ubifs ubi0:data /mnt

UBIFS: default file-system created
UBIFS: background thread "ubifs_bgt0_0" started, PID 1010
UBIFS: mounted UBI device 0, volume 0, name "data"
UBIFS: LEB size: 262016 bytes (255 KiB), min./max. I/O unit sizes: 8 bytes/256 
bytes
UBIFS: FS size: 35110144 bytes (33 MiB, 134 LEBs), journal size 2096129 bytes 
(1 MiB, 7 LEBs)
UBIFS: reserved for root: 1658338 bytes (1619 KiB)
UBIFS: media format: w4/r0 (latest is w4/r0), UUID 
696FFD7B-1957-4ABD-9FDC-ED0EEB674D9D, small LPT model

It's perfectly working from Linux env, however U-Boot don't want to attach UBI 
partition.

Please help me identify the problem!

Best regards,
Denis Bakhvalov

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Re: [U-Boot] Problem with mounting a jffs2 partition on flash.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek,

I tried mainline U-boot with your patches as well as socfpga branch.
Still no success.
There is no output on the console.
Once again when I'm uploading old version of U-boot and preloader (from 2013) 
at least I can see the output on the console.

What could be the next step?

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with mounting a jffs2 partition on flash.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

> > I tried mainline U-boot with your patches as well as socfpga branch.
> > Still no success.
>
> Did you try the image I sent you ? That one is tested to work on AV SoCDK.

I tried it also. The same result.

> > There is no output on the console.
> > Once again when I'm uploading old version of U-boot and preloader (from 
> > 2013) at least I can see the output on the console.
> > 
> > What could be the next step?
> 
> Press the "WARM RESET" button of the HPS (located top-right, if you have
> the board oriented with HPS ethernet on the top-left). Do you
> see any console output then ? You do use the top-right miniUSB port
> for console, right ?

Currently board is integrated in RF unit. I will put off the cover and press it.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with mounting a jffs2 partition on flash.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek,

> > Press the "WARM RESET" button of the HPS (located top-right, if you have
> > the board oriented with HPS ethernet on the top-left). Do you
> > see any console output then ? You do use the top-right miniUSB port
> > for console, right ?
> 
> Currently board is integrated in RF unit. I will put off the cover and press 
> it.

I took off the cover and:
1. We don't have socfpga dev kit. There is only fpga itself. 
Sorry for that, but I haven't ever opened the unit before.
I assume that the main board is produced by Nokia.
2. Maybe this is the problem, that we are targeting socfpga Dev Kit?
3. I can send you some photos to check.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with mounting a jffs2 partition on flash.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek,

> That's fine, just check if you did some modifications to the altera fork
> of u-boot. Especially interesting would be PLL/pinmux/DRAM config.

I tried to launch altera branch from here: 
https://github.com/altera-opensource/u-boot-socfpga.
It didn't work out of the box as well.
I will try to extract the difference in source codes and will let you know 
about the results.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with mounting a jffs2 partition on flash.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek,

> Please just use mainline everything. If you use Arria V SoCDK, you can
> just grab 2016.01 , compile it and write u-boot-with-spl-dtb.sfp to
> offset 0x0 of the QSPI and it should just magically work.

I haven't found the file with the name u-boot-with-spl-dtb.sfp.

denis@DendiMachine:~/WorkSpace/u-boot$ ls -l
total 8544
drwxrwxr-x   2 denis denis4096 lut 10 22:46 api
drwxrwxr-x  17 denis denis4096 lut 10 22:46 arch
drwxrwxr-x 201 denis denis4096 lut 10 22:46 board
drwxrwxr-x   2 denis denis4096 sty 11 23:15 build
drwxrwxr-x   2 denis denis   12288 lut 11 10:50 cmd
drwxrwxr-x   4 denis denis   20480 lut 11 10:50 common
-rw-rw-r--   1 denis denis2260 sty 11 22:32 config.mk
drwxrwxr-x   2 denis denis   61440 lut 10 22:46 configs
drwxrwxr-x   2 denis denis4096 lut 11 10:45 disk
drwxrwxr-x   8 denis denis4096 lut 10 22:46 doc
drwxrwxr-x  46 denis denis4096 lut 11 10:45 drivers
drwxrwxr-x   2 denis denis4096 lut 11 10:46 dts
drwxrwxr-x   4 denis denis4096 sty 11 22:32 examples
drwxrwxr-x  12 denis denis4096 lut 11 10:45 fs
drwxrwxr-x  28 denis denis   12288 lut 11 10:45 include
-rw-rw-r--   1 denis denis1863 sty 11 22:32 Kbuild
-rw-rw-r--   1 denis denis7669 lut 10 22:46 Kconfig
drwxrwxr-x  11 denis denis4096 lut 11 10:50 lib
drwxrwxr-x   2 denis denis4096 lut 10 22:46 Licenses
-rw-rw-r--   1 denis denis   10765 lut 10 22:46 MAINTAINERS
-rwxrwxr-x   1 denis denis   23247 sty 11 22:32 MAKEALL
-rw-rw-r--   1 denis denis   53021 lut 10 22:46 Makefile
drwxrwxr-x   2 denis denis4096 lut 11 10:46 net
drwxrwxr-x   6 denis denis4096 sty 11 22:32 post
-rw-rw-r--   1 denis denis  235198 lut 10 22:46 README
drwxrwxr-x   4 denis denis4096 lut 10 22:46 scripts
-rw-rw-r--   1 denis denis  17 sty 11 22:32 snapshot.commit
drwxrwxr-x  11 denis denis4096 lut 11 10:50 spl
-rw-rw-r--   1 denis denis   75047 lut 11 10:46 System.map
drwxrwxr-x  10 denis denis4096 lut 11 10:46 test
drwxrwxr-x  15 denis denis4096 lut 11 10:50 tools
-rwxrwxr-x   1 denis denis 3492298 lut 11 10:50 u-boot
-rw-rw-r--   1 denis denis  431333 lut 11 10:50 u-boot.bin
-rw-rw-r--   1 denis denis   26288 lut 11 10:46 u-boot.cfg
-rw-rw-r--   1 denis denis   16301 lut 11 10:46 u-boot.dtb
-rw-rw-r--   1 denis denis  431333 lut 11 10:50 u-boot-dtb.bin
-rw-rw-r--   1 denis denis  431397 lut 11 10:46 u-boot-dtb.img
-rw-rw-r--   1 denis denis  431397 lut 11 10:50 u-boot.img
-rw-rw-r--   1 denis denis1286 lut 11 10:46 u-boot.lds
-rw-rw-r--   1 denis denis  561107 lut 11 10:50 u-boot.map
-rw-rw-r--   1 denis denis  415032 lut 11 10:50 u-boot-nodtb.bin
-rw-rw-r--   1 denis denis 1245202 lut 11 10:46 u-boot.srec
-rw-rw-r--   1 denis denis  693541 lut 11 10:50 u-boot-with-spl.sfp

denis@DendiMachine:~/WorkSpace/u-boot$ ls ./spl/ -l
total 1292
drwxrwxr-x 3 denis denis   4096 lut 11 10:46 arch
drwxrwxr-x 3 denis denis   4096 lut 11 10:46 board
drwxrwxr-x 2 denis denis   4096 lut 11 10:46 cmd
drwxrwxr-x 4 denis denis   4096 lut 11 10:46 common
drwxrwxr-x 9 denis denis   4096 lut 11 10:46 drivers
drwxrwxr-x 2 denis denis   4096 lut 11 10:46 dts
drwxrwxr-x 2 denis denis   4096 lut 11 10:46 fs
drwxrwxr-x 2 denis denis   4096 lut 11 10:45 include
drwxrwxr-x 3 denis denis   4096 lut 11 10:50 lib
-rwxrwxr-x 1 denis denis 932073 lut 11 10:50 u-boot-spl
-rw-rw-r-- 1 denis denis  53943 lut 11 10:50 u-boot-spl.bin
-rw-rw-r-- 1 denis denis  26129 lut 11 10:46 u-boot-spl.cfg
-rw-rw-r-- 1 denis denis903 lut 11 10:46 u-boot-spl.dtb
-rw-rw-r-- 1 denis denis  53943 lut 11 10:50 u-boot-spl-dtb.bin
-rw-rw-r-- 1 denis denis   1192 lut 11 10:46 u-boot-spl.lds
-rw-rw-r-- 1 denis denis 137422 lut 11 10:50 u-boot-spl.map
-rwxrwxr-x 1 denis denis  52880 lut 11 10:50 u-boot-spl-nodtb.bin
-rw-rw-r-- 1 denis denis160 lut 11 10:50 u-boot-spl-pad.bin
-rw-rw-r-- 1 denis denis  65536 lut 11 10:50 u-boot-spl.sfp

There is only target "u-boot-with-spl.sfp".
I'm a little bit confused which file is the proper one.
Can I use u-boot-with-spl.sfp from the root folder?

>>> I was more interested in the procedure you used. I usually install mainline
>>> U-Boot onto a board which boots from QSPI this way:
>> 
>>> $ quartus_hps -c 1 -o PV -a 0x0 u-boot-with-spl-dtb.sfp
>> 
>> Yes, exactly. But we have separated SPL and U-Boot images and put them 
>> separately (with two commands).

> Please don't :-)

Ok. Can you please briefly explain why?

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with mounting a jffs2 partition on flash.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek,

Here are my build steps:

denis@DendiMachine:~/WorkSpace/u-boot$ make clean
  CLEAN   dts/../arch/arm/dts
  CLEAN   dts
  CLEAN   examples/standalone
  CLEAN   tools
  CLEAN   tools/lib tools/common
  CLEAN   spl/arch spl/board spl/cmd spl/common spl/drivers spl/dts spl/fs 
spl/lib spl/u-boot-spl spl/u-boot-spl.bin spl/u-boot-spl.cfg spl/u-boot-spl.dtb 
spl/u-boot-spl-dtb.bin spl/u-boot-spl.lds spl/u-boot-spl.map 
spl/u-boot-spl-nodtb.bin spl/u-boot-spl-pad.bin spl/u-boot-spl.sfp
  CLEAN   u-boot u-boot.bin u-boot.cfg u-boot.dtb u-boot-dtb.bin u-boot-dtb.img 
u-boot.img u-boot.lds u-boot.map u-boot-nodtb.bin u-boot.srec System.map
denis@DendiMachine:~/WorkSpace/u-boot$ make distclean
  CLEAN   scripts/basic
  CLEAN   scripts/kconfig
  CLEAN   include/config include/generated spl
  CLEAN   .config .config.old include/autoconf.mk include/autoconf.mk.dep 
include/config.h
denis@DendiMachine:~/WorkSpace/u-boot$ make clean
denis@DendiMachine:~/WorkSpace/u-boot$ make distclean
denis@DendiMachine:~/WorkSpace/u-boot$ git pull
Already up-to-date.
denis@DendiMachine:~/WorkSpace/u-boot$ git describe
v2016.03-rc1-138-gcc8d698
denis@DendiMachine:~/WorkSpace/u-boot$ git status
On branch master
Your branch is up-to-date with 'origin/master'.

Changes not staged for commit:
  (use "git add ..." to update what will be committed)
  (use "git checkout -- ..." to discard changes in working directory)

modified:   include/configs/socfpga_arria5_socdk.h// here I only 
changed SDRAM configuration

no changes added to commit (use "git add" and/or "git commit -a")
denis@DendiMachine:~/WorkSpace/u-boot$ make socfpga_arria5_defconfig
  HOSTCC  scripts/basic/fixdep
  HOSTCC  scripts/kconfig/conf.o
  SHIPPED scripts/kconfig/zconf.tab.c
  SHIPPED scripts/kconfig/zconf.lex.c
  SHIPPED scripts/kconfig/zconf.hash.c
  HOSTCC  scripts/kconfig/zconf.tab.o
  HOSTLD  scripts/kconfig/conf
#
# configuration written to .config
#
denis@DendiMachine:~/WorkSpace/u-boot$ make -j9

But after compilation I don't have such file.

I have installed:
- linaro toolchain
- u-boot-tools
- device-tree-compiler

All env variables should be ok, because in other way it won't compile.

make u-boot-with-spl-dtb.sfp doesn't work for me because there is no such 
target in Makefile.
What I'm doing wrong?
I will try to clone sources and build it from the scratch.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with mounting a jffs2 partition on flash.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

$ quartus_hps -c 1 -o PV -a 0x0 u-boot-with-spl.sfp.bin
// here ".bin" because current programmer requires so. I think it shouldn't be 
a problem.

>From manual:
"HPS Flash Programmer
The utility accepts a Binary File with a required ".bin" extension.
The HPS flash programmer command-line syntax is:
quartus_hps  "

Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version

After that I power off/on the unit and nothing happened.
I also compared md5 while copying - everything should be ok.

I tried it 2 times with no success:
Looks like unit is no booting.
No output in the console is visible.

If I change the images back (that is currently in official release) - at least 
bootloader pass and u-boot is also launching.

Does it mean that there is something wrong with SPL configuration?
Or maybe I need some patches from altera in order to make them working?
Because I can see some traces of applied patches in the svn history.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] [PATCH] arm: socfpga: Add missing CONFIG_BUILD_TARGET

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

$ quartus_hps -c 1 -o PV -a 0x0 u-boot-with-spl.sfp.bin
// here ".bin" because current programmer requires so. I think it shouldn't be 
a problem.

>From manual:
"HPS Flash Programmer
The utility accepts a Binary File with a required ".bin" extension.
The HPS flash programmer command-line syntax is:
quartus_hps  "

Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version

After that I power off/on the unit and nothing happened.
I also compared md5 while copying - everything should be ok.

I tried it 2 times with no success:
Looks like unit is no booting.
No output in the console is visible.

If I change the images back (that is currently in official release) - at least 
bootloader pass and u-boot is also launching.

Does it mean that there is something wrong with SPL configuration?
Or maybe I need some patches from altera in order to make them working?
Because I can see some traces of applied patches in the svn history.

Best regards,
Denis Bakhvalov

MBB Radio Platforms, RFSW

-Original Message-
From: EXT Marek Vasut [mailto:ma...@denx.de] 
Sent: Thursday, February 11, 2016 14:02
To: u-boot@lists.denx.de
Cc: Marek Vasut <ma...@denx.de>; Dinh Nguyen <dingu...@opensource.altera.com>; 
Chin Liang See <cl...@altera.com>; Bakhvalov, Denis (Nokia - PL/Wroclaw) 
<denis.bakhva...@nokia.com>
Subject: [PATCH] arm: socfpga: Add missing CONFIG_BUILD_TARGET

Add the missing CONFIG_BUILD_TARGET to get u-boot-with-spl.sfp built
automatically upon running make in the source tree.

Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Chin Liang See <cl...@altera.com>
Cc: Denis Bakhvalov <denis.bakhva...@nokia.com>
---
 include/configs/socfpga_common.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 8de0ab9..0501bd1 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -30,6 +30,9 @@
 
 #define CONFIG_TIMESTAMP   /* Print image info with timestamp */
 
+/* add target to build it automatically upon "make" */
+#define CONFIG_BUILD_TARGET"u-boot-with-spl.sfp"
+
 /*
  * Memory configurations
  */
-- 
2.1.4

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Re: [U-Boot] [PATCH] arm: socfpga: Add missing CONFIG_BUILD_TARGET

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Sorry.
My bad.

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with mounting a jffs2 partition on flash.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

> There is output, but it takes a while for the USB-to-UART chip to kick
> in after restart, so you don't see it. I will send you two more patches,
> so apply them and it should get you up and running. The QSPI NOR boot
> was not enabled on AV/CV SoCDK.

> You can also grab the latest stuff here:
> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=summary

I made those changes, but still no progress.

Currently I'm building u-boot from 
git://git.denx.de/u-boot.git
Should I use
git://git.denx.de/u-boot-socfpga.git
?

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with mounting a jffs2 partition on flash.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Marek,

> That's not mainline SPL. Please use mainline SPL with mainline U-Boot.
> Mixing and matching various versions of U-Boot and SPL is not supported.

> Is there any reason why you are using non-mainline SPL ?

We received information from Altera that we should stick to this previous 
version of SPL. 
Even if we decide to upgrade U-Boot itself.
I don't know why. They just wrote it. 
Although I will try both variants.

> I thought you were using mainline U-Boot, but this output is from non-mainline
> U-Boot now. And it also contains some odd debug prints which are not even 
> present in the U-Boot Altera delivers. I have to admit, I am quite confused.

Sorry for confusing you. We tried both variants.
With old version I had problems with creating jffs2/ubifs upon a partition that 
contains Linux kernel.

My colleague tried to build U-Boot 2016.01. But he failed with hanging U-Boot 
as a result.
I will try to do it once again and let you know about the results.

> I suppose you have Arria V SoCDK and you're trying to run U-Boot 2016.01 on
> it, right ? Can you load the mainline SPL and mainline U-Boot and see if
> that works for you? If it does not, please share the entire boot log .

I will try to do.

> If you have a custom board, you will need to change the memory timing bits
> based on the output from Quartus . This is slightly more involved in both
> the altera setup and mainline setup.

Thanks for that hint.

> I was more interested in the procedure you used. I usually install mainline
> U-Boot onto a board which boots from QSPI this way:

> $ quartus_hps -c 1 -o PV -a 0x0 u-boot-with-spl-dtb.sfp

Yes, exactly. But we have separated SPL and U-Boot images and put them 
separately (with two commands).

> Is this u-boot 2016.01 or the ancient version provided by Altera please ?

This is the old version (2013).

> Is there any reason why you don't use Linux 4.4 ? There are customers who
> are using this on socfpga just fine, including FPGA manager and DT overlays
> to deal with the FPGA part.

This is good question on which I'm not ready to answer yet.
I understand that the newer the better, but this is still not an easy decision.
Anyway I will think about that after I will solve my issue with U-Boot .

Best regards,
Denis Bakhvalov
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Re: [U-Boot] Problem with mounting a jffs2 partition on flash.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi,

Thank you for you responses!

@To Marek:

> It would be very helpful to see the whole boot output, not just U-Boot output.
> For example SPL output is missing. Are you using mainline U-Boot SPL or not ?

Here is the output from SPL:

U-Boot SPL 2013.01.01-svn564 (May 27 2015 - 17:58:12)
Board Type :  // I changed it
Preloader Ver.: 00.01.03.00
QSPI Access Mode: Single Access
BOARD : Altera SOCFPGA Arria V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 10 KHz
CLOCK: MMC clock 12500 KHz
CLOCK: QSPI clock 40 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 512 MiB
SF: Read data capture delay calibrated to 3 (0 - 7)
SF: Detected S25FL512S with page size 512, total: 67108864

Here is the output from U-Boot:

U-Boot 2013.01.01-svn578 (Jan 08 2016 - 16:02:29)
VERSION : 00.02.04.00
U-Boot code: 0140 -> 01049080  BSS: -> 01089908
IRQ Stack: 0badc0de
FIQ Stack: 0badc0de
CPU   : Altera SOCFPGA Platform
BOARD :   // I changed it
I2C:   ready
monitor len: 000898C8
ramsize: 1F00
TLB table from 1eff to 1eff4000
Top of RAM usable for U-Boot at: 1eff
Reserving 550k for U-Boot at: 1ef66000
Reserving 640k for malloc() at: 1eec6000
Reserving 32 Bytes for Board Info at: 1eec5fe0
Reserving 128 Bytes for Global Data at: 1eec5f60
Reserving 2048 Bytes for IRQ stack at: 1eec5760
New Stack Pointer is: 1eec5750
DRAM:  496 MiB
relocation Offset is: 1df65fc0
dram_bank_mmu_setup: bank: 0
monitor flash len: 00051840
Now running in RAM - U-Boot at: 1ef66000
spi_setup_slave: bus 0 cs 0 max_hz 50MHz mode 3
spi_claim_bus: bus:0 cs:0
cadence_qspi_apb_chipselect : chipselect 0 decode 0
cadence_qspi_apb_config_baudrate_div: ref_clk 4Hz sclk 5000Hz Div 
0x3
cadence_qspi_apb_config_baudrate_div: ref_clk 4Hz sclk 100Hz Div 0xf
cadence_qspi_apb_config_baudrate_div: ref_clk 4Hz sclk 5000Hz Div 
0x3
SF: Read data capture delay calibrated to 3 (0 - 7)
SF: Configuration Register : READ : CMD : 0x35
spi_claim_bus: bus:0 cs:0
cadence_qspi_apb_chipselect : chipselect 0 decode 0
cadence_qspi_apb_config_baudrate_div: ref_clk 4Hz sclk 5000Hz Div 
0x3
SF: Bank Register : WRITE : CMD : 0x17 : BANK : 0x80
SF: Opt Area Data : READ : CMD : { 0x4b : 0x0010 }
spi_claim_bus: bus:0 cs:0
cadence_qspi_apb_chipselect : chipselect 0 decode 0
cadence_qspi_apb_config_baudrate_div: ref_clk 4Hz sclk 5000Hz Div 
0x3
SF: Detected S25FL512S with page size 512, total 67108864 bytes
SF: Detected S25FL512S with page size 512, total: 67108864
READ: 0x10 => cmd = { 0x0b 0x001008 } len = 0x2
spi_claim_bus: bus:0 cs:0
cadence_qspi_apb_chipselect : chipselect 0 decode 0
cadence_qspi_apb_config_baudrate_div: ref_clk 4Hz sclk 5000Hz Div 
0x3
READ: 0x14 => cmd = { 0x0b 0x001408 } len = 0x2
spi_claim_bus: bus:0 cs:0
cadence_qspi_apb_chipselect : chipselect 0 decode 0
cadence_qspi_apb_config_baudrate_div: ref_clk 4Hz sclk 5000Hz Div 
0x3
Destroy Hash Table: 1efae2a0 table = 
Create Hash Table: N=512
... 
// then a lot of prints setting env variables.

> How did you install the U-Boot on your board ?
U-boot is simply stored to flash using USB blaster from Altera.

@To Wolfgang:

> What do you mean by "current" here?  UBI/UBIFS support in U-Boot was
> actually adapted from the Linux kernel, so Linux support for UBI/UBIFS
> predates the U-Boot code by a long, long time.

Ok, I tried to make it work with UBI/UBIFS:

1. From Linux env I erased partition:
flasheraseall /dev/mtd5
2. I'm able to work with this partition is Linux env:
ubiattach /dev/ubi_ctrl -m 5
ubimkvol /dev/ubi0 -N myUbifs -s 35MiB
mount -t ubifs ubi0_0 /mnt
3. But from U-Boot it is not working:
All commands as before:
U-BOOT # sf probe 0 0 0
U-BOOT # mtdparts
...
---list_partitions---

device nor0 , # parts = 4
 #: namesizeoffset  mask_flags
 0: boot0x0010  0x  0
 1: bootenv 0x0008  0x0010  0
 2: SomeInfo0x0198  0x0018  0
 3: jffs2spart  0x0250  0x01b0  0

U-BOOT # ubi part ubifspart

---mtdparts_init---
last_ids  : nor0=snor0
env_ids   : nor0=snor0
last_parts: mtdparts=snor0:1M(boot),512k(bootenv),26112k(SomeInfo),-(ubifspart)
env_parts : mtdparts=snor0:1M(boot),512k(bootenv),26112k(SomeInfo),-(ubifspart)

last_partition : nor0,0
env_partition  : nor0,0
--- find_dev_and_part ---
id = ubifspart
--- find_dev_and_part ---
id = ubifspart
Creating 1 MTD partitions on "nor0":
0x01b0-0x0400 : "mtd=3"
raise: Signal # 8 caught
raise: Signal # 8 caught
UBI: attaching mtd1 to ubi0
raise: Signal # 8 caught
UBI: physical eraseblock size:   0 bytes (0 

Re: [U-Boot] Problem with mounting a jffs2 partition on flash.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Hi Wolfgang,

Thank you for your quick reply.

> 1) Is there any specific reason for using JFFS2?  We consider this
>   pretty much deprecated today and usually tend to prefer UBI/UBIFS.

Yes, I'm aware that jffs2 is quite old and ubifs is a successor of jffs2, but 
the reason is that current Linux Kernel has no support for UBI.
It means that if will use UBI in U-boot we can't see the contents in Lunix env 
after it starts.
I understand that it should have solution, but it requires recompiling Linux 
kernel which is also time consuming.

So, for a proof of concept I decided to make it work with jffs2.

> 2) Especially with SoCFPGA it is highly recommended to use current
>   mainline code.

> As mentioned, it is highly recommended to use current mainline
> instead.

> OK - I understand this is with the OLD version of U-Boot, right?
Yes, current logs are from OLD U-boot version.

> What exactly are these "other problems" ?

U-Boot launches, but after that it is hanging.
U-Boot 2016.01 (Feb 05 2016 - 14:15:47 +0100)

CPU:   Altera SoCFPGA Platform
FPGA:  Altera Arria V, D5, version 0x0
BOOT:  QSPI Flash (3.0V)
   Watchdog enabled
I2C:   ready
DRAM:

I will try to tackle this problem also.
However, I must say that I don't have much experience with U-Boot, so maybe I'm 
missing something obvious?

Can you please share some examples of correct configuration for such use case 
(jffs2 partition on NOR flash with SPI)?
I spent some time digging into the code, enabling different defines, so now it 
is complete mess in my sources.

Best regards,
Denis Bakhvalov

MBB Radio Platforms, RFSW
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[U-Boot] Problem with mounting a jffs2 partition on flash.

[Bakhvalov, Denis (Nokia - PL/Wroclaw)]

Dear U-boot Support,

My name is Denis and I'm representing Nokia.

We want to have flexibility in choosing which Linux kernel image to load for 
different HW configurations.
But we don't want to define several partitions and use hardcoded addresses on 
the flash to fetch the needed
Linux kernel image. We want to keep them in a one big partition and choose 
between them using their filenames.

That's why we want to mount a jffs2 partition on flash at U-boot stage. 
Unfortunately we've faced some problems and we need help from your side.
We have Altera SOCFPGA Arria V Board. We use U-boot from SOC Embedded Design 
Suite.  We have NOR flash with SPI interface (S25FL512S).

I prepared Jffs2 partition from Linux env using flash_eraseall -j command. It 
is perfectly mountable from Linux env, I can put files on it etc.
1.  Currently we are using U-boot 2013:
U-Boot 2013.01.01 (Jan 26 2016 - 11:50:12)
VERSION : 00.02.04.00

We are ok to upgrade our U-boot to a fresh one, however we faced other problems 
with it.

Here is the actual problem:

# mtdparts
...
---list_partitions---

device nor0 , # parts = 4
#: namesizeoffset  mask_flags
0: boot0x0010  0x  0
1: bootenv 0x0008  0x0010  0
2: SomeInfo0x0198  0x0018  0
3: jffs2spart  0x0250  0x01b0  0

--- mtd_part_info: partition number 0 for device nor0 (snor0)

active partition: nor0,0 - (boot) 0x0010 @ 0x

# chpart nor0,3
...
=> mtddevnum 3,
=> mtddevname jffs2spart
partition changed to nor0,3

# ls

--- jffs2_part_info: partition number 3 for device nor0 (snor0)
rescan: First time in use
raise: Signal # 8 caught
Scanning JFFS2 FS:  done.

**The directory Entries**

**The fragment Entries**

As you can see ls command fails.

I tried to change U-boot configuration several times, with no success.
I can paste my configuration if needed.

But first I would like to hear major hints. Because it could happen so, that 
I'm doing something wrong.

Your support would be greatly appreciated!


Best regards,
Denis Bakhvalov

MBB Radio Platforms, RFSW



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