Re: [PATCH v1] doc: imx: imxrt1170: Document imxrt1170-evk board
Hi Jesse, On 01/02/24 16:00, Jesse Taube wrote: Add documentation for imxrt1170-evk. Signed-off-by: Jesse Taube looks good to me Reviewed-by: Giulio Benetti Best regards -- Giulio Benetti CEO&CTO@Benetti Engineering sas --- doc/board/nxp/imxrt1170-evk.rst | 42 + 1 file changed, 42 insertions(+) create mode 100644 doc/board/nxp/imxrt1170-evk.rst diff --git a/doc/board/nxp/imxrt1170-evk.rst b/doc/board/nxp/imxrt1170-evk.rst new file mode 100644 index 00..4acccdcc93 --- /dev/null +++ b/doc/board/nxp/imxrt1170-evk.rst @@ -0,0 +1,42 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +imxrt1170-evk += + +How to use U-Boot on NXP i.MXRT1170 EVK +--- + +- Build U-Boot for i.MXRT1170 EVK: + +.. code-block:: bash + + $ make mrproper + $ make imxrt1170-evk_defconfig + $ make + +This will generate the SPL image called SPL and the u-boot.img. + +- Flash the SPL image into the micro SD card: + +.. code-block:: bash + + $sudo dd if=SPL of=/dev/sdX bs=1k seek=1 conv=notrunc; sync + +- Flash the u-boot.img image into the micro SD card: + +.. code-block:: bash + + $sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128 conv=notrunc; sync + +- Jumper settings:: + + SW1: 1 0 1 0 + SW2: 0 0 0 0 0 0 0 0 1 0 0 0 + +where 0 means bottom position and 1 means top position (from the +switch label numbers reference). + +- Connect the USB cable between the EVK and the PC for the console. + The USB console connector is the one close the ethernet connector + +- Insert the micro SD card in the board, power it up and U-Boot messages should come up.
Re: [PATCH v1 1/2] imx: imxrt1050-evk: Add support for SPI flash booting
Hello Jesse, Fabio, All, On 31/01/24 02:44, Jesse T wrote: On Mon, Jan 29, 2024 at 8:34 AM Fabio Estevam wrote: On Sun, Jan 28, 2024 at 6:43 PM Jesse Taube wrote: +++ b/configs/imxrt1050-evk_fspi_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y Out of curiosity: what are the problems if the D-Cache is turned on? I don't remember this was asked when we submitted the original imxrt1050-evk_defconfig The problem is that mmu_set_region_dcache_behaviour() is not implemented for armv7m and mxsfb.c requires it when DCache is enabled, that's why I've disabled. So we can keep it as is or implement armv7m complete mmu_set_region_dcache_behaviour() Best regards -- Giulio Benetti CEO&CTO@Benetti Engineering sas
Re: [PATCH v1 1/2] imx: imxrt1050-evk: Add support for SPI flash booting
Hi Jesse,
On 28/01/24 22:43, Jesse Taube wrote:
This add some macros to change addresses to use flexspi.
This commit adds support for booting the imxrt1050-evk from spi.
It adds imximage config and the ability for SPL to boot from NOR.
Signed-off-by: Jesse Taube
---
arch/arm/dts/imxrt1050-evk-u-boot.dtsi| 31 ++
arch/arm/mach-imx/imxrt/Kconfig | 1 +
.../freescale/imxrt1050-evk/imximage-nor.cfg | 41 +++
board/freescale/imxrt1050-evk/imximage.cfg| 10 +-
board/freescale/imxrt1050-evk/imxrt1050-evk.c | 7 +-
configs/imxrt1050-evk_defconfig | 8 +-
configs/imxrt1050-evk_fspi_defconfig | 100 ++
include/configs/imxrt1050-evk.h | 6 ++
8 files changed, 198 insertions(+), 6 deletions(-)
create mode 100644 board/freescale/imxrt1050-evk/imximage-nor.cfg
create mode 100644 configs/imxrt1050-evk_fspi_defconfig
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index a9095e736b..3f54411b7b 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -8,6 +8,10 @@
#include "imxrt1050-pinfunc.h"
/ {
+ binman: binman {
+ multiple-images;
+ };
+
aliases {
display0 = &lcdif;
usbphy0 = &usbphy1;
@@ -113,6 +117,33 @@
};
};
+&binman {
+#ifdef CONFIG_FSPI_CONF_HEADER
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ fspi_conf_block {
+ filename = CONFIG_FSPI_CONF_FILE;
+ type = "blob-ext";
+ offset = <0x0>;
+ };
+
+ spl {
+ filename = "SPL";
+ offset = <0x1000>;
+ type = "blob-ext";
+ };
+
+ binman_uboot: uboot {
+ filename = "u-boot.img";
+ offset = <0x1>;
+ type = "blob-ext";
+ };
+ };
+#endif
+};
+
&osc {
bootph-pre-ram;
};
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
index c1d6b09e77..f702f6 100644
--- a/arch/arm/mach-imx/imxrt/Kconfig
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -2,6 +2,7 @@ if ARCH_IMXRT
config IMXRT
bool
+ select BINMAN
select SYS_FSL_ERRATUM_ESDHC135
config IMXRT1020
diff --git a/board/freescale/imxrt1050-evk/imximage-nor.cfg
b/board/freescale/imxrt1050-evk/imximage-nor.cfg
new file mode 100644
index 00..fb7b6489a3
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/imximage-nor.cfg
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti
thanks for giving me credits but I haven't worked on this, so please
drop my Copyright and add yours here.
Best regards
--
Giulio Benetti
CEO&CTO@Benetti Engineering sas
+ */
+
+#include
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM nor
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type AddressValue
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * 0x400AC044 is used to configure the flexram.
+ * Unfortunatly seting all to OCRAM only works for MMC
+ * and setting all to DTCM only works for FLEXSPI NOR.
+ * This configureation fortunaly works for both SPI and MMC.
+*/
+/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */
+DATA 4 0x400AC044 0x55aa
+/* Use FLEXRAM_BANK_CFG to config FlexRAM */
+SET_BIT 4 0x400AC040 0x4
diff --git a/board/freescale/imxrt1050-evk/imximage.cfg
b/board/freescale/imxrt1050-evk/imximage.cfg
index f1f09fd7eb..dd5c231b39 100644
--- a/board/freescale/imxrt1050-evk/imximage.cfg
+++ b/board/freescale/imxrt1050-evk/imximage.cfg
@@ -29,7 +29,13 @@ BOOT_FROMsd
*value value to be stored in the register
*/
-/* Set all FlexRAM as OCRAM(01b) */
-DATA 4 0x400AC044 0x
+/*
+ * 0x400AC044 is used to configure the flexram.
+ * Unfortunatly seting all to OCRAM only works for MMC
+ * and setting all to DTCM only works for FLEXSPI NOR.
+ * This configureation fortunaly works for both SPI and MMC.
+*/
+/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */
+DATA 4 0x400AC044 0x55aa
/* Use FLEXRAM_BANK_CFG to config FlexRAM */
SET_BIT 4 0x400AC040 0x4
diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c
b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
index 4b82ee5e9c..d4e39fd914 100644
--- a/board/freescale/i
Re: [PATCH] net: phy: broadcom: add BCM5221 phy support
Hello Marek,
thanks for reviewing,
On 12/08/23 08:19, Marek Vasut wrote:
On 8/11/23 23:42, Giulio Benetti wrote:
Add BCM5221 phy support.
Why not port Linux drivers/net/sungem_phy.c instead ?
That already supports the PHY .
That was my idea too in the beginning, but sungem_phy.c is a hidden
tristate choice in Kconfig that depends on CONFIG_PCI and is not part of
the Linux standard drivers/net/phy/ folder.
It's only chosen by Toshiba CONFIG_SPIDER_NET and CONFIG_SUNGEM that
depends on PCI that in order depend on NET_VENDOR_SUN, so it looks like
legacy code and indeed while checking with git last commit that added
some support I've found it was back in 2011.
I've sent a patch for adding BCM5221 to Linux too:
https://lore.kernel.org/lkml/20230811215322.8679-1-giulio.bene...@benettiengineering.com/
and nobody pointed me to use sungem_phy.c
Sponsored by: Tekvox Inc.
Cc: Jim Reinhart
Cc: James Autry
Cc: Matthew Maron
Signed-off-by: Giulio Benetti
---
drivers/net/phy/broadcom.c | 99 ++
1 file changed, 99 insertions(+)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 36c70da181..a1996e6059 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -34,6 +34,26 @@
#define MIIM_BCM_CHANNEL_WIDTH 0x2000
+#define MII_BCM5221_INTREG 0x1a /* Interrupt register */
+#define MII_BCM5221_IR_MASK 0x0100 /* Mask all interrupts */
+#define MII_BCM5221_IR_LINK_EN 0x0200 /* Link status change
enable */
+#define MII_BCM5221_IR_SPEED_EN 0x0400 /* Link speed change
enable */
+#define MII_BCM5221_IR_DUPLEX_EN 0x0800 /* Duplex mode change
enable */
+#define MII_BCM5221_IR_ENABLE 0x4000 /* Interrupt enable */
+
+#define MII_BCM5221_BRCMTEST 0x1f /* Brcm test register */
+#define MII_BCM5221_BT_SRE 0x0080 /* Shadow register enable */
+
+#define MII_BCM5221_AE_GSR 0x1c /* BCM5221 Auxiliary Error &
+ * General Status Register
+ */
+#define MII_BCM5221_AE_GSR_DIS_MDIX 0x0800 /* BCM5221 Disable
MDIX */
+#define MII_BCM5221_SHDW_AM4_FLPM 0x0002 /* BCM5221 Force Low
Power
+ * Mode
+ */
+
+#define MII_BCM5221_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */
+
static void bcm_phy_write_misc(struct phy_device *phydev,
u16 reg, u16 chl, u16 value)
{
@@ -311,6 +331,75 @@ static int bcm5482_startup(struct phy_device
*phydev)
return bcm54xx_parse_status(phydev);
}
+static int bcm_bcm5221_config(struct phy_device *phydev)
+{
+ int reg, err, err2, brcmtest;
+
+ phy_reset(phydev);
+
+ /* The datasheet indicates the PHY needs up to 1us to complete a
reset,
+ * build some slack here.
+ */
+ udelay(2000);
1 us and 2000 us is a huge difference , why such a long delay ?
I agree with you, only I've found in Linux drivers/net/phy/broadcom.c
usleep_range(1000, 2000) even if the comment above states 1us so for
consistency I've added the worst case 2000us.
But while writing I see that usleep_range(1000, 2000) is an additional
delay added after software reset finished, indeed in Datasheet page 33:
https://docs.broadcom.com/doc/5221-DS07-405-RDS.pdf
they state:
"
...until the reset process is completed, which requires approximately 1 µs.
"
and phy_reset() already waits for RESET bit to be cleared, so that is
really an additional delay. It's not that clear to be honest.
+ /* The PHY requires 65 MDC clock cycles to complete a write
operation
+ * and turnaround the line properly.
+ *
+ * We ignore -EIO here as the MDIO controller (e.g.:
mdio-bcm-unimac)
+ * may flag the lack of turn-around as a read failure. This is
+ * particularly true with this combination since the MDIO controller
+ * only used 64 MDC cycles. This is not a critical failure in this
+ * specific case and it has no functional impact otherwise, so we
let
+ * that one go through. If there is a genuine bus error, the next
read
+ * of MII_BCM5221_INTREG will error out.
+ */
Shouldn't this be fixed on the MDIO/MAC driver level?
Yes you're right, but at the moment in Linux they deal with it like
this. I don't have access to such mdio-bcm-unimac so I don't know how
to test, reproduce and fix the problem at MAC level :-/
+ err = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+ if (err < 0 && err != -EIO)
+ return err;
+
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BCM5221_INTREG);
+ if (reg < 0)
+ return reg;
+
+ /* Mask interrupts globally since we don't use interrupt */
+ reg = MII_BCM5221_IR_MASK;
+
+ err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BCM5221_INTREG, reg);
+ if (err < 0)
+ return err;
+
+ /* Enable auto MDIX */
+ err = phy_modify(phydev, MDIO_
[PATCH] net: phy: broadcom: add BCM5221 phy support
Add BCM5221 phy support.
Sponsored by: Tekvox Inc.
Cc: Jim Reinhart
Cc: James Autry
Cc: Matthew Maron
Signed-off-by: Giulio Benetti
---
drivers/net/phy/broadcom.c | 99 ++
1 file changed, 99 insertions(+)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 36c70da181..a1996e6059 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -34,6 +34,26 @@
#define MIIM_BCM_CHANNEL_WIDTH0x2000
+#define MII_BCM5221_INTREG 0x1a/* Interrupt register */
+#define MII_BCM5221_IR_MASK0x0100 /* Mask all interrupts */
+#define MII_BCM5221_IR_LINK_EN 0x0200 /* Link status change enable */
+#define MII_BCM5221_IR_SPEED_EN0x0400 /* Link speed change enable */
+#define MII_BCM5221_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */
+#define MII_BCM5221_IR_ENABLE 0x4000 /* Interrupt enable */
+
+#define MII_BCM5221_BRCMTEST 0x1f/* Brcm test register */
+#define MII_BCM5221_BT_SRE 0x0080 /* Shadow register enable */
+
+#define MII_BCM5221_AE_GSR 0x1c/* BCM5221 Auxiliary Error &
+* General Status Register
+*/
+#define MII_BCM5221_AE_GSR_DIS_MDIX0x0800 /* BCM5221 Disable MDIX */
+#define MII_BCM5221_SHDW_AM4_FLPM 0x0002 /* BCM5221 Force Low Power
+* Mode
+*/
+
+#define MII_BCM5221_SHDW_AUXMODE4 0x1a/* Auxiliary mode 4 */
+
static void bcm_phy_write_misc(struct phy_device *phydev,
u16 reg, u16 chl, u16 value)
{
@@ -311,6 +331,75 @@ static int bcm5482_startup(struct phy_device *phydev)
return bcm54xx_parse_status(phydev);
}
+static int bcm_bcm5221_config(struct phy_device *phydev)
+{
+ int reg, err, err2, brcmtest;
+
+ phy_reset(phydev);
+
+ /* The datasheet indicates the PHY needs up to 1us to complete a reset,
+* build some slack here.
+*/
+ udelay(2000);
+
+ /* The PHY requires 65 MDC clock cycles to complete a write operation
+* and turnaround the line properly.
+*
+* We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac)
+* may flag the lack of turn-around as a read failure. This is
+* particularly true with this combination since the MDIO controller
+* only used 64 MDC cycles. This is not a critical failure in this
+* specific case and it has no functional impact otherwise, so we let
+* that one go through. If there is a genuine bus error, the next read
+* of MII_BCM5221_INTREG will error out.
+*/
+ err = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+ if (err < 0 && err != -EIO)
+ return err;
+
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BCM5221_INTREG);
+ if (reg < 0)
+ return reg;
+
+ /* Mask interrupts globally since we don't use interrupt */
+ reg = MII_BCM5221_IR_MASK;
+
+ err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BCM5221_INTREG, reg);
+ if (err < 0)
+ return err;
+
+ /* Enable auto MDIX */
+ err = phy_modify(phydev, MDIO_DEVAD_NONE, MII_BCM5221_AE_GSR,
+MII_BCM5221_AE_GSR_DIS_MDIX, 0);
+ if (err < 0)
+ return err;
+
+ /* Enable shadow register access */
+ brcmtest = phy_read(phydev, MDIO_DEVAD_NONE, MII_BCM5221_BRCMTEST);
+ if (brcmtest < 0)
+ return brcmtest;
+
+ reg = brcmtest | MII_BCM5221_BT_SRE;
+
+ err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BCM5221_BRCMTEST, reg);
+ if (err < 0)
+ return err;
+
+ /* Exit low power mode */
+ err = phy_modify(phydev, MDIO_DEVAD_NONE, MII_BCM5221_SHDW_AUXMODE4,
+MII_BCM5221_SHDW_AM4_FLPM, 0);
+ if (err < 0)
+ goto done;
+
+done:
+ /* Disable shadow register access */
+ err2 = phy_write(phydev, MDIO_DEVAD_NONE, MII_BCM5221_BRCMTEST,
brcmtest);
+ if (!err)
+ err = err2;
+
+ return err;
+}
+
U_BOOT_PHY_DRIVER(bcm5461s) = {
.name = "Broadcom BCM5461S",
.uid = 0x2060c0,
@@ -350,3 +439,13 @@ U_BOOT_PHY_DRIVER(bcm_cygnus) = {
.startup = &genphy_startup,
.shutdown = &genphy_shutdown,
};
+
+U_BOOT_PHY_DRIVER(BCM5221_driver) = {
+ .name = "Broadcom BCM5221 PHY",
+ .uid = 0x004061e0,
+ .mask = 0xf0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &bcm_bcm5221_config,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
--
2.34.1
Re: [PATCH] arm: mx6: module_fuse: fix build failure due to wrong argument name
Hello All, On 07/04/23 03:52, Peng Fan wrote: On 4/7/2023 12:17 AM, Giulio Benetti wrote: nodeoff variable should be variable off returned by fdt_path_offset() so let's rename it to off. Signed-off-by: Giulio Benetti Reviewed-by: Peng Fan I kindly ping Best regards -- CEO/CTO@Benetti Engineering sas
Re: Support for NXP S32K3 Family
Hi Ashok, On 20/04/23 11:19, Ashok Kumar wrote: Hey Simon, Thanks for the suggestions. Sure, I will try to get some more information to build u-boot for S32K family. I have ported i.MXRT10xx family to uboot while Jesse the i.MXRT11xx family and then we ported the initial support to Linux too. I have checked the S32K family but it doesn't have a sdram bus so even if on some component u-boot can run then I don't know if you could run Linux or other OSes :-/ While S32G2/3 instead support DDR3L/LPDDR4 but they have a lot of cortex-M7 and a lot of cortex-A53. This is a completely different architecture. S32R same as S32G. S32Z2 and S32E2 instead are based on cortex-R52+M33 and they both support LPDDR4 memory. It depends on your goal. Best regards -- CEO/CTO@Benetti Engineering sas I will contact you back If I need more information from your side. Cheers, Ashok On 19/04/2023 23:40, Simon Glass wrote: Hi Ashok, On Wed, 19 Apr 2023 at 21:42, Ashok Kumar wrote: Hi Simon, Thanks for the reply. NXP people said we don't support this feature for S32K family. I am just wondering whether I can get any help from the u-boot sources? I would expect you would need to add support for the board. You can see Cortex-M support for NXP i.MXRT and STM32, so far. I imagine there will be some differences, such as peripherals, memory layout, etc. If there is another bootloader or some libraries available that should provide some hints. Regards, Simon Regards Ashok On 19/04/2023 02:45, Simon Glass wrote: Hi Ashok, On Fri, 14 Apr 2023 at 08:55, Ashok Kumar wrote: Hi Folks, I am trying to build a u-boot boot-loader for my S32K344 board. Can you guys please help me, which defconf/config file is suitable for my S32K344 board for building a u-boot binaries? If you look in MAINTAINERS you should be able to find contacts for NXP. Regards, Simon
[PATCH] arm: mx6: module_fuse: fix build failure due to wrong argument name
nodeoff variable should be variable off returned by fdt_path_offset() so
let's rename it to off.
Signed-off-by: Giulio Benetti
---
arch/arm/mach-imx/mx6/module_fuse.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mx6/module_fuse.c
b/arch/arm/mach-imx/mx6/module_fuse.c
index 0f4565e311..b58f11c1e5 100644
--- a/arch/arm/mach-imx/mx6/module_fuse.c
+++ b/arch/arm/mach-imx/mx6/module_fuse.c
@@ -206,7 +206,7 @@ int ft_system_setup(void *blob, struct bd_info *bd)
if (off < 0)
continue; /* Not found, skip it */
add_status:
- rc = fdt_setprop(blob, nodeoff, "status", status,
+ rc = fdt_setprop(blob, off, "status", status,
strlen(status) + 1);
if (rc) {
if (rc == -FDT_ERR_NOSPACE) {
--
2.34.1
[PATCH 2/2] sunxi: video: Add support for active low LCD power pin
On some board gpio to power LCD can be active low, so let's add
CONFIG_VIDEO_LCD_POWER_ACTIVE_LOW to allow this.
Signed-off-by: Giulio Benetti
---
arch/arm/mach-sunxi/Kconfig | 7 +++
drivers/video/sunxi/sunxi_display.c | 4
2 files changed, 11 insertions(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index dbe6005daa..a7375b53a6 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -867,6 +867,13 @@ config VIDEO_LCD_POWER
Set the power enable pin for the LCD panel. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+config VIDEO_LCD_POWER_ACTIVE_LOW
+ bool "LCD panel power enable pin is inverted"
+ depends on VIDEO_SUNXI
+ default n
+ ---help---
+ Set this if the lcd power pin is active low.
+
config VIDEO_LCD_RESET
string "LCD panel reset pin"
depends on VIDEO_SUNXI
diff --git a/drivers/video/sunxi/sunxi_display.c
b/drivers/video/sunxi/sunxi_display.c
index 2ee6212c58..12b542d65b 100644
--- a/drivers/video/sunxi/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c
@@ -588,7 +588,11 @@ static void sunxi_lcdc_panel_enable(void)
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
if (pin >= 0) {
gpio_request(pin, "lcd_power");
+#ifdef CONFIG_VIDEO_LCD_POWER_ACTIVE_LOW
+ gpio_direction_output(pin, 0);
+#else
gpio_direction_output(pin, 1);
+#endif
}
if (reset_pin >= 0)
--
2.34.1
[PATCH 1/2] pwm: sunxi: enable pwm0 support on sun7i
sun7i pwm is equal to sun4i and sun5i so enable pwm0 the same way for sun7i. Signed-off-by: Giulio Benetti --- arch/arm/include/asm/arch-sunxi/pwm.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-sunxi/pwm.h b/arch/arm/include/asm/arch-sunxi/pwm.h index b89bddd2e8..1a1c6e0c54 100644 --- a/arch/arm/include/asm/arch-sunxi/pwm.h +++ b/arch/arm/include/asm/arch-sunxi/pwm.h @@ -26,7 +26,8 @@ #define SUNXI_PWM_PERIOD_80PCT 0x04af03c0 -#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN5I +#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN5I || \ +defined CONFIG_MACH_SUN7I #define SUNXI_PWM_PIN0 SUNXI_GPB(2) #define SUNXI_PWM_MUX SUN4I_GPB_PWM #endif -- 2.34.1
Re: [PATCH v5 3/8] imxrt1050: synchronise device tree with linux
Hi Marcel,
On 07/11/22 22:22, Marcel Ziswiler wrote:
From: Marcel Ziswiler
Synchronise device tree with linux v6.1-rc3.
Note: Nowadays, the intent is for them regular device trees to just be
synchronised from them Linux kernel device trees and any and all U-Boot
specific changes need to go into the -u-boot.dtsi device tree include
files which BTW get included automatically by the U-Boot build system.
Signed-off-by: Marcel Ziswiler
Reviewed-by: Giulio Benetti
and I've tested on the board and both lcd and usb works correctly so:
Tested-by: Giulio Benetti
Thank you for the contribution!
Best regards
--
Giulio Benetti
CEO/CTO@Benetti Engineering sas
---
Changes in v5:
- Add clock-names "per" to lpuart and re-add lcdif and usb* nodes as
pointed out by Giulio.
Changes in v4:
- Use imxrt1050-evk-u-boot.dtsi as provided/tested by Jesse.
- Explain intent in commit message as pointed out by Giulio.
- Re-synched with v6.1-rc3.
Changes in v3:
- Incorporate feedback from Jesse.
Changes in v2:
- imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks!
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 274 ++--
arch/arm/dts/imxrt1050-evk.dts | 257 +++---
arch/arm/dts/imxrt1050-pinfunc.h| 2 +-
arch/arm/dts/imxrt1050.dtsi | 168 +---
include/dt-bindings/clock/imxrt1050-clock.h | 9 +-
5 files changed, 366 insertions(+), 344 deletions(-)
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index 617cece448..e217dfd9eb 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -4,9 +4,18 @@
* Author(s): Giulio Benetti
*/
+#include
+#include "imxrt1050-pinfunc.h"
+
/ {
+ aliases {
+ display0 = &lcdif;
+ usbphy0 = &usbphy1;
+ };
+
chosen {
u-boot,dm-spl;
+ tick-timer = &gpt;
};
clocks {
@@ -15,6 +24,92 @@
soc {
u-boot,dm-spl;
+
+ usbphy1: usbphy@400d9000 {
+ compatible = "fsl,imxrt-usbphy";
+ reg = <0x400d9000 0x1000>;
+ interrupts = ;
+ };
+
+ usbmisc: usbmisc@402e0800 {
+ #index-cells = <1>;
+ compatible = "fsl,imxrt-usbmisc";
+ reg = <0x402e0800 0x200>;
+ clocks = <&clks IMXRT1050_CLK_USBOH3>;
+ };
+
+ usbotg1: usb@402e {
+ compatible = "fsl,imxrt-usb", "fsl,imx27-usb";
+ reg = <0x402e 0x200>;
+ interrupts = ;
+ clocks = <&clks IMXRT1050_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ lcdif: lcdif@402b8000 {
+ compatible = "fsl,imxrt-lcdif";
+ reg = <0x402b8000 0x4000>;
+ interrupts = ;
+ clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>,
+<&clks IMXRT1050_CLK_LCDIF_APB>;
+ clock-names = "pix", "axi";
+ assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
+ assigned-clock-parents = <&clks
IMXRT1050_CLK_PLL5_VIDEO>;
+ status = "disabled";
+ };
+
+ semc: semc@402f {
+ compatible = "fsl,imxrt-semc";
+ reg = <0x402f 0x4000>;
+ clocks = <&clks IMXRT1050_CLK_SEMC>;
+ pinctrl-0 = <&pinctrl_semc>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+ };
+};
+
+&semc {
+ u-boot,dm-spl;
+ /*
+* Memory configuration from sdram datasheet IS42S16160J-6BLI
+*/
+ fsl,sdram-mux = /bits/ 8 ;
+ fsl,sdram-control = /bits/ 8 ;
+ fsl,sdram-timing = /bits/ 8 <0x2
+0x2
+0x9
+0x1
+0x5
+0x6
+
+0x20
+0
Re: [PATCH v4 3/8] imxrt1050: synchronise device tree with linux
Hi Marcel,
On 05/11/22 12:30, Marcel Ziswiler wrote:
From: Marcel Ziswiler
Synchronise device tree with linux v6.1-rc3.
Note: Nowadays, the intent is for them regular device trees to just be
synchronised from them Linux kernel device trees and any and all U-Boot
specific changes need to go into the -u-boot.dtsi device tree include
files which BTW get included automatically by the U-Boot build system.
Signed-off-by: Marcel Ziswiler
---
Changes in v4:
- Use imxrt1050-evk-u-boot.dtsi as provided/tested by Jesse.
- Explain intent in commit message as pointed out by Giulio.
- Re-synched with v6.1-rc3.
Changes in v3:
- Incorporate feedback from Jesse.
Changes in v2:
- imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks!
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 174 +++--
arch/arm/dts/imxrt1050-evk.dts | 257 +++-
arch/arm/dts/imxrt1050-pinfunc.h| 2 +-
arch/arm/dts/imxrt1050.dtsi | 168 ++---
include/dt-bindings/clock/imxrt1050-clock.h | 9 +-
5 files changed, 263 insertions(+), 347 deletions(-)
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index 617cece448..d6eba12576 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -4,9 +4,13 @@
* Author(s): Giulio Benetti
*/
+#include
+#include "imxrt1050-pinfunc.h"
+
/ {
chosen {
u-boot,dm-spl;
+ tick-timer = &gpt;
};
clocks {
@@ -15,6 +19,53 @@
soc {
u-boot,dm-spl;
+ semc: semc@402f {
+ compatible = "fsl,imxrt-semc";
+ reg = <0x402f 0x4000>;
+ clocks = <&clks IMXRT1050_CLK_SEMC>;
+ pinctrl-0 = <&pinctrl_semc>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+ };
+};
+
+&semc {
+ u-boot,dm-spl;
+ /*
+* Memory configuration from sdram datasheet IS42S16160J-6BLI
+*/
+ fsl,sdram-mux = /bits/ 8 ;
+ fsl,sdram-control = /bits/ 8 ;
+ fsl,sdram-timing = /bits/ 8 <0x2
+0x2
+0x9
+0x1
+0x5
+0x6
+
+0x20
+0x09
+0x01
+0x00
+
+0x04
+0x0A
+0x21
+0x50>;
+
+ bank1: bank@0 {
+ fsl,base-address = <0x8000>;
+ fsl,memory-size = ;
+ u-boot,dm-spl;
};
};
@@ -31,60 +82,143 @@
};
&gpio1 {
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
u-boot,dm-spl;
};
&gpio2 {
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
u-boot,dm-spl;
};
&gpio3 {
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
u-boot,dm-spl;
};
&gpio4 {
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
u-boot,dm-spl;
};
&gpio5 {
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
u-boot,dm-spl;
};
-&gpt1 {
+&gpt {
+ clocks = <&osc>;
+ compatible = "fsl,imxrt-gpt";
+ status = "okay";
u-boot,dm-spl;
};
&lpuart1 { /* console */
+ compatible = "fsl,imxrt-lpuart";
As Jesse pointed me privately here you need to add:
clock-names = "per";
to be compatible with lpuart u-boot driver.
With that corrected it boots correctly.
But you also need to re-add the lcdif and usb* nodes here in
-u-boot.dtsi file because lcdif and usb are supported in u-boot but
still not in Linux.
Best regards
--
Giulio Benetti
CEO/CTO@Benetti Engineering sas
u-boot,dm-spl;
};
-&semc {
+&iomuxc {
u-boot,dm-spl;
-
- bank1: bank@0 {
+ compatible = "fsl,imxrt-iomuxc";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+
+ pinctrl_semc: semcgrp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
+ 0xf1/* SEMC_D0 */
+ MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
+ 0xf1/* SEMC_D1 */
+ MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
+ 0xf1/* SEMC_
Re: [PATCH v4 2/8] imxrt1020: migrate to build system included -u-boot.dtsi
Hi Marcel,
On 05/11/22 12:30, Marcel Ziswiler wrote:
From: Marcel Ziswiler
Migrate to using automatic build system included -u-boot.dtsi device
tree include files.
Signed-off-by: Marcel Ziswiler
Reviewed-by: Giulio Benetti
and:
Tested-by: Giulio Benetti
--
Giulio Benetti
CEO/CTO@Benetti Engineering sas
---
Changes in v4:
- Re-named commit subject and re-worded commit message to indicate
migration to automatic build system included -u-boot.dtsi device
tree include files. Thanks to Giulio for pointing this out.
arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 7 ---
arch/arm/dts/imxrt1020-evk.dts | 1 -
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index 9e1b074d2e..7cab486f5f 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -67,9 +67,6 @@
imxrt1020-evk {
u-boot,dm-spl;
- pinctrl_lpuart1: lpuart1grp {
- u-boot,dm-spl;
- };
pinctrl_semc: semcgrp {
u-boot,dm-spl;
@@ -81,6 +78,10 @@
};
};
+&pinctrl_lpuart1 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index 22ae5ed735..d4d1de4ea8 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -6,7 +6,6 @@
/dts-v1/;
#include "imxrt1020.dtsi"
-#include "imxrt1020-evk-u-boot.dtsi"
#include "imxrt1020-pinfunc.h"
/ {
Re: [PATCH v3 3/8] imxrt1050: synchronise device tree with linux
Hi Marcel,
> Il giorno 24 ott 2022, alle ore 00:13, Marcel Ziswiler
> ha scritto:
>
> Hi Giulio
>
>> On Sun, 2022-10-23 at 01:47 +0200, Giulio Benetti wrote:
>> Hi Marcel,
>>
>> Il 22/10/2022 23:42, Marcel Ziswiler ha scritto:
>>> From: Marcel Ziswiler
>>>
>>> Synchronise device tree with linux v6.0-rc1.
>>>
>>> Signed-off-by: Marcel Ziswiler
>>>
>>> ---
>>>
>>> Changes in v3:
>>> - Incorporate feedback from Jesse.
>>>
>>> Changes in v2:
>>> - imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio.
>>> Thanks!
>>>
>>> arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 162 ++--
>>> arch/arm/dts/imxrt1050-evk.dts | 257 +++-
>>> arch/arm/dts/imxrt1050-pinfunc.h| 2 +-
>>> arch/arm/dts/imxrt1050.dtsi | 168 ++---
>>> include/dt-bindings/clock/imxrt1050-clock.h | 9 +-
>>> 5 files changed, 255 insertions(+), 343 deletions(-)
>>>
>>> diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
>>> b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
>>> index 617cece448..bf40ada234 100644
>>> --- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
>>> +++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
>>> @@ -4,8 +4,12 @@
>>>* Author(s): Giulio Benetti
>>>*/
>>>
>>> +#include
>>> +#include "imxrt1050-pinfunc.h"
>>> +
>>> / {
>>> chosen {
>>> + tick-timer = &gpt;
>>> u-boot,dm-spl;
>>> };
>>>
>>> @@ -15,6 +19,52 @@
>>>
>>> soc {
>>> u-boot,dm-spl;
>>> +
>>> + semc@402f {
>>> + compatible = "fsl,imxrt-semc";
>>> + clocks = <&clks IMXRT1050_CLK_SEMC>;
>>> + pinctrl-0 = <&pinctrl_semc>;
>>> + pinctrl-names = "default";
>>> + reg = <0x402f 0x4000>;
>>> + status = "okay";
>>> + u-boot,dm-spl;
>>> +
>>> + /*
>>> +* Memory configuration from sdram datasheet
>>> IS42S16160J-6BLI
>>> +*/
>>> + fsl,sdram-mux = /bits/ 8 >> + MUX_CSX0_SDRAM_CS1
>>> + 0
>>> + 0
>>> + 0
>>> + 0>;
>>> + fsl,sdram-control = /bits/ 8 >> + BL_8
>>> + COL_9BITS
>>> + CL_3>;
>>> + fsl,sdram-timing = /bits/ 8 <0x2
>>> +0x2
>>> +0x9
>>> +0x1
>>> +0x5
>>> +0x6
>>> +
>>> +0x20
>>> +0x09
>>> +0x01
>>> +0x00
>>> +
>>> +0x04
>>> +0x0A
>>> +0x21
>>> +0x50>;
>>> +
>>> + bank1: bank@0 {
>>> + fsl,base-address = <0x8000>;
>>> + fsl,memory-size = ;
>>> + u-boot,dm-spl;
>>> + };
>>> + };
>>> };
>>> };
>>>
>>> @@ -50,41 +100,121 @@
>>> u-boot,dm-spl;
>>> };
>>>
Re: [PATCH v3 2/8] imxrt1020: fix lpuart issue in common u-boot device tree
Hi Marcel,
> Il giorno 24 ott 2022, alle ore 00:01, Marcel Ziswiler
> ha scritto:
>
> Hi Giulio
>
>> On Sun, 2022-10-23 at 01:32 +0200, Giulio Benetti wrote:
>> Hi Marcel,
>>
>> thanks for contributing,
>
> You are very welcome.
>
>> Il 22/10/2022 23:42, Marcel Ziswiler ha scritto:
>>> From: Marcel Ziswiler
>>>
>>> Fix lpuart issue in common U-Boot device tree.
>>
>> There's no need to repeat in commit log the subject.
>
> Well, most maintainers do want an actual commit message and won't accept it
> being empty. For trivial commits
> like this one it is quite common to therefore just repeat the subject.
You’re right, this is project dependent, here in uboot they want it like that.
>
>>> Signed-off-by: Marcel Ziswiler
>>> ---
>>>
>>> (no changes since v1)
>>>
>>> arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 7 ---
>>> arch/arm/dts/imxrt1020-evk.dts | 1 -
>>> 2 files changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
>>> b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
>>> index 9e1b074d2e..7cab486f5f 100644
>>> --- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
>>> +++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
>>> @@ -67,9 +67,6 @@
>>>
>>> imxrt1020-evk {
>>> u-boot,dm-spl;
>>> - pinctrl_lpuart1: lpuart1grp {
>>> - u-boot,dm-spl;
>>> - };
>>>
>>> pinctrl_semc: semcgrp {
>>> u-boot,dm-spl;
>>> @@ -81,6 +78,10 @@
>>> };
>>> };
>>>
>>> +&pinctrl_lpuart1 {
>>> + u-boot,dm-spl;
>>> +};
>>> +
>>
>> I don't understand the goal of this change, can you elaborate?
>
> Well, the goal is to use them Linux kernel device trees and have any required
> changes in such -u-boot.dtsi
> device tree include files. As such we may just reference resp. node by its
> handle and subsequently add that U-
> Boot specific property.
Ah yes and
>
>> As I remember pinctrl_lpuart1 already works correctly. The same goes
>> for:
>> pinctrl_semc
>> pinctrl_usdhc0
>>
>> So you're not fixing something.
>
> Well, I am basically fixing it for when them device trees get synchronised
> from the Linux kernel. One may
> basically consider out-of-synch device trees being an issue in need of fixing.
Yes. Can you please add this explanation in commit log? It’s easier to keep
track and to review too.
>
>>> &usdhc1 {
>>> u-boot,dm-spl;
>>> };
>>> diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
>>> index 22ae5ed735..d4d1de4ea8 100644
>>> --- a/arch/arm/dts/imxrt1020-evk.dts
>>> +++ b/arch/arm/dts/imxrt1020-evk.dts
>>> @@ -6,7 +6,6 @@
>>>
>>> /dts-v1/;
>>> #include "imxrt1020.dtsi"
>>> -#include "imxrt1020-evk-u-boot.dtsi"
>>
>> This ^^^ is needed, please revert it.
>
> No, you do not understand. We just synchronise them device trees from the
> Linux kernel. Nothing should ever be
> changed here. Any and all U-Boot specific changes need to go into the
> -u-boot.dtsi device tree include files
> which BTW get included automatically by the U-Boot build system.
This has been changed during time. Can you please add this note too in commit
log?
>
>>> #include "imxrt1020-pinfunc.h"
>>>
>>> / {
>>
>> Have you also tested the change on a board?
>
> As outlined in the cover letter I did not test each and every board as I do
> not have them all available. If you
> do have some of those boards available I would appreciate you giving it a try.
Yes I do have 1020 so I can give a try of V4.
Best regards
Giulio
>
> Thanks!
>
>> Best regards
>> --
>> Giulio Benetti
>> CEO/CTO@Benetti Engineering sas
>
> Cheers
>
> Marcel
Re: [PATCH v3 3/8] imxrt1050: synchronise device tree with linux
Hi Marcel,
Il 22/10/2022 23:42, Marcel Ziswiler ha scritto:
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
Changes in v3:
- Incorporate feedback from Jesse.
Changes in v2:
- imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks!
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 162 ++--
arch/arm/dts/imxrt1050-evk.dts | 257 +++-
arch/arm/dts/imxrt1050-pinfunc.h| 2 +-
arch/arm/dts/imxrt1050.dtsi | 168 ++---
include/dt-bindings/clock/imxrt1050-clock.h | 9 +-
5 files changed, 255 insertions(+), 343 deletions(-)
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index 617cece448..bf40ada234 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -4,8 +4,12 @@
* Author(s): Giulio Benetti
*/
+#include
+#include "imxrt1050-pinfunc.h"
+
/ {
chosen {
+ tick-timer = &gpt;
u-boot,dm-spl;
};
@@ -15,6 +19,52 @@
soc {
u-boot,dm-spl;
+
+ semc@402f {
+ compatible = "fsl,imxrt-semc";
+ clocks = <&clks IMXRT1050_CLK_SEMC>;
+ pinctrl-0 = <&pinctrl_semc>;
+ pinctrl-names = "default";
+ reg = <0x402f 0x4000>;
+ status = "okay";
+ u-boot,dm-spl;
+
+ /*
+* Memory configuration from sdram datasheet
IS42S16160J-6BLI
+*/
+ fsl,sdram-mux = /bits/ 8 ;
+ fsl,sdram-control = /bits/ 8 ;
+ fsl,sdram-timing = /bits/ 8 <0x2
+0x2
+0x9
+0x1
+0x5
+0x6
+
+0x20
+0x09
+0x01
+0x00
+
+0x04
+0x0A
+0x21
+0x50>;
+
+ bank1: bank@0 {
+ fsl,base-address = <0x8000>;
+ fsl,memory-size = ;
+ u-boot,dm-spl;
+ };
+ };
};
};
@@ -50,41 +100,121 @@
u-boot,dm-spl;
};
-&gpt1 {
+&gpt {
+ clocks = <&osc>;
+ compatible = "fsl,imxrt-gpt";
+ status = "okay";
u-boot,dm-spl;
};
&lpuart1 { /* console */
+ compatible = "fsl,imxrt-lpuart";
u-boot,dm-spl;
};
-&semc {
- u-boot,dm-spl;
-
- bank1: bank@0 {
- u-boot,dm-spl;
- };
-};
-
&iomuxc {
u-boot,dm-spl;
imxrt1050-evk {
u-boot,dm-spl;
- pinctrl_lpuart1: lpuart1grp {
- u-boot,dm-spl;
- };
pinctrl_semc: semcgrp {
- u-boot,dm-spl;
- };
-
- pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
+ 0xf1/* SEMC_D0 */
+ MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
+ 0xf1/* SEMC_D1 */
+ MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
+ 0xf1/* SEMC_D2 */
+ MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
+ 0xf1/* SEMC_D3 */
+ MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
+ 0xf1/* SEMC_D4 */
+ MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
+ 0xf1/* SEMC_D5 */
+ MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
+ 0xf1/* SEMC_D6 */
+ MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
+ 0xf1/* SEMC_D7 */
+ MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
+ 0xf1
Re: [PATCH v3 2/8] imxrt1020: fix lpuart issue in common u-boot device tree
Hi Marcel,
thanks for contributing,
Il 22/10/2022 23:42, Marcel Ziswiler ha scritto:
From: Marcel Ziswiler
Fix lpuart issue in common U-Boot device tree.
There's no need to repeat in commit log the subject.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 7 ---
arch/arm/dts/imxrt1020-evk.dts | 1 -
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index 9e1b074d2e..7cab486f5f 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -67,9 +67,6 @@
imxrt1020-evk {
u-boot,dm-spl;
- pinctrl_lpuart1: lpuart1grp {
- u-boot,dm-spl;
- };
pinctrl_semc: semcgrp {
u-boot,dm-spl;
@@ -81,6 +78,10 @@
};
};
+&pinctrl_lpuart1 {
+ u-boot,dm-spl;
+};
+
I don't understand the goal of this change, can you elaborate?
As I remember pinctrl_lpuart1 already works correctly. The same goes
for:
pinctrl_semc
pinctrl_usdhc0
So you're not fixing something.
&usdhc1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index 22ae5ed735..d4d1de4ea8 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -6,7 +6,6 @@
/dts-v1/;
#include "imxrt1020.dtsi"
-#include "imxrt1020-evk-u-boot.dtsi"
This ^^^ is needed, please revert it.
#include "imxrt1020-pinfunc.h"
/ {
Have you also tested the change on a board?
Best regards
--
Giulio Benetti
CEO/CTO@Benetti Engineering sas
Re: Wolfgang Denk
On 21/10/22 17:11, Stefano Babic wrote: Dear U-Boot community, it is my very sad duty to inform you that Wolfgang Denk, the father of U-Boot, passed away last week. We have lost a great developer and a very good friend. I met Wolfgang the first time quite 25 years ago, when we worked for the same company. I was hired as consultant for a (at the time very frequently used) RTOS. I had no time to introduce me, because Wolfgang interrupted me with : "Just install Linux !". Well, of course I did. It was the first good suggestion he gave me. Many others followed. Wolfgang was a pioneer and strong supporter of Open Source, in the time when Linux for Embedded System started its first steps. In many occasions he had strong discussions with customers to explain the advantages of Open Source, and he rejected business contracts if customer was going against his principles. We will miss him. Rest in peace, my friend Stefano Babic I'm very sorry, rest in peace Wolfgang Denk and thank you for what you have created. -- Giulio Benetti Benetti Engineering sas
Re: [PATCH 6/6] sunxi: add CherryPi-F1C200s support
Hi Andre,
On 18/10/22 16:01, Andre Przywara wrote:
On Fri, 14 Oct 2022 01:04:18 -0400
Jesse Taube wrote:
Hi Jesse, Giulio,
thanks for having a look and for the testing!
You're welcome:
Tested-by: Giulio Benetti
Best regards
--
Giulio Benetti
CEO/CTO@Benetti Engineering sas
On 10/13/22 05:53, Andre Przywara wrote:
On 13/10/2022 09:33, Clément Péron wrote:
Hi Clément,
On Wed, 12 Oct 2022 at 18:35, Andre Przywara wrote:
The CherryPi F1C200s board is a small development board, featuring the
F1C200s with 64MB of co-packaged DRAM. It comes with two USB-C sockets,
of which one is connected to a USB-UART chip, that provides easy access
to UART1.
A similar board is trying to been upstreamed by Icenowy:
see : https://lore.kernel.org/lkml/20221012055602.1544944-11-...@icenowy.me/
[PATCH v2 10/10] ARM: dts: suniv: add device tree for PopStick v1.1
Maybe we should take into account the remarks that Krzysztof Kozlowski
made to follow the same device-tree rules on U-boot.
Yeah, thanks for the heads up, I saw that. I just wanted to post this to
demonstrate what needs to be done. I will be sending a Linux DT patch
anyway, since DTs need to go via Linux anyway.
Thanks,
Andre
Regards,
Clement
Beside the usual micro-SD card slot, the board comes with a SPI NAND
flash chip, which is not yet supported.
Signed-off-by: Andre Przywara
---
.../dts/suniv-f1c100s-cherrypi-f1c200s.dts| 45 +++
configs/cherrypi_f1c200s_defconfig| 11 +
2 files changed, 56 insertions(+)
create mode 100644 arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts
create mode 100644 configs/cherrypi_f1c200s_defconfig
diff --git a/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts
b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts
new file mode 100644
index 000..f0ebcb6d893
--- /dev/null
+++ b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2022 Arm Ltd.
+ * based on another DT, which is:
+ * Copyright 2018 Icenowy Zheng
Her email changed IDK if it is proper to change here.
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+/ {
+ model = "Cherry Pi F1C200s";
+ compatible = "lctech,cherrypi-f1c200s", "allwinner,suniv-f1c100s";
+
+ aliases {
+ mmc0 = &mmc0;
+ serial0 = &uart1;
+ spi0 = &spi0;
no need for spi.
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ disable-wp;
+ status = "okay";
+ vmmc-supply = <®_vcc3v3>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pa_pins>;
+ status = "okay";
+};
diff --git a/configs/cherrypi_f1c200s_defconfig
b/configs/cherrypi_f1c200s_defconfig
new file mode 100644
index 000..306d363f485
--- /dev/null
+++ b/configs/cherrypi_f1c200s_defconfig
@@ -0,0 +1,11 @@
+CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-cherrypi-f1c200s"
+CONFIG_SPL=y
+CONFIG_MACH_SUNIV=y
+CONFIG_DRAM_CLK=156
+CONFIG_DRAM_ZQ=0
You need
+CONFIG_SPL_STACK=0x8000
I posted "[PATCH 1/2] sunxi: Kconfig: use SoC-wide values for some symbols"
(https://lore.kernel.org/u-boot/20220913234335.24902-2-andre.przyw...@arm.com/)
that solves that issue.
That patch is applied before this series in the tree, so no change should
be needed.
Thanks for the report!
Cheers,
Andre
I will test this on both 100s and 200s.
Thanks,
Jesse Taube
+CONFIG_SUNXI_MINIMUM_DRAM_MB=64
+# CONFIG_VIDEO_SUNXI is not set
+CONFIG_CONS_INDEX=2
--
2.25.1
Re: [PATCH v2 8/8] ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig
Hi Fabio, Jesse, On 18/06/22 02:43, Fabio Estevam wrote: Hi Jesse, On Fri, Jun 17, 2022 at 1:42 PM Jesse Taube wrote: Add a base defconfig for the i.MXRT1170 This should be part of the patch that adds support for the board (1/8). +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y Any reason to turn off DCACHE? This is due to missing DCACHE function mmu_set_region_dcache_behaviour() there is only an empty stub for it and so in the case of i.MXRT1050 when using mxsfb.c, that calls that function, I've preferred to disable until one day I had time to make it work correctly, but I have no time. Best regards -- Giulio Benetti CTO/CEO@Benetti Engineering sas
Re: [PATCH] drivers/adc/rockchip-saradc: remove double semi-colon
On 14/03/22 09:04, Kever Yang wrote: Hi Giulio, Thanks for your patch, it's a good catching. Could you please update the subject with "rockchip: adc: ", and add a simple description in the commit message? Empy commit message is not allowed according to U-Boot patch commit rules :( Oh, I've forgotten about this in u-boot. Just sent V2: https://patchwork.ozlabs.org/project/uboot/patch/20220314090943.821630-1-giulio.bene...@benettiengineering.com/ and tagged V1 as superseded in patchwork. Best regards -- Giulio Benetti Benetti Engineering sas Thanks, - Kever Giulio Benetti 于2022年2月4日周五 09:19写道： Signed-off-by: Giulio Benetti --- drivers/adc/rockchip-saradc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index e464d33f22..e0cbab6aa0 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -131,7 +131,7 @@ int rockchip_saradc_of_to_plat(struct udevice *dev) } priv->data = data; - uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;; + uc_pdata->data_mask = (1 << priv->data->num_bits) - 1; uc_pdata->data_format = ADC_DATA_FORMAT_BIN; uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5; uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1; -- 2.25.1
[PATCH v2] rockchip: saradc: remove double semi-colon
Remove double semi-colon that has been forgotten while adding the driver. This is only a style fix since it doesn't change the functionality of the driver. Signed-off-by: Giulio Benetti --- V1->V2: * Improved commit log as suggested by Kever Yang --- drivers/adc/rockchip-saradc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index e464d33f22..e0cbab6aa0 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -131,7 +131,7 @@ int rockchip_saradc_of_to_plat(struct udevice *dev) } priv->data = data; - uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;; + uc_pdata->data_mask = (1 << priv->data->num_bits) - 1; uc_pdata->data_format = ADC_DATA_FORMAT_BIN; uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5; uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1; -- 2.25.1
Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
Hi Stanley, > Il giorno 11 mar 2022, alle ore 03:13, Stanley Chu > ha scritto: > > Hi Tom, > We need time to prepare linux dts, can I send the rest of the drivers > first or need to wait until the linux dts is submitted? > Because I want to remove some unused nodes/properties away from linux > dts to reduce dtb size, can we use different dts for uboot? You can add a specific -uboot.dtsi file where you tag every node to be or not to be part of final uboot .dtb This way the original .dts file will be synced with Linux, except the -uboot.dtsi inclusion. Take a look at upstreamed .dts files and look for uboot.dtsi suffix files. Best regards —- Giulio Benetti Benetti Engineering sas > Thanks a lot for your comments. > > -- > Stanley > >> On Fri, Mar 11, 2022 at 2:49 AM Tom Rini wrote: >> >>> On Wed, Dec 15, 2021 at 10:57:52AM +0800, Stanley Chu wrote: >>> >>> Add basic support for the Nuvoton NPCM845 BMC. >>> >>> Signed-off-by: Stanley Chu >> >> I see there's a number of outstanding questions to this first part of >> the port. Can you please address them? Furthermore, the defconfig and >> dts patches should be part of this first patch and the dts needs to be >> in linux-next at least, if not a full linux kernel release. Thanks and >> sorry for the delay here. >> >> -- >> Tom
Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
On 11/03/22 02:06, Giulio Benetti wrote: Hi Stanley, On 11/03/22 01:50, Stanley Chu wrote: Hi Giulio, Thank you for your comment, I've submitted a clk driver patch to address this. https://patchwork.ozlabs.org/project/uboot/patch/20220225075954.3965-1-ys...@nuvoton.com/ Good to see that! But I think you should submit the entire patchset: https://patchwork.ozlabs.org/project/uboot/list/?series=276836&state=%2A&archive=both including this patch as V2. Otherwise it's difficult to test it. As you see in Patchwork you have superseded and changes requested on other patches. So you should modify them accordingly and send V2 series. If other patches have been applied then send only the ones not applied. But as I can see here they are still not applied. Ah, forgotten to mention, please add me and other people involved in reviewing in Cc for V2. Thank you! Best regards -- Giulio Benetti Benetti Engineering sas
Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
Hi Stanley, On 11/03/22 01:50, Stanley Chu wrote: Hi Giulio, Thank you for your comment, I've submitted a clk driver patch to address this. https://patchwork.ozlabs.org/project/uboot/patch/20220225075954.3965-1-ys...@nuvoton.com/ Good to see that! But I think you should submit the entire patchset: https://patchwork.ozlabs.org/project/uboot/list/?series=276836&state=%2A&archive=both including this patch as V2. Otherwise it's difficult to test it. As you see in Patchwork you have superseded and changes requested on other patches. So you should modify them accordingly and send V2 series. If other patches have been applied then send only the ones not applied. But as I can see here they are still not applied. Kind regards -- Giulio Benetti Benetti Engineering sas -- Stanley On Wed, Dec 15, 2021 at 8:12 PM Giulio Benetti wrote: Hi Stanley, On 15/12/21 03:57, Stanley Chu wrote: Add basic support for the Nuvoton NPCM845 BMC. Signed-off-by: Stanley Chu --- arch/arm/Kconfig | 9 + arch/arm/Makefile | 1 + arch/arm/include/asm/arch-npcm8xx/clock.h | 164 arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++ arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++ arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 + arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++ arch/arm/mach-nuvoton/Kconfig | 24 ++ arch/arm/mach-nuvoton/Makefile| 1 + arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++ arch/arm/mach-nuvoton/npcm8xx/Makefile| 1 + arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 Here ^^^ you setup timer, but it should be a separate driver IMHO. At least this is what I've done for imxrt. Same goes for clock, there is no clock driver and you setup spi clock directly inside the same file with npcm_sysintf_init() while that should be part of the clock driver. Also all defines regarding to clocks and peripherals should go into their driver. arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 Here you've mixed up the architecture(above) and the board(below) in a single patch. board/nuvoton/arbel/Kconfig | 18 ++ board/nuvoton/arbel/Makefile | 1 + board/nuvoton/arbel/arbel.c | 33 +++ include/configs/arbel.h | 54 arbel should be arbel-evk I stop here, because there could be big changes if others agree. Best regards -- Giulio Benetti Benetti Engineering sas 17 files changed, 924 insertions(+) create mode 100644 arch/arm/include/asm/arch-npcm8xx/clock.h create mode 100644 arch/arm/include/asm/arch-npcm8xx/espi.h create mode 100644 arch/arm/include/asm/arch-npcm8xx/gcr.h create mode 100644 arch/arm/include/asm/arch-npcm8xx/gpio.h create mode 100644 arch/arm/include/asm/arch-npcm8xx/rst.h create mode 100644 arch/arm/mach-nuvoton/Kconfig create mode 100644 arch/arm/mach-nuvoton/Makefile create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Kconfig create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Makefile create mode 100644 arch/arm/mach-nuvoton/npcm8xx/cpu.c create mode 100644 arch/arm/mach-nuvoton/npcm8xx/reset.c create mode 100644 board/nuvoton/arbel/Kconfig create mode 100644 board/nuvoton/arbel/Makefile create mode 100644 board/nuvoton/arbel/arbel.c create mode 100644 include/configs/arbel.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f7f03837fe..80ec42f6be 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1952,6 +1952,13 @@ config TARGET_XENGUEST_ARM64 select LINUX_KERNEL_IMAGE_HEADER select XEN_SERIAL select SSCANF + +config ARCH_NPCM + bool "Support Nuvoton SoCs" + select DM + select OF_CONTROL + imply CMD_DM + endchoice config SUPPORT_PASSING_ATAGS @@ -2150,6 +2157,8 @@ source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-nexell/Kconfig" +source "arch/arm/mach-nuvoton/Kconfig" + source "board/armltd/total_compute/Kconfig" source "board/bosch/shc/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ad757e982e..29a0250ab6 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -92,6 +92,7 @@ machine-$(CONFIG_ARCH_VERSAL) += versal machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp machine-$(CONFIG_ARCH_ZYNQMP_R5)+= zynqmp-r5 +machine-$(CONFIG_ARCH_NPCM) += nuvoton machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) diff --git a/arch/arm/include/asm/arch-npcm8xx/clock.h b/arch/arm/include/asm/arch-npcm8xx/clock.h new file mode 100644 index 00..088b536b7b --- /dev/null +++ b/arch/arm/include/asm/arch-npcm8xx/clock.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2021 Nuvoton Technology Corp. + */ + +#
[PATCH] drivers/adc/rockchip-saradc: remove double semi-colon
Signed-off-by: Giulio Benetti --- drivers/adc/rockchip-saradc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index e464d33f22..e0cbab6aa0 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -131,7 +131,7 @@ int rockchip_saradc_of_to_plat(struct udevice *dev) } priv->data = data; - uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;; + uc_pdata->data_mask = (1 << priv->data->num_bits) - 1; uc_pdata->data_format = ADC_DATA_FORMAT_BIN; uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5; uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1; -- 2.25.1
Re: Please test U-Boot Allwinner F1C100s support
Hi Andre, Jesse, All, On 31/01/22 19:13, Jesse Taube wrote: On 1/31/22 08:07, Giulio Benetti wrote: Hi Andre, Il giorno 31 gen 2022, alle ore 13:57, Andre Przywara ha scritto: On Mon, 31 Jan 2022 13:17:52 +0100 Giulio Benetti wrote: Hi All, I've tried several times on both F1C100s and F1C200s, maybe I'm doing something wrong but it doesn't work :-/ I burn sd-card with: # sudo dd if=u-boot-sunxi-with-spl.bin of=/dev/sdb bs=1k seek=8 I've triple-checked that the file has been written there by dumping the sd-card and I see it's written at 0x2000, so 8K offset, like the mangoPI image for example. But no uart output. I haven't looked in detail what would be needed for the SPL part of the MMC driver to really work, I just checked that the base addresses are correct, the pinmux looked alright as well. The DT nodes are not needed for the SPL, and I don't see other changes related to MMC in the original series? Yes that’s true. Do you see UART output from the SPL, or nothing at all? Unfortunately nothing either with SPL And you are not using UART0 on the PortF pins, so multiplexed with the MMC, I guess? I use PE0 and PE1 Uart0 according to dts. Have you got such board to test it? Or we can wait for Jesse or George. I’ve used the git you’ve pointed. Anyway I think we’re very close to have it working. At least my work “behind the scenes” will be worth, right Jesse :-)? Yes, I'm sorry there wasn't much mention of you on this patch. I Just woke up, sorry i couldn't be here earlier, I'll take a look with Giulio. I've tested succesfully on both F1C100s and 200s boards! https://source.denx.de/u-boot/custodians/u-boot-sunxi/-/tree/f1c100s I've realized with Jesse that here with me I have 3 USB->Serial converter broken!!! With the 4th it worked and I've checked with scope that was hidden by garbage on my desk :-) So it works! Sorry for the noise Kind regards -- Giulio Benetti Benetti Engineering sas
Re: Please test U-Boot Allwinner F1C100s support
Hi Andre, On 31/01/22 14:57, Andre Przywara wrote: On Mon, 31 Jan 2022 14:07:54 +0100 Giulio Benetti wrote: Hi Giulio, Il giorno 31 gen 2022, alle ore 13:57, Andre Przywara ha scritto: On Mon, 31 Jan 2022 13:17:52 +0100 Giulio Benetti wrote: Hi All, I've tried several times on both F1C100s and F1C200s, maybe I'm doing something wrong but it doesn't work :-/ I burn sd-card with: # sudo dd if=u-boot-sunxi-with-spl.bin of=/dev/sdb bs=1k seek=8 I've triple-checked that the file has been written there by dumping the sd-card and I see it's written at 0x2000, so 8K offset, like the mangoPI image for example. But no uart output. I haven't looked in detail what would be needed for the SPL part of the MMC driver to really work, I just checked that the base addresses are correct, the pinmux looked alright as well. The DT nodes are not needed for the SPL, and I don't see other changes related to MMC in the original series? Yes that’s true. Do you see UART output from the SPL, or nothing at all? Unfortunately nothing either with SPL That is interesting. If there would be a problem with the MMC code, you should at least see the SPL banner, and then see it failing loading U-Boot proper. Yes I take it FEL boot works? Yes, it does work on both F1C100s and 200s boards :-/ Maybe we miss something with the clock setup that the BROM does for us during FEL operation? Yes, it sounds like that, it's a classic Can you try to clear the area between the end of the SPL and the beginning of the U-Boot proper image (dd if=/dev/zero of=/dev/sdX bs=1k seek=32 count=8)? I've zeroed the first 32MB of sd-card now, so we're sure nothing can interfere. # sudo dd if=/dev/zero of=/dev/sda bs=1M count=32 # sync # sudo dd if=u-boot-sunxi-with-spl.bin of=/dev/sda bs=1k seek=8 # sync (/dev/sda is my sd-card for real since I have m.2 ssd) Does any other branch work with SD card booting? Can you check the SPL size in there (with hexdump -C u-boot-sunxi-with-spl.bin | head, check for the halfword at 0x10)? This is the result of the command: ``` 16 00 00 ea 65 47 4f 4e 2e 42 54 30 64 04 71 7c |eGON.BT0d.q|| 0010 00 60 00 00 53 50 4c 02 00 00 00 00 00 00 00 00 |.`..SPL.| 0020 2c 00 00 00 00 00 00 00 00 00 00 00 73 75 6e 69 |,...suni| 0030 76 2d 66 31 63 31 30 30 73 2d 6c 69 63 68 65 65 |v-f1c100s-lichee| 0040 70 69 2d 6e 61 6e 6f 00 00 00 00 00 00 00 00 00 |pi-nano.| 0050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 || 0060 0f 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 || 0070 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 || 0080 a0 00 00 00 a0 00 00 00 a0 00 00 00 a0 00 00 00 || 0090 a0 00 00 00 a0 00 00 00 a0 00 00 00 ef be ad de || ``` And you are not using UART0 on the PortF pins, so multiplexed with the MMC, I guess? I use PE0 and PE1 Uart0 according to dts. Have you got such board to test it? That's the problem: I am driving blindfolded, because I don't have hardware :-( Yeah, but I've read you've ordered it! :-) Jesse has it working so maybe he can check how clocks are setup after BROM using u-boot itself. I've never understood why Allwinner/Rockchip place jtag on the sd-card pins. I really hate it, it would take so few with free jtag pins to check this :-/ Ciao :-) -- Giulio Benetti Benetti Engineering sas Cheers, Andre Or we can wait for Jesse or George. I’ve used the git you’ve pointed. Anyway I think we’re very close to have it working. At least my work “behind the scenes” will be worth, right Jesse :-)? Best regards —- Giulio Benetti Benetti Engineering sas Cheers, Andre Am I doing something wrong? Best regards
Re: Please test U-Boot Allwinner F1C100s support
Hi Andre, > Il giorno 31 gen 2022, alle ore 13:57, Andre Przywara > ha scritto: > > On Mon, 31 Jan 2022 13:17:52 +0100 > Giulio Benetti wrote: > >> Hi All, >> >> I've tried several times on both F1C100s and F1C200s, maybe I'm doing >> something wrong but it doesn't work :-/ >> >> I burn sd-card with: >> # sudo dd if=u-boot-sunxi-with-spl.bin of=/dev/sdb bs=1k seek=8 >> >> I've triple-checked that the file has been written there by dumping the >> sd-card and I see it's written at 0x2000, so 8K offset, like the mangoPI >> image for example. But no uart output. > > I haven't looked in detail what would be needed for the SPL part of the > MMC driver to really work, I just checked that the base addresses are > correct, the pinmux looked alright as well. > The DT nodes are not needed for the SPL, and I don't see other changes > related to MMC in the original series? Yes that’s true. > Do you see UART output from the SPL, or nothing at all? Unfortunately nothing either with SPL > And you are not using UART0 on the PortF pins, so multiplexed with the > MMC, I guess? I use PE0 and PE1 Uart0 according to dts. Have you got such board to test it? Or we can wait for Jesse or George. I’ve used the git you’ve pointed. Anyway I think we’re very close to have it working. At least my work “behind the scenes” will be worth, right Jesse :-)? Best regards —- Giulio Benetti Benetti Engineering sas > > Cheers, > Andre > > > >> >> Am I doing something wrong? >> >> Best regards >
Re: Please test U-Boot Allwinner F1C100s support
Hi All, I've tried several times on both F1C100s and F1C200s, maybe I'm doing something wrong but it doesn't work :-/ I burn sd-card with: # sudo dd if=u-boot-sunxi-with-spl.bin of=/dev/sdb bs=1k seek=8 I've triple-checked that the file has been written there by dumping the sd-card and I see it's written at 0x2000, so 8K offset, like the mangoPI image for example. But no uart output. Am I doing something wrong? Best regards -- Giulio Benetti Benetti Engineering sas On 31/01/22 11:47, Giulio Benetti wrote: Hi Andre and Jesse, I test it today on both F1C100s and F1C200s! Lichee Pi Nano and the Jesse’s board with F1C200s. Best regards —- Giulio Benetti Benetti Engineering sas Il giorno 31 gen 2022, alle ore 03:12, Jesse Taube ha scritto: On 1/30/22 21:04, Andre Przywara wrote: Hi, thanks to the tireless work of Jesse, I think the basic Allwinner F1C100s support for mainline U-Boot is now ready to be merged. Since I don't have the hardware, can any of you who have boards please give it a try on their hardware? I would really love to see some confirmations before I merge it. I really have to thank you for reviewing! I put a branch here: https://source.denx.de/u-boot/custodians/u-boot-sunxi/-/tree/f1c100s This should probably work on any F1C100s board, using the LicheePi Nano defconfig. Also curious about the F1C200s (looking at you, George ;-) I have tested on both. Giulio has them aswell now. This is very basic support at this point, there is no USB or SPI support, and even the SD card is not usable from U-Boot proper. Sd card will work if we add it to the dts. I am hopeful we can add MMC and SPI support still in this cycle, but I don't want to hold back this series any longer, and it should be relatively simple support patches. I have patches for both spi-boot and U-Boot proper spi suport. I did manage to get it to find the boot device with: `u32 brom_call = *(u32*)(fel_stash.sp-4);` in mach-sunxi/board.c with the suggestion that Stephen said. Should I submit after it gets into master or is tomorrow fine. Many thanks, Jesse Taube What should work though is booting via FEL and from SD card (the SPL MMC code is in place, if I am not mistaken). Just booting it to a U-Boot prompt via both methods would be a great test already. Maybe you can even upload a kernel and initrd via FEL and boot it from there, using $fdtcontroladdr for the DT address, for instance. Any replies would be highly appreciated! Many thanks, Andre
Re: Please test U-Boot Allwinner F1C100s support
Hi Andre and Jesse, I test it today on both F1C100s and F1C200s! Lichee Pi Nano and the Jesse’s board with F1C200s. Best regards —- Giulio Benetti Benetti Engineering sas > Il giorno 31 gen 2022, alle ore 03:12, Jesse Taube > ha scritto: > > > >> On 1/30/22 21:04, Andre Przywara wrote: >> Hi, >> thanks to the tireless work of Jesse, I think the basic Allwinner >> F1C100s support for mainline U-Boot is now ready to be merged. Since I >> don't have the hardware, can any of you who have boards please give it a >> try on their hardware? I would really love to see some confirmations >> before I merge it. > > I really have to thank you for reviewing! > >> I put a branch here: >> https://source.denx.de/u-boot/custodians/u-boot-sunxi/-/tree/f1c100s >> This should probably work on any F1C100s board, using the LicheePi Nano >> defconfig. Also curious about the F1C200s (looking at you, George ;-) > > I have tested on both. Giulio has them aswell now. > >> This is very basic support at this point, there is no USB or SPI >> support, and even the SD card is not usable from U-Boot proper. > > Sd card will work if we add it to the dts. > >> I am hopeful we can add MMC and SPI support still in this cycle, but I don't >> want to hold back this series any longer, and it should be relatively >> simple support patches. > > I have patches for both spi-boot and U-Boot proper spi suport. > I did manage to get it to find the boot device with: > `u32 brom_call = *(u32*)(fel_stash.sp-4);` in mach-sunxi/board.c with the > suggestion that Stephen said. Should I submit after it gets into master or is > tomorrow fine. > > Many thanks, >Jesse Taube >> What should work though is booting via FEL and from SD card (the SPL >> MMC code is in place, if I am not mistaken). Just booting it to a U-Boot >> prompt via both methods would be a great test already. Maybe you can >> even upload a kernel and initrd via FEL and boot it from there, using >> $fdtcontroladdr for the DT address, for instance. >> Any replies would be highly appreciated! >> Many thanks, >> Andre
Re: [PATCH 1/2] clk: imx: select [SPL_]CLK_COMPOSITE_CCF for imxrt10{20|50}
Hi Heiko, > Il giorno 30 gen 2022, alle ore 07:38, Heiko Thiery > ha scritto: > > The clock composite is required when using the clock framework. So > select it automatically. > > Signed-off-by: Heiko Thiery Thank you Reviewed-by: Giulio Benetti Best regards —- Giulio Benetti Benetti Engineering sas > --- > drivers/clk/imx/Kconfig | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig > index a2cd0347c3..cdd348020b 100644 > --- a/drivers/clk/imx/Kconfig > +++ b/drivers/clk/imx/Kconfig > @@ -76,6 +76,7 @@ config SPL_CLK_IMXRT1020 >depends on ARCH_IMXRT && SPL >select SPL_CLK >select SPL_CLK_CCF > +select SPL_CLK_COMPOSITE_CCF >help > This enables SPL DM/DTS support for clock driver in i.MXRT1020 > > @@ -84,6 +85,7 @@ config CLK_IMXRT1020 >depends on ARCH_IMXRT >select CLK >select CLK_CCF > +select CLK_COMPOSITE_CCF >help > This enables support clock driver for i.MXRT1020 platforms. > > @@ -92,6 +94,7 @@ config SPL_CLK_IMXRT1050 >depends on ARCH_IMXRT && SPL >select SPL_CLK >select SPL_CLK_CCF > +select SPL_CLK_COMPOSITE_CCF >help > This enables SPL DM/DTS support for clock driver in i.MXRT1050 > > @@ -100,5 +103,6 @@ config CLK_IMXRT1050 >depends on ARCH_IMXRT >select CLK >select CLK_CCF > +select CLK_COMPOSITE_CCF >help > This enables support clock driver for i.MXRT1050 platforms. > -- > 2.30.2 >
Re: [PATCH 2/2] configs/*imxrt10*: remove [SPL_]CLK_COMPOSITE_CCF
Hi Heiko,
> Il giorno 30 gen 2022, alle ore 07:39, Heiko Thiery
> ha scritto:
>
> This option is selected implicitly when [SPL_]CLK_IMXRT10{20|50} is selected.
>
> Signed-off-by: Heiko Thiery
Thank you
Reviewed-by: Giulio Benetti
Best regards
—-
Giulio Benetti
Benetti Engineering sas
> ---
> configs/imxrt1020-evk_defconfig | 2 --
> configs/imxrt1050-evk_defconfig | 2 --
> 2 files changed, 4 deletions(-)
>
> diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig
> index 22cb5cbea7..dafa4a505a 100644
> --- a/configs/imxrt1020-evk_defconfig
> +++ b/configs/imxrt1020-evk_defconfig
> @@ -45,8 +45,6 @@ CONFIG_TFTP_BLOCKSIZE=512
> CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> # CONFIG_OF_TRANSLATE is not set
> -CONFIG_SPL_CLK_COMPOSITE_CCF=y
> -CONFIG_CLK_COMPOSITE_CCF=y
> CONFIG_SPL_CLK_IMXRT1020=y
> CONFIG_CLK_IMXRT1020=y
> # CONFIG_SPL_DM_GPIO is not set
> diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
> index 044b984f14..09dcc9e6e3 100644
> --- a/configs/imxrt1050-evk_defconfig
> +++ b/configs/imxrt1050-evk_defconfig
> @@ -49,8 +49,6 @@ CONFIG_TFTP_BLOCKSIZE=512
> CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> # CONFIG_OF_TRANSLATE is not set
> -CONFIG_SPL_CLK_COMPOSITE_CCF=y
> -CONFIG_CLK_COMPOSITE_CCF=y
> CONFIG_SPL_CLK_IMXRT1050=y
> CONFIG_CLK_IMXRT1050=y
> # CONFIG_SPL_DM_GPIO is not set
> --
> 2.30.2
>
Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
On 29/01/22 22:19, Jesse Taube wrote:
On 1/29/22 16:05, Jesse Taube wrote:
On 1/29/22 15:59, Samuel Holland wrote:
On 1/29/22 5:51 AM, Andre Przywara wrote:
On Fri, 28 Jan 2022 22:21:28 -0500
Jesse Taube wrote:
On 1/26/22 09:38, Jesse Taube wrote:
On 1/26/22 09:13, Andre Przywara wrote:
On Tue, 4 Jan 2022 19:35:06 -0500
Jesse Taube wrote:
u32 spl_boot_device(void)
{
return sunxi_get_boot_device();
}
+#else
+/*
+ * suniv BROM do not pass the boot media type to SPL, so we try with the
+ * boot sequence in BROM: mmc0->spinor->fail.
+ */
+void board_boot_order(u32 *spl_boot_list)
+{
+ /*
+* See the comments above in sunxi_get_boot_device() for information
+* about FEL boot.
+*/
+ if (!is_boot0_magic(SPL_ADDR + 4)) {
+ spl_boot_list[0] = BOOT_DEVICE_BOARD;
+ return;
+ }
+
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
So does that mean that it tries MMC first, even when booted via SPI? So if
there is a *non*-bootable microSD card in, it will read something from
sector 80, and will execute that if this is a FIT or legacy image?
yes
Uh sorry to bother you again but I cant seem to find a way to find where
the bootrom got the spl. I could check other periphirals like pinmux. I
could also just have it configured at build. Are both these options
okay? I will try to find a way to find the boot device at runtime first.
Don't bother for this version, it's fine as it is now, we can refine
this later. It's only a problem if there is a non-valid SPL, but a
valid U-Boot proper legacy image on the SD card.
I don't want to have a build time option, we try to keep a single image
for all boot sources.
So eventually I'd prefer the pinmux/clock check, since that's cheaper.
The alternative would be to read the SPL (again), check for a valid
header and verify the checksum. You can look at this for inspiration:
https://patchwork.ozlabs.org/project/uboot/patch/20210712100651.6912-3-andre.przyw...@arm.com/
I checked the boot ROM code (thanks Jesse!), and indeed it does not report where
it loaded SPL from, or make any other changes to the loaded eGON image. The boot
ROM also completely cleans up its clock and pinctrl changes, regardless of the
success/failure of a specific boot device.
There's a function which loads some value to r2, but that gets called before the
"load eGON from storage" functions, so r2 will be clobbered.
So as far as I can tell, the only way to determine the boot device, other than
reimplementing the BROM in SPL, is to look at the return address on the top of
the BROM's stack. These are the possible values (in order of execution):
0x40f8: mmc0
0x4114: spi0 NAND
0x4130: spi0 NOR
0x4150: mmc1
If i save it in save_boot_params it does change when in a different boot
device. Ill look into it more.
the sp is also a good idea.
Sry Im just dumb. it does change but it is because it doesn't clean the
registers.
Thanks sam, looking at the stack is the best option.
I've been too late :-)
So happy assembly coding Jesse!
Best regards
--
Giulio Benetti
Benetti Engineering sas
Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
default "sun5i" if MACH_SUN5I >>>>>>default "sun6i" if MACH_SUN6I >>>>>> @@ -805,7 +814,7 @@ config VIDEO_SUNXI >>>>>>config VIDEO_HDMI >>>>>>bool "HDMI output support" >>>>>> -depends on VIDEO_SUNXI && !MACH_SUN8I >>>>>> +depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV >>>>>>default y >>>>>>---help--- >>>>>>Say Y here to add support for outputting video over HDMI. >>>>>> @@ -1005,6 +1014,7 @@ config GMAC_TX_DELAY >>>>>>Set the GMAC Transmit Clock Delay Chain value. >>>>>>config SPL_STACK_R_ADDR >>>>>> +default 0x81e0 if MACH_SUNIV >>>>>>default 0x4fe0 if MACH_SUN4I >>>>>>default 0x4fe0 if MACH_SUN5I >>>>>>default 0x4fe0 if MACH_SUN6I >>>>>> @@ -1016,7 +1026,7 @@ config SPL_STACK_R_ADDR >>>>>>config SPL_SPI_SUNXI >>>>>>bool "Support for SPI Flash on Allwinner SoCs in SPL" >>>>>> -depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || >>>>>> MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 >>>>>> +depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || >>>>>> MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || >>>>>> MACH_SUNIV >>>>> >>>>> I think this is premature without the corresponding patch to >>>>> spl_spi_sunxi.c. >>>> Ill look into this. >>>>> >>>>>>help >>>>>> Enable support for SPI Flash. This option allows SPL to read >>>>>> from >>>>>> sunxi SPI Flash. It uses the same method as the boot ROM, so >>>>>> does >>>>>> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c >>>>>> index 3ef179742c..2fee86b49b 100644 >>>>>> --- a/arch/arm/mach-sunxi/board.c >>>>>> +++ b/arch/arm/mach-sunxi/board.c >>>>>> @@ -86,7 +86,8 @@ static int gpio_init(void) >>>>>>sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); >>>>>>sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); >>>>>>#endif >>>>>> -#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40) >>>>>> +#if (defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)) || \ >>>>>> +defined(CONFIG_MACH_SUNIV) >>>>>>sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); >>>>>>sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); >>>>>>#else >>>>>> @@ -94,6 +95,10 @@ static int gpio_init(void) >>>>>>sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); >>>>>>#endif >>>>>>sunxi_gpio_set_pull(SUNXI_GPF(4), 1); >>>>>> +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV) >>>>>> +sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0); >>>>>> +sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0); >>>>>> +sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP); >>>>>>#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \ >>>>>> defined(CONFIG_MACH_SUN7I) || \ >>>>>> defined(CONFIG_MACH_SUN8I_R40)) >>>>>> @@ -219,7 +224,8 @@ void s_init(void) >>>>>>/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ >>>>>>#endif >>>>>>-#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) >>>>>> +#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) && \ >>>>>> +!defined(CONFIG_MACH_SUNIV) >>>>> >>>>> That looks correct for now, but should become obsolete with my >>>>> lowlevel_init cleanup series. >>>> Yes in V2 i fix this line, but it breaks compiling without your patch. >>>> Idk if you want a bad compile or a bad merge. >>>>> >>>>>>/* Enable SMP mode for CPU0, by setting bit 6 of Auxili
Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
Hi Jesse, Andre,
On 29/01/22 22:05, Jesse Taube wrote:
On 1/29/22 15:59, Samuel Holland wrote:
On 1/29/22 5:51 AM, Andre Przywara wrote:
On Fri, 28 Jan 2022 22:21:28 -0500
Jesse Taube wrote:
On 1/26/22 09:38, Jesse Taube wrote:
On 1/26/22 09:13, Andre Przywara wrote:
On Tue, 4 Jan 2022 19:35:06 -0500
Jesse Taube wrote:
u32 spl_boot_device(void)
{
return sunxi_get_boot_device();
}
+#else
+/*
+ * suniv BROM do not pass the boot media type to SPL, so we try with the
+ * boot sequence in BROM: mmc0->spinor->fail.
+ */
+void board_boot_order(u32 *spl_boot_list)
+{
+ /*
+* See the comments above in sunxi_get_boot_device() for information
+* about FEL boot.
+*/
+ if (!is_boot0_magic(SPL_ADDR + 4)) {
+ spl_boot_list[0] = BOOT_DEVICE_BOARD;
+ return;
+ }
+
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
So does that mean that it tries MMC first, even when booted via SPI? So if
there is a *non*-bootable microSD card in, it will read something from
sector 80, and will execute that if this is a FIT or legacy image?
yes
Uh sorry to bother you again but I cant seem to find a way to find where
the bootrom got the spl. I could check other periphirals like pinmux. I
could also just have it configured at build. Are both these options
okay? I will try to find a way to find the boot device at runtime first.
Don't bother for this version, it's fine as it is now, we can refine
this later. It's only a problem if there is a non-valid SPL, but a
valid U-Boot proper legacy image on the SD card.
I don't want to have a build time option, we try to keep a single image
for all boot sources.
So eventually I'd prefer the pinmux/clock check, since that's cheaper.
The alternative would be to read the SPL (again), check for a valid
header and verify the checksum. You can look at this for inspiration:
https://patchwork.ozlabs.org/project/uboot/patch/20210712100651.6912-3-andre.przyw...@arm.com/
I checked the boot ROM code (thanks Jesse!), and indeed it does not report where
it loaded SPL from, or make any other changes to the loaded eGON image. The boot
ROM also completely cleans up its clock and pinctrl changes, regardless of the
success/failure of a specific boot device.
There's a function which loads some value to r2, but that gets called before the
"load eGON from storage" functions, so r2 will be clobbered.
Samuel, are you sure about this? Maybe Jesse can double check what
happens stepping here:
https://elixir.bootlin.com/u-boot/latest/source/arch/arm/cpu/armv7/start.S#L40
Because Jesse mentioned R2 contains the value, so I expect it to be here.
So as far as I can tell, the only way to determine the boot device, other than
reimplementing the BROM in SPL, is to look at the return address on the top of
the BROM's stack. These are the possible values (in order of execution):
0x40f8: mmc0
0x4114: spi0 NAND
0x4130: spi0 NOR
0x4150: mmc1
If i save it in save_boot_params it does change when in a different boot
device. Ill look into it more.
Are the values in R2 the same as the other sunxi SoCs?
And if yes, you can save it in a global variable here:
https://elixir.bootlin.com/u-boot/latest/source/arch/arm/cpu/armv7/start.S#L40
since that is the very beginning of SPL using a #ifdef SUNIV/#endif
the sp is also a good idea.
This is also another good option. But if the previous works I would go
for that IMHO.
Best regards
--
Giulio Benetti
Benetti Engineering sas
Re: [PATCH 00/11] Add support for SUNIV and F1C100s.
Hi All, On 05/01/22 13:54, Jesse Taube wrote: On 1/5/22 07:14, Andre Przywara wrote: On Wed, 05 Jan 2022 19:36:29 +0800 Icenowy Zheng wrote: Hi Jesse, 在 2022-01-04星期二的 19:34 -0500，Jesse Taube写道： This patch set aims to add suport for the SUNIV and F1C100s. Suport has been in linux for a while now, but not in u-boot. This patchset contains: - CPU specific initialization code - SUNIV dram driver - SUNIV clock driver adaption - SUNIV gpio driver adaption - SUNIV uart driver adaption - F1C100s basic support I am hoping to get Icenowy's patches in as it seems she hasnt submitted in a while. The only edits I made to her code is rebasing it against ML and changing some formating. I also re-grouped her commits. I got too lazy to send it (because I think F1C100s is just too weak)... I am wondering if the dram driver should be moved into device drivers rather than in mach-sunxi. I am also wondering if it is okay to submit some one elses code, and if so how should I do so. As you are keeping my SoB and adding yours, it's totally okay. Thanks Icenowy for confirming! Jesse: yes, it's perfectly fine to send patches from someone else, as long as you keep the authorship, their SoB, and add your's. Typical reasons are lack of time or interest from the original author. But it's customary to ask the author first I did but it must have gotten lost in the cosmos. , and care should be taken when changing patches, as this might not be in the interest of the original author (and they are the ones who will get blamed for bugs). Also please mark the series either as a Resend or as a v2. So with Icenowy's confirmation above I consider this fine. But what was actually holding back this series was lack of review, testing and/or interest. Well the price of the SOC has gained it some popularity, aswell as a couple forum posts. Similar to Icenowy my personal interest in crufty old cores is somewhat limited, so this wasn't very high on my priority list. It is very slow but its a good challenge. Slow depending on application :-) Two of my customers would like to use it in Q2/Q3 for very low-end HMIs. And as I see, one of the last F1Cxxx is F1C800s released in 2017. Here the good thing they have is ram onboard. So given that there is apparently some interest now: Can you confirm that you have reviewed the series, or at least tested this? I have tested this yes. I would be interested to know if a second pair of eyes had a look, and to what extent. I'm Sending giulio.benetti@ some boards I made he will also test. I'm sure many other people will be willing to test aswell. Yes, I'll test on Jesse's board and on Lichee-pi-nano too when I have time, this way I'll be able to give a Tested-by: me. Best regards -- Giulio Benetti Benetti Engineering sas I don't have any hardware, so would need to rely on others to make sure this code is somewhat sane. I can send you one of my many boards :) And it basically looks like a v2 of Icenowy's series, so can you give a Changelog of the differences? I skimmed over her original series back then, so I would be interested in what makes this version special. It passes checkpatch on the latest. Cheers, Andre Thanks for cleaning up these patches! ;-) NP! I took https://github.com/Lichee-Pi/u-boot/tree/nano-v2018.01 re-based it against mainline and fixed formatting in a few files. I also removed the spi-flash driver as it was causing issues and we can boot from sdcard for now. there are some things I did to make the old code compatible with new code but mostly preprocessor and configs. For the dram driver I had to change a bit but none of the logic, i am worried that i may have to move it to /drivers. Do you want a more comprehensive list of changes?
Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
Hi Stanley,
On 15/12/21 03:57, Stanley Chu wrote:
Add basic support for the Nuvoton NPCM845 BMC.
Signed-off-by: Stanley Chu
---
arch/arm/Kconfig | 9 +
arch/arm/Makefile | 1 +
arch/arm/include/asm/arch-npcm8xx/clock.h | 164
arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++
arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++
arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 +
arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++
arch/arm/mach-nuvoton/Kconfig | 24 ++
arch/arm/mach-nuvoton/Makefile| 1 +
arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++
arch/arm/mach-nuvoton/npcm8xx/Makefile| 1 +
arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170
Here ^^^ you setup timer, but it should be a separate driver IMHO. At
least this is what I've done for imxrt.
Same goes for clock, there is no clock driver and you setup spi clock
directly inside the same file with npcm_sysintf_init() while that should
be part of the clock driver.
Also all defines regarding to clocks and peripherals should go into
their driver.
arch/arm/mach-nuvoton/npcm8xx/reset.c | 51
Here you've mixed up the architecture(above) and the board(below) in a
single patch.
board/nuvoton/arbel/Kconfig | 18 ++
board/nuvoton/arbel/Makefile | 1 +
board/nuvoton/arbel/arbel.c | 33 +++
include/configs/arbel.h | 54
arbel should be arbel-evk
I stop here, because there could be big changes if others agree.
Best regards
--
Giulio Benetti
Benetti Engineering sas
17 files changed, 924 insertions(+)
create mode 100644 arch/arm/include/asm/arch-npcm8xx/clock.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/espi.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/gcr.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/gpio.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/rst.h
create mode 100644 arch/arm/mach-nuvoton/Kconfig
create mode 100644 arch/arm/mach-nuvoton/Makefile
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Kconfig
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Makefile
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/cpu.c
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/reset.c
create mode 100644 board/nuvoton/arbel/Kconfig
create mode 100644 board/nuvoton/arbel/Makefile
create mode 100644 board/nuvoton/arbel/arbel.c
create mode 100644 include/configs/arbel.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f7f03837fe..80ec42f6be 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1952,6 +1952,13 @@ config TARGET_XENGUEST_ARM64
select LINUX_KERNEL_IMAGE_HEADER
select XEN_SERIAL
select SSCANF
+
+config ARCH_NPCM
+ bool "Support Nuvoton SoCs"
+ select DM
+ select OF_CONTROL
+ imply CMD_DM
+
endchoice
config SUPPORT_PASSING_ATAGS
@@ -2150,6 +2157,8 @@ source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-nexell/Kconfig"
+source "arch/arm/mach-nuvoton/Kconfig"
+
source "board/armltd/total_compute/Kconfig"
source "board/bosch/shc/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ad757e982e..29a0250ab6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -92,6 +92,7 @@ machine-$(CONFIG_ARCH_VERSAL) += versal
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
+machine-$(CONFIG_ARCH_NPCM)+= nuvoton
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
diff --git a/arch/arm/include/asm/arch-npcm8xx/clock.h b/arch/arm/include/asm/arch-npcm8xx/clock.h
new file mode 100644
index 00..088b536b7b
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/clock.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#ifndef _NPCM_CLOCK_H_
+#define _NPCM_CLOCK_H_
+
+#define NPCM_CLK_BA0xF0801000
+enum {
+ APB1 = 1,
+ APB2 = 2,
+ APB3 = 3,
+ APB4 = 4,
+ APB5 = 5,
+ SPI0 = 10,
+ SPI1 = 11,
+ SPI3 = 13,
+ SPIX = 14,
+};
+
+/* Clock Select Register (CLKSEL) */
+#define CLKSEL_RCPCKSEL 27
+#define CLKSEL_RGSEL25
+#define CLKSEL_GFXMSEL 21
+#define CLKSEL_CLKOUTSEL18
+#define CLKSEL_PCICKSEL 16
+#define CLKSEL_ADCCKSEL 14
+#define CLKSEL_MCCKSEL 12
+#define CLKSEL_SUCKSEL 10
+#define CLKSEL_UARTCKSEL8
+#define CLKSEL_SDCKSEL 6
+#define CLKSEL_PIXCKSEL 4
+#define CLKSEL_CPUCKSEL 0
+
+/* Clock Divider Control Register 1 (CLKDIV1) */
+#define CLKDIV1_ADCCKDIV28
[PATCH 1/2] board/sunxi/dram_sun4i_auto: use DRAM_MEMORY_TYPE_DDR3 instead of magic number 3
Since DRAM_MEMORY_TYPE_DDR3 is defined let's use it instead of magic
number 3.
Signed-off-by: Giulio Benetti
---
board/sunxi/dram_sun4i_auto.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/sunxi/dram_sun4i_auto.c b/board/sunxi/dram_sun4i_auto.c
index e8bbee4ee5..547d1c0cb4 100644
--- a/board/sunxi/dram_sun4i_auto.c
+++ b/board/sunxi/dram_sun4i_auto.c
@@ -4,7 +4,7 @@
static struct dram_para dram_para = {
.clock = CONFIG_DRAM_CLK,
- .type = 3,
+ .type = DRAM_MEMORY_TYPE_DDR3,
.rank_num = 1,
.density = 0,
.io_width = 0,
--
2.25.1
[PATCH 2/2] board/sunxi/dram_sun5i_auto: use DRAM_MEMORY_TYPE_DDR3 instead of magic number 3
Since DRAM_MEMORY_TYPE_DDR3 is defined let's use it instead of magic
number 3.
Signed-off-by: Giulio Benetti
---
board/sunxi/dram_sun5i_auto.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c
index a5f4f8b743..517506ccc4 100644
--- a/board/sunxi/dram_sun5i_auto.c
+++ b/board/sunxi/dram_sun5i_auto.c
@@ -7,7 +7,7 @@
static struct dram_para dram_para = {
.clock = CONFIG_DRAM_CLK,
.mbus_clock = CONFIG_DRAM_MBUS_CLK,
- .type = 3,
+ .type = DRAM_MEMORY_TYPE_DDR3,
.rank_num = 1,
.density = 0,
.io_width = 0,
--
2.25.1
[PATCH] video: mxsfb: fix clk_get_by_name() return value check
If clk_get_by_name() returns 0 it means it executed successfully while now
we consider it as an error. So let's check if return value is negative to
be an error. Otherwise this prevents "axi" and "disp_axi" to be enabled.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 98d2965711..5f85c0c3eb 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -89,7 +89,7 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
}
ret = clk_get_by_name(dev, "axi", &clk);
- if (!ret) {
+ if (ret < 0) {
debug("%s: Failed to get mxs axi clk: %d\n", __func__, ret);
} else {
ret = clk_enable(&clk);
@@ -100,7 +100,7 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
}
ret = clk_get_by_name(dev, "disp_axi", &clk);
- if (!ret) {
+ if (ret < 0) {
debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__,
ret);
} else {
ret = clk_enable(&clk);
--
2.25.1
Re: External dts building
Hi Simon, > Il giorno 15 ott 2021, alle ore 02:53, Simon Glass ha > scritto: > > Hi Giulio, > >> On Thu, 14 Oct 2021 at 15:12, Giulio Benetti >> wrote: >> >> Hi Simon, >> >> Il giorno 14 ott 2021, alle ore 22:43, Simon Glass ha >> scritto: >> >> Hi Giulio, >> >> On Thu, 14 Oct 2021 at 13:23, Giulio Benetti >> wrote: >> >> >> Hi Simon, >> >> >> Il giorno 14 ott 2021, alle ore 20:24, Simon Glass ha >> scritto: >> >> >> Hi, >> >> >> On Thu, 14 Oct 2021 at 07:46, Tom Rini wrote: >> >> >> On Thu, Oct 14, 2021 at 02:53:30AM +0200, Giulio Benetti wrote: >> >> >> Hello All, >> >> >> is there a way to pass a dts file without touching the >> arch/arm/boot/dts/Makefile? >> >> >> On Buildroot we support the possibility to pass an external dts by copying >> it to the uboot sources to >> >> be built but since uboot version 2020.01 it doesn’t work anymore. >> >> >> So I’ve proposed a patch to prepend the dts file in the Makefile above, but >> this has drawbacks, like we reconfigure(it keeps adding files every time). >> >> >> So I ask you, is there a more canonical way already to achieve this? >> >> >> Not exactly, and it's something we're very much actively discussing >> >> right now. >> >> >> Are you using 'make DEVICE_TREE=xxx' ? >> >> >> Yes but it doesn’t work if you don’t add an entry into arch/arm/dts/Makefile >> >> Before version 2020.01 worked, but not after it. >> >> >> What board are you building? >> >> >> A20-OLinuXino-Lime_defconfig for but without CONFIG_DEFAULT_DEVICE_TREE >> undefined, >> so if you try to pass DEVICE_TREE= pointing to an external .dts file copied >> to arch/arm/dts/ make doesn’t find the entry in Makefile and it can’t build >> it. >> >> This is useful in build systems like Buildroot where you can provide an >> external defconfig as well as an external .dts file. >> >> So here the solution I see is to create an entry in arch/arm/dts/Makefile on >> the top of the file afte copying the .dts file we want to build. >> But on Buildroot they’ve pointed me to ask upstream(here) if there’s a more >> canonical way or to work together to achieve the goal: >> >> https://patchwork.ozlabs.org/project/buildroot/patch/20210209201303.195093-1-giulio.bene...@benettiengineering.com/ > > How about not disabling CONFIG_DEFAULT_DEVICE_TREE ? That should work OK. But if I’m not wrong the problem of the dts/Makefile remains. If .dts file is not assigned to dtb-y it won’t be built. And in the case of Buildroot we have 2 ways to use external dts files: 1) patch uboot adding the dts and the entry in dts/Makefile 2) copy .dts file(let’s say located in ~/my-folder/my.dts) to arch/arm/dts/my.dts and prepend the dtb-y += my.dts in arch/arm/dts/Makefile and here problem arises. Because it can work once but we need to make it possible to have ‘make uboot-rebuild/reconfigure’ (Buildroot has such targets). This way is not easy at all to prepend the dtb-y at the top of the file without re-prepending it again and again. It worked up to uboot < 2020.01, but I still haven’t bisected to see the “offending” commit. Maybe I can try and find out why it behaves like that. What about that? Best regards Giulio > > Regards, > Simon > >> >> Sorry if this e-mail is html but I’m on mobile :-/ >> >> Best regards >> Giulio Benetti >> >> >> Regards, >> Simon
Re: External dts building
On 10/14/21 8:22 PM, Tom Rini wrote: On Thu, Oct 14, 2021 at 08:08:37PM +0200, Giulio Benetti wrote: Il giorno 14 ott 2021, alle ore 15:45, Tom Rini ha scritto: On Thu, Oct 14, 2021 at 02:53:30AM +0200, Giulio Benetti wrote: Hello All, is there a way to pass a dts file without touching the arch/arm/boot/dts/Makefile? On Buildroot we support the possibility to pass an external dts by copying it to the uboot sources to be built but since uboot version 2020.01 it doesn’t work anymore. So I’ve proposed a patch to prepend the dts file in the Makefile above, but this has drawbacks, like we reconfigure(it keeps adding files every time). So I ask you, is there a more canonical way already to achieve this? Not exactly, and it's something we're very much actively discussing right now. Ok, thank you. Is there already a thread about this? https://lore.kernel.org/u-boot/20211013010120.96851-1-...@chromium.org/ is the start of it. Thank you -- Giulio Benetti Benetti Engineering sas
Re: External dts building
Hi Simon, > Il giorno 14 ott 2021, alle ore 22:43, Simon Glass ha > scritto: > > Hi Giulio, > >> On Thu, 14 Oct 2021 at 13:23, Giulio Benetti >> wrote: >> >> Hi Simon, >> >>>> Il giorno 14 ott 2021, alle ore 20:24, Simon Glass ha >>>> scritto: >>> >>> Hi, >>> >>>> On Thu, 14 Oct 2021 at 07:46, Tom Rini wrote: >>>> >>>>> On Thu, Oct 14, 2021 at 02:53:30AM +0200, Giulio Benetti wrote: >>>>> >>>>> Hello All, >>>>> >>>>> is there a way to pass a dts file without touching the >>>>> arch/arm/boot/dts/Makefile? >>>>> >>>>> On Buildroot we support the possibility to pass an external dts by >>>>> copying it to the uboot sources to >>>>> be built but since uboot version 2020.01 it doesn’t work anymore. >>>>> >>>>> So I’ve proposed a patch to prepend the dts file in the Makefile above, >>>>> but this has drawbacks, like we reconfigure(it keeps adding files every >>>>> time). >>>>> >>>>> So I ask you, is there a more canonical way already to achieve this? >>>> >>>> Not exactly, and it's something we're very much actively discussing >>>> right now. >>> >>> Are you using 'make DEVICE_TREE=xxx' ? >> >> Yes but it doesn’t work if you don’t add an entry into arch/arm/dts/Makefile >> Before version 2020.01 worked, but not after it. > > What board are you building? A20-OLinuXino-Lime_defconfig for but without CONFIG_DEFAULT_DEVICE_TREE undefined, so if you try to pass DEVICE_TREE= pointing to an external .dts file copied to arch/arm/dts/ make doesn’t find the entry in Makefile and it can’t build it. This is useful in build systems like Buildroot where you can provide an external defconfig as well as an external .dts file. So here the solution I see is to create an entry in arch/arm/dts/Makefile on the top of the file afte copying the .dts file we want to build. But on Buildroot they’ve pointed me to ask upstream(here) if there’s a more canonical way or to work together to achieve the goal: https://patchwork.ozlabs.org/project/buildroot/patch/20210209201303.195093-1-giulio.bene...@benettiengineering.com/ Sorry if this e-mail is html but I’m on mobile :-/ Best regards Giulio Benetti > > Regards, > Simon
Re: External dts building
Hi Simon, > Il giorno 14 ott 2021, alle ore 20:24, Simon Glass ha > scritto: > > Hi, > >> On Thu, 14 Oct 2021 at 07:46, Tom Rini wrote: >> >>> On Thu, Oct 14, 2021 at 02:53:30AM +0200, Giulio Benetti wrote: >>> >>> Hello All, >>> >>> is there a way to pass a dts file without touching the >>> arch/arm/boot/dts/Makefile? >>> >>> On Buildroot we support the possibility to pass an external dts by copying >>> it to the uboot sources to >>> be built but since uboot version 2020.01 it doesn’t work anymore. >>> >>> So I’ve proposed a patch to prepend the dts file in the Makefile above, but >>> this has drawbacks, like we reconfigure(it keeps adding files every time). >>> >>> So I ask you, is there a more canonical way already to achieve this? >> >> Not exactly, and it's something we're very much actively discussing >> right now. > > Are you using 'make DEVICE_TREE=xxx' ? Yes but it doesn’t work if you don’t add an entry into arch/arm/dts/Makefile Before version 2020.01 worked, but not after it. Best regards Giulio > > Regards, > Simon
Re: External dts building
> Il giorno 14 ott 2021, alle ore 15:45, Tom Rini ha > scritto: > > On Thu, Oct 14, 2021 at 02:53:30AM +0200, Giulio Benetti wrote: > >> Hello All, >> >> is there a way to pass a dts file without touching the >> arch/arm/boot/dts/Makefile? >> >> On Buildroot we support the possibility to pass an external dts by copying >> it to the uboot sources to >> be built but since uboot version 2020.01 it doesn’t work anymore. >> >> So I’ve proposed a patch to prepend the dts file in the Makefile above, but >> this has drawbacks, like we reconfigure(it keeps adding files every time). >> >> So I ask you, is there a more canonical way already to achieve this? > > Not exactly, and it's something we're very much actively discussing > right now. Ok, thank you. Is there already a thread about this? Best regards Giulio Benetti Benetti Engineering sas > > -- > Tom
External dts building
Hello All, is there a way to pass a dts file without touching the arch/arm/boot/dts/Makefile? On Buildroot we support the possibility to pass an external dts by copying it to the uboot sources to be built but since uboot version 2020.01 it doesn’t work anymore. So I’ve proposed a patch to prepend the dts file in the Makefile above, but this has drawbacks, like we reconfigure(it keeps adding files every time). So I ask you, is there a more canonical way already to achieve this? Thanks in advance Best regards Giulio Benetti Benetti Engineering sas
[PATCH 6/6] configs: imxrt1050-evk: enable host usb support and its command
Now that usb host is supported let's enable it on this board. Signed-off-by: Giulio Benetti --- configs/imxrt1050-evk_defconfig | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index 9c8bdb07dc..9f509f3b9f 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -32,8 +32,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_USB=y # CONFIG_CMD_MII is not set -# CONFIG_DOS_PARTITION is not set +# CONFIG_SPL_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_OF_CONTROL=y @@ -65,6 +66,10 @@ CONFIG_FSL_LPUART=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_IMX_GPT_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_EHCI_HCD=y CONFIG_DM_VIDEO=y CONFIG_BACKLIGHT_GPIO=y CONFIG_SYS_WHITE_ON_BLACK=y -- 2.25.1
[PATCH 5/6] ARM: dts: imxrt1050-evk: enable usbotg1 node as host
Enable usbotg1 port node as host usb.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index 81db1a446d..324cf7af96 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -260,3 +260,8 @@
};
};
};
+
+&usbotg1 {
+ dr_mode = "host";
+ status = "okay";
+};
--
2.25.1
[PATCH 4/6] ARM: dts: imxrt1050: add usbotg1, usbphy1 and usbmisc nodes
Usb is now supported so add all required nodes for it in imxrt1050.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index ec1eb88e45..6814352d9a 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -23,6 +23,7 @@
gpio4 = &gpio5;
mmc0 = &usdhc1;
serial0 = &lpuart1;
+ usbphy0 = &usbphy1;
};
clocks {
@@ -165,5 +166,31 @@
clocks = <&osc>;
status = "disabled";
};
+
+ usbphy1: usbphy@400d9000 {
+ compatible = "fsl,imxrt-usbphy";
+ reg = <0x400d9000 0x1000>;
+ interrupts = ;
+ };
+
+ usbmisc: usbmisc@402e0800 {
+ #index-cells = <1>;
+ compatible = "fsl,imxrt-usbmisc";
+ reg = <0x402e0800 0x200>;
+ clocks = <&clks IMXRT1050_CLK_USBOH3>;
+ };
+
+ usbotg1: usb@402e {
+ compatible = "fsl,imxrt-usb", "fsl,imx27-usb";
+ reg = <0x402e 0x200>;
+ interrupts = ;
+ clocks = <&clks IMXRT1050_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
};
};
--
2.25.1
[PATCH 3/6] usb: ehci-mx6: add support for i.MXRT
Add support for usb1 and usb2 present on i.IMXRT.
Signed-off-by: Giulio Benetti
---
arch/arm/include/asm/arch-imxrt/imx-regs.h | 4
drivers/usb/host/Kconfig | 2 +-
drivers/usb/host/ehci-mx6.c| 13 +++--
3 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h
b/arch/arm/include/asm/arch-imxrt/imx-regs.h
index 44c95dcd11..d01e6ca2e0 100644
--- a/arch/arm/include/asm/arch-imxrt/imx-regs.h
+++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h
@@ -23,4 +23,8 @@
#include
#endif
+#define USB_BASE_ADDR 0x402E
+#define USB_PHY0_BASE_ADDR 0x400D9000
+#define USB_PHY1_BASE_ADDR 0x400DA000
+
#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index bf5d82f035..f34cba2395 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -149,7 +149,7 @@ config USB_EHCI_MX5
config USB_EHCI_MX6
bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller"
- depends on ARCH_MX6 || ARCH_MX7ULP
+ depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT
default y
---help---
Enables support for the on-chip EHCI controller on i.MX6 SoCs.
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 06be9deaaa..238c93183b 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -177,7 +177,7 @@ static void __maybe_unused
usb_power_config_mx7ulp(void *usbphy) { }
#endif
-#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
static const unsigned phy_bases[] = {
USB_PHY0_BASE_ADDR,
#if defined(USB_PHY1_BASE_ADDR)
@@ -340,7 +340,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
enum usb_init_type type;
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
u32 controller_spacing = 0x200;
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
@@ -382,7 +382,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
return ret;
}
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
usb_power_config_mx6(anatop, index);
#elif defined (CONFIG_MX7)
usb_power_config_mx7(usbnc);
@@ -392,7 +392,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
usb_oc_config(usbnc, index);
-#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
if (index < ARRAY_SIZE(phy_bases)) {
usb_internal_phy_clock_gate((void __iomem *)phy_bases[index],
1);
usb_phy_enable(ehci, (void __iomem *)phy_bases[index]);
@@ -504,7 +504,7 @@ static int ehci_usb_phy_mode(struct udevice *dev)
* About fsl,usbphy, Refer to
* Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
*/
- if (is_mx6() || is_mx7ulp()) {
+ if (is_mx6() || is_mx7ulp() || is_imxrt()) {
phy_off = fdtdec_lookup_phandle(blob,
offset,
"fsl,usbphy");
@@ -671,7 +671,7 @@ static int ehci_usb_probe(struct udevice *dev)
usb_oc_config(priv->misc_addr, priv->portnr);
-#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
usb_internal_phy_clock_gate(priv->phy_addr, 1);
usb_phy_enable(ehci, priv->phy_addr);
#endif
@@ -757,6 +757,7 @@ int ehci_usb_remove(struct udevice *dev)
static const struct udevice_id mx6_usb_ids[] = {
{ .compatible = "fsl,imx27-usb" },
{ .compatible = "fsl,imx7d-usb" },
+ { .compatible = "fsl,imxrt-usb" },
{ }
};
--
2.25.1
[PATCH 1/6] ARM: IMXRT: introduce is_imxrt*() macros and get_cpu_rev()
We need those macros to instruct drivers on how to behave for SoC specific
quirks, so let's add it as done for other i.MX SoCs.
Signed-off-by: Giulio Benetti
---
arch/arm/include/asm/arch-imx/cpu.h | 3 +++
arch/arm/include/asm/mach-imx/sys_proto.h | 4
arch/arm/mach-imx/imxrt/soc.c | 12
3 files changed, 19 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h
b/arch/arm/include/asm/arch-imx/cpu.h
index bb13e07b66..267a094e5a 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -50,6 +50,8 @@
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP0x92 /* dummy ID */
+#define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */
+#define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
@@ -57,6 +59,7 @@
#define MXC_SOC_MX70x70
#define MXC_SOC_IMX8M 0x80
#define MXC_SOC_IMX8 0x90 /* dummy */
+#define MXC_SOC_IMXRT 0xB0 /* dummy */
#define MXC_SOC_MX7ULP 0xE0 /* dummy */
#define CHIP_REV_1_00x10
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index c7668ffc4d..b612189849 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -31,6 +31,7 @@ struct bd_info;
#define is_mx7() (is_soc_type(MXC_SOC_MX7))
#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
#define is_imx8() (is_soc_type(MXC_SOC_IMX8))
+#define is_imxrt() (is_soc_type(MXC_SOC_IMXRT))
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
@@ -78,6 +79,9 @@ struct bd_info;
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
+#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
+#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
+
#ifdef CONFIG_MX6
#define IMX6_SRC_GPR10_BMODE BIT(28)
#define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c
index c533f3554a..ba015992ee 100644
--- a/arch/arm/mach-imx/imxrt/soc.c
+++ b/arch/arm/mach-imx/imxrt/soc.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
int arch_cpu_init(void)
@@ -35,3 +36,14 @@ int arch_cpu_init(void)
return 0;
}
+
+u32 get_cpu_rev(void)
+{
+#if defined(CONFIG_IMXRT1020)
+ return MXC_CPU_IMXRT1020 << 12;
+#elif defined(CONFIG_IMXRT1050)
+ return MXC_CPU_IMXRT1050 << 12;
+#else
+#error This IMXRT SoC is not supported
+#endif
+}
--
2.25.1
[PATCH 2/6] clk: imx: clk-imxrt1050: introduce IMXRT1050_CLK_USBOH3
Usb needs IMXRT1050_CLK_USBOH3 clock to be enabled, so let's add it to
clock driver.
Signed-off-by: Giulio Benetti
---
drivers/clk/imx/clk-imxrt1050.c | 2 ++
include/dt-bindings/clock/imxrt1050-clock.h | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index eb6847f865..3e17161002 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -259,6 +259,8 @@ static int imxrt1050_clk_probe(struct udevice *dev)
imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
clk_dm(IMXRT1050_CLK_LCDIF_PIX,
imx_clk_gate2("lcdif_pix", "lcdif", base + 0x74, 10));
+ clk_dm(IMXRT1050_CLK_USBOH3,
+ imx_clk_gate2("usboh3", "pll3_usb_otg", base + 0x80, 0));
struct clk *clk, *clk1;
diff --git a/include/dt-bindings/clock/imxrt1050-clock.h
b/include/dt-bindings/clock/imxrt1050-clock.h
index 09b65e5df2..f74dbbcf93 100644
--- a/include/dt-bindings/clock/imxrt1050-clock.h
+++ b/include/dt-bindings/clock/imxrt1050-clock.h
@@ -61,6 +61,7 @@
#define IMXRT1050_CLK_PLL6_ENET52
#define IMXRT1050_CLK_PLL7_USB_HOST53
#define IMXRT1050_CLK_LCDIF_PIX54
-#define IMXRT1050_CLK_END 55
+#define IMXRT1050_CLK_USBOH3 55
+#define IMXRT1050_CLK_END 56
#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
--
2.25.1
[PATCH 0/6] i.MXRT1050 add Usb Host support
This patchset adds Usb Host support for imxrt1050-evk board adjusting the compatible driver ehci-mx6. This allows to read a FAT usb key connected to usbotg1 port of imxrt1050-evk board. Giulio Benetti (6): ARM: IMXRT: introduce is_imxrt*() macros and get_cpu_rev() clk: imx: clk-imxrt1050: introduce IMXRT1050_CLK_USBOH3 usb: ehci-mx6: add support for i.MXRT ARM: dts: imxrt1050: add usbotg1, usbphy1 and usbmisc nodes ARM: dts: imxrt1050-evk: enable usbotg1 node as host configs: imxrt1050-evk: enable host usb support and its command arch/arm/dts/imxrt1050-evk.dts | 5 arch/arm/dts/imxrt1050.dtsi | 27 + arch/arm/include/asm/arch-imx/cpu.h | 3 +++ arch/arm/include/asm/arch-imxrt/imx-regs.h | 4 +++ arch/arm/include/asm/mach-imx/sys_proto.h | 4 +++ arch/arm/mach-imx/imxrt/soc.c | 12 + configs/imxrt1050-evk_defconfig | 7 +- drivers/clk/imx/clk-imxrt1050.c | 2 ++ drivers/usb/host/Kconfig| 2 +- drivers/usb/host/ehci-mx6.c | 13 +- include/dt-bindings/clock/imxrt1050-clock.h | 3 ++- 11 files changed, 73 insertions(+), 9 deletions(-) -- 2.25.1
[PATCH 2/3] ARM: dts: imxrt1020-evk: move all u-boot, dm-spl to imxrt1020-evk-u-boot.dtsi file
At the moment a lot of u-boot,dm-spl properties are present in board .dts
file but this is not correct since u-boot,dm-spl property is u-boot
specific and must be listed into the separate imrt1020-evk-u-boot.dtsi
file. So let's move every u-boot,dm-spl property present in
imxrt1020-evk.dts to imxrt1020-evk-u-boot.dtsi file.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 34 ++
arch/arm/dts/imxrt1020.dtsi| 10
2 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index 34d19e06c5..121665a2d2 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -8,6 +8,38 @@
chosen {
u-boot,dm-spl;
};
+
+ clocks {
+ u-boot,dm-spl;
+ };
+
+ soc {
+ u-boot,dm-spl;
+ };
+};
+
+&osc {
+ u-boot,dm-spl;
+};
+
+&clks {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
};
&gpt1 {
@@ -19,6 +51,8 @@
};
&semc {
+ u-boot,dm-spl;
+
bank1: bank@0 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
index cab608c644..884d57f614 100644
--- a/arch/arm/dts/imxrt1020.dtsi
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -23,7 +23,6 @@
};
clocks {
- u-boot,dm-spl;
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0>;
@@ -37,7 +36,6 @@
};
osc: osc {
- u-boot,dm-spl;
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2400>;
@@ -45,10 +43,7 @@
};
soc {
- u-boot,dm-spl;
-
semc: semc@402f {
- u-boot,dm-spl;
compatible = "fsl,imxrt-semc";
reg = <0x402f 0x4000>;
clocks = <&clks IMXRT1020_CLK_SEMC>;
@@ -73,7 +68,6 @@
};
clks: ccm@400fc000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt1020-ccm";
reg = <0x400fc000 0x4000>;
interrupts = ,
@@ -82,7 +76,6 @@
};
usdhc1: usdhc@402c {
- u-boot,dm-spl;
compatible = "fsl,imxrt-usdhc";
reg = <0x402c 0x1>;
interrupts = ;
@@ -95,7 +88,6 @@
};
gpio1: gpio@401b8000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401b8000 0x4000>;
interrupts = ,
@@ -107,7 +99,6 @@
};
gpio2: gpio@401bc000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401bc000 0x4000>;
interrupts = ,
@@ -119,7 +110,6 @@
};
gpio3: gpio@401c {
- u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401c 0x4000>;
interrupts = ,
--
2.25.1
[PATCH 3/3] ARM: dts: imxrt1020: add gpio5 node to this SoC
i.MXRT1020 supports gpio5, so let's add a node for it.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
index 884d57f614..5ba314f995 100644
--- a/arch/arm/dts/imxrt1020.dtsi
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -120,6 +120,17 @@
#interrupt-cells = <2>;
};
+ gpio5: gpio@400c {
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x400c 0x4000>;
+ interrupts = ,
+ ;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
gpt1: gpt1@401ec000 {
compatible = "fsl,imxrt-gpt";
reg = <0x401ec000 0x4000>;
--
2.25.1
[PATCH 1/3] ARM: dts: imxrt1050-evk: move all u-boot, dm-spl to imxrt1050-evk-u-boot.dtsi file
At the moment a lot of u-boot,dm-spl properties are present in board .dts
file but this is not correct since u-boot,dm-spl property is u-boot
specific and must be listed into the separate imrt1050-evk-u-boot.dtsi
file. So let's move every u-boot,dm-spl property present in
imxrt1050-evk.dts to imxrt1050-evk-u-boot.dtsi file.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 38 ++
arch/arm/dts/imxrt1050.dtsi| 13 -
2 files changed, 38 insertions(+), 13 deletions(-)
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index a4b50f0bb2..3168c2df2c 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -8,6 +8,42 @@
chosen {
u-boot,dm-spl;
};
+
+ clocks {
+ u-boot,dm-spl;
+ };
+
+ soc {
+ u-boot,dm-spl;
+ };
+};
+
+&osc {
+ u-boot,dm-spl;
+};
+
+&clks {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
};
&gpt1 {
@@ -19,6 +55,8 @@
};
&semc {
+ u-boot,dm-spl;
+
bank1: bank@0 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 5f5a98e19e..e21f92864f 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -27,10 +27,7 @@
};
clocks {
- u-boot,dm-spl;
-
osc: osc {
- u-boot,dm-spl;
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2400>;
@@ -38,10 +35,7 @@
};
soc {
- u-boot,dm-spl;
-
semc: semc@402f {
- u-boot,dm-spl;
compatible = "fsl,imxrt-semc";
reg = <0x402f 0x4000>;
clocks = <&clks IMXRT1050_CLK_SEMC>;
@@ -66,7 +60,6 @@
};
clks: ccm@400fc000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt1050-ccm";
reg = <0x400fc000 0x4000>;
interrupts = ,
@@ -75,7 +68,6 @@
};
usdhc1: usdhc@402c {
- u-boot,dm-spl;
compatible = "fsl,imxrt-usdhc";
reg = <0x402c 0x1>;
interrupts = ;
@@ -88,7 +80,6 @@
};
gpio1: gpio@401b8000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401b8000 0x4000>;
interrupts = ,
@@ -100,7 +91,6 @@
};
gpio2: gpio@401bc000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401bc000 0x4000>;
interrupts = ,
@@ -112,7 +102,6 @@
};
gpio3: gpio@401c {
- u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401c 0x4000>;
interrupts = ,
@@ -124,7 +113,6 @@
};
gpio4: gpio@401c4000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401c4000 0x4000>;
interrupts = ,
@@ -136,7 +124,6 @@
};
gpio5: gpio@400c {
- u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x400c 0x4000>;
interrupts = ,
--
2.25.1
Re: [PATCH 0/5] Fix i.MXRT1050 hang on lcdif init and improve DT for mxsfb
Hi Stefano, On 5/13/21 10:14 AM, Stefano Babic wrote: Hi Giulio, On 13.05.21 00:12, Giulio Benetti wrote: Hi Stefano, On 5/2/21 1:44 AM, Giulio Benetti wrote: On 4/13/21 1:05 AM, Giulio Benetti wrote: On 4/13/21 1:03 AM, Giulio Benetti wrote: This patchset fixes u-boot hang on i.MXRT1050 while setting lcdif in mxsfb driver. There are 2 gates to be enabled to initialize mxsfb so let's introduce the missing gate as a clock and rename "per" clock to "pix" clock since in the other .dts files using *-lcdif "pix" is used. This patchset add also "disp_axi" clock enabling in mxsfb that should make able to every i.MX SoC with lcdif using DT. I didn't test it other than i.MXRT1050 since I don't have the boards. If someone can test it it would be great. Note that i.MX23/28 should fail using DT instead because they don't specify any clock-names in their dts. I've forgotten to specify that this patchset depends on this patchset: https://patchwork.ozlabs.org/project/uboot/list/?series=237909 This ^^^ series is superseeded by v2: https://patchwork.ozlabs.org/project/uboot/list/?series=241701 Current patchset is not superseeded, only the one which depends to is superseeded by v2. Do you prefer me to send a unique patchset with all patches of both patchsets? Yes, or in patchset becomes a mess. Please send a complete series, thanks ! Well I've merged in a unique patchset both patchsets[1], sorry for my e-mail mess. [1]: https://patchwork.ozlabs.org/project/uboot/list/?series=243591 Best regards -- Giulio Benetti Benetti Engineering sas
[PATCH v3 18/22] video: mxsfb: add enabling of "disp_axi" clock
Some SoC needs "disp_axi" clock to be enabled, so let's try to retrieve it
and enabling. If it fails it gives only a debug(), but this clock as well
as "axi" clock is not mandatory.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 147bd668fe..523d8a8d98 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -98,6 +98,17 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
return;
}
}
+
+ ret = clk_get_by_name(dev, "disp_axi", &clk);
+ if (!ret) {
+ debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__,
ret);
+ } else {
+ ret = clk_enable(&clk);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs disp_axi clk: %d\n",
ret);
+ return;
+ }
+ }
#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
--
2.25.1
[PATCH v3 15/22] ARM: dts: imxrt1050-evk: add device_type = "memory" to memory node
Now device_type = "memory" is mandatory to allow u-boot to read memory
node, so let's add it to memory node.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index 6d21f2b738..2052d4eb4e 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -20,6 +20,7 @@
};
memory {
+ device_type = "memory";
reg = <0x8000 0x200>;
};
};
--
2.25.1
[PATCH v3 07/22] ARM: dts: imxrt1020-evk-u-boot: make gpt1 present for SPL
Timer needs to be already enabled in spl, so let's add its node to spl dtb.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index d32c98de9c..34d19e06c5 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -10,6 +10,10 @@
};
};
+&gpt1 {
+ u-boot,dm-spl;
+};
+
&lpuart1 { /* console */
u-boot,dm-spl;
};
--
2.25.1
[PATCH v3 13/22] ARM: dts: imxrt1050-evk: set gpt1 as tick-timer for u-boot
Let's set gpt1 as u-boot timer.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index e592330332..6d21f2b738 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -16,6 +16,7 @@
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
+ tick-timer = &gpt1;
};
memory {
--
2.25.1
[PATCH v3 14/22] ARM: dts: imxrt1050-evk-u-boot: make gpt1 present for SPL
Timer needs to be already enabled in spl, so let's add its node to spl dtb.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index fb4f7f6f9d..a4b50f0bb2 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -10,6 +10,10 @@
};
};
+&gpt1 {
+ u-boot,dm-spl;
+};
+
&lpuart1 { /* console */
u-boot,dm-spl;
};
--
2.25.1
[PATCH v3 21/22] ARM: dts: imxrt1050: set lcdif clocks according to mxsfb driver
Lcdif needs both "pix" and "axi" clocks to be enabled so let's add them to lcdif node. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index eb5e09e971..ec1eb88e45 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -150,8 +150,9 @@ compatible = "fsl,imxrt-lcdif"; reg = <0x402b8000 0x4000>; interrupts = ; - clocks = <&clks IMXRT1050_CLK_LCDIF>; - clock-names = "per"; + clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>, +<&clks IMXRT1050_CLK_LCDIF_APB>; + clock-names = "pix", "axi"; assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>; assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>; status = "disabled"; -- 2.25.1
[PATCH v3 19/22] clk: imx: clk-imxrt1050: introduce LCDIF_PIX and rename LCDIF to LCDIF_APB
Lcd peripheral needs 2 different gates to be enable to work, so let's
introduce the missing one(LCDIF_PIX) and rename the existing one
(LCDIF_APB).
Signed-off-by: Giulio Benetti
---
drivers/clk/imx/clk-imxrt1050.c | 6 --
include/dt-bindings/clock/imxrt1050-clock.h | 5 +++--
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 594093ee5f..eb6847f865 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -255,8 +255,10 @@ static int imxrt1050_clk_probe(struct udevice *dev)
imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
clk_dm(IMXRT1050_CLK_SEMC,
imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
- clk_dm(IMXRT1050_CLK_LCDIF,
- imx_clk_gate2("lcdif", "lcdif_podf", base + 0x74, 10));
+ clk_dm(IMXRT1050_CLK_LCDIF_APB,
+ imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+ clk_dm(IMXRT1050_CLK_LCDIF_PIX,
+ imx_clk_gate2("lcdif_pix", "lcdif", base + 0x74, 10));
struct clk *clk, *clk1;
diff --git a/include/dt-bindings/clock/imxrt1050-clock.h
b/include/dt-bindings/clock/imxrt1050-clock.h
index c174f90c1a..09b65e5df2 100644
--- a/include/dt-bindings/clock/imxrt1050-clock.h
+++ b/include/dt-bindings/clock/imxrt1050-clock.h
@@ -52,7 +52,7 @@
#define IMXRT1050_CLK_USDHC2 43
#define IMXRT1050_CLK_LPUART1 44
#define IMXRT1050_CLK_SEMC 45
-#define IMXRT1050_CLK_LCDIF46
+#define IMXRT1050_CLK_LCDIF_APB46
#define IMXRT1050_CLK_PLL1_ARM 47
#define IMXRT1050_CLK_PLL2_SYS 48
#define IMXRT1050_CLK_PLL3_USB_OTG 49
@@ -60,6 +60,7 @@
#define IMXRT1050_CLK_PLL5_VIDEO 51
#define IMXRT1050_CLK_PLL6_ENET52
#define IMXRT1050_CLK_PLL7_USB_HOST53
-#define IMXRT1050_CLK_END 54
+#define IMXRT1050_CLK_LCDIF_PIX54
+#define IMXRT1050_CLK_END 55
#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
--
2.25.1
[PATCH v3 18/22] video: mxsfb: add enabling of "disp_axi" clock
Some SoC needs "disp_axi" clock to be enabled, so let's try to retrieve it
and enabling. If it fails it gives only a debug(), but this clock as well
as "axi" clock is not mandatory.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 147bd668fe..523d8a8d98 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -98,6 +98,17 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
return;
}
}
+
+ ret = clk_get_by_name(dev, "disp_axi", &clk);
+ if (!ret) {
+ debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__,
ret);
+ } else {
+ ret = clk_enable(&clk);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs disp_axi clk: %d\n",
ret);
+ return;
+ }
+ }
#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
--
2.25.1
[PATCH v3 11/22] ARM: dts: imxrt1050: add gpt1 node
Add gpt1 node for using it as timer.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index b7cc3fbc2a..6f9da3fe8a 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -154,5 +154,13 @@
clock-names = "per";
status = "disabled";
};
+
+ gpt1: gpt1@401ec000 {
+ compatible = "fsl,imxrt-gpt";
+ reg = <0x401ec000 0x4000>;
+ interrupts = <100>;
+ clocks = <&osc>;
+ status = "disabled";
+ };
};
};
--
2.25.1
Re: [PATCH v3 18/22] video: mxsfb: add enabling of "disp_axi" clock
Sorry for this patch sent twice. My e-mail provider doesn't let me send
more than 18 e-mail at a time, so I need to send it in 2 times and I've
left this.
Best regards
--
Giulio Benetti
Benetti Engineering sas
On 5/13/21 12:19 PM, Giulio Benetti wrote:
Some SoC needs "disp_axi" clock to be enabled, so let's try to retrieve it
and enabling. If it fails it gives only a debug(), but this clock as well
as "axi" clock is not mandatory.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 147bd668fe..523d8a8d98 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -98,6 +98,17 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
return;
}
}
+
+ ret = clk_get_by_name(dev, "disp_axi", &clk);
+ if (!ret) {
+ debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__,
ret);
+ } else {
+ ret = clk_enable(&clk);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs disp_axi clk: %d\n",
ret);
+ return;
+ }
+ }
#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
[PATCH v3 20/22] ARM: dts: imxrt1050: move lcdif assigned clock to dtsi
Since we assume pll5 is the default lcdif clock source let's move
assigned-clocks(-parents) properties to .dtsi file.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 3 ---
arch/arm/dts/imxrt1050.dtsi| 2 ++
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index 2052d4eb4e..dc66fc9c37 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -238,9 +238,6 @@
display = <&display0>;
status = "okay";
- assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
- assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
-
display0: display0 {
bits-per-pixel = <16>;
bus-width = <16>;
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 6f9da3fe8a..eb5e09e971 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -152,6 +152,8 @@
interrupts = ;
clocks = <&clks IMXRT1050_CLK_LCDIF>;
clock-names = "per";
+ assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
+ assigned-clock-parents = <&clks
IMXRT1050_CLK_PLL5_VIDEO>;
status = "disabled";
};
--
2.25.1
[PATCH v3 22/22] ARM: dts: imxrt1050-evk: remove u-boot,dm-spl
We don't need lcdif to be enable in SPL, so let's remove u-boot,dm-spl.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index dc66fc9c37..81db1a446d 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -189,7 +189,6 @@
};
pinctrl_lcdif: lcdifgrp {
- u-boot,dm-spl;
fsl,pins = <
MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK
0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE
0x1b0b1
--
2.25.1
[PATCH v3 10/22] ARM: dts: imxrt1050: add node label to osc
Let's add node label to osc to be used as clock source for other nodes.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index a9281001e5..b7cc3fbc2a 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -28,7 +28,7 @@
clocks {
u-boot,dm-spl;
- osc {
+ osc: osc {
u-boot,dm-spl;
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
--
2.25.1
[PATCH v3 17/22] video: mxsfb: add enabling of "axi" clock other than "per" clock
On some SoC mxsfb needs more than one clock gate(actual "per" clock). So
let's introduce "axi" clock that can be provided but it's not mandatory.
This is inspired from linux mxsfb driver. Also let's rename "per" clock to
"pix" clock for compatibility with already existing .dts lcdif nodes
implementation.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index e1fd36a62d..147bd668fe 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -67,26 +67,37 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
uint32_t vdctrl0;
#if CONFIG_IS_ENABLED(CLK)
- struct clk per_clk;
+ struct clk clk;
int ret;
- ret = clk_get_by_name(dev, "per", &per_clk);
+ ret = clk_get_by_name(dev, "pix", &clk);
if (ret) {
- dev_err(dev, "Failed to get mxs clk: %d\n", ret);
+ dev_err(dev, "Failed to get mxs pix clk: %d\n", ret);
return;
}
- ret = clk_set_rate(&per_clk, timings->pixelclock.typ);
+ ret = clk_set_rate(&clk, timings->pixelclock.typ);
if (ret < 0) {
- dev_err(dev, "Failed to set mxs clk: %d\n", ret);
+ dev_err(dev, "Failed to set mxs pix clk: %d\n", ret);
return;
}
- ret = clk_enable(&per_clk);
+ ret = clk_enable(&clk);
if (ret < 0) {
- dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
+ dev_err(dev, "Failed to enable mxs pix clk: %d\n", ret);
return;
}
+
+ ret = clk_get_by_name(dev, "axi", &clk);
+ if (!ret) {
+ debug("%s: Failed to get mxs axi clk: %d\n", __func__, ret);
+ } else {
+ ret = clk_enable(&clk);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs axi clk: %d\n", ret);
+ return;
+ }
+ }
#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
--
2.25.1
[PATCH v3 16/22] configs: imxrt1050-evk: enable imx gpt timer as tick-timer
Let's enable imx-gpt-timer in imx1050-evk defconfig. Signed-off-by: Giulio Benetti --- configs/imxrt1050-evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index d03572e7db..9c8bdb07dc 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -64,6 +64,7 @@ CONFIG_IMXRT_SDRAM=y CONFIG_FSL_LPUART=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y CONFIG_DM_VIDEO=y CONFIG_BACKLIGHT_GPIO=y CONFIG_SYS_WHITE_ON_BLACK=y -- 2.25.1
[PATCH v3 01/22] arm: imxrt: soc: make mpu regions generic
This mpu handling works for every i.MXRT SoC that we have, so let's
generalize imxrt1050_region_config to imxrt_region_config.
Signed-off-by: Giulio Benetti
---
arch/arm/mach-imx/imxrt/soc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c
index 8e7d15160d..c533f3554a 100644
--- a/arch/arm/mach-imx/imxrt/soc.c
+++ b/arch/arm/mach-imx/imxrt/soc.c
@@ -14,7 +14,7 @@ int arch_cpu_init(void)
{
int i;
- struct mpu_region_config imxrt1050_region_config[] = {
+ struct mpu_region_config imxrt_region_config[] = {
{ 0x, REGION_0, XN_DIS, PRIV_RW_USR_RW,
STRONG_ORDER, REGION_4GB },
{ PHYS_SDRAM, REGION_1, XN_DIS, PRIV_RW_USR_RW,
@@ -29,8 +29,8 @@ int arch_cpu_init(void)
* the whole 4GB address space.
*/
disable_mpu();
- for (i = 0; i < ARRAY_SIZE(imxrt1050_region_config); i++)
- mpu_config(&imxrt1050_region_config[i]);
+ for (i = 0; i < ARRAY_SIZE(imxrt_region_config); i++)
+ mpu_config(&imxrt_region_config[i]);
enable_mpu();
return 0;
--
2.25.1
[PATCH v3 12/22] ARM: dts: imxrt1050-evk: enable gpt1 timer
Enable gpt1 timer.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index b5e781275e..e592330332 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -215,6 +215,10 @@
};
};
+&gpt1 {
+ status = "okay";
+};
+
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
--
2.25.1
[PATCH v3 03/22] ARM: dts: imxrt1020: add node label to osc
Let's add node label to osc to be used as clock source for other nodes.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
index 97f3cec9f3..0a3a3b451a 100644
--- a/arch/arm/dts/imxrt1020.dtsi
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -36,7 +36,7 @@
clock-frequency = <0>;
};
- osc {
+ osc: osc {
u-boot,dm-spl;
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
--
2.25.1
[PATCH v3 09/22] configs: imxrt1020-evk: enable imx gpt timer as tick-timer
Let's enable imx-gpt-timer in imx1020-evk defconfig. Signed-off-by: Giulio Benetti --- configs/imxrt1020-evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig index ad408ebef8..f0b05b7165 100644 --- a/configs/imxrt1020-evk_defconfig +++ b/configs/imxrt1020-evk_defconfig @@ -61,6 +61,7 @@ CONFIG_IMXRT_SDRAM=y CONFIG_FSL_LPUART=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y CONFIG_SHA1=y CONFIG_SHA256=y CONFIG_HEXDUMP=y -- 2.25.1
[PATCH v3 08/22] ARM: dts: imxrt1020-evk: add device_type = "memory" to memory node
Now device_type = "memory" is mandatory to allow u-boot to read memory
node, so let's add it to memory node.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020-evk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index b527206fcf..2da79e5c20 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -20,6 +20,7 @@
};
memory {
+ device_type = "memory";
reg = <0x8000 0x200>;
};
};
--
2.25.1
[PATCH v3 06/22] ARM: dts: imxrt1020-evk: set gpt1 as tick-timer for u-boot
Let's set gpt1 as u-boot timer.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020-evk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index a471ff3838..b527206fcf 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -16,6 +16,7 @@
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
+ tick-timer = &gpt1;
};
memory {
--
2.25.1
[PATCH v3 05/22] ARM: dts: imxrt1020-evk: enable gpt1 timer
Enable gpt1 timer.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020-evk.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index ece13601bd..a471ff3838 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -186,6 +186,10 @@
};
};
+&gpt1 {
+ status = "okay";
+};
+
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
--
2.25.1
[PATCH v3 04/22] ARM: dts: imxrt1020: add gpt1 node
Add gpt1 node for using it as timer.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
index 0a3a3b451a..cab608c644 100644
--- a/arch/arm/dts/imxrt1020.dtsi
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -129,5 +129,13 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ gpt1: gpt1@401ec000 {
+ compatible = "fsl,imxrt-gpt";
+ reg = <0x401ec000 0x4000>;
+ interrupts = <100>;
+ clocks = <&osc>;
+ status = "disabled";
+ };
};
};
--
2.25.1
[PATCH v3 02/22] timer: imx-gpt: Add timer support for i.MX SoCs family
This timer driver uses GPT Timer (General Purpose Timer) available on
a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator
as well as peripheral clock.
Signed-off-by: Giulio Benetti
[Giulio: added the driver's stub and handled peripheral clock prescaler
setting making driver to work correctly]
Signed-off-by: Jesse Taube
[Jesse: added init, setting prescaler for 24Mhz support and enabling
timer]
---
drivers/timer/Kconfig | 7 ++
drivers/timer/Makefile| 1 +
drivers/timer/imx-gpt-timer.c | 162 ++
3 files changed, 170 insertions(+)
create mode 100644 drivers/timer/imx-gpt-timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 80743a2551..ee81dfa776 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -227,4 +227,11 @@ config MCHP_PIT64B_TIMER
Select this to enable support for Microchip 64-bit periodic
interval timer.
+config IMX_GPT_TIMER
+ bool "NXP i.MX GPT timer support"
+ depends on TIMER
+ help
+ Select this to enable support for the timer found on
+ NXP i.MX devices.
+
endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index eb5c48cc6c..e214ba7268 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
obj-$(CONFIG_MCHP_PIT64B_TIMER)+= mchp-pit64b-timer.o
+obj-$(CONFIG_IMX_GPT_TIMER)+= imx-gpt-timer.o
diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c
new file mode 100644
index 00..72be297754
--- /dev/null
+++ b/drivers/timer/imx-gpt-timer.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021
+ * Author(s): Giulio Benetti
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define GPT_CR_EN BIT(0)
+#define GPT_CR_FRR BIT(9)
+#define GPT_CR_EN_24M BIT(10)
+#define GPT_CR_SWR BIT(15)
+
+#define GPT_PR_PRESCALER24M_MASK 0xF000
+#define GPT_PR_PRESCALER24M_SHIFT 12
+#define GPT_PR_PRESCALER24M_MAX(GPT_PR_PRESCALER24M_MASK >>
GPT_PR_PRESCALER24M_SHIFT)
+#define GPT_PR_PRESCALER_MASK 0x0FFF
+#define GPT_PR_PRESCALER_SHIFT 0
+#define GPT_PR_PRESCALER_MAX (GPT_PR_PRESCALER_MASK >>
GPT_PR_PRESCALER_SHIFT)
+
+#define GPT_CLKSRC_IPG_CLK (1 << 6)
+#define GPT_CLKSRC_IPG_CLK_24M (5 << 6)
+
+/* If CONFIG_SYS_HZ_CLOCK not specified et's default to 3Mhz */
+#ifndef CONFIG_SYS_HZ_CLOCK
+#define CONFIG_SYS_HZ_CLOCK300
+#endif
+
+struct imx_gpt_timer_regs {
+ u32 cr;
+ u32 pr;
+ u32 sr;
+ u32 ir;
+ u32 ocr1;
+ u32 ocr2;
+ u32 ocr3;
+ u32 icr1;
+ u32 icr2;
+ u32 cnt;
+};
+
+struct imx_gpt_timer_priv {
+ struct imx_gpt_timer_regs *base;
+};
+
+static u64 imx_gpt_timer_get_count(struct udevice *dev)
+{
+ struct imx_gpt_timer_priv *priv = dev_get_priv(dev);
+ struct imx_gpt_timer_regs *regs = priv->base;
+
+ return timer_conv_64(readl(®s->cnt));
+}
+
+static int imx_gpt_setup(struct imx_gpt_timer_regs *regs, u32 rate)
+{
+ u32 prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+
+ /* Reset the timer */
+ setbits_le32(®s->cr, GPT_CR_SWR);
+
+ /* Wait for timer to finish reset */
+ while (readl(®s->cr) & GPT_CR_SWR)
+ ;
+
+ if (rate == 2400UL) {
+ /* Set timer frequency if using 24M clock source */
+ if (prescaler > GPT_PR_PRESCALER24M_MAX)
+ return -EINVAL;
+
+ /* Set 24M prescaler */
+ writel((prescaler << GPT_PR_PRESCALER24M_SHIFT), ®s->pr);
+ /* Set Oscillator as clock source, enable 24M input and set gpt
+* in free-running mode
+*/
+ writel(GPT_CLKSRC_IPG_CLK_24M | GPT_CR_EN_24M | GPT_CR_FRR,
®s->cr);
+ } else {
+ if (prescaler > GPT_PR_PRESCALER_MAX)
+ return -EINVAL;
+
+ /* Set prescaler */
+ writel((prescaler << GPT_PR_PRESCALER_SHIFT), ®s->pr);
+ /* Set Peripheral as clock source and set gpt in free-running
+* mode
+*/
+ writel(GPT_CLKSRC_IPG_CLK | GPT_CR_FRR, ®s->cr);
+ }
+
+ /* Start timer */
+ setbits_le32(®s->cr, GPT_CR_EN);
+
+ return 0;
+}
+
+static int imx_gpt_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct imx_gpt_timer_priv *priv = dev_get_priv(dev);
+ struct imx_gpt_timer_regs *regs;
+ s
[PATCH v3 00/22] Fix i.MXRT1020/50
This patchset adds imx-gpt-timer driver that is supported by i.MXRT and also a lot of other i.MX* SoCs. This driver is needed for i.MXRT SoC family that is lacking at the moment the timer at all and that makes u-boot to fail running on i.MXRT. There are also some fixes in imxrt10*0-evk.dts and other minor fixed and improvements and specifically on imxrt1050 has been fixed lcdif init hang. --- V1->V2: * fixed 32 to 64 bit conversion on timer as suggested by Sean Anderson V2->V3: * merge with patchset with https://patchwork.ozlabs.org/project/uboot/list/?series=238842&state=* that fixes lcdif init hang * improve some commit log --- Giulio Benetti (22): arm: imxrt: soc: make mpu regions generic timer: imx-gpt: Add timer support for i.MX SoCs family ARM: dts: imxrt1020: add node label to osc ARM: dts: imxrt1020: add gpt1 node ARM: dts: imxrt1020-evk: enable gpt1 timer ARM: dts: imxrt1020-evk: set gpt1 as tick-timer for u-boot ARM: dts: imxrt1020-evk-u-boot: make gpt1 present for SPL ARM: dts: imxrt1020-evk: add device_type = "memory" to memory node configs: imxrt1020-evk: enable imx gpt timer as tick-timer ARM: dts: imxrt1050: add node label to osc ARM: dts: imxrt1050: add gpt1 node ARM: dts: imxrt1050-evk: enable gpt1 timer ARM: dts: imxrt1050-evk: set gpt1 as tick-timer for u-boot ARM: dts: imxrt1050-evk-u-boot: make gpt1 present for SPL ARM: dts: imxrt1050-evk: add device_type = "memory" to memory node configs: imxrt1050-evk: enable imx gpt timer as tick-timer video: mxsfb: add enabling of "axi" clock other than "per" clock video: mxsfb: add enabling of "disp_axi" clock clk: imx: clk-imxrt1050: introduce LCDIF_PIX and rename LCDIF to LCDIF_APB ARM: dts: imxrt1050: move lcdif assigned clock to dtsi ARM: dts: imxrt1050: set lcdif clocks according to mxsfb driver ARM: dts: imxrt1050-evk: remove u-boot,dm-spl arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 4 + arch/arm/dts/imxrt1020-evk.dts | 6 + arch/arm/dts/imxrt1020.dtsi | 10 +- arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 4 + arch/arm/dts/imxrt1050-evk.dts | 10 +- arch/arm/dts/imxrt1050.dtsi | 17 +- arch/arm/mach-imx/imxrt/soc.c | 6 +- configs/imxrt1020-evk_defconfig | 1 + configs/imxrt1050-evk_defconfig | 1 + drivers/clk/imx/clk-imxrt1050.c | 6 +- drivers/timer/Kconfig | 7 + drivers/timer/Makefile | 1 + drivers/timer/imx-gpt-timer.c | 162 drivers/video/mxsfb.c | 36 - include/dt-bindings/clock/imxrt1050-clock.h | 5 +- 15 files changed, 254 insertions(+), 22 deletions(-) create mode 100644 drivers/timer/imx-gpt-timer.c -- 2.25.1
[PATCH v3 00/22] Fix i.MXRT1020/50
This patchset adds imx-gpt-timer driver that is supported by i.MXRT and also a lot of other i.MX* SoCs. This driver is needed for i.MXRT SoC family that is lacking at the moment the timer at all and that makes u-boot to fail running on i.MXRT. There are also some fixes in imxrt10*0-evk.dts and other minor fixed and improvements and specifically on imxrt1050 has been fixed lcdif init hang. --- V1->V2: * fixed 32 to 64 bit conversion on timer as suggested by Sean Anderson V2->V3: * merge with patchset with https://patchwork.ozlabs.org/project/uboot/list/?series=238842&state=* that fixes lcdif init hang * improve some commit log --- Giulio Benetti (22): arm: imxrt: soc: make mpu regions generic timer: imx-gpt: Add timer support for i.MX SoCs family ARM: dts: imxrt1020: add node label to osc ARM: dts: imxrt1020: add gpt1 node ARM: dts: imxrt1020-evk: enable gpt1 timer ARM: dts: imxrt1020-evk: set gpt1 as tick-timer for u-boot ARM: dts: imxrt1020-evk-u-boot: make gpt1 present for SPL ARM: dts: imxrt1020-evk: add device_type = "memory" to memory node configs: imxrt1020-evk: enable imx gpt timer as tick-timer ARM: dts: imxrt1050: add node label to osc ARM: dts: imxrt1050: add gpt1 node ARM: dts: imxrt1050-evk: enable gpt1 timer ARM: dts: imxrt1050-evk: set gpt1 as tick-timer for u-boot ARM: dts: imxrt1050-evk-u-boot: make gpt1 present for SPL ARM: dts: imxrt1050-evk: add device_type = "memory" to memory node configs: imxrt1050-evk: enable imx gpt timer as tick-timer video: mxsfb: add enabling of "axi" clock other than "per" clock video: mxsfb: add enabling of "disp_axi" clock clk: imx: clk-imxrt1050: introduce LCDIF_PIX and rename LCDIF to LCDIF_APB ARM: dts: imxrt1050: move lcdif assigned clock to dtsi ARM: dts: imxrt1050: set lcdif clocks according to mxsfb driver ARM: dts: imxrt1050-evk: remove u-boot,dm-spl arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 4 + arch/arm/dts/imxrt1020-evk.dts | 6 + arch/arm/dts/imxrt1020.dtsi | 10 +- arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 4 + arch/arm/dts/imxrt1050-evk.dts | 10 +- arch/arm/dts/imxrt1050.dtsi | 17 +- arch/arm/mach-imx/imxrt/soc.c | 6 +- configs/imxrt1020-evk_defconfig | 1 + configs/imxrt1050-evk_defconfig | 1 + drivers/clk/imx/clk-imxrt1050.c | 6 +- drivers/timer/Kconfig | 7 + drivers/timer/Makefile | 1 + drivers/timer/imx-gpt-timer.c | 162 drivers/video/mxsfb.c | 36 - include/dt-bindings/clock/imxrt1050-clock.h | 5 +- 15 files changed, 254 insertions(+), 22 deletions(-) create mode 100644 drivers/timer/imx-gpt-timer.c -- 2.25.1
Re: [PATCH 0/5] Fix i.MXRT1050 hang on lcdif init and improve DT for mxsfb
Hi Stefano, On 5/2/21 1:44 AM, Giulio Benetti wrote: On 4/13/21 1:05 AM, Giulio Benetti wrote: On 4/13/21 1:03 AM, Giulio Benetti wrote: This patchset fixes u-boot hang on i.MXRT1050 while setting lcdif in mxsfb driver. There are 2 gates to be enabled to initialize mxsfb so let's introduce the missing gate as a clock and rename "per" clock to "pix" clock since in the other .dts files using *-lcdif "pix" is used. This patchset add also "disp_axi" clock enabling in mxsfb that should make able to every i.MX SoC with lcdif using DT. I didn't test it other than i.MXRT1050 since I don't have the boards. If someone can test it it would be great. Note that i.MX23/28 should fail using DT instead because they don't specify any clock-names in their dts. I've forgotten to specify that this patchset depends on this patchset: https://patchwork.ozlabs.org/project/uboot/list/?series=237909 This ^^^ series is superseeded by v2: https://patchwork.ozlabs.org/project/uboot/list/?series=241701 Current patchset is not superseeded, only the one which depends to is superseeded by v2. Do you prefer me to send a unique patchset with all patches of both patchsets? Kind regards -- Giulio Benetti Benetti Engineering sas
Re: [PATCH 03/16] ARM: dts: imxrt1020: add alias to osc
> Il giorno 3 mag 2021, alle ore 20:21, Fabio Estevam ha > scritto: > > On Mon, May 3, 2021 at 2:52 PM Giulio Benetti > wrote: > >> Ok, is it ok if it even repeats the first line? Because I don’t know what >> write more than that. > > Yes, that would be fine. Ok thank you. This was a doubt I always had. Giulio
Re: [PATCH 03/16] ARM: dts: imxrt1020: add alias to osc
Hi Gabio,
> Il giorno 3 mag 2021, alle ore 16:01, Fabio Estevam ha
> scritto:
>
> Hi Giulio,
>
>> On Wed, Apr 7, 2021 at 4:03 PM Giulio Benetti
>> wrote:
>>
>> Signed-off-by: Giulio Benetti
>> ---
>> arch/arm/dts/imxrt1020.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
>> index 97f3cec9f3..0a3a3b451a 100644
>> --- a/arch/arm/dts/imxrt1020.dtsi
>> +++ b/arch/arm/dts/imxrt1020.dtsi
>> @@ -36,7 +36,7 @@
>>clock-frequency = <0>;
>>};
>>
>> - osc {
>> + osc: osc {
>
> Nit: what you are adding here is a "node label", not an "alias".
Thank you, you’re right.
>
> It would be nice to always add a commit log, even if it is a short one.
Ok, is it ok if it even repeats the first line? Because I don’t know what write
more than that.
Best regards
Giulio Benetti
Re: [PATCH 0/5] Fix i.MXRT1050 hang on lcdif init and improve DT for mxsfb
On 4/13/21 1:05 AM, Giulio Benetti wrote: On 4/13/21 1:03 AM, Giulio Benetti wrote: This patchset fixes u-boot hang on i.MXRT1050 while setting lcdif in mxsfb driver. There are 2 gates to be enabled to initialize mxsfb so let's introduce the missing gate as a clock and rename "per" clock to "pix" clock since in the other .dts files using *-lcdif "pix" is used. This patchset add also "disp_axi" clock enabling in mxsfb that should make able to every i.MX SoC with lcdif using DT. I didn't test it other than i.MXRT1050 since I don't have the boards. If someone can test it it would be great. Note that i.MX23/28 should fail using DT instead because they don't specify any clock-names in their dts. I've forgotten to specify that this patchset depends on this patchset: https://patchwork.ozlabs.org/project/uboot/list/?series=237909 This ^^^ series is superseeded by v2: https://patchwork.ozlabs.org/project/uboot/list/?series=241701 Best regards -- Giulio Benetti Benetti Engineering sas
[PATCH v2 16/16] configs: imxrt1050-evk: enable imx gpt timer as tick-timer
Signed-off-by: Giulio Benetti --- configs/imxrt1050-evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index f639ea7623..e74473511d 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -65,6 +65,7 @@ CONFIG_IMXRT_SDRAM=y CONFIG_FSL_LPUART=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y CONFIG_DM_VIDEO=y CONFIG_BACKLIGHT_GPIO=y CONFIG_SYS_WHITE_ON_BLACK=y -- 2.25.1
[PATCH v2 15/16] ARM: dts: imxrt1050-evk: add device_type = "memory" to memory node
Now device_type = "memory" is mandatory to allow u-boot to read memory
node, so let's add it to memory node.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index 6d21f2b738..2052d4eb4e 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -20,6 +20,7 @@
};
memory {
+ device_type = "memory";
reg = <0x8000 0x200>;
};
};
--
2.25.1
[PATCH v2 14/16] ARM: dts: imxrt1050-evk-u-boot: make gpt1 present for SPL
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index fb4f7f6f9d..a4b50f0bb2 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -10,6 +10,10 @@
};
};
+&gpt1 {
+ u-boot,dm-spl;
+};
+
&lpuart1 { /* console */
u-boot,dm-spl;
};
--
2.25.1
[PATCH v2 13/16] ARM: dts: imxrt1050-evk: set gpt1 as tick-timer for u-boot
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index e592330332..6d21f2b738 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -16,6 +16,7 @@
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
+ tick-timer = &gpt1;
};
memory {
--
2.25.1
[PATCH v2 12/16] ARM: dts: imxrt1050-evk: enable gpt1 timer
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index b5e781275e..e592330332 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -215,6 +215,10 @@
};
};
+&gpt1 {
+ status = "okay";
+};
+
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
--
2.25.1
[PATCH v2 11/16] ARM: dts: imxrt1050: add gpt1 node
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index b7cc3fbc2a..6f9da3fe8a 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -154,5 +154,13 @@
clock-names = "per";
status = "disabled";
};
+
+ gpt1: gpt1@401ec000 {
+ compatible = "fsl,imxrt-gpt";
+ reg = <0x401ec000 0x4000>;
+ interrupts = <100>;
+ clocks = <&osc>;
+ status = "disabled";
+ };
};
};
--
2.25.1
[PATCH v2 10/16] ARM: dts: imxrt1050: add alias to osc
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index a9281001e5..b7cc3fbc2a 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -28,7 +28,7 @@
clocks {
u-boot,dm-spl;
- osc {
+ osc: osc {
u-boot,dm-spl;
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
--
2.25.1
[PATCH v2 09/16] configs: imxrt1020-evk: enable imx gpt timer as tick-timer
Signed-off-by: Giulio Benetti --- configs/imxrt1020-evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig index 9bddb69cd4..51ff702bc6 100644 --- a/configs/imxrt1020-evk_defconfig +++ b/configs/imxrt1020-evk_defconfig @@ -62,6 +62,7 @@ CONFIG_IMXRT_SDRAM=y CONFIG_FSL_LPUART=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y CONFIG_SHA1=y CONFIG_SHA256=y CONFIG_HEXDUMP=y -- 2.25.1
[PATCH v2 08/16] ARM: dts: imxrt1020-evk: add device_type = "memory" to memory node
Now device_type = "memory" is mandatory to allow u-boot to read memory
node, so let's add it to memory node.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020-evk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index b527206fcf..2da79e5c20 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -20,6 +20,7 @@
};
memory {
+ device_type = "memory";
reg = <0x8000 0x200>;
};
};
--
2.25.1
[PATCH v2 07/16] ARM: dts: imxrt1020-evk-u-boot: make gpt1 present for SPL
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index d32c98de9c..34d19e06c5 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -10,6 +10,10 @@
};
};
+&gpt1 {
+ u-boot,dm-spl;
+};
+
&lpuart1 { /* console */
u-boot,dm-spl;
};
--
2.25.1
[PATCH v2 06/16] ARM: dts: imxrt1020-evk: set gpt1 as tick-timer for u-boot
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020-evk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index a471ff3838..b527206fcf 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -16,6 +16,7 @@
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
+ tick-timer = &gpt1;
};
memory {
--
2.25.1
[PATCH v2 05/16] ARM: dts: imxrt1020-evk: enable gpt1 timer
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020-evk.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index ece13601bd..a471ff3838 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -186,6 +186,10 @@
};
};
+&gpt1 {
+ status = "okay";
+};
+
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
--
2.25.1
