[PATCH 00/11] drivers: Driver support for ADI SC5xx SoCs
This series adds all of the supported peripheral drivers for the sc5xx series of SoCs from Analog Devices and other drivers that are used by the evaluation kits, such as a GPIO expander used by the EZLITE carrier boards. This series is based on uboot/next as it references the sc5xx machine type at times and currently passes CI. Greg Malysa (4): pinctrl: Add support for ADI SC5XX-family pinctrl gpio: Add support for SC5XX-family processor GPIO driver net: Add support for ADI SC5xx SoCs with DWC QoS ethernet dma: Add driver for ADI SC5xx-family SoC MDMA functionality Nathan Barrett-Morrison (7): gpio: Add support for ADI ADP5588 GPIO expander chips usb: musb-new: Add support for Analog Devices SC5xx SoCs i2c: Add support for ADI SC5XX-family I2C peripheral watchdog: Add support for ADI SC5XX-family watchdog peripheral remoteproc: Add in SHARC loading for ADI SC5XX-family processors spi: Add support for ADI SC5XX-family processor SPI peripherals mmc: Add support for ADI SC5XX-family processor SDHCI peripherals MAINTAINERS| 11 + drivers/dma/Kconfig| 7 + drivers/dma/Makefile | 1 + drivers/dma/adi_dma.c | 255 + drivers/gpio/Kconfig | 17 + drivers/gpio/Makefile | 2 + drivers/gpio/adp5588_gpio.c| 208 drivers/gpio/gpio-adi-adsp.c | 179 +++ drivers/i2c/Kconfig| 7 + drivers/i2c/Makefile | 1 + drivers/i2c/adi_i2c.c | 393 ++ drivers/mmc/Kconfig| 8 + drivers/mmc/Makefile | 1 + drivers/mmc/adi_sdhci.c| 152 ++ drivers/net/Kconfig| 7 + drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 6 + drivers/net/dwc_eth_qos.h | 2 + drivers/net/dwc_eth_qos_adi.c | 101 drivers/pinctrl/Kconfig| 8 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-adi-adsp.c | 156 ++ drivers/remoteproc/Kconfig | 11 + drivers/remoteproc/Makefile| 1 + drivers/remoteproc/adi_sc5xx_rproc.c | 276 ++ drivers/spi/Kconfig| 6 + drivers/spi/Makefile | 1 + drivers/spi/adi_spi3.c | 690 + drivers/usb/musb-new/Kconfig | 7 + drivers/usb/musb-new/Makefile | 1 + drivers/usb/musb-new/sc5xx.c | 202 drivers/watchdog/Kconfig | 9 + drivers/watchdog/Makefile | 1 + drivers/watchdog/adi_wdt.c | 145 ++ include/dt-bindings/pinctrl/adi-adsp.h | 21 + 35 files changed, 2895 insertions(+) create mode 100644 drivers/dma/adi_dma.c create mode 100644 drivers/gpio/adp5588_gpio.c create mode 100644 drivers/gpio/gpio-adi-adsp.c create mode 100644 drivers/i2c/adi_i2c.c create mode 100644 drivers/mmc/adi_sdhci.c create mode 100644 drivers/net/dwc_eth_qos_adi.c create mode 100644 drivers/pinctrl/pinctrl-adi-adsp.c create mode 100644 drivers/remoteproc/adi_sc5xx_rproc.c create mode 100644 drivers/spi/adi_spi3.c create mode 100644 drivers/usb/musb-new/sc5xx.c create mode 100644 drivers/watchdog/adi_wdt.c create mode 100644 include/dt-bindings/pinctrl/adi-adsp.h -- 2.43.2
[PATCH 11/11] mmc: Add support for ADI SC5XX-family processor SDHCI peripherals
From: Nathan Barrett-Morrison
Co-developed-by: Greg Malysa
Signed-off-by: Greg Malysa
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Artamonovs
Signed-off-by: Nathan Barrett-Morrison
---
MAINTAINERS | 1 +
drivers/mmc/Kconfig | 8 +++
drivers/mmc/Makefile| 1 +
drivers/mmc/adi_sdhci.c | 152
4 files changed, 162 insertions(+)
create mode 100644 drivers/mmc/adi_sdhci.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 1131c85d22..b4c00c4d5a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -614,6 +614,7 @@ F: drivers/dma/adi_dma.c
F: drivers/gpio/adp5588_gpio.c
F: drivers/gpio/gpio-adi-adsp.c
F: drivers/i2c/adi_i2c.c
+F: drivers/mmc/adi_sdhci.c
F: drivers/net/dwc_eth_qos_adi.c
F: drivers/pinctrl/pinctrl-adi-adsp.c
F: drivers/remoteproc/adi_sc5xx_rproc.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index d0944793c9..f32c8a3c13 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -283,6 +283,14 @@ config MMC_DW_ROCKCHIP
SD 3.0, SDIO 3.0 and MMC 4.5 and supports common eMMC chips as well
as removeable SD and micro-SD cards.
+config MMC_SDHCI_ADI
+ bool "ADI SD/MMC controller support"
+ depends on DM_MMC && OF_CONTROL
+ depends on MMC_SDHCI && MMC_SDHCI_ADMA
+ help
+ This enables support for the SD/MMC controller included in some Analog
+ Devices SC5XX Socs.
+
config MMC_DW_SOCFPGA
bool "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
depends on ARCH_SOCFPGA
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 72c3fb66ce..eac8c28ee5 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_MMC_SDHCI_MV)+= mv_sdhci.o
obj-$(CONFIG_MMC_SDHCI_NPCM)+= npcm_sdhci.o
obj-$(CONFIG_MMC_SDHCI_PIC32) += pic32_sdhci.o
obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_ADI)+= adi_sdhci.o
obj-$(CONFIG_MMC_SDHCI_S5P)+= s5p_sdhci.o
obj-$(CONFIG_MMC_SDHCI_STI)+= sti_sdhci.o
obj-$(CONFIG_MMC_SDHCI_TANGIER)+= tangier_sdhci.o
diff --git a/drivers/mmc/adi_sdhci.c b/drivers/mmc/adi_sdhci.c
new file mode 100644
index 00..a8484e0e7a
--- /dev/null
+++ b/drivers/mmc/adi_sdhci.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison
+ * Contact: Greg Malysa
+ *
+ * Based on Rockchip's sdhci.c file
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/* 400KHz is max freq for card ID etc. Use that as min */
+#define EMMC_MIN_FREQ 40
+
+#define ADMA_BOUNDARY_ALGN SZ_128M
+#define BOUNDARY_OK(addr, len) \
+ (((addr) | (ADMA_BOUNDARY_ALGN - 1)) == (((addr) + (len) - 1) | \
+ (ADMA_BOUNDARY_ALGN - 1)))
+/* We split a descriptor for every crossing of the ADMA alignment boundary,
+ * so we need an additional descriptor for every expected crossing.
+ * As I understand it, the max expected transaction size is:
+ * CONFIG_SYS_MMC_MAX_BLK_COUNT * MMC_MAX_BLOCK_LEN
+ *
+ * With the way the SDHCI-ADMA driver is implemented, if ADMA_MAX_LEN was a
+ * clean power of two, we'd only ever need +1 descriptor as the first
+ * descriptor that got split would then bring the remaining DMA
+ * destination addresses into alignment. Unfortunately, it's currently
+ * hardcoded to a non-power-of-two value.
+ *
+ * If that ever becomes parameterized, ADMA max length can be set to
+ * 0x1, and set this to 1.
+ */
+#define ADMA_POTENTIAL_CROSSINGS \
+ DIV_ROUND_UP((CONFIG_SYS_MMC_MAX_BLK_COUNT * MMC_MAX_BLOCK_LEN), \
+ADMA_BOUNDARY_ALGN)
+/* +1 descriptor for each crossing.
+ */
+#define ADMA_TABLE_EXTRA_SZ (ADMA_POTENTIAL_CROSSINGS * ADMA_DESC_LEN)
+
+struct adi_sdhc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct adi_sdhc {
+ struct sdhci_host host;
+ void *base;
+};
+
+void adi_dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
+dma_addr_t addr, int len, bool end)
+{
+ int tmplen, offset;
+
+ if (likely(!len || BOUNDARY_OK(addr, len))) {
+ sdhci_adma_write_desc(host, desc, addr, len, end);
+ return;
+ }
+
+ offset = addr & (ADMA_BOUNDARY_ALGN - 1);
+ tmplen = ADMA_BOUNDARY_ALGN - offset;
+ sdhci_adma_write_desc(host, desc, addr, tmplen, false);
+
+ addr += tmplen;
+ len -= tmplen;
+ sdhci_adma_write_desc(host, desc, addr, len, end);
+}
+
+struct sdhci_ops adi_dwcmshc_sdhci_ops = {
+ .adma_write_desc = adi_dwcmshc_adma_write_desc,
+};
+
+static int adi
[PATCH 10/11] spi: Add support for ADI SC5XX-family processor SPI peripherals
From: Nathan Barrett-Morrison This adds support for the ADI-specific SPI driver present in the ADI SC5xx line of SoCs. This IP block is distinct from the QSPI/OSPI block that uses the Cadence driver. Both may be used at once with appropriate pin muxing configuration. Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Angelo Dureghello Signed-off-by: Angelo Dureghello Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Co-developed-by: Piotr Wojtaszczyk Signed-off-by: Piotr Wojtaszczyk Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs Signed-off-by: Nathan Barrett-Morrison --- MAINTAINERS| 1 + drivers/spi/Kconfig| 6 + drivers/spi/Makefile | 1 + drivers/spi/adi_spi3.c | 690 + 4 files changed, 698 insertions(+) create mode 100644 drivers/spi/adi_spi3.c diff --git a/MAINTAINERS b/MAINTAINERS index 8ca7da4c02..1131c85d22 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -618,6 +618,7 @@ F: drivers/net/dwc_eth_qos_adi.c F: drivers/pinctrl/pinctrl-adi-adsp.c F: drivers/remoteproc/adi_sc5xx_rproc.c F: drivers/serial/serial_adi_uart4.c +F: drivers/spi/adi_spi3.c F: drivers/timer/adi_sc5xx_timer.c F: drivers/usb/musb-new/sc5xx.c F: drivers/watchdog/adi_wdt.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 35030ab355..6634494d84 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -52,6 +52,12 @@ config SPI_DIRMAP if DM_SPI +config ADI_SPI3 + bool "Enable ADI SPI Driver" + help + Enable the ADI (Analog Devices) SPI controller driver. This + driver enables the support for SC5XX spi controller. + config ALTERA_SPI bool "Altera SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 32d7bf7237..fa1b47f2f9 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -19,6 +19,7 @@ obj-y += spi.o obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o endif +obj-$(CONFIG_ADI_SPI3) += adi_spi3.o obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_APPLE_SPI) += apple_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o diff --git a/drivers/spi/adi_spi3.c b/drivers/spi/adi_spi3.c new file mode 100644 index 00..9e75050a89 --- /dev/null +++ b/drivers/spi/adi_spi3.c @@ -0,0 +1,690 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Converted to driver model by Nathan Barrett-Morrison + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + * Contact: Ian Roberts + * Contact: Piotr Wojtaszczyk + * + */ + +#include +#include +#include +#include +#include +#include + +#define SPI_IDLE_VAL 0xff + +#define MAX_CTRL_CS 7 + +/* SPI_CONTROL */ +#define SPI_CTL_EN 0x0001 /* Enable */ +#define SPI_CTL_MSTR0x0002 /* Master/Slave */ +#define SPI_CTL_PSSE0x0004 /* controls modf error in master mode */ +#define SPI_CTL_ODM 0x0008 /* Open Drain Mode */ +#define SPI_CTL_CPHA0x0010 /* Clock Phase */ +#define SPI_CTL_CPOL0x0020 /* Clock Polarity */ +#define SPI_CTL_ASSEL 0x0040 /* Slave Select Pin Control */ +#define SPI_CTL_SELST 0x0080 /* Slave Select Polarity in transfers */ +#define SPI_CTL_EMISO 0x0100 /*Enable MISO */ +#define SPI_CTL_SIZE0x0600 /*Word Transfer Size */ +#define SPI_CTL_SIZE08 0x /*SIZE: 8 bits */ +#define SPI_CTL_SIZE16 0x0200 /*SIZE: 16 bits */ +#define SPI_CTL_SIZE32 0x0400 /*SIZE: 32 bits */ +#define SPI_CTL_LSBF0x1000 /*LSB First */ +#define SPI_CTL_FCEN0x2000 /*Flow-Control Enable */ +#define SPI_CTL_FCCH0x4000 /*Flow-Control Channel Selection */ +#define SPI_CTL_FCPL0x8000 /*Flow-Control Polarity */ +#define SPI_CTL_FCWM0x0003 /*Flow-Control Water-Mark */ +#define SPI_CTL_FIFO0 0x /*FCWM: Tx empty or Rx Full */ +#define SPI_CTL_FIFO1 0x0001 /*FCWM: Tx empty or Rx full (>=75%) */ +#define SPI_CTL_FIFO2 0x0002 /*FCWM: Tx empty or Rx full (>=50%) */ +#define SPI_CTL_FMODE 0x0004 /*Fast-mode Enable */ +#define SPI_CTL_MIOM0x0030 /*Multiple I/O Mode */ +#define SPI_CTL_MIO_DIS 0x /*MIOM: Disable */ +#define SPI_CTL_MIO_DUAL0x0010 /*MIOM: Enable DIOM (Dual I/O Mode) */ +#define SPI_CTL_MIO_QUAD0x0020 /*MIOM: Enable QUAD (Quad SPI Mode) */ +#define SPI_CTL_SOSI0x0040 /*Start on MOSI */ +#define SPI_CTL_MMWEM 0x4000 /*Start on MMWEM */ +#define SPI_CTL_MMSE0x8000 /*Start on MMSE */ +/* SPI_RX_CONTROL */ +#define SPI_RXCTL_REN 0x0001 /*Receive Channel Enable */ +#define SPI_RXCTL_RTI 0x0004 /*Receive Transfer Initiate */ +#define SPI_RXCTL_RWCEN
[PATCH 09/11] remoteproc: Add in SHARC loading for ADI SC5XX-family processors
From: Nathan Barrett-Morrison This adds the ability to load ldr-formatted files to the SHARC coprocessors using the rproc interface. Only a minimal subset of rproc functionality is supported: loading and starting the remote core. Secure boot and signed ldr verification are not available at this time through the U-Boot interface. Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Co-developed-by: Piotr Wojtaszczyk Signed-off-by: Piotr Wojtaszczyk Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs Signed-off-by: Nathan Barrett-Morrison --- MAINTAINERS | 1 + drivers/remoteproc/Kconfig | 11 ++ drivers/remoteproc/Makefile | 1 + drivers/remoteproc/adi_sc5xx_rproc.c | 276 +++ 4 files changed, 289 insertions(+) create mode 100644 drivers/remoteproc/adi_sc5xx_rproc.c diff --git a/MAINTAINERS b/MAINTAINERS index ce92ce107d..8ca7da4c02 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -616,6 +616,7 @@ F: drivers/gpio/gpio-adi-adsp.c F: drivers/i2c/adi_i2c.c F: drivers/net/dwc_eth_qos_adi.c F: drivers/pinctrl/pinctrl-adi-adsp.c +F: drivers/remoteproc/adi_sc5xx_rproc.c F: drivers/serial/serial_adi_uart4.c F: drivers/timer/adi_sc5xx_timer.c F: drivers/usb/musb-new/sc5xx.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index a49802c132..3f7cebaeb7 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -13,6 +13,7 @@ config REMOTEPROC depends on DM # Please keep the configuration alphabetically sorted. + config K3_SYSTEM_CONTROLLER bool "Support for TI' K3 System Controller" select REMOTEPROC @@ -22,6 +23,16 @@ config K3_SYSTEM_CONTROLLER help Say 'y' here to add support for TI' K3 System Controller. +config REMOTEPROC_ADI_SC5XX + bool "Support for ADI SC5xx SHARC cores" + select REMOTEPROC + depends on DM + depends on ARCH_SC5XX + depends on SYSCON + help + Say 'y' here to add support for loading code onto SHARC cores in + an ADSP-SC5xx SoC from Analog Devices + config REMOTEPROC_SANDBOX bool "Support for Test processor for Sandbox" select REMOTEPROC diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index e09ed1aa4d..c2aaf6f8c3 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_$(SPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o # Remote proc drivers - Please keep this list alphabetically sorted. obj-$(CONFIG_K3_SYSTEM_CONTROLLER) += k3_system_controller.o +obj-$(CONFIG_REMOTEPROC_ADI_SC5XX) += adi_sc5xx_rproc.o obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o diff --git a/drivers/remoteproc/adi_sc5xx_rproc.c b/drivers/remoteproc/adi_sc5xx_rproc.c new file mode 100644 index 00..fc9730ef32 --- /dev/null +++ b/drivers/remoteproc/adi_sc5xx_rproc.c @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + * + * Analog Devices SC5xx remoteproc driver for loading code onto SHARC cores + */ + +#include +#include +#include +#include +#include +#include + +/* Register offsets */ +#ifdef CONFIG_SC58X +#define ADI_RCU_REG_CTL0x00 +#define ADI_RCU_REG_STAT 0x04 +#define ADI_RCU_REG_CRCTL 0x08 +#define ADI_RCU_REG_CRSTAT 0x0c +#define ADI_RCU_REG_SIDIS 0x10 +#define ADI_RCU_REG_SISTAT 0x14 +#define ADI_RCU_REG_BCODE 0x1c +#define ADI_RCU_REG_SVECT0 0x20 +#define ADI_RCU_REG_SVECT1 0x24 +#define ADI_RCU_REG_SVECT2 0x28 +#define ADI_RCU_REG_MSG0x60 +#define ADI_RCU_REG_MSG_SET0x64 +#define ADI_RCU_REG_MSG_CLR0x68 +#else +#define ADI_RCU_REG_CTL0x00 +#define ADI_RCU_REG_STAT 0x04 +#define ADI_RCU_REG_CRCTL 0x08 +#define ADI_RCU_REG_CRSTAT 0x0c +#define ADI_RCU_REG_SRRQSTAT 0x18 +#define ADI_RCU_REG_SIDIS 0x1c +#define ADI_RCU_REG_SISTAT 0x20 +#define ADI_RCU_REG_SVECT_LCK 0x24 +#define ADI_RCU_REG_BCODE 0x28 +#define ADI_RCU_REG_SVECT0 0x2c +#define ADI_RCU_REG_SVECT1 0x30 +#define ADI_RCU_REG_SVECT2 0x34 +#define ADI_RCU_REG_MSG0x6c +#define ADI_RCU_REG_MSG_SET0x70 +#define ADI_RCU_REG_MSG_CLR0x74 +#endif /* CONFIG_SC58X */ + +/* Register bit definitions */ +#define ADI_RCU_CTL_SYSRST BIT(0) + +/* Bit values for the RCU0_MSG register */ +#define RCU0_MSG_C0IDLE0x0100 /* Core 0 Id
[PATCH 08/11] dma: Add driver for ADI SC5xx-family SoC MDMA functionality
Add a rudimentary MDMA driver for the Analog Devices SC5xx SoCs,
primarily intended for use with and tested against the QSPI/OSPI
IP included in the SoC.
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Artamonovs
Signed-off-by: Greg Malysa
---
MAINTAINERS | 1 +
drivers/dma/Kconfig | 7 ++
drivers/dma/Makefile | 1 +
drivers/dma/adi_dma.c | 255 ++
4 files changed, 264 insertions(+)
create mode 100644 drivers/dma/adi_dma.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 6feb7e540b..ce92ce107d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -610,6 +610,7 @@ T: git https://github.com/analogdevicesinc/lnxdsp-u-boot
F: arch/arm/include/asm/arch-adi/
F: arch/arm/mach-sc5xx/
F: drivers/clk/adi/
+F: drivers/dma/adi_dma.c
F: drivers/gpio/adp5588_gpio.c
F: drivers/gpio/gpio-adi-adsp.c
F: drivers/i2c/adi_i2c.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 3c64e89464..4b47be6b01 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -76,6 +76,13 @@ config XILINX_DPDMA
this file is used as placeholder for driver. The main reason is
to record compatible string and calling power domain driver.
+config ADI_DMA
+ bool "ADI DMA driver"
+ depends on DMA && DMA_CHANNELS
+ help
+ Enable DMA support for Analog Devices SOCs, such as the SC5xx.
+ Currently this is a minimalistic driver tested against OSPI use only.
+
if APBH_DMA
config APBH_DMA_BURST
bool "Enable DMA BURST"
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 48811eaaeb..00d765864c 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -13,5 +13,6 @@ obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
obj-$(CONFIG_TI_EDMA3) += ti-edma3.o
obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o
obj-$(CONFIG_XILINX_DPDMA) += xilinx_dpdma.o
+obj-$(CONFIG_ADI_DMA) += adi_dma.o
obj-y += ti/
diff --git a/drivers/dma/adi_dma.c b/drivers/dma/adi_dma.c
new file mode 100644
index 00..56eceff712
--- /dev/null
+++ b/drivers/dma/adi_dma.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Analog Devices DMA controller driver
+ *
+ * (C) Copyright 2024 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison
+ * Contact: Greg Malysa
+ * Contact: Ian Roberts
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define HAS_MDMA BIT(0)
+
+#define REG_ADDRSTART 0x04
+#define REG_CFG0x08
+#define REG_XCNT 0x0C
+#define REG_XMOD 0x10
+#define REG_STAT 0x30
+
+#define BITP_DMA_CFG_MSIZE8
+#define BITP_DMA_CFG_PSIZE4
+#define BITM_DMA_CFG_WNR 0x0002
+#define BITM_DMA_CFG_EN 0x0001
+#define ENUM_DMA_CFG_XCNT_INT0x0010
+
+#define BITP_DMA_STAT_PBWID 12
+#define BITP_DMA_STAT_ERRC4
+#define BITM_DMA_STAT_PBWID 0x3000
+#define BITM_DMA_STAT_ERRC 0x0070
+#define BITM_DMA_STAT_PIRQ 0x0004
+#define BITM_DMA_STAT_IRQERR 0x0002
+#define BITM_DMA_STAT_IRQDONE0x0001
+
+#define DMA_MDMA_SRC_DEFAULT_CONFIG(psize, msize) \
+ (BITM_DMA_CFG_EN | ((psize) << BITP_DMA_CFG_PSIZE) | ((msize) <<
BITP_DMA_CFG_MSIZE))
+#define DMA_MDMA_DST_DEFAULT_CONFIG(psize, msize) \
+ (BITM_DMA_CFG_EN | BITM_DMA_CFG_WNR | ENUM_DMA_CFG_XCNT_INT | \
+ ((psize) << BITP_DMA_CFG_PSIZE) | ((msize) << BITP_DMA_CFG_MSIZE))
+
+struct adi_dma_channel {
+ int id;
+ struct adi_dma *dma;
+ void __iomem *iosrc;
+ void __iomem *iodest;
+};
+
+struct adi_dma {
+ struct udevice *dev;
+ struct adi_dma_channel channels[1];
+ void __iomem *ioaddr;
+ unsigned long hw_cfg;
+};
+
+static const struct udevice_id dma_dt_ids[] = {
+ { .compatible = "adi,mdma-controller", .data = HAS_MDMA },
+ { }
+};
+
+static u8 adi_dma_get_msize(u32 n_bytecount, u32 n_address)
+{
+ /* Calculate MSIZE, PSIZE, XCNT and XMOD */
+ u8 n_msize = 0;
+ u32 n_value = n_bytecount | n_address;
+ u32 n_mask = 0x1;
+
+ for (n_msize = 0; n_msize < 5; n_msize++, n_mask <<= 1) {
+ if ((n_value & n_mask) == n_mask)
+ break;
+ }
+
+ return n_msize;
+}
+
+static int adi_dma_get_ch_error(void __iomem *ch)
+{
+ u32 cause = (readl(ch + REG_STAT) & BITM_DMA_STAT_ERRC) >>
+ BITP_DMA_STAT_ERRC;
+ switch (cause) {
+ case 0:
+
[PATCH 07/11] watchdog: Add support for ADI SC5XX-family watchdog peripheral
From: Nathan Barrett-Morrison
Co-developed-by: Greg Malysa
Signed-off-by: Greg Malysa
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Artamonovs
Signed-off-by: Nathan Barrett-Morrison
---
MAINTAINERS| 1 +
drivers/watchdog/Kconfig | 9 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/adi_wdt.c | 145 +
4 files changed, 156 insertions(+)
create mode 100644 drivers/watchdog/adi_wdt.c
diff --git a/MAINTAINERS b/MAINTAINERS
index c1685f0352..6feb7e540b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -618,6 +618,7 @@ F: drivers/pinctrl/pinctrl-adi-adsp.c
F: drivers/serial/serial_adi_uart4.c
F: drivers/timer/adi_sc5xx_timer.c
F: drivers/usb/musb-new/sc5xx.c
+F: drivers/watchdog/adi_wdt.c
F: include/env/adi/
ARM SNAPDRAGON
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 8318fd77a3..5a62000272 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -94,6 +94,15 @@ config WDT_APPLE
The watchdog will perform a full SoC reset resulting in a
reboot of the entire system.
+config WDT_ADI
+ bool "Analog Devices watchdog timer support"
+ select WDT
+ select SPL_WDT if SPL
+ depends on (SC57X || SC58X || SC59X || SC59X_64)
+ help
+ Enable this to support Watchdog Timer on ADI SC57X, SC58X, SC59X,
+ and SC59X_64 processors
+
config WDT_ARMADA_37XX
bool "Marvell Armada 37xx watchdog timer support"
depends on WDT && ARMADA_3700
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 7b39adcf0f..7ad61b513c 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -50,3 +50,4 @@ obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o
obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
obj-$(CONFIG_WDT_XILINX) += xilinx_wwdt.o
+obj-$(CONFIG_WDT_ADI) += adi_wdt.o
diff --git a/drivers/watchdog/adi_wdt.c b/drivers/watchdog/adi_wdt.c
new file mode 100644
index 00..67d17dc692
--- /dev/null
+++ b/drivers/watchdog/adi_wdt.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Converted to driver model by Nathan Barrett-Morrison
+ *
+ * Contact: Nathan Barrett-Morrison
+ * Contact: Greg Malysa
+ *
+ * adi_wtd.c - driver for ADI on-chip watchdog
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define WDOG_CTL 0x0
+#define WDOG_CNT 0x4
+#define WDOG_STAT 0x8
+
+#define RCU_CTL 0x0
+#define RCU_STAT 0x4
+
+#define SEC_GCTL 0x0
+#define SEC_FCTL 0x10
+#define SEC_SCTL0 0x800
+
+#define WDEN 0x0010
+#define WDDIS 0x0AD0
+
+struct adi_wdt_priv {
+ void __iomem *rcu_base;
+ void __iomem *sec_base;
+ void __iomem *wdt_base;
+ struct clk clock;
+};
+
+static int adi_wdt_reset(struct udevice *dev)
+{
+ struct adi_wdt_priv *priv = dev_get_priv(dev);
+
+ writel(0, priv->wdt_base + WDOG_STAT);
+
+ return 0;
+}
+
+static int adi_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ struct adi_wdt_priv *priv = dev_get_priv(dev);
+ u32 sctl_val;
+
+ /* Disable SYSCD_RESETb input and clear the RCU0 reset status */
+ writel(0xf, priv->rcu_base + RCU_STAT);
+ writel(0x0, priv->rcu_base + RCU_CTL);
+
+ /* reset the SEC controller */
+ writel(0x2, priv->sec_base + SEC_GCTL);
+ writel(0x2, priv->sec_base + SEC_FCTL);
+
+ udelay(50);
+
+ /* enable SEC fault event */
+ writel(0x1, priv->sec_base + SEC_GCTL);
+
+ /* ANOMALY 3614 Spurious External Fault event occurs when FCTL
+* is re-programmed when currently active fault is not cleared
+*/
+ writel(0xc0, priv->sec_base + SEC_FCTL);
+ writel(0xc1, priv->sec_base + SEC_FCTL);
+
+ /* enable SEC fault source for watchdog0 */
+ sctl_val = readl((priv->sec_base + SEC_SCTL0) + 3 * 8) | 0x6;
+ writel(sctl_val, (priv->sec_base + SEC_SCTL0) + 3 * 8);
+
+ /* Enable SYSCD_RESETb input */
+ writel(0x100, priv->rcu_base + RCU_CTL);
+
+ /* enable watchdog0 */
+ writel(WDDIS, priv->wdt_base + WDOG_CTL);
+
+ writel(timeout_ms / 1000 *
+ (clk_get_rate(>clock) / (IS_ENABLED(CONFIG_SC58X) ? 2 :
1)),
+ priv->wdt_base + WDOG_CNT);
+
+ writel(0, priv->wdt_base + WDOG_STAT);
+ writel(WDEN, priv->wdt_base + WDOG_CTL);
+
+ return 0;
+}
+
+static int adi_wdt_probe(struct udevice *dev)
+{
+ struct adi_wdt_priv *priv = dev_get_priv(dev);
+ int ret;
+ struct resource res;
+
+ ret = dev_read_resource_byname(dev, "rcu", );
+ if
[PATCH 06/11] net: Add support for ADI SC5xx SoCs with DWC QoS ethernet
The ADI SC598 includes a Designware QoS 5.20a IP block. This
commit adds support for using the existing ethernet QoS driver
with the SC598 SoC.
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Artamonovs
Signed-off-by: Greg Malysa
---
MAINTAINERS | 1 +
drivers/net/Kconfig | 7 +++
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 ++
drivers/net/dwc_eth_qos.h | 2 +
drivers/net/dwc_eth_qos_adi.c | 101 ++
6 files changed, 118 insertions(+)
create mode 100644 drivers/net/dwc_eth_qos_adi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 977233451e..c1685f0352 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -613,6 +613,7 @@ F: drivers/clk/adi/
F: drivers/gpio/adp5588_gpio.c
F: drivers/gpio/gpio-adi-adsp.c
F: drivers/i2c/adi_i2c.c
+F: drivers/net/dwc_eth_qos_adi.c
F: drivers/pinctrl/pinctrl-adi-adsp.c
F: drivers/serial/serial_adi_uart4.c
F: drivers/timer/adi_sc5xx_timer.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index b4ff033afa..9ae471e371 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -236,6 +236,13 @@ config DWC_ETH_QOS
Of Service) IP block. The IP supports many options for bus type,
clocking/reset structure, and feature list.
+config DWC_ETH_QOS_ADI
+ bool "Synopsys DWC Ethernet QOS device support for ADI SC59x-64 parts"
+ depends on DWC_ETH_QOS
+ help
+ The Synopsis Designware Ethernet QoS IP block with the specific
+ configuration used in the ADI ADSP-SC59X 64 bit SoCs
+
config DWC_ETH_QOS_IMX
bool "Synopsys DWC Ethernet QOS device support for IMX"
depends on DWC_ETH_QOS
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index dce71685c3..612f5644f3 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_DWC_ETH_QOS_ADI) += dwc_eth_qos_adi.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 67ac86f82b..10528368ca 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1544,6 +1544,12 @@ static const struct udevice_id eqos_ids[] = {
.compatible = "starfive,jh7110-dwmac",
.data = (ulong)_jh7110_config
},
+#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_ADI)
+ {
+ .compatible = "adi,sc59x-dwmac-eqos",
+ .data = (ulong)_adi_config
+ },
#endif
{ }
};
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index 8b3d0d464d..1b28f2a056 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -84,6 +84,7 @@ struct eqos_mac_regs {
#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
#define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1
#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
+#define EQOS_MAC_MDIO_ADDRESS_CR_150_250 4
#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT2
@@ -293,3 +294,4 @@ extern struct eqos_config eqos_qcom_config;
extern struct eqos_config eqos_stm32mp13_config;
extern struct eqos_config eqos_stm32mp15_config;
extern struct eqos_config eqos_jh7110_config;
+extern struct eqos_config eqos_adi_config;
diff --git a/drivers/net/dwc_eth_qos_adi.c b/drivers/net/dwc_eth_qos_adi.c
new file mode 100644
index 00..8e770c0dcb
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_adi.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * (C) Copyright 2024 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa
+ * Additional Contact: Nathan Barrett-Morrison
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "dwc_eth_qos.h"
+
+static int eqos_start_resets_adi(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ u32 val;
+
+ /*
+* Settings need to latch with the DMA reset below. Currently only
+* rgmii is supported but other phy interfaces may be supported in
+* the future
+*/
+ sc5xx_enable_rgmii();
+
+ val = readl(>dma_regs->mode);
+ val |= EQOS_DMA_MODE_SWR;
+ writel(val, >dma_regs->mode);
+
+ return 0;
[PATCH 05/11] i2c: Add support for ADI SC5XX-family I2C peripheral
From: Nathan Barrett-Morrison Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Co-developed-by: Angelo Dureghello Signed-off-by: Angelo Dureghello Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs Signed-off-by: Nathan Barrett-Morrison --- MAINTAINERS | 1 + drivers/i2c/Kconfig | 7 + drivers/i2c/Makefile | 1 + drivers/i2c/adi_i2c.c | 393 ++ 4 files changed, 402 insertions(+) create mode 100644 drivers/i2c/adi_i2c.c diff --git a/MAINTAINERS b/MAINTAINERS index 3bcdb73e6e..977233451e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -612,6 +612,7 @@ F: arch/arm/mach-sc5xx/ F: drivers/clk/adi/ F: drivers/gpio/adp5588_gpio.c F: drivers/gpio/gpio-adi-adsp.c +F: drivers/i2c/adi_i2c.c F: drivers/pinctrl/pinctrl-adi-adsp.c F: drivers/serial/serial_adi_uart4.c F: drivers/timer/adi_sc5xx_timer.c diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 34b02114dc..efcb0589ca 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -154,6 +154,13 @@ config SPL_DM_I2C_GPIO bindings are supported. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt +config SYS_I2C_ADI + bool "ADI I2C driver" + depends on DM_I2C && (SC57X || SC58X || SC59X || SC59X_64) + help + Add support for the ADI (Analog Devices) I2C driver as used + in SC57X, SC58X, SC59X, SC59X_64. + config SYS_I2C_AT91 bool "Atmel I2C driver" depends on DM_I2C && ARCH_AT91 diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 00b90523c6..30c1a43a57 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += i2c_core.o +obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o obj-$(CONFIG_SYS_I2C_AST2600) += ast2600_i2c.o obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c new file mode 100644 index 00..cfc5561299 --- /dev/null +++ b/drivers/i2c/adi_i2c.c @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Converted to driver model by Nathan Barrett-Morrison + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#include +#include +#include +#include +#include + +#define CLKLOW(x) ((x) & 0xFF) // Periods Clock Is Held Low +#define CLKHI(y) (((y) & 0xFF) << 0x8) // Periods Clock Is High + +#define PRESCALE0x007F // SCLKs Per Internal Time Reference (10MHz) +#define TWI_ENA 0x0080 // TWI Enable +#define SCCB0x0200 // SCCB Compatibility Enable + +#define SEN 0x0001 // Slave Enable +#define SADD_LEN0x0002 // Slave Address Length +#define STDVAL 0x0004 // Slave Transmit Data Valid +#define TSC_NAK 0x0008 // NAK Generated At Conclusion Of Transfer +#define GEN 0x0010 // General Call Adrress Matching Enabled + +#define SDIR0x0001 // Slave Transfer Direction +#define GCALL 0x0002 // General Call Indicator + +#define MEN 0x0001 // Master Mode Enable +#define MADD_LEN0x0002 // Master Address Length +#define MDIR0x0004 // Master Transmit Direction (RX/TX*) +#define FAST0x0008 // Use Fast Mode Timing Specs +#define STOP0x0010 // Issue Stop Condition +#define RSTART 0x0020 // Repeat Start or Stop* At End Of Transfer +#define DCNT0x3FC0 // Data Bytes To Transfer +#define SDAOVR 0x4000 // Serial Data Override +#define SCLOVR 0x8000 // Serial Clock Override + +#define MPROG 0x0001 // Master Transfer In Progress +#define LOSTARB 0x0002 // Lost Arbitration Indicator (Xfer Aborted) +#define ANAK0x0004 // Address Not Acknowledged +#define DNAK0x0008 // Data Not Acknowledged +#define BUFRDERR0x0010 // Buffer Read Error +#define BUFWRERR0x0020 // Buffer Write Error +#define SDASEN 0x0040 // Serial Data Sense +#define SCLSEN 0x0080 // Serial Clock Sense +#define BUSBUSY 0x0100 // Bus Busy Indicator + +#define SINIT 0x0001 // Slave Transfer Initiated +#define SCOMP 0x0002 // Slave Transfer Complete +#define SERR0x0004 // Slave Transfer Error +#define SOVF0x0008 // Slave Overflow +#define MCOMP 0x0010 // Master Transfer Complete +#define MERR0x
[PATCH 04/11] usb: musb-new: Add support for Analog Devices SC5xx SoCs
From: Nathan Barrett-Morrison
This adds support for the MUSB-based USB controller found in the
Analog Devices SC57x and SC58x SoCs.
Co-developed-by: Greg Malysa
Signed-off-by: Greg Malysa
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Artamonovs
Signed-off-by: Nathan Barrett-Morrison
---
MAINTAINERS | 1 +
drivers/usb/musb-new/Kconfig | 7 ++
drivers/usb/musb-new/Makefile | 1 +
drivers/usb/musb-new/sc5xx.c | 202 ++
4 files changed, 211 insertions(+)
create mode 100644 drivers/usb/musb-new/sc5xx.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 7d07d13dbc..3bcdb73e6e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -615,6 +615,7 @@ F: drivers/gpio/gpio-adi-adsp.c
F: drivers/pinctrl/pinctrl-adi-adsp.c
F: drivers/serial/serial_adi_uart4.c
F: drivers/timer/adi_sc5xx_timer.c
+F: drivers/usb/musb-new/sc5xx.c
F: include/env/adi/
ARM SNAPDRAGON
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index c52afd41a7..ad9072a532 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -22,6 +22,13 @@ config USB_MUSB_GADGET
Enables the MUSB USB dual-role controller in gadget mode.
if USB_MUSB_HOST || USB_MUSB_GADGET
+config USB_MUSB_SC5XX
+bool "Analog Devices MUSB support"
+depends on (SC57X || SC58X)
+ help
+Say y here to enable support for the USB controller on
+ADI SC57X/SC58X processors.
+
config USB_MUSB_DA8XX
bool "Enable DA8xx MUSB Controller"
depends on ARCH_DAVINCI
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index 396ff02654..6638772dac 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
obj-$(CONFIG_USB_MUSB_TI) += ti-musb.o
obj-$(CONFIG_USB_MUSB_UX500) += ux500.o
+obj-$(CONFIG_USB_MUSB_SC5XX) += sc5xx.o
ccflags-y := $(call cc-option,-Wno-unused-variable) \
$(call cc-option,-Wno-unused-but-set-variable) \
diff --git a/drivers/usb/musb-new/sc5xx.c b/drivers/usb/musb-new/sc5xx.c
new file mode 100644
index 00..16201480b4
--- /dev/null
+++ b/drivers/usb/musb-new/sc5xx.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * ADI SC5XX MUSB "glue layer"
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Loosely ported from Linux driver:
+ * Author: Nathan Barrett-Morrison
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "linux-compat.h"
+#include "musb_core.h"
+#include "musb_uboot.h"
+
+#define MUSB_SOFTRST 0x7f
+#define MUSB_SOFTRST_NRST BIT(0)
+#define MUSB_SOFTRST_NRSTXBIT(1)
+
+#define REG_USB_VBUS_CTL 0x380
+#define REG_USB_ID_CTL 0x382
+#define REG_USB_PHY_CTL0x394
+#define REG_USB_PLL_OSC0x398
+#define REG_USB_UTMI_CTL 0x39c
+
+/* controller data */
+struct sc5xx_musb_data {
+ struct musb_host_data mdata;
+ struct device dev;
+};
+
+#define to_sc5xx_musb_data(d) \
+ container_of(d, struct sc5xx_musb_data, dev)
+
+static void sc5xx_musb_disable(struct musb *musb)
+{
+ /* no way to shut the controller */
+}
+
+static int sc5xx_musb_enable(struct musb *musb)
+{
+ /* soft reset by NRSTx */
+ musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
+ /* set mode */
+ musb_platform_set_mode(musb, musb->board_mode);
+
+ return 0;
+}
+
+static irqreturn_t sc5xx_interrupt(int irq, void *hci)
+{
+ struct musb *musb = hci;
+ irqreturn_t ret = IRQ_NONE;
+ u8 devctl;
+
+ musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
+ musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
+ musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
+
+ if (musb->int_usb & MUSB_INTR_VBUSERROR) {
+ musb->int_usb &= ~MUSB_INTR_VBUSERROR;
+ devctl = musb_readw(musb->mregs, MUSB_DEVCTL);
+ devctl |= MUSB_DEVCTL_SESSION;
+ musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+ }
+ if (musb->int_usb || musb->int_tx || musb->int_rx) {
+ musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
+ musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
+ musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
+ ret = musb_interrupt(musb);
+ }
+
+ if (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))
+ musb_writeb(musb->mregs, REG_USB_VBUS_CTL, 0x0);
+
+ return ret;
+}
+
+static int sc5xx_m
[PATCH 03/11] gpio: Add support for ADI ADP5588 GPIO expander chips
From: Nathan Barrett-Morrison
This adds support for the ADP588 GPIO expander from Analog Devices. It
is accessed over I2C and provides up to 18 pins. It is largely a port of
the Linux driver developed by Michael Hennerich
Signed-off-by: Ian Roberts
Signed-off-by: Greg Malysa
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Artamonovs
Signed-off-by: Nathan Barrett-Morrison
---
MAINTAINERS | 1 +
drivers/gpio/Kconfig| 8 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/adp5588_gpio.c | 208
4 files changed, 218 insertions(+)
create mode 100644 drivers/gpio/adp5588_gpio.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 5d7b0f39ac..7d07d13dbc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -610,6 +610,7 @@ T: git https://github.com/analogdevicesinc/lnxdsp-u-boot
F: arch/arm/include/asm/arch-adi/
F: arch/arm/mach-sc5xx/
F: drivers/clk/adi/
+F: drivers/gpio/adp5588_gpio.c
F: drivers/gpio/gpio-adi-adsp.c
F: drivers/pinctrl/pinctrl-adi-adsp.c
F: drivers/serial/serial_adi_uart4.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 142fe44533..37be5008f3 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -531,6 +531,14 @@ config DM_PCA953X
Now, max 24 bits chips and PCA953X compatible chips are
supported
+config ADP5588_GPIO
+ bool "ADP5588 GPIO expander driver"
+ depends on DM_GPIO && DM_I2C
+ help
+ Say yes here to support GPIO functionality of ADI ADP5588 chips.
+
+ The ADP5588 is an 18-port I2C GPIO expander and keypad controller.
+
config SPL_DM_PCA953X
bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports in SPL"
depends on SPL_DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ba58fbafd1..f3935638f9 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -72,6 +72,7 @@ obj-$(CONFIG_NOMADIK_GPIO)+= nmk_gpio.o
obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o
obj-$(CONFIG_$(SPL_)MAX77663_GPIO) += max77663_gpio.o
obj-$(CONFIG_SL28CPLD_GPIO)+= sl28cpld-gpio.o
+obj-$(CONFIG_ADP5588_GPIO) += adp5588_gpio.o
obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o
obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o
obj-$(CONFIG_FTGPIO010)+= ftgpio010.o
diff --git a/drivers/gpio/adp5588_gpio.c b/drivers/gpio/adp5588_gpio.c
new file mode 100644
index 00..d081e16989
--- /dev/null
+++ b/drivers/gpio/adp5588_gpio.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * GPIO Chip driver for Analog Devices
+ * ADP5588/ADP5587 I/O Expander and QWERTY Keypad Controller
+ *
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison
+ * Contact: Greg Malysa
+ *
+ * Based on Michael Hennerich's Linux driver:
+ * Michael Hennerich
+ *
+ */
+
+#include
+#include
+#include
+
+#define ADP5588_MAXGPIO 18
+#define ADP5588_BANK(offs) ((offs) >> 3)
+#define ADP5588_BIT(offs) (1u << ((offs) & 0x7))
+
+#define DEV_ID 0x00/* Device ID */
+#define GPIO_DAT_STAT1 0x14/* GPIO Data Status, Read twice to clear */
+#define GPIO_DAT_STAT2 0x15/* GPIO Data Status, Read twice to clear */
+#define GPIO_DAT_STAT3 0x16/* GPIO Data Status, Read twice to clear */
+#define GPIO_DAT_OUT1 0x17/* GPIO DATA OUT */
+#define GPIO_DAT_OUT2 0x18/* GPIO DATA OUT */
+#define GPIO_DAT_OUT3 0x19/* GPIO DATA OUT */
+#define GPIO_INT_EN10x1A/* GPIO Interrupt Enable */
+#define GPIO_INT_EN20x1B/* GPIO Interrupt Enable */
+#define GPIO_INT_EN30x1C/* GPIO Interrupt Enable */
+#define KP_GPIO10x1D/* Keypad or GPIO Selection */
+#define KP_GPIO20x1E/* Keypad or GPIO Selection */
+#define KP_GPIO30x1F/* Keypad or GPIO Selection */
+#define GPIO_DIR1 0x23/* GPIO Data Direction */
+#define GPIO_DIR2 0x24/* GPIO Data Direction */
+#define GPIO_DIR3 0x25 /* GPIO Data Direction */
+#define GPIO_PULL1 0x2C/* GPIO Pull Disable */
+#define GPIO_PULL2 0x2D/* GPIO Pull Disable */
+#define GPIO_PULL3 0x2E/* GPIO Pull Disable */
+#define ID_MASK0x0F
+
+struct adp5588_gpio {
+ u8 dat_out[3];
+ u8 dir[3];
+};
+
+static int adp5588_gpio_read(struct udevice *dev, u8 reg)
+{
+ int ret;
+ u8 val;
+
+ ret = dm_i2c_read(dev, reg, , 1);
+
+ if (ret < 0) {
+ pr_err("%s: read error\n", __func__);
+ return ret;
+ }
+
+ return val;
+}
+
+static int adp5588_gpio_write(struct udevice *dev, u8 reg, u8 val)
+{
+ int ret;
+
+ ret = dm_i2c_write(dev, reg, , 1);
+ if (ret < 0) {
+ pr_err("%s: write error\n"
[PATCH 02/11] gpio: Add support for SC5XX-family processor GPIO driver
This adds support for using the GPIO pins on the SC5XX family of SoCs
from Analog Devices.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Artamonovs
Signed-off-by: Greg Malysa
---
MAINTAINERS | 1 +
drivers/gpio/Kconfig | 9 ++
drivers/gpio/Makefile| 1 +
drivers/gpio/gpio-adi-adsp.c | 179 +++
4 files changed, 190 insertions(+)
create mode 100644 drivers/gpio/gpio-adi-adsp.c
diff --git a/MAINTAINERS b/MAINTAINERS
index dabc7d0591..5d7b0f39ac 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -610,6 +610,7 @@ T: git https://github.com/analogdevicesinc/lnxdsp-u-boot
F: arch/arm/include/asm/arch-adi/
F: arch/arm/mach-sc5xx/
F: drivers/clk/adi/
+F: drivers/gpio/gpio-adi-adsp.c
F: drivers/pinctrl/pinctrl-adi-adsp.c
F: drivers/serial/serial_adi_uart4.c
F: drivers/timer/adi_sc5xx_timer.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b050585389..142fe44533 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -97,6 +97,15 @@ config SPL_DM_GPIO_LOOKUP_LABEL
different gpios on different hardware versions
for the same functionality in board code.
+config ADI_GPIO
+ bool "ADI GPIO driver"
+ depends on DM_GPIO && (SC57X || SC58X || SC59X || SC59X_64)
+ help
+ This driver supports GPIO banks on SC5xx processors. It
+ supports inputs and outputs but does not support pin
+ interrupt functionality (PINT) or other features in the
+ Linux version of the driver.
+
config ALTERA_PIO
bool "Altera PIO driver"
depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 4a29315435..ba58fbafd1 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_TPL_)DM_GPIO) += gpio-uclass.o
obj-$(CONFIG_$(SPL_)DM_PCA953X)+= pca953x_gpio.o
+obj-$(CONFIG_ADI_GPIO) += gpio-adi-adsp.o
obj-$(CONFIG_ASPEED_GPIO) += gpio-aspeed.o
obj-$(CONFIG_AT91_GPIO)+= at91_gpio.o
obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o
diff --git a/drivers/gpio/gpio-adi-adsp.c b/drivers/gpio/gpio-adi-adsp.c
new file mode 100644
index 00..0ce00572e0
--- /dev/null
+++ b/drivers/gpio/gpio-adi-adsp.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa
+ * Additional Contact: Nathan Barrett-Morrison
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define ADSP_PORT_MMIO_SIZE0x80
+#define ADSP_PORT_PIN_SIZE 16
+
+#define ADSP_PORT_REG_FER 0x00
+#define ADSP_PORT_REG_FER_SET 0x04
+#define ADSP_PORT_REG_FER_CLEAR0x08
+#define ADSP_PORT_REG_DATA 0x0c
+#define ADSP_PORT_REG_DATA_SET 0x10
+#define ADSP_PORT_REG_DATA_CLEAR 0x14
+#define ADSP_PORT_REG_DIR 0x18
+#define ADSP_PORT_REG_DIR_SET 0x1c
+#define ADSP_PORT_REG_DIR_CLEAR0x20
+#define ADSP_PORT_REG_INEN 0x24
+#define ADSP_PORT_REG_INEN_SET 0x28
+#define ADSP_PORT_REG_INEN_CLEAR 0x2c
+#define ADSP_PORT_REG_PORT_MUX 0x30
+#define ADSP_PORT_REG_DATA_TGL 0x34
+#define ADSP_PORT_REG_POLAR0x38
+#define ADSP_PORT_REG_POLAR_SET0x3c
+#define ADSP_PORT_REG_POLAR_CLEAR 0x40
+#define ADSP_PORT_REG_LOCK 0x44
+#define ADSP_PORT_REG_TRIG_TGL 0x48
+
+struct adsp_gpio_priv {
+ void __iomem *base;
+ int ngpio;
+};
+
+static u32 get_port(unsigned int pin)
+{
+ return pin / ADSP_PORT_PIN_SIZE;
+}
+
+static u32 get_offset(unsigned int pin)
+{
+ return pin % ADSP_PORT_PIN_SIZE;
+}
+
+static int adsp_gpio_input(struct udevice *udev, unsigned int pin)
+{
+ struct adsp_gpio_priv *priv = dev_get_priv(udev);
+ u32 port, offset;
+ void __iomem *portbase;
+
+ if (pin < priv->ngpio) {
+ port = get_port(pin);
+ offset = get_offset(pin);
+ portbase = priv->base + port * ADSP_PORT_MMIO_SIZE;
+
+ iowrite16(BIT(offset), portbase + ADSP_PORT_REG_FER_CLEAR);
+ iowrite16(BIT(offset), portbase + ADSP_PORT_REG_DIR_CLEAR);
+ iowrite16(BIT(offset), portbase + ADSP_PORT_REG_INEN_SET);
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int adsp_gpio_output(struct udevice *udev, unsigned int pin, int value)
+{
+ struct adsp_gpio_priv *priv = dev_get_priv(udev);
+ u32 port, offset;
+ void __iomem *portbase;
+
+ if (pin
[PATCH 01/11] pinctrl: Add support for ADI SC5XX-family pinctrl
This adds support for pin configuration on the Analog Devices SC5XX SoC
family. This commit is largely a port of the Linux driver, which has not
yet been submitted upstream.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Artamonovs
Signed-off-by: Greg Malysa
---
---
MAINTAINERS| 1 +
drivers/pinctrl/Kconfig| 8 ++
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-adi-adsp.c | 156 +
include/dt-bindings/pinctrl/adi-adsp.h | 21
5 files changed, 187 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-adi-adsp.c
create mode 100644 include/dt-bindings/pinctrl/adi-adsp.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 6853288975..dabc7d0591 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -610,6 +610,7 @@ T: git https://github.com/analogdevicesinc/lnxdsp-u-boot
F: arch/arm/include/asm/arch-adi/
F: arch/arm/mach-sc5xx/
F: drivers/clk/adi/
+F: drivers/pinctrl/pinctrl-adi-adsp.c
F: drivers/serial/serial_adi_uart4.c
F: drivers/timer/adi_sc5xx_timer.c
F: include/env/adi/
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index a1d53cfbdb..0f3fb65e4e 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -170,6 +170,14 @@ config PINCTRL_APPLE
both the GPIO definitions and pin control functions for each
available multiplex function.
+config PINCTRL_ADI
+ bool "ADI pinctrl driver"
+ depends on DM && (SC57X || SC58X || SC59X || SC59X_64)
+ help
+ This driver enables pinctrl support on SC5xx processors. This
+ driver covers only the pin configuration functionality, and
+ GPIO functionality is contained in the separate GPIO driver.
+
config PINCTRL_AR933X
bool "QCA/Athores ar933x pin control driver"
depends on DM && SOC_AR933X
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 6d7b7cd905..7dd56774bd 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -3,6 +3,7 @@
obj-y += pinctrl-uclass.o
obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o
+obj-$(CONFIG_PINCTRL_ADI) += pinctrl-adi-adsp.o
obj-$(CONFIG_PINCTRL_APPLE)+= pinctrl-apple.o
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
diff --git a/drivers/pinctrl/pinctrl-adi-adsp.c
b/drivers/pinctrl/pinctrl-adi-adsp.c
new file mode 100644
index 00..717ac8e005
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-adi-adsp.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa
+ * Additional Contact: Nathan Barrett-Morrison
+ *
+ * dm pinctrl implementation for ADI ADSP SoCs
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define ADSP_PORT_MMIO_SIZE0x80
+#define ADSP_PORT_PIN_SIZE 16
+
+#define ADSP_PORT_PORT_MUX_BITS2
+#define ADSP_PORT_PORT_MUX_MASK0x03
+#define ADSP_PINCTRL_FUNCTION_COUNT 4
+
+#define ADSP_PORT_REG_FER 0x00
+#define ADSP_PORT_REG_FER_SET 0x04
+#define ADSP_PORT_REG_FER_CLEAR0x08
+#define ADSP_PORT_REG_DATA 0x0c
+#define ADSP_PORT_REG_DATA_SET 0x10
+#define ADSP_PORT_REG_DATA_CLEAR 0x14
+#define ADSP_PORT_REG_DIR 0x18
+#define ADSP_PORT_REG_DIR_SET 0x1c
+#define ADSP_PORT_REG_DIR_CLEAR0x20
+#define ADSP_PORT_REG_INEN 0x24
+#define ADSP_PORT_REG_INEN_SET 0x28
+#define ADSP_PORT_REG_INEN_CLEAR 0x2c
+#define ADSP_PORT_REG_PORT_MUX 0x30
+#define ADSP_PORT_REG_DATA_TGL 0x34
+#define ADSP_PORT_REG_POLAR0x38
+#define ADSP_PORT_REG_POLAR_SET0x3c
+#define ADSP_PORT_REG_POLAR_CLEAR 0x40
+#define ADSP_PORT_REG_LOCK 0x44
+#define ADSP_PORT_REG_TRIG_TGL 0x48
+
+struct adsp_pinctrl_priv {
+ void __iomem *base;
+ int npins;
+ char pinbuf[16];
+};
+
+static u32 get_port(unsigned int pin)
+{
+ return pin / ADSP_PORT_PIN_SIZE;
+}
+
+static u32 get_offset(unsigned int pin)
+{
+ return pin % ADSP_PORT_PIN_SIZE;
+}
+
+static int adsp_pinctrl_pinmux_set(struct udevice *udev, unsigned int pin,
unsigned int func)
+{
+ struct adsp_pinctrl_priv *priv = dev_get_priv(udev);
+ void __iomem *portbase;
+ u32 port, offset;
+ u32 val;
+
+ if (pin >= priv->npins)
+ return -ENODEV;
+
+
Re: [PATCH] usb: dwc2: Add in version 4xx compatibility
> > > > If you have access to the hardware that has a 4.20a dwc2 controller, > > maybe you can help testing the patch above patch as well? My hardware unfortunately only has a 4.00a controller so I cannot test the 4.20a reset functionality. However, Kongyang Liu's patch works for me as a replacement for our submission and functions correctly otherwise on our hardware, so I am fine with moving forward on his patch. If that's meaningful enough I can add a tested by tag to the other patch from me. > > +CC Liu on this thread, maybe it is best if the two of you figure out > the best common approach that works for you both ? I am also open to collaborating on any other changes as needed.
Re: [GIT PULL] Please pull u-boot-mmc master
On Tue, Apr 30, 2024 at 3:42 AM Francesco Dolcini wrote: > > On Mon, Apr 29, 2024 at 03:39:53PM -0500, Judith Mendez wrote: > > A patch in this series caused a regression for AM62x SK with the > > following error: > > +1, this affects also Verdin AM62. Hi, please try https://patchwork.ozlabs.org/project/uboot/patch/20240501185331.1189647-1-alexander.sverd...@siemens.com/ as this should explain the issue and also fix it.
Re: [PATCH] mmc: sdhci: Correct ADMA_DESC_LEN to 12
Thanks for fixing this for me.
> Confusion probably originates from Linux commit 685e444bbaa0
> ("mmc: sdhci: Add ADMA2 64-bit addressing support for V4 mode"), but
> the latter "V4 mode" was never ported to U-Boot.
I have one of the rare platforms that does not support 64-bit ADMA2 V3
so we also submitted 5359cd1135 ("mmc: Support 32-bit only ADMA on
64-bit platforms") to support that, but if we saw hardware that
required v4 descriptors or someone insisted on it, we'd need to add
another Kconfig for it. Do you think we should port the rest of the v4
support? What about mirroring the kernel's dynamic behavior by
checking the combination of capabilities and control registers to
figure out which mode to use rather than hardcoding it?
--
Greg Malysa
Timesys Corporation
Re: [GIT PULL] Please pull u-boot-mmc master
I am also looking into it since it's our change that is causing the issue. The functions modified don't return status codes so that must mean that it is causing the transaction to be configured incorrectly. However I don't have hardware to test these platforms locally, but I might be able to get a coworker who has an am62 platform to help me test (not sure which one though). Some things I would like to look at first: 1) host->ops->adma_write_desc is expected to be NULL on this platform. If it weren't it'd probably crash instead but it seems like a decent starting point. I believe this corresponds to j721e_4bit_sdhci_ops in this case? 2) Could we compare the contents of the descriptors that are written in sdhci_adma_write_desc between working and broken builds? 3) sdhci_adma_init is only called if the descriptor table is null; is there any chance it has a random value instead of NULL to start off, so it isn't called and adma_addr is not populated correctly? Thanks, Greg -- Greg Malysa Timesys Corporation
[PATCH v2 1/4] arch: arm: Add Analog Devices SC5xx machine type
From: Nathan Barrett-Morrison Add support for the SC5xx machine type from Analog Devices. This includes support for the SC57x, SC58x, SC59x, and SC59x-64 SoCs, which have many common features such as common ADI IP blocks, and SHARC DSP cores. This commit introduces core functionality required for all boards using an SC5xx SoC, such as: - SPL configuration - Required CPU hooks such as reset - Boot ROM interaction to load the stage 2 bootloader in the reference configuration. Other options are possible but not officially supported at this time - SoC-common configuration expected to be reused by all boards - Early initialization for system clocks and DDR controller Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs Signed-off-by: Nathan Barrett-Morrison --- Changes in v2: - Removed MACH_TYPE constants and any references to setting the MACH_TYPE as it is not used by this platform - Removed additional compiler flags from config.mk - Converted to text env. Each board is expected to provide a text env and #include env/adi/adi_boot.env if it wants to use the reference ADI boot flow - Some further cleanup on use of Kconfigs--some per board settings affecting dmcinit and clkinit have been converted to Kconfigs instead of config header constants - Reviewed #include usage and pruned unnecessary files - Passes gitlab CI run locally --- MAINTAINERS | 13 + arch/arm/Kconfig | 5 + arch/arm/Makefile| 1 + arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h | 39 + arch/arm/include/asm/arch-adi/sc5xx/soc.h| 18 + arch/arm/include/asm/arch-adi/sc5xx/spl.h| 43 + arch/arm/mach-sc5xx/Kconfig | 475 + arch/arm/mach-sc5xx/Makefile | 19 + arch/arm/mach-sc5xx/config.mk| 16 + arch/arm/mach-sc5xx/init/Makefile| 11 + arch/arm/mach-sc5xx/init/clkinit.c | 558 +++ arch/arm/mach-sc5xx/init/clkinit.h | 18 + arch/arm/mach-sc5xx/init/dmcinit.c | 954 +++ arch/arm/mach-sc5xx/init/dmcinit.h | 31 + arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h | 62 ++ arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h | 50 + arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h | 50 + arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h | 49 + arch/arm/mach-sc5xx/rcu.c| 22 + arch/arm/mach-sc5xx/sc57x.c | 32 + arch/arm/mach-sc5xx/sc58x.c | 32 + arch/arm/mach-sc5xx/sc59x.c | 43 + arch/arm/mach-sc5xx/sc59x_64.c | 97 ++ arch/arm/mach-sc5xx/soc.c| 179 arch/arm/mach-sc5xx/spl.c| 102 ++ include/env/adi/adi_boot.env | 122 +++ 26 files changed, 3041 insertions(+) create mode 100644 arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h create mode 100644 arch/arm/include/asm/arch-adi/sc5xx/soc.h create mode 100644 arch/arm/include/asm/arch-adi/sc5xx/spl.h create mode 100644 arch/arm/mach-sc5xx/Kconfig create mode 100644 arch/arm/mach-sc5xx/Makefile create mode 100644 arch/arm/mach-sc5xx/config.mk create mode 100644 arch/arm/mach-sc5xx/init/Makefile create mode 100644 arch/arm/mach-sc5xx/init/clkinit.c create mode 100644 arch/arm/mach-sc5xx/init/clkinit.h create mode 100644 arch/arm/mach-sc5xx/init/dmcinit.c create mode 100644 arch/arm/mach-sc5xx/init/dmcinit.h create mode 100644 arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h create mode 100644 arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h create mode 100644 arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h create mode 100644 arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h create mode 100644 arch/arm/mach-sc5xx/rcu.c create mode 100644 arch/arm/mach-sc5xx/sc57x.c create mode 100644 arch/arm/mach-sc5xx/sc58x.c create mode 100644 arch/arm/mach-sc5xx/sc59x.c create mode 100644 arch/arm/mach-sc5xx/sc59x_64.c create mode 100644 arch/arm/mach-sc5xx/soc.c create mode 100644 arch/arm/mach-sc5xx/spl.c create mode 100644 include/env/adi/adi_boot.env diff --git a/MAINTAINERS b/MAINTAINERS index 83fd68e3f3..f743ce9f9d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -598,6 +598,19 @@ R: Marc Murphy S: Supported F: arch/arm/dts/am335x-sancloud* +ARM SC5XX +M: Nathan Barrett-Morrison +M: Greg Malysa +M: Ian Roberts +M: Vasileios Bimpikas +M: Utsav Agarwal +M: Arturs Artamonovs +S: Supported +T: git https://github.com/analogdevicesinc/lnxdsp-u-boot +F: arch/arm/include/asm/arch-adi/ +F: arch/arm/mach-sc5xx/ +F: include/env/adi/ + ARM SNAPDRAGON M: Caleb Connolly M: Neil Armstrong diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a0842e1933..ded35cb65c 100644 --- a/arch/arm/Kconfig +++ b/arch
[PATCH v2 0/4] arm: Add Analog Devices SC5xx Machine Type
This series adds support for the ADI SC5xx machine type and includes two core drivers that are required for being able to boot any board--a UART driver, the gptimer driver which is used as a clock reference (CNTVCNT is not supported on the armv7 sc5xx SoCs) and the clock tree driver. Our corresponding Linux support relies on u-boot configuring the clocks correctly before booting, so it is not possible to boot any board without the CGU/CDU configuration happening here. There are also no board files, device trees, or defconfigs included here, but some common definitions that will be used to build board files currently are. The sc5xx SoCs themselves include many armv7 families (sc57x, sc58x, and sc594) all using an ARM Cortex-A5, and one armv8 family (sc598) indended to be a drop-in replacement for the SC594 in terms of peripherals, with a Cortex-A55 instead. Some of the configuration code in dmcinit and clkinit is quite scary and causes a lot of checkpatch violations. It is modified from code initially provided by ADI, but it has not been fully rewritten. There's a question of how important it is to clean up this code--it has some quality violations, but it has been in use (including in production) for over two years and is known to work for performing the low level SoC initialization, while a rewrite might introduce timing or sequence bugs that could take a significant amount of time to detect in the future. Thank you! Changes in v2: - Removed MACH_TYPE constants and any references to setting the MACH_TYPE as it is not used by this platform - Removed additional compiler flags from config.mk - Converted to text env. Each board is expected to provide a text env and #include env/adi/adi_boot.env if it wants to use the reference ADI boot flow - Some further cleanup on use of Kconfigs--some per board settings affecting dmcinit and clkinit have been converted to Kconfigs instead of config header constants - Converted some #ifdef blocks into soc-specific functions with common functionality in soc.c, such as configuring SECUREC0, 1, and 2. - Reviewed #include usage and pruned unnecessary files - Passes gitlab CI run locally - Added gptimer driver to this series because a minimal system can't boot without it Greg Malysa (1): drivers: timer: Add in driver support for ADI SC5XX-family GP timer peripheral Nathan Barrett-Morrison (3): arch: arm: Add Analog Devices SC5xx machine type drivers: clk: adi: Add in SC5XX-family clock driver drivers: serial: Add in UART for ADI SC5XX-family processors MAINTAINERS | 16 + arch/arm/Kconfig | 5 + arch/arm/Makefile| 1 + arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h | 39 + arch/arm/include/asm/arch-adi/sc5xx/soc.h| 18 + arch/arm/include/asm/arch-adi/sc5xx/spl.h| 43 + arch/arm/mach-sc5xx/Kconfig | 475 + arch/arm/mach-sc5xx/Makefile | 19 + arch/arm/mach-sc5xx/config.mk| 16 + arch/arm/mach-sc5xx/init/Makefile| 11 + arch/arm/mach-sc5xx/init/clkinit.c | 558 +++ arch/arm/mach-sc5xx/init/clkinit.h | 18 + arch/arm/mach-sc5xx/init/dmcinit.c | 954 +++ arch/arm/mach-sc5xx/init/dmcinit.h | 31 + arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h | 62 ++ arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h | 50 + arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h | 50 + arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h | 49 + arch/arm/mach-sc5xx/rcu.c| 22 + arch/arm/mach-sc5xx/sc57x.c | 32 + arch/arm/mach-sc5xx/sc58x.c | 32 + arch/arm/mach-sc5xx/sc59x.c | 43 + arch/arm/mach-sc5xx/sc59x_64.c | 97 ++ arch/arm/mach-sc5xx/soc.c| 179 arch/arm/mach-sc5xx/spl.c| 102 ++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/adi/Kconfig | 83 ++ drivers/clk/adi/Makefile | 16 + drivers/clk/adi/clk-adi-pll.c| 93 ++ drivers/clk/adi/clk-adi-sc57x.c | 206 drivers/clk/adi/clk-adi-sc58x.c | 222 + drivers/clk/adi/clk-adi-sc594.c | 231 + drivers/clk/adi/clk-adi-sc598.c | 308 ++ drivers/clk/adi/clk-shared.c | 48 + drivers/clk/adi/clk.h| 123 +++ drivers/serial/Makefile | 1 + drivers/serial/serial_adi_uart4.c| 225 + drivers/timer/Kconfig| 8 + drivers/timer/Makefile | 1 + drivers/timer/adi_sc5xx_timer.c | 145 +++ include/dt-bindings/clock/adi-sc5xx-clock.h | 271 ++ include/env/adi/adi_boot.env | 122 +++ 43 files changed, 5027 insertions
[PATCH v2 2/4] drivers: clk: adi: Add in SC5XX-family clock driver
From: Nathan Barrett-Morrison This adds support for the SC5XX clock trees which are required for reading clock speeds on the SoCs. This is largely a port of the same support for Linux, which has not yet been submitted upstream. Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs Signed-off-by: Nathan Barrett-Morrison --- (no changes since v1) MAINTAINERS | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile| 1 + drivers/clk/adi/Kconfig | 83 ++ drivers/clk/adi/Makefile| 16 + drivers/clk/adi/clk-adi-pll.c | 93 ++ drivers/clk/adi/clk-adi-sc57x.c | 206 + drivers/clk/adi/clk-adi-sc58x.c | 222 ++ drivers/clk/adi/clk-adi-sc594.c | 231 +++ drivers/clk/adi/clk-adi-sc598.c | 308 drivers/clk/adi/clk-shared.c| 48 +++ drivers/clk/adi/clk.h | 123 include/dt-bindings/clock/adi-sc5xx-clock.h | 271 + 13 files changed, 1604 insertions(+) create mode 100644 drivers/clk/adi/Kconfig create mode 100644 drivers/clk/adi/Makefile create mode 100644 drivers/clk/adi/clk-adi-pll.c create mode 100644 drivers/clk/adi/clk-adi-sc57x.c create mode 100644 drivers/clk/adi/clk-adi-sc58x.c create mode 100644 drivers/clk/adi/clk-adi-sc594.c create mode 100644 drivers/clk/adi/clk-adi-sc598.c create mode 100644 drivers/clk/adi/clk-shared.c create mode 100644 drivers/clk/adi/clk.h create mode 100644 include/dt-bindings/clock/adi-sc5xx-clock.h diff --git a/MAINTAINERS b/MAINTAINERS index f743ce9f9d..78e3d59f96 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -609,6 +609,7 @@ S: Supported T: git https://github.com/analogdevicesinc/lnxdsp-u-boot F: arch/arm/include/asm/arch-adi/ F: arch/arm/mach-sc5xx/ +F: drivers/clk/adi/ F: include/env/adi/ ARM SNAPDRAGON diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 017dd260a5..d8c619add4 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -246,6 +246,7 @@ config CLK_ZYNQMP This clock driver adds support for clock realted settings for ZynqMP platform. +source "drivers/clk/adi/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/at91/Kconfig" source "drivers/clk/exynos/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 638ad04bae..847b9b2911 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o obj-$(CONFIG_$(SPL_TPL_)CLK_GPIO) += clk-gpio.o +obj-y += adi/ obj-y += analogbits/ obj-y += imx/ obj-$(CONFIG_CLK_JH7110) += starfive/ diff --git a/drivers/clk/adi/Kconfig b/drivers/clk/adi/Kconfig new file mode 100644 index 00..5745bedf88 --- /dev/null +++ b/drivers/clk/adi/Kconfig @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2022 - Analog Devices, Inc. +# +# Written and/or maintained by Timesys Corporation +# +# Contact: Nathan Barrett-Morrison +# Contact: Greg Malysa +# + +config COMMON_CLK_ADI_SHARED + bool "Enable shared ADI clock framework code" + help + Required for shared code between SoC clock drivers. Automatically + selected by an appropriate SoC-specific clock driver version. + +config COMMON_CLK_ADI_SC598 + bool "Clock driver for ADI SC598 SoCs" + select DM + select CLK + select CLK_CCF + select OF_CONTROL + select CMD_CLK + select SPL_DM if SPL + select SPL_CLK if SPL + select SPL_CLK_CCF if SPL + select SPL_OF_CONTROL if SPL + select COMMON_CLK_ADI_SHARED + depends on SC59X_64 + help + This driver supports the system clocks on Analog Devices SC598-series + SoCs. It includes CGU and CDU clocks and supports gating unused clocks. + Modifying PLL configuration is not supported; that must be done prior + to booting the kernel. Clock dividers after the PLLs may be configured. + +config COMMON_CLK_ADI_SC594 + bool "Clock driver for ADI SC594 SoCs" + select DM + select CLK + select CLK_CCF + select OF_CONTROL + select CMD_CLK + select SPL_DM if SPL + select SPL_CLK if SPL + select SPL_CLK_CCF if SPL + select SPL_OF_CONTROL if SPL + select COMMON_CLK_ADI_SHARED + depends on SC59X + help + This driver supports the system clocks on Analog Devices SC594-series + SoCs. It includes CGU and CDU clocks and
[PATCH v2 3/4] drivers: serial: Add in UART for ADI SC5XX-family processors
From: Nathan Barrett-Morrison
Co-developed-by: Greg Malysa
Signed-off-by: Greg Malysa
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Artamonovs
Signed-off-by: Nathan Barrett-Morrison
---
(no changes since v1)
MAINTAINERS | 1 +
drivers/serial/Makefile | 1 +
drivers/serial/serial_adi_uart4.c | 225 ++
3 files changed, 227 insertions(+)
create mode 100644 drivers/serial/serial_adi_uart4.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 78e3d59f96..74310c8f9d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -610,6 +610,7 @@ T: git https://github.com/analogdevicesinc/lnxdsp-u-boot
F: arch/arm/include/asm/arch-adi/
F: arch/arm/mach-sc5xx/
F: drivers/clk/adi/
+F: drivers/serial/serial_adi_uart4.c
F: include/env/adi/
ARM SNAPDRAGON
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 403ab1ded6..dbe598b740 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -65,3 +65,4 @@ obj-$(CONFIG_S5P4418_PL011_SERIAL) += serial_s5p4418_pl011.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
endif
+obj-$(CONFIG_UART4_SERIAL) += serial_adi_uart4.o
diff --git a/drivers/serial/serial_adi_uart4.c
b/drivers/serial/serial_adi_uart4.c
new file mode 100644
index 00..45f8315d0a
--- /dev/null
+++ b/drivers/serial/serial_adi_uart4.c
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Converted to driver model by Nathan Barrett-Morrison
+ *
+ * Contact: Nathan Barrett-Morrison
+ * Contact: Greg Malysa
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * UART4 Masks
+ */
+
+/* UART_CONTROL */
+#define UENBIT(0)
+#define LOOP_ENA BIT(1)
+#define UMOD (3 << 4)
+#define UMOD_UART (0 << 4)
+#define UMOD_MDB BIT(4)
+#define UMOD_IRDA BIT(4)
+#define WLS(3 << 8)
+#define WLS_5 (0 << 8)
+#define WLS_6 BIT(8)
+#define WLS_7 (2 << 8)
+#define WLS_8 (3 << 8)
+#define STBBIT(12)
+#define STBH BIT(13)
+#define PENBIT(14)
+#define EPSBIT(15)
+#define STPBIT(16)
+#define FPEBIT(17)
+#define FFEBIT(18)
+#define SB BIT(19)
+#define FCPOL BIT(22)
+#define RPOLC BIT(23)
+#define TPOLC BIT(24)
+#define MRTS BIT(25)
+#define XOFF BIT(26)
+#define ARTS BIT(27)
+#define ACTS BIT(28)
+#define RFIT BIT(29)
+#define RFRT BIT(30)
+
+/* UART_STATUS */
+#define DR BIT(0)
+#define OE BIT(1)
+#define PE BIT(2)
+#define FE BIT(3)
+#define BI BIT(4)
+#define THRE BIT(5)
+#define TEMT BIT(7)
+#define TFIBIT(8)
+#define ASTKY BIT(9)
+#define ADDR BIT(10)
+#define RO BIT(11)
+#define SCTS BIT(12)
+#define CTSBIT(16)
+#define RFCS BIT(17)
+
+/* UART_EMASK */
+#define ERBFI BIT(0)
+#define ETBEI BIT(1)
+#define ELSI BIT(2)
+#define EDSSI BIT(3)
+#define EDTPTI BIT(4)
+#define ETFI BIT(5)
+#define ERFCI BIT(6)
+#define EAWI BIT(7)
+#define ERXS BIT(8)
+#define ETXS BIT(9)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct uart4_reg {
+ u32 revid;
+ u32 control;
+ u32 status;
+ u32 scr;
+ u32 clock;
+ u32 emask;
+ u32 emaskst;
+ u32 emaskcl;
+ u32 rbr;
+ u32 thr;
+ u32 taip;
+ u32 tsr;
+ u32 rsr;
+ u32 txdiv_cnt;
+ u32 rxdiv_cnt;
+};
+
+struct adi_uart4_platdata {
+ // Hardware registers
+ struct uart4_reg *regs;
+
+ // Enable divide-by-one baud rate setting
+ bool edbo;
+};
+
+static int adi_uart4_set_brg(struct udevice *dev, int baudrate)
+{
+ struct adi_uart4_platdata *plat = dev_get_plat(dev);
+ struct uart4_reg *regs = plat->regs;
+ u32 divisor, uart_base_clk_rate;
+ struct clk uart_base_clk;
+
+ if (clk_get_by_index(dev, 0, _base_clk)) {
+ dev_err(dev, "Could not get UART base clock\n");
+ return -1;
+ }
+
+ uart_base_clk_r
[PATCH v2 4/4] drivers: timer: Add in driver support for ADI SC5XX-family GP timer peripheral
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Co-developed-by: Angelo Dureghello
Signed-off-by: Angelo Dureghello
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Greg Malysa
---
Changes in v2:
- Added gptimer driver to this series because a minimal system can't
boot without it
---
MAINTAINERS | 1 +
drivers/timer/Kconfig | 8 ++
drivers/timer/Makefile | 1 +
drivers/timer/adi_sc5xx_timer.c | 145
4 files changed, 155 insertions(+)
create mode 100644 drivers/timer/adi_sc5xx_timer.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 74310c8f9d..eddd4f2c23 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -611,6 +611,7 @@ F: arch/arm/include/asm/arch-adi/
F: arch/arm/mach-sc5xx/
F: drivers/clk/adi/
F: drivers/serial/serial_adi_uart4.c
+F: drivers/timer/adi_sc5xx_timer.c
F: include/env/adi/
ARM SNAPDRAGON
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 60519c3b53..6b1de82ae3 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -50,6 +50,14 @@ config TIMER_EARLY
use an early timer. These functions must be supported by your timer
driver: timer_early_get_count() and timer_early_get_rate().
+config ADI_SC5XX_TIMER
+ bool "ADI ADSP-SC5xx Timer Support"
+ depends on TIMER && (SC57X || SC58X || SC59X || SC59X_64)
+ help
+ gptimer based timer support on ADI's ADSP-SC5xx platforms. Available
+ but not required on sc59x-64-based platforms (598 and similar).
+ Required on 32-bit platforms (sc57x, sc58x, sc594 and earlier).
+
config ALTERA_TIMER
bool "Altera timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index b93145e8d4..fb95c8899e 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -3,6 +3,7 @@
# Copyright (C) 2015 Thomas Chou
obj-y += timer-uclass.o
+obj-$(CONFIG_ADI_SC5XX_TIMER) += adi_sc5xx_timer.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o
obj-$(CONFIG_ARC_TIMER)+= arc_timer.o
diff --git a/drivers/timer/adi_sc5xx_timer.c b/drivers/timer/adi_sc5xx_timer.c
new file mode 100644
index 00..11c098434a
--- /dev/null
+++ b/drivers/timer/adi_sc5xx_timer.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Converted to driver model by Nathan Barrett-Morrison
+ *
+ * Author: Greg Malysa
+ * Additional Contact: Nathan Barrett-Morrison
+ *
+ * dm timer implementation for ADI ADSP-SC5xx SoCs
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * Timer Configuration Register Bits
+ */
+#define TIMER_OUT_DIS 0x0800
+#define TIMER_PULSE_HI 0x0080
+#define TIMER_MODE_PWM_CONT 0x000c
+
+#define __BFP(m) u16 m; u16 __pad_##m
+
+struct gptimer3 {
+ __BFP(config);
+ u32 counter;
+ u32 period;
+ u32 width;
+ u32 delay;
+};
+
+struct gptimer3_group_regs {
+ __BFP(run);
+ __BFP(enable);
+ __BFP(disable);
+ __BFP(stop_cfg);
+ __BFP(stop_cfg_set);
+ __BFP(stop_cfg_clr);
+ __BFP(data_imsk);
+ __BFP(stat_imsk);
+ __BFP(tr_msk);
+ __BFP(tr_ie);
+ __BFP(data_ilat);
+ __BFP(stat_ilat);
+ __BFP(err_status);
+ __BFP(bcast_per);
+ __BFP(bcast_wid);
+ __BFP(bcast_dly);
+};
+
+#define MAX_TIM_LOAD 0x
+
+struct adi_gptimer_priv {
+ struct gptimer3_group_regs __iomem *timer_group;
+ struct gptimer3 __iomem *timer_base;
+ u32 prev;
+ u64 upper;
+};
+
+static u64 adi_gptimer_get_count(struct udevice *udev)
+{
+ struct adi_gptimer_priv *priv = dev_get_priv(udev);
+
+ u32 now = readl(>timer_base->counter);
+
+ if (now < priv->prev)
+ priv->upper += (1ull << 32);
+
+ priv->prev = now;
+
+ return (priv->upper + (u64)now);
+}
+
+static const struct timer_ops adi_gptimer_ops = {
+ .get_count = adi_gptimer_get_count,
+};
+
+static int adi_gptimer_probe(struct udevice *udev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(udev);
+ struct adi_gptimer_priv *priv = dev_get_priv(udev);
+ struct clk clk;
+ u16 imask;
+ int ret;
+
+ priv->timer_group = dev_remap_addr_index(udev, 0);
+ priv->timer_base = dev_remap_addr_index(udev, 1);
+ priv->upper = 0;
+ priv->prev = 0;
+
+ if (!priv->timer_group || !priv->timer_base) {
+ dev_err(udev, "Missing timer_group or timer_base reg
entries\n");
+ return -ENODEV;
+ }
+
+ ret = clk_get_by_index(udev, 0, );
+ if (ret < 0) {
+
[PATCH v2] mmc: sdhci: introduce adma_write_desc() hook to struct sdhci_ops
From: Ian Roberts
Add this hook so that it can be overridden with driver specific
implementations. We also let the original sdhci_adma_write_desc()
accept so that the function can set its new value. Then export
the function so that it could be reused by driver's specific
implementations.
The above is a port of Linux kernel commit 54552e4948cbf
In addition, allow drivers to allocate their own ADMA descriptor
tables if additional space is required.
Finally, fix the assignment of adma_addr to fix compiler warning
on 64-bit platforms that still use 32-bit DMA addressing.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Co-developed-by: Greg Malysa
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
---
Changes in v2:
- Switch from #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) to #ifdef
CONFIG_MMC_SDHCI_ADMA_HELPERS, as CONFIG_IS_ENABLED() causes a build
failure during SPL builds when CONFIG_SPL_MMC is set.
- Passed CI before submitting this time
---
drivers/mmc/fsl_esdhc.c | 2 +-
drivers/mmc/sdhci-adma.c | 41 +++-
drivers/mmc/sdhci.c | 8 +---
include/sdhci.h | 12 ++--
4 files changed, 44 insertions(+), 19 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index d50669..bd0671cc52 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -252,7 +252,7 @@ static void esdhc_setup_dma(struct fsl_esdhc_priv *priv,
struct mmc_data *data)
priv->adma_desc_table) {
debug("Using ADMA2\n");
/* prefer ADMA2 if it is available */
- sdhci_prepare_adma_table(priv->adma_desc_table, data,
+ sdhci_prepare_adma_table(NULL, priv->adma_desc_table, data,
priv->dma_addr);
adma_addr = virt_to_phys(priv->adma_desc_table);
diff --git a/drivers/mmc/sdhci-adma.c b/drivers/mmc/sdhci-adma.c
index 8213223d3f..8c38448b6a 100644
--- a/drivers/mmc/sdhci-adma.c
+++ b/drivers/mmc/sdhci-adma.c
@@ -9,9 +9,10 @@
#include
#include
-static void sdhci_adma_desc(struct sdhci_adma_desc *desc,
- dma_addr_t addr, u16 len, bool end)
+void sdhci_adma_write_desc(struct sdhci_host *host, void **next_desc,
+ dma_addr_t addr, int len, bool end)
{
+ struct sdhci_adma_desc *desc = *next_desc;
u8 attr;
attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
@@ -19,17 +20,30 @@ static void sdhci_adma_desc(struct sdhci_adma_desc *desc,
attr |= ADMA_DESC_ATTR_END;
desc->attr = attr;
- desc->len = len;
+ desc->len = len & 0x;
desc->reserved = 0;
desc->addr_lo = lower_32_bits(addr);
#ifdef CONFIG_DMA_ADDR_T_64BIT
desc->addr_hi = upper_32_bits(addr);
#endif
+
+ *next_desc += ADMA_DESC_LEN;
+}
+
+static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
+ void **desc, dma_addr_t addr,
+ int len, bool end)
+{
+ if (host && host->ops && host->ops->adma_write_desc)
+ host->ops->adma_write_desc(host, desc, addr, len, end);
+ else
+ sdhci_adma_write_desc(host, desc, addr, len, end);
}
/**
* sdhci_prepare_adma_table() - Populate the ADMA table
*
+ * @host: Pointer to the sdhci_host
* @table: Pointer to the ADMA table
* @data: Pointer to MMC data
* @addr: DMA address to write to or read from
@@ -39,25 +53,26 @@ static void sdhci_adma_desc(struct sdhci_adma_desc *desc,
* Please note, that the table size depends on CONFIG_SYS_MMC_MAX_BLK_COUNT and
* we don't have to check for overflow.
*/
-void sdhci_prepare_adma_table(struct sdhci_adma_desc *table,
- struct mmc_data *data, dma_addr_t addr)
+void sdhci_prepare_adma_table(struct sdhci_host *host,
+ struct sdhci_adma_desc *table,
+ struct mmc_data *data, dma_addr_t start_addr)
{
+ dma_addr_t addr = start_addr;
uint trans_bytes = data->blocksize * data->blocks;
- uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
- struct sdhci_adma_desc *desc = table;
- int i = desc_count;
+ void *next_desc = table;
+ int i = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
while (--i) {
- sdhci_adma_desc(desc, addr, ADMA_MAX_LEN, false);
+ __sdhci_adma_write_desc(host, _desc, addr,
+ ADMA_MAX_LEN, false);
addr += ADMA_MAX_LEN;
trans_bytes -= ADMA_MAX_LEN;
- desc++;
}
- sdhci_adma_desc(desc, addr, trans_bytes, true);
+ __sdhci_adma_write_desc(host, _desc, addr, trans_bytes, true);
-
Re: [PATCH] mmc: sdhci: introduce adma_write_desc() hook to struct sdhci_ops
Hi,
> Some target are failed to build. (e.g, j721e_beagleboneai64_r5)
>
> +drivers/mmc/sdhci-adma.c: In function '__sdhci_adma_write_desc':
> +drivers/mmc/sdhci-adma.c:37:43: error: 'const struct sdhci_ops' has no
> member named 'adma_write_desc'
> + 37 | if (host && host->ops && host->ops->adma_write_desc)
> + | ^~
> +drivers/mmc/sdhci-adma.c:38:26: error: 'const struct sdhci_ops' has no
> member named 'adma_write_desc'
> + 38 | host->ops->adma_write_desc(host, desc, addr, len,
> end);
> + | ^~
> +make[3]: *** [scripts/Makefile.build:257: drivers/mmc/sdhci-adma.o] Error 1
> +make[2]: *** [scripts/Makefile.build:397: drivers/mmc] Error 2
I will test v2 with CI before resubmitting so that this issue is
fixed. It is caused by the change and explanation below:
> > > diff --git a/include/sdhci.h b/include/sdhci.h
> > > index a1b74e3bd7..4bde7db5c7 100644
> > > --- a/include/sdhci.h
> > > +++ b/include/sdhci.h
> > > @@ -291,6 +291,11 @@ struct sdhci_ops {
> > > * Return: 0 if successful, -ve on error
> > > */
> > > int (*set_enhanced_strobe)(struct sdhci_host *host);
> > > +
> > > +#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
> > > + void(*adma_write_desc)(struct sdhci_host *host, void **desc,
> > > + dma_addr_t addr, int len, bool end);
> > > +#endif
> > > };
We got a little too excited about following checkpatch's
recommendations (no #ifdef CONFIG_xyz, prefer #if
CONFIG_IS_ENABLED(xyz)), which breaks down in this case:
CONFIG_IS_ENABLED(xyz) checks if:
- regular build and CONFIG_xyz is enabled (this portion succeeds)
- SPL build and CONFIG_SPL_xyz is enabled (this portion fails)
drivers/mmc/Makefile builds sdhci-adma.o based on
CONFIG_SDHCI_ADMA_HELPERS only.
There is no CONFIG_SPL_SDHCI_ADMA_HELPERS so CONFIG_IS_ENABLED fails
while building the SPL version of sdhci-adma.o as the structure
definition is different. This only appears on platforms which have
CONFIG_SPL_MMC enabled, which our platform did not, so I missed this
interaction earlier. I apologize for this mistake.
This will be fixed in v2 by changing the #if back to #ifdef
CONFIG_MMC_SDHCI_ADMA_HELPERS, which I will submit after CI finishes
running to verify on all platforms.
Thanks,
Greg
--
Greg Malysa
Timesys Corporation
Re: [PATCH] usb: dwc2: Add in version 4xx compatibility
Hi Mattijs, > Please avoid top-posting when replying, it makes following the > discussion more difficult: > https://www.kernel.org/doc/html/latest/process/submitting-patches.html#use-trimmed-interleaved-replies-in-email-discussions Will do. Sorry about that; I'm still learning about this approach to email. > Looking at > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=65dc2e725286106f99c6f6b78e3d9c52c15f3a9c > > we can see that the following is added: > #define DWC2_CORE_REV_MASK 0x > > This makes me believe that the versioning follows a well known pattern. I can submit a v2 next week to bring it in line with the kernel's approach. > Note that this change is also part of: > https://lore.kernel.org/all/20240328131811.94559-1-seashell11234...@gmail.com/ Or if you prefer I can also drop our patch and we can pursue this linked patch with both 4xx compatibility and the 420a reset handling. Thanks, Greg
Re: [PATCH 0/3] arm: Add Analog Devices SC5xx Machine Type
I'm afraid I have to admit I don't know. I'll work with our IT team to make sure we can run CI locally, and when v2 comes around the answer will be yes. On Thu, Apr 11, 2024 at 7:52 PM Tom Rini wrote: > > On Thu, Apr 11, 2024 at 07:37:27PM -0400, Greg Malysa wrote: > > > > This series adds support for the ADI SC5xx machine type and includes two > > core drivers that are required for being able to boot any board--a UART > > driver and the clock tree driver. Our corresponding Linux support relies > > on u-boot configuring the clocks correctly before booting, so it is not > > possible to boot any board without the CGU/CDU configuration happening > > here. The clock tree itself is only used by the UART in this minimal > > patch set, but is of course broadly useful for all other peripheral > > drivers to be submitted in future patch sets. There are also no board > > files or defconfigs included here, but some common definitions that will > > be used to build board files currently are. > > > > Some of the configuration code in dmcinit and clkinit is quite scary and > > causes a lot of checkpatch violations. It is modified from code > > initially provided by ADI, but it has not been fully rewritten. There's > > a question of how important it is to clean up this code--it has some > > quality violations, but it has been in use (including in production) for > > over two years and is known to work for performing the low level SoC > > initialization, while a rewrite might introduce bugs that could take a > > significant amount of time to detect in the future. > > > > Please provide any feedback or comments that will be helpful in creating > > a v2 of this patch that will be ready to submit for inclusion into the > > main tree, as well as general observations that we should consider in > > other driver patches before submitting them. > > Does this series pass CI currently? Thanks. > > -- > Tom -- Greg Malysa Timesys Corporation
Re: [PATCH 1/3] arch: arm: Add Analog Devices SC5xx machine type
Hi Tom, Thanks for the quick feedback. I'll go through our patches and review the #include usage as part of preparing for v2, and we'll work out switching to the plain text environment as well. I'll drop the custom compiler options and make sure we weren't actually relying on them--possibly it was just necessary for the initial set of init code we started with. I believe we're not using the mach type constants anywhere so that will be straightforward to drop as well. Thanks, Greg On Thu, Apr 11, 2024 at 7:58 PM Tom Rini wrote: > > On Thu, Apr 11, 2024 at 07:37:28PM -0400, Greg Malysa wrote: > > > From: Nathan Barrett-Morrison > > > > Add support for the SC5xx machine type from Analog Devices. This > > includes support for the SC57x, SC58x, SC59x, and SC59x-64 SoCs, which > > have many common features such as common ADI IP blocks, and SHARC DSP > > cores. This commit introduces core functionality required for all boards > > using an SC5xx SoC, such as: > > > > - SPL configuration > > - Required CPU hooks such as reset > > - Boot ROM interaction to load the stage 2 bootloader in the reference > > configuration. Other options are possible but not officially supported > > at this time > > - SoC-common configuration expected to be reused by all boards > > - Early initialization for system clocks and DDR controller > > > > Co-developed-by: Greg Malysa > > Signed-off-by: Greg Malysa > > Co-developed-by: Ian Roberts > > Signed-off-by: Ian Roberts > > Signed-off-by: Vasileios Bimpikas > > Signed-off-by: Utsav Agarwal > > Signed-off-by: Arturs Artamonovs > > Signed-off-by: Nathan Barrett-Morrison > > > > --- > > > > > > --- > > MAINTAINERS | 13 + > > arch/arm/Kconfig | 6 + > > arch/arm/Makefile| 1 + > > arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h | 115 +++ > > arch/arm/include/asm/arch-adi/sc5xx/soc.h| 18 + > > arch/arm/include/asm/arch-adi/sc5xx/spl.h| 41 + > > arch/arm/include/asm/mach-types.h| 4 + > > We shouldn't be adding more to mach-types.h. > > > arch/arm/mach-sc5xx/Kconfig | 464 + > > Here and elsewhere I think I saw whitespace issues (help should be > ) in the entries, along with adding "default n" for > new options, and that's not needed as n is the default. > > [snip] > > diff --git a/arch/arm/mach-sc5xx/config.mk b/arch/arm/mach-sc5xx/config.mk > > new file mode 100644 > > index 00..b80644d6dc > > --- /dev/null > > +++ b/arch/arm/mach-sc5xx/config.mk > [snip] > > +ifndef CONFIG_SC59X_64 > > + # Select the Analog Devices processor. > > + PLATFORM_RELFLAGS += -fno-stack-protector -std=gnu89 > > +endif > > We should be using the defaults here. > > Also: > - Please switch to plain text environment instead of defining in board.h > and so on. > - Audit your #include usage, I saw more that is likely needed > for example. > > -- > Tom -- Greg Malysa Timesys Corporation
[PATCH 1/3] arch: arm: Add Analog Devices SC5xx machine type
From: Nathan Barrett-Morrison Add support for the SC5xx machine type from Analog Devices. This includes support for the SC57x, SC58x, SC59x, and SC59x-64 SoCs, which have many common features such as common ADI IP blocks, and SHARC DSP cores. This commit introduces core functionality required for all boards using an SC5xx SoC, such as: - SPL configuration - Required CPU hooks such as reset - Boot ROM interaction to load the stage 2 bootloader in the reference configuration. Other options are possible but not officially supported at this time - SoC-common configuration expected to be reused by all boards - Early initialization for system clocks and DDR controller Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs Signed-off-by: Nathan Barrett-Morrison --- --- MAINTAINERS | 13 + arch/arm/Kconfig | 6 + arch/arm/Makefile| 1 + arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h | 115 +++ arch/arm/include/asm/arch-adi/sc5xx/soc.h| 18 + arch/arm/include/asm/arch-adi/sc5xx/spl.h| 41 + arch/arm/include/asm/mach-types.h| 4 + arch/arm/mach-sc5xx/Kconfig | 464 + arch/arm/mach-sc5xx/Makefile | 19 + arch/arm/mach-sc5xx/config.mk| 21 + arch/arm/mach-sc5xx/init/Makefile| 11 + arch/arm/mach-sc5xx/init/clkinit.c | 543 +++ arch/arm/mach-sc5xx/init/clkinit.h | 18 + arch/arm/mach-sc5xx/init/dmcinit.c | 973 +++ arch/arm/mach-sc5xx/init/dmcinit.h | 29 + arch/arm/mach-sc5xx/init/init.c | 68 ++ arch/arm/mach-sc5xx/init/init.h | 37 + arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h | 63 ++ arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h | 51 + arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h | 51 + arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h | 50 + arch/arm/mach-sc5xx/rcu.c| 22 + arch/arm/mach-sc5xx/sc57x.c | 21 + arch/arm/mach-sc5xx/sc58x.c | 21 + arch/arm/mach-sc5xx/sc59x.c | 32 + arch/arm/mach-sc5xx/sc59x_64.c | 36 + arch/arm/mach-sc5xx/soc.c| 142 +++ arch/arm/mach-sc5xx/spl.c| 140 +++ include/configs/sc_adi_common.h | 226 + 29 files changed, 3236 insertions(+) create mode 100644 arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h create mode 100644 arch/arm/include/asm/arch-adi/sc5xx/soc.h create mode 100644 arch/arm/include/asm/arch-adi/sc5xx/spl.h create mode 100644 arch/arm/mach-sc5xx/Kconfig create mode 100644 arch/arm/mach-sc5xx/Makefile create mode 100644 arch/arm/mach-sc5xx/config.mk create mode 100644 arch/arm/mach-sc5xx/init/Makefile create mode 100644 arch/arm/mach-sc5xx/init/clkinit.c create mode 100644 arch/arm/mach-sc5xx/init/clkinit.h create mode 100644 arch/arm/mach-sc5xx/init/dmcinit.c create mode 100644 arch/arm/mach-sc5xx/init/dmcinit.h create mode 100644 arch/arm/mach-sc5xx/init/init.c create mode 100644 arch/arm/mach-sc5xx/init/init.h create mode 100644 arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h create mode 100644 arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h create mode 100644 arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h create mode 100644 arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h create mode 100644 arch/arm/mach-sc5xx/rcu.c create mode 100644 arch/arm/mach-sc5xx/sc57x.c create mode 100644 arch/arm/mach-sc5xx/sc58x.c create mode 100644 arch/arm/mach-sc5xx/sc59x.c create mode 100644 arch/arm/mach-sc5xx/sc59x_64.c create mode 100644 arch/arm/mach-sc5xx/soc.c create mode 100644 arch/arm/mach-sc5xx/spl.c create mode 100644 include/configs/sc_adi_common.h diff --git a/MAINTAINERS b/MAINTAINERS index 83fd68e3f3..9693b86ddd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -598,6 +598,19 @@ R: Marc Murphy S: Supported F: arch/arm/dts/am335x-sancloud* +ARM SC5XX +M: Nathan Barrett-Morrison +M: Greg Malysa +M: Ian Roberts +M: Vasileios Bimpikas +M: Utsav Agarwal +M: Arturs Artamonovs +S: Supported +T: git https://github.com/analogdevicesinc/lnxdsp-u-boot +F: arch/arm/include/asm/arch-adi/ +F: arch/arm/mach-sc5xx/ +F: include/configs/sc_adi_common.h + ARM SNAPDRAGON M: Caleb Connolly M: Neil Armstrong diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a0842e1933..fdaf4e23d0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1843,6 +1843,10 @@ config TARGET_LS1046AFRWY development platform that supports the QorIQ LS1046A Layerscape Architecture processor. +config ARCH_SC5XX + bool "Analog Devices SC5XX-processor family" + select STATIC_MACH_TYPE + config T
[PATCH 0/3] arm: Add Analog Devices SC5xx Machine Type
This series adds support for the ADI SC5xx machine type and includes two core drivers that are required for being able to boot any board--a UART driver and the clock tree driver. Our corresponding Linux support relies on u-boot configuring the clocks correctly before booting, so it is not possible to boot any board without the CGU/CDU configuration happening here. The clock tree itself is only used by the UART in this minimal patch set, but is of course broadly useful for all other peripheral drivers to be submitted in future patch sets. There are also no board files or defconfigs included here, but some common definitions that will be used to build board files currently are. Some of the configuration code in dmcinit and clkinit is quite scary and causes a lot of checkpatch violations. It is modified from code initially provided by ADI, but it has not been fully rewritten. There's a question of how important it is to clean up this code--it has some quality violations, but it has been in use (including in production) for over two years and is known to work for performing the low level SoC initialization, while a rewrite might introduce bugs that could take a significant amount of time to detect in the future. Please provide any feedback or comments that will be helpful in creating a v2 of this patch that will be ready to submit for inclusion into the main tree, as well as general observations that we should consider in other driver patches before submitting them. Thank you! Nathan Barrett-Morrison (3): arch: arm: Add Analog Devices SC5xx machine type drivers: clk: adi: Add in SC5XX-family clock driver drivers: serial: Add in UART for ADI SC5XX-family processors MAINTAINERS | 15 + arch/arm/Kconfig | 6 + arch/arm/Makefile| 1 + arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h | 115 +++ arch/arm/include/asm/arch-adi/sc5xx/soc.h| 18 + arch/arm/include/asm/arch-adi/sc5xx/spl.h| 41 + arch/arm/include/asm/mach-types.h| 4 + arch/arm/mach-sc5xx/Kconfig | 464 + arch/arm/mach-sc5xx/Makefile | 19 + arch/arm/mach-sc5xx/config.mk| 21 + arch/arm/mach-sc5xx/init/Makefile| 11 + arch/arm/mach-sc5xx/init/clkinit.c | 543 +++ arch/arm/mach-sc5xx/init/clkinit.h | 18 + arch/arm/mach-sc5xx/init/dmcinit.c | 973 +++ arch/arm/mach-sc5xx/init/dmcinit.h | 29 + arch/arm/mach-sc5xx/init/init.c | 68 ++ arch/arm/mach-sc5xx/init/init.h | 37 + arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h | 63 ++ arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h | 51 + arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h | 51 + arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h | 50 + arch/arm/mach-sc5xx/rcu.c| 22 + arch/arm/mach-sc5xx/sc57x.c | 21 + arch/arm/mach-sc5xx/sc58x.c | 21 + arch/arm/mach-sc5xx/sc59x.c | 32 + arch/arm/mach-sc5xx/sc59x_64.c | 36 + arch/arm/mach-sc5xx/soc.c| 142 +++ arch/arm/mach-sc5xx/spl.c| 140 +++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/adi/Kconfig | 83 ++ drivers/clk/adi/Makefile | 16 + drivers/clk/adi/clk-adi-pll.c| 94 ++ drivers/clk/adi/clk-adi-sc57x.c | 205 drivers/clk/adi/clk-adi-sc58x.c | 221 + drivers/clk/adi/clk-adi-sc594.c | 230 + drivers/clk/adi/clk-adi-sc598.c | 307 ++ drivers/clk/adi/clk-shared.c | 48 + drivers/clk/adi/clk.h| 122 +++ drivers/serial/Makefile | 1 + drivers/serial/serial_adi_uart4.c| 228 + include/configs/sc_adi_common.h | 226 + include/dt-bindings/clock/adi-sc5xx-clock.h | 271 ++ 43 files changed, 5066 insertions(+) create mode 100644 arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h create mode 100644 arch/arm/include/asm/arch-adi/sc5xx/soc.h create mode 100644 arch/arm/include/asm/arch-adi/sc5xx/spl.h create mode 100644 arch/arm/mach-sc5xx/Kconfig create mode 100644 arch/arm/mach-sc5xx/Makefile create mode 100644 arch/arm/mach-sc5xx/config.mk create mode 100644 arch/arm/mach-sc5xx/init/Makefile create mode 100644 arch/arm/mach-sc5xx/init/clkinit.c create mode 100644 arch/arm/mach-sc5xx/init/clkinit.h create mode 100644 arch/arm/mach-sc5xx/init/dmcinit.c create mode 100644 arch/arm/mach-sc5xx/init/dmcinit.h create mode 100644 arch/arm/mach-sc5xx/init/init.c create mode 100644 arch/arm/mach-sc5xx/init/init.h create mode 100644 arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h create mode 100644 arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h create mode
[PATCH 2/3] drivers: clk: adi: Add in SC5XX-family clock driver
From: Nathan Barrett-Morrison This adds support for the SC5XX clock trees which are required for reading clock speeds on the SoCs. This is largely a port of the same support for Linux, which has not yet been submitted upstream. Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs Signed-off-by: Nathan Barrett-Morrison --- MAINTAINERS | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile| 1 + drivers/clk/adi/Kconfig | 83 ++ drivers/clk/adi/Makefile| 16 + drivers/clk/adi/clk-adi-pll.c | 94 ++ drivers/clk/adi/clk-adi-sc57x.c | 205 + drivers/clk/adi/clk-adi-sc58x.c | 221 ++ drivers/clk/adi/clk-adi-sc594.c | 230 +++ drivers/clk/adi/clk-adi-sc598.c | 307 drivers/clk/adi/clk-shared.c| 48 +++ drivers/clk/adi/clk.h | 122 include/dt-bindings/clock/adi-sc5xx-clock.h | 271 + 13 files changed, 1600 insertions(+) create mode 100644 drivers/clk/adi/Kconfig create mode 100644 drivers/clk/adi/Makefile create mode 100644 drivers/clk/adi/clk-adi-pll.c create mode 100644 drivers/clk/adi/clk-adi-sc57x.c create mode 100644 drivers/clk/adi/clk-adi-sc58x.c create mode 100644 drivers/clk/adi/clk-adi-sc594.c create mode 100644 drivers/clk/adi/clk-adi-sc598.c create mode 100644 drivers/clk/adi/clk-shared.c create mode 100644 drivers/clk/adi/clk.h create mode 100644 include/dt-bindings/clock/adi-sc5xx-clock.h diff --git a/MAINTAINERS b/MAINTAINERS index 9693b86ddd..a9f52a6c7e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -609,6 +609,7 @@ S: Supported T: git https://github.com/analogdevicesinc/lnxdsp-u-boot F: arch/arm/include/asm/arch-adi/ F: arch/arm/mach-sc5xx/ +F: drivers/clk/adi/ F: include/configs/sc_adi_common.h ARM SNAPDRAGON diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 017dd260a5..d8c619add4 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -246,6 +246,7 @@ config CLK_ZYNQMP This clock driver adds support for clock realted settings for ZynqMP platform. +source "drivers/clk/adi/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/at91/Kconfig" source "drivers/clk/exynos/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 638ad04bae..847b9b2911 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o obj-$(CONFIG_$(SPL_TPL_)CLK_GPIO) += clk-gpio.o +obj-y += adi/ obj-y += analogbits/ obj-y += imx/ obj-$(CONFIG_CLK_JH7110) += starfive/ diff --git a/drivers/clk/adi/Kconfig b/drivers/clk/adi/Kconfig new file mode 100644 index 00..5745bedf88 --- /dev/null +++ b/drivers/clk/adi/Kconfig @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2022 - Analog Devices, Inc. +# +# Written and/or maintained by Timesys Corporation +# +# Contact: Nathan Barrett-Morrison +# Contact: Greg Malysa +# + +config COMMON_CLK_ADI_SHARED + bool "Enable shared ADI clock framework code" + help + Required for shared code between SoC clock drivers. Automatically + selected by an appropriate SoC-specific clock driver version. + +config COMMON_CLK_ADI_SC598 + bool "Clock driver for ADI SC598 SoCs" + select DM + select CLK + select CLK_CCF + select OF_CONTROL + select CMD_CLK + select SPL_DM if SPL + select SPL_CLK if SPL + select SPL_CLK_CCF if SPL + select SPL_OF_CONTROL if SPL + select COMMON_CLK_ADI_SHARED + depends on SC59X_64 + help + This driver supports the system clocks on Analog Devices SC598-series + SoCs. It includes CGU and CDU clocks and supports gating unused clocks. + Modifying PLL configuration is not supported; that must be done prior + to booting the kernel. Clock dividers after the PLLs may be configured. + +config COMMON_CLK_ADI_SC594 + bool "Clock driver for ADI SC594 SoCs" + select DM + select CLK + select CLK_CCF + select OF_CONTROL + select CMD_CLK + select SPL_DM if SPL + select SPL_CLK if SPL + select SPL_CLK_CCF if SPL + select SPL_OF_CONTROL if SPL + select COMMON_CLK_ADI_SHARED + depends on SC59X + help + This driver supports the system clocks on Analog Devices SC594-series + SoCs. It includes CGU and CDU clocks and supports gating
[PATCH 3/3] drivers: serial: Add in UART for ADI SC5XX-family processors
From: Nathan Barrett-Morrison
Co-developed-by: Greg Malysa
Signed-off-by: Greg Malysa
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Artamonovs
Signed-off-by: Nathan Barrett-Morrison
---
MAINTAINERS | 1 +
drivers/serial/Makefile | 1 +
drivers/serial/serial_adi_uart4.c | 228 ++
3 files changed, 230 insertions(+)
create mode 100644 drivers/serial/serial_adi_uart4.c
diff --git a/MAINTAINERS b/MAINTAINERS
index a9f52a6c7e..b1f206bb05 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -610,6 +610,7 @@ T: git https://github.com/analogdevicesinc/lnxdsp-u-boot
F: arch/arm/include/asm/arch-adi/
F: arch/arm/mach-sc5xx/
F: drivers/clk/adi/
+F: drivers/serial/serial_adi_uart4.c
F: include/configs/sc_adi_common.h
ARM SNAPDRAGON
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 403ab1ded6..dbe598b740 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -65,3 +65,4 @@ obj-$(CONFIG_S5P4418_PL011_SERIAL) += serial_s5p4418_pl011.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
endif
+obj-$(CONFIG_UART4_SERIAL) += serial_adi_uart4.o
diff --git a/drivers/serial/serial_adi_uart4.c
b/drivers/serial/serial_adi_uart4.c
new file mode 100644
index 00..b92ce3ddd1
--- /dev/null
+++ b/drivers/serial/serial_adi_uart4.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Converted to driver model by Nathan Barrett-Morrison
+ *
+ * Contact: Nathan Barrett-Morrison
+ * Contact: Greg Malysa
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * UART4 Masks
+ */
+
+/* UART_CONTROL */
+#define UENBIT(0)
+#define LOOP_ENA BIT(1)
+#define UMOD (3 << 4)
+#define UMOD_UART (0 << 4)
+#define UMOD_MDB BIT(4)
+#define UMOD_IRDA BIT(4)
+#define WLS(3 << 8)
+#define WLS_5 (0 << 8)
+#define WLS_6 BIT(8)
+#define WLS_7 (2 << 8)
+#define WLS_8 (3 << 8)
+#define STBBIT(12)
+#define STBH BIT(13)
+#define PENBIT(14)
+#define EPSBIT(15)
+#define STPBIT(16)
+#define FPEBIT(17)
+#define FFEBIT(18)
+#define SB BIT(19)
+#define FCPOL BIT(22)
+#define RPOLC BIT(23)
+#define TPOLC BIT(24)
+#define MRTS BIT(25)
+#define XOFF BIT(26)
+#define ARTS BIT(27)
+#define ACTS BIT(28)
+#define RFIT BIT(29)
+#define RFRT BIT(30)
+
+/* UART_STATUS */
+#define DR BIT(0)
+#define OE BIT(1)
+#define PE BIT(2)
+#define FE BIT(3)
+#define BI BIT(4)
+#define THRE BIT(5)
+#define TEMT BIT(7)
+#define TFIBIT(8)
+#define ASTKY BIT(9)
+#define ADDR BIT(10)
+#define RO BIT(11)
+#define SCTS BIT(12)
+#define CTSBIT(16)
+#define RFCS BIT(17)
+
+/* UART_EMASK */
+#define ERBFI BIT(0)
+#define ETBEI BIT(1)
+#define ELSI BIT(2)
+#define EDSSI BIT(3)
+#define EDTPTI BIT(4)
+#define ETFI BIT(5)
+#define ERFCI BIT(6)
+#define EAWI BIT(7)
+#define ERXS BIT(8)
+#define ETXS BIT(9)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct uart4_reg {
+ u32 revid;
+ u32 control;
+ u32 status;
+ u32 scr;
+ u32 clock;
+ u32 emask;
+ u32 emaskst;
+ u32 emaskcl;
+ u32 rbr;
+ u32 thr;
+ u32 taip;
+ u32 tsr;
+ u32 rsr;
+ u32 txdiv_cnt;
+ u32 rxdiv_cnt;
+};
+
+struct adi_uart4_platdata {
+ // Hardware registers
+ struct uart4_reg *regs;
+
+ // Enable divide-by-one baud rate setting
+ bool edbo;
+};
+
+static int adi_uart4_set_brg(struct udevice *dev, int baudrate)
+{
+ struct adi_uart4_platdata *plat = dev_get_plat(dev);
+ struct uart4_reg *regs = plat->regs;
+ u32 divisor, uart_base_clk_rate;
+ struct clk uart_base_clk;
+
+ if (clk_get_by_index(dev, 0, _base_clk)) {
+ printf("%s: Could not get UART base clock\n", dev->name);
+ return -1;
+
[PATCH 00/11] cadence-qspi: Add DTR support including PHY mode calibration
This series introduces support for DTR mode for the Cadence QSPI/OSPI IP. We have been developing it against the SC594/SC598 from ADI, so there are some limitations specific to our hardware's capabilities. Ideally this series could be enhanced with features introduced in a patch series submitted by AMD, but currently no work has been done to reconcile the two. So this is somewhere between an RFC patch and a patch series we wish to submit as-is for inclusion. Beyond the specific support for the QSPI peripheral, this series also introduces a more general calibration framework as part of the spi system in order to facilitate integration of calibration support for other controllers within a consistent approach. Ian Roberts (11): mtd: spi-nor: Add calibration hook for high speed SPI mtd: spi-nor: Octal DTR support for IS25*x spi: cadence-quadspi: Enable DDR bit for DTR commands spi: cadence-quadspi: enable opcode extension based on command length spi: cadence-quadspi: disable automatic write enable spi: cadence-quadspi: unconditionally disable auto status register reads spi: cadence-quadspi: Remove redundant DTR state spi: cadence-quadspi: Direct mode does not support zero length addresses spi: cadence-quadspi: Add support for memory DMA channel transfers spi: cadence-quadspi: Add DT control of max Read Delay Capture value spi: cadence-quadspi: Implement high speed calibration doc/device-tree-bindings/spi/spi-bus.txt | 4 + doc/device-tree-bindings/spi/spi-cadence.txt | 11 + drivers/mtd/spi/Kconfig | 12 + drivers/mtd/spi/spi-nor-core.c | 246 drivers/mtd/spi/spi-nor-ids.c| 6 +- drivers/spi/cadence_qspi.c | 444 ++ drivers/spi/cadence_qspi.h | 105 +++- drivers/spi/cadence_qspi_apb.c | 572 +++ drivers/spi/spi-mem.c| 24 + include/linux/mtd/spi-nor.h | 13 + include/spi-mem.h| 19 + 11 files changed, 1226 insertions(+), 230 deletions(-) -- 2.43.2
[PATCH 11/11] spi: cadence-quadspi: Implement high speed calibration
From: Ian Roberts
Implement the spi-mem calibration hook for high speed flash operation for
use on the SC59x SOCs. The Cadence controller IP has support for the DQS
signal and a PHY mode that facilitates speeds greater than 50MHz.
At high speeds, the IO lines must be calibrated for signal propagation
delay. This calibration is intended to be executed in the final IO
configuration mode. That is, if 8-lane DDR IO operation is the use case,
calibration must occur while that mode is enabled. For example, there
might be excess noise on a single IO lane while operating in 8-lane mode
that then limits the speed of the entire bus. SPI bus drivers are not
involved in the control of the SPI flash chip operating mode, and
performing the switch is done by the SPI-nor subsystem. To add to this
complexity, different IO modes use different command sets, and different
flash chips may also modify this command set further. Thus, we must lean
on the spi-nor subsystem through the spi-mem calibration function for the
most portable implementation of calibration.
The original calibration code in this driver only calibrates the Read
Delay Capture value, over a single lane, over only 3 bytes in the readid
command. This produces unreliable calibrations in single IO mode and is
unusable in DDR or multi-IO modes.
The prior calibration implementation is replaced in favor of the new
approach when CONFIG_SPI_FLASH_HS_CALIB is defined. The old
implementation is still available when not defined. However, the previous
implementation has been tweaked to take advantage of code reuse and to
fix an invalid SPI chip select read from the dm_spi_ops set_speed
callback. It would always return the same invalid CS number, never
triggering a recalibration if the chip changes. However, this driver was
not implemented with support for multiple chips on the bus in mind
anyway. For example:
* of_to_plat only scans the first subnode for flash-specific
configuration, and thus only a single copy of this info is declared in
the plat and priv structs.
* Defining cdns,read-delay overrides any automatic recalibration that
would normally occur from a chip select change to this single value.
A few additional comments, checks, and renames have been made to make
this more clear. The new calibration implementation explicitly disallows
changing the chip after calibration until it is properly implemented in
the driver. The legacy implementation will still allow the chip to change
but now correctly trigger a recalibration after the chip select changes.
The issue with cdns,read-delay and multi-IO modes is only fixed in the
new implementation.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
---
doc/device-tree-bindings/spi/spi-cadence.txt | 9 +
drivers/spi/cadence_qspi.c | 392 +--
drivers/spi/cadence_qspi.h | 77 ++--
drivers/spi/cadence_qspi_apb.c | 327 ++--
4 files changed, 641 insertions(+), 164 deletions(-)
diff --git a/doc/device-tree-bindings/spi/spi-cadence.txt
b/doc/device-tree-bindings/spi/spi-cadence.txt
index 9bd7ef8bed..4ee0b628e3 100644
--- a/doc/device-tree-bindings/spi/spi-cadence.txt
+++ b/doc/device-tree-bindings/spi/spi-cadence.txt
@@ -31,3 +31,12 @@ connected flash properties
n_ss_out low and first bit transfer
- cdns,max-read-delay : Max safe value to use for the read capture delay
during auto calibration.
+- cdns,spi-calib-frequency : Max safe SPI clock frequency to use before bus
+calibration is performed.
+- cdns,dqs : Enable use of the DQS signal with the flash chip.
+- cdns,phy : Enable use of the high-speed PHY feature with the
+ flash chip. Generally required for speeds higher
+ than 50MHz.
+- cdns,read-delay : Optional pre-calibrated Read Delay Capture value.
+- cdns,phyrxdly: Optional pre-calibrated PHY RX Delay value.
+- cdns,phytxdly: Optional pre-calibrated PHY TX Delay value.
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 3778a469d4..1db3167a5b 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -30,6 +31,20 @@
#define CQSPI_READ 2
#define CQSPI_WRITE3
+static bool is_calibrated(struct cadence_spi_priv *priv,
+ struct spi_slave *slave)
+{
+ return (priv->qspi_calibrated_hz == priv->req_hz) &&
+ (priv->qspi_calibrated_cs == spi_chip_select(slave->dev));
+}
+
+static void set_calibrated(struct cadence_spi_priv *priv,
+ struct spi_slave *slave)
+{
+ priv->qspi_calibrated_hz = pri
[PATCH 07/11] spi: cadence-quadspi: Remove redundant DTR state
From: Ian Roberts
cadence_spi_mem_supports_op() already checks that every memory operation
either has all DTR booleans set or cleared. Thus, there is no need to
store a cached dtr value. The command DTR state can be used since it is
not optional like the other fields.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
---
drivers/spi/cadence_qspi.c | 6 ++
drivers/spi/cadence_qspi.h | 1 -
drivers/spi/cadence_qspi_apb.c | 27 ---
3 files changed, 14 insertions(+), 20 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index f4593c47b8..a2644d9e11 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -362,6 +362,12 @@ static bool cadence_spi_mem_supports_op(struct spi_slave
*slave,
bool all_true, all_false;
/*
+* For an op to be DTR, cmd phase along with every other non-empty
+* phase should have dtr field set to 1. If an op phase has zero
+* nbytes, ignore its dtr field; otherwise, check its dtr field.
+* Also, dummy checks not performed here Since supports_op()
+* already checks that all or none of the fields are DTR.
+*
* op->dummy.dtr is required for converting nbytes into ncycles.
* Also, don't check the dtr field of the op phase having zero nbytes.
*/
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 355919cb23..5704f5a3f6 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -265,7 +265,6 @@ struct cadence_spi_priv {
u8 inst_width;
u8 addr_width;
u8 data_width;
- booldtr;
};
/* Functions call declaration */
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index d347cb8d47..2600370f85 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -120,17 +120,6 @@ static int cadence_qspi_set_protocol(struct
cadence_spi_priv *priv,
{
int ret;
- /*
-* For an op to be DTR, cmd phase along with every other non-empty
-* phase should have dtr field set to 1. If an op phase has zero
-* nbytes, ignore its dtr field; otherwise, check its dtr field.
-* Also, dummy checks not performed here Since supports_op()
-* already checks that all or none of the fields are DTR.
-*/
- priv->dtr = op->cmd.dtr &&
- (!op->addr.nbytes || op->addr.dtr) &&
- (!op->data.nbytes || op->data.dtr);
-
ret = cadence_qspi_buswidth_to_inst_type(op->cmd.buswidth);
if (ret < 0)
return ret;
@@ -449,7 +438,7 @@ int cadence_qspi_apb_command_read_setup(struct
cadence_spi_priv *priv,
return ret;
ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_STIG_LSB,
- priv->dtr);
+ op->cmd.dtr);
if (ret)
return ret;
@@ -484,13 +473,13 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv
*priv,
return log_msg_ret("QSPI: Invalid command length", -EINVAL);
}
- if (opcode == CMD_4BYTE_OCTAL_READ && !priv->dtr)
+ if (opcode == CMD_4BYTE_OCTAL_READ && !op->cmd.dtr)
opcode = CMD_4BYTE_FAST_READ;
reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
/* Set up dummy cycles. */
- dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr);
+ dummy_clk = cadence_qspi_calc_dummy(op, op->cmd.dtr);
if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
return -ENOTSUPP;
@@ -547,7 +536,7 @@ int cadence_qspi_apb_command_write_setup(struct
cadence_spi_priv *priv,
return ret;
ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_STIG_LSB,
- priv->dtr);
+ op->cmd.dtr);
if (ret)
return ret;
@@ -597,7 +586,7 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv
*priv,
}
/* Set up dummy cycles. */
- dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr);
+ dummy_clk = cadence_qspi_calc_dummy(op, op->cmd.dtr);
if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
return -EOPNOTSUPP;
@@ -645,7 +634,7 @@ int cadence_qspi_apb_read_setup(struct cadence_spi_priv
*priv,
return ret;
ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_READ_LSB,
- priv->dtr);
+ op->cmd.dtr);
if (ret)
return ret;
@@ -673,7 +662,7 @@ int cadence_qspi_apb_read_setup(struct cadence_s
[PATCH 10/11] spi: cadence-quadspi: Add DT control of max Read Delay Capture value
From: Ian Roberts
On some SOCs (eg sc59x), attempting to use too high of a Read
Delay Capture value can cause the controller DMA to lock up. Thus,
add a device tree configuration property to allow controlling
the max Read Delay Capture value.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
---
doc/device-tree-bindings/spi/spi-cadence.txt | 2 ++
drivers/spi/cadence_qspi.c | 9 -
drivers/spi/cadence_qspi.h | 2 ++
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/doc/device-tree-bindings/spi/spi-cadence.txt
b/doc/device-tree-bindings/spi/spi-cadence.txt
index 69e02c1c4b..9bd7ef8bed 100644
--- a/doc/device-tree-bindings/spi/spi-cadence.txt
+++ b/doc/device-tree-bindings/spi/spi-cadence.txt
@@ -29,3 +29,5 @@ connected flash properties
select (n_ss_out).
- cdns,tslch-ns: Delay in master reference clocks between
setting
n_ss_out low and first bit transfer
+- cdns,max-read-delay : Max safe value to use for the read capture delay
+ during auto calibration.
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index a5e921cae7..3778a469d4 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -104,7 +104,7 @@ static int spi_calibration(struct udevice *bus, uint hz)
/* use back the intended clock and find low range */
cadence_spi_write_speed(bus, hz);
- for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
+ for (i = 0; i < priv->max_read_delay; i++) {
/* Disable QSPI */
cadence_qspi_apb_controller_disable(base);
@@ -246,6 +246,7 @@ static int cadence_spi_probe(struct udevice *bus)
priv->fifo_depth= plat->fifo_depth;
priv->fifo_width= plat->fifo_width;
priv->trigger_address = plat->trigger_address;
+ priv->max_read_delay= plat->max_read_delay;
priv->read_delay= plat->read_delay;
priv->ahbsize = plat->ahbsize;
priv->max_hz= plat->max_hz;
@@ -456,6 +457,10 @@ static int cadence_spi_of_to_plat(struct udevice *bus)
plat->is_dma = dev_read_bool(bus, "cdns,is-dma");
+ plat->max_read_delay = dev_read_u32_default(bus,
+ "cdns,max-read-delay",
+
CQSPI_READ_CAPTURE_MAX_DELAY);
+
/* All other parameters are embedded in the child node */
subnode = cadence_qspi_get_subnode(bus);
if (!ofnode_valid(subnode)) {
@@ -484,6 +489,8 @@ static int cadence_spi_of_to_plat(struct udevice *bus)
*/
plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay",
-1);
+ if (plat->read_delay > plat->max_read_delay)
+ plat->read_delay = plat->max_read_delay;
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
__func__, plat->regbase, plat->ahbbase, plat->max_hz,
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 9c15d3c6df..d7a02f0870 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -214,6 +214,7 @@ struct cadence_spi_plat {
fdt_addr_t ahbsize;
booluse_dac_mode;
int read_delay;
+ int max_read_delay;
/* Flash parameters */
u32 page_size;
@@ -260,6 +261,7 @@ struct cadence_spi_priv {
unsigned intprevious_hz;
u32 wr_delay;
int read_delay;
+ int max_read_delay;
struct reset_ctl_bulk *resets;
u32 page_size;
--
2.43.2
[PATCH 09/11] spi: cadence-quadspi: Add support for memory DMA channel transfers
From: Ian Roberts
On the SC59x platform, the Cadence SPI IP block can use memory DMA
channels to execute transactions. Existing Cadence DMA support attempts
appears to be SOC specific and not generic. Thus, framework to use the
DMA subsystem was added. On the SC59x, DMA to the Cadence SPI block is
connected via memory DMA instead of peripheral DMA. In addition, some
of the memory DMA channels are recommended over others for better
transaction performance. This initial implementation simply uses the
recommended memory channel indicated from the device tree. Peripheral
DMA support can be added later for platforms that need it.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
---
drivers/spi/cadence_qspi.c | 47
drivers/spi/cadence_qspi.h | 31 +--
drivers/spi/cadence_qspi_apb.c | 99 ++
3 files changed, 164 insertions(+), 13 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index a2644d9e11..a5e921cae7 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -7,6 +7,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -194,6 +196,42 @@ static int cadence_spi_set_speed(struct udevice *bus, uint
hz)
return 0;
}
+#if CONFIG_IS_ENABLED(DMA_CHANNELS)
+static int cadence_spi_probe_dma(struct udevice *bus)
+{
+ struct cadence_spi_priv *priv = dev_get_priv(bus);
+ struct dma_dev_priv *dma_uc;
+ int hasdma;
+ int ret;
+
+ hasdma = (ofnode_read_u32(dev_ofnode(bus), "dmas", NULL) == 0) &&
+(ofnode_read_u32(dev_ofnode(bus), "dma-names", NULL) == 0);
+ if (!hasdma)
+ return 0;
+
+ ret = dma_get_by_name(bus, "dst", >dstdma);
+ if (ret != 0)
+ return 0;
+
+ dma_uc = dev_get_uclass_priv(priv->dstdma.dev);
+
+ if (dma_uc->supported == DMA_SUPPORTS_MEM_TO_MEM) {
+ /* We were given a specific DMA channel that only
+* supports mem-to-mem transactions.
+*/
+ priv->hasdma = hasdma;
+ priv->ops.direct_read_copy = cadence_qspi_apb_read_copy_mdma;
+ priv->ops.direct_write_copy = cadence_qspi_apb_write_copy_mdma;
+ return 0;
+ }
+
+ /* Todo: Implement device DMA channel modes when needed
+* (DMA_SUPPORTS_MEM_TO_DEV, DMA_SUPPORTS_DEV_TO_MEM).
+*/
+ return -ENOSYS;
+}
+#endif
+
static int cadence_spi_probe(struct udevice *bus)
{
struct cadence_spi_plat *plat = dev_get_plat(bus);
@@ -219,6 +257,9 @@ static int cadence_spi_probe(struct udevice *bus)
priv->tchsh_ns = plat->tchsh_ns;
priv->tslch_ns = plat->tslch_ns;
+ priv->ops.direct_read_copy = cadence_qspi_apb_direct_read_copy;
+ priv->ops.direct_write_copy = cadence_qspi_apb_direct_write_copy;
+
if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI,
ZYNQMP_PM_CAPABILITY_ACCESS,
ZYNQMP_PM_MAX_QOS,
@@ -252,6 +293,12 @@ static int cadence_spi_probe(struct udevice *bus)
priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
+ if (CONFIG_IS_ENABLED(DMA_CHANNELS)) {
+ ret = cadence_spi_probe_dma(bus);
+ if (ret)
+ return ret;
+ }
+
/* Versal and Versal-NET use spi calibration to set read delay */
if (CONFIG_IS_ENABLED(ARCH_VERSAL) ||
CONFIG_IS_ENABLED(ARCH_VERSAL_NET))
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 5704f5a3f6..9c15d3c6df 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -223,7 +223,16 @@ struct cadence_spi_plat {
u32 tchsh_ns;
u32 tslch_ns;
- boolis_dma;
+ boolis_dma;
+};
+
+struct cadence_spi_priv;
+
+struct cadence_drv_ops {
+ int (*direct_read_copy)(struct cadence_spi_priv *priv,
+ void *dst, u64 src, size_t len);
+ int (*direct_write_copy)(struct cadence_spi_priv *priv,
+const void *src, u64 dst, size_t len);
};
struct cadence_spi_priv {
@@ -234,11 +243,17 @@ struct cadence_spi_priv {
unsigned intfifo_depth;
unsigned intfifo_width;
unsigned inttrigger_address;
- fdt_addr_t ahbsize;
+ fdt_addr_t ahbsize;
size_t cmd_len;
u8 cmd_buf[32];
size_t data_len;
+ boolhasdma;
+#if CONFIG_IS_ENABLED(DMA_CHANNELS)
+ struct dma dstdma;
+#endif
+ struct cadence_drv_ops ops;
+
int
[PATCH 08/11] spi: cadence-quadspi: Direct mode does not support zero length addresses
From: Ian Roberts
It is not possible to configure the Cadence SPI IP block to use a zero
length address in DMA read or write commands.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
---
drivers/spi/cadence_qspi_apb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 2600370f85..340889c271 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -784,7 +784,7 @@ int cadence_qspi_apb_read_execute(struct cadence_spi_priv
*priv,
cadence_qspi_apb_enable_linear_mode(true);
- if (priv->use_dac_mode && (from + len < priv->ahbsize)) {
+ if (op->addr.nbytes && priv->use_dac_mode && (from + len <
priv->ahbsize)) {
if (len < 256 ||
dma_memcpy(buf, priv->ahbbase + from, len) < 0) {
memcpy_fromio(buf, priv->ahbbase + from, len);
@@ -970,7 +970,7 @@ int cadence_qspi_apb_write_execute(struct cadence_spi_priv
*priv,
size_t len = op->data.nbytes;
cadence_qspi_apb_enable_linear_mode(true);
- if (priv->use_dac_mode && (to + len < priv->ahbsize)) {
+ if (op->addr.nbytes && priv->use_dac_mode && (to + len <
priv->ahbsize)) {
memcpy_toio(priv->ahbbase + to, buf, len);
if (!cadence_qspi_wait_idle(priv->regbase))
return -EIO;
--
2.43.2
[PATCH 06/11] spi: cadence-quadspi: unconditionally disable auto status register reads
From: Ian Roberts
In addition to the given reason for the conditional disable
of this feature for DTR:
Theoretically, some flashes have their WIP bit in different
bit positions or have a different bit polarity. spi-nor
currently does not have an interface in place to dictate
this information to this driver for proper configuration.
The default of the controller hardware has this status register
auto polling without expiration. This means that if there is any
controller misconfiguration or communication failure, it will
completely lock up the controller.
Thus, unconditionally disable this feature for now.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
---
drivers/spi/cadence_qspi_apb.c | 46 ++
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 176cff5338..d347cb8d47 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -853,19 +853,29 @@ int cadence_qspi_apb_write_setup(struct cadence_spi_priv
*priv,
writel(op->addr.val, priv->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
- if (priv->dtr) {
- /*
-* Some flashes like the cypress Semper flash expect a 4-byte
-* dummy address with the Read SR command in DTR mode, but this
-* controller does not support sending address with the Read SR
-* command. So, disable write completion polling on the
-* controller's side. spi-nor will take care of polling the
-* status register.
-*/
- reg = readl(priv->regbase + CQSPI_REG_WR_COMPLETION_CTRL);
- reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
- writel(reg, priv->regbase + CQSPI_REG_WR_COMPLETION_CTRL);
- }
+ /*
+* Some flashes like the cypress Semper flash expect a 4-byte
+* dummy address with the Read SR command in DTR mode, but this
+* controller does not support sending address with the Read SR
+* command. So, disable write completion polling on the
+* controller's side. spi-nor will take care of polling the
+* status register.
+*
+* Theoretically, some flashes have their WIP bit in different
+* bit positions or have a different bit polarity. spi-nor
+* currently does not have an interface in place to dictate
+* this information to this driver for proper configuration.
+*
+* The default of the controller hardware has this status register
+* auto polling without expiration. This means that if there is any
+* controller misconfiguration or communication failure, it will
+* completely lock up the controller.
+*
+* Thus, unconditionally disable this feature for now.
+*/
+ reg = readl(priv->regbase + CQSPI_REG_WR_COMPLETION_CTRL);
+ reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
+ writel(reg, priv->regbase + CQSPI_REG_WR_COMPLETION_CTRL);
reg = readl(priv->regbase + CQSPI_REG_SIZE);
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
@@ -970,16 +980,8 @@ int cadence_qspi_apb_write_execute(struct cadence_spi_priv
*priv,
const void *buf = op->data.buf.out;
size_t len = op->data.nbytes;
- /*
-* Some flashes like the Cypress Semper flash expect a dummy 4-byte
-* address (all 0s) with the read status register command in DTR mode.
-* But this controller does not support sending dummy address bytes to
-* the flash when it is polling the write completion register in DTR
-* mode. So, we can not use direct mode when in DTR mode for writing
-* data.
-*/
cadence_qspi_apb_enable_linear_mode(true);
- if (!priv->dtr && priv->use_dac_mode && (to + len < priv->ahbsize)) {
+ if (priv->use_dac_mode && (to + len < priv->ahbsize)) {
memcpy_toio(priv->ahbbase + to, buf, len);
if (!cadence_qspi_wait_idle(priv->regbase))
return -EIO;
--
2.43.2
[PATCH 01/11] mtd: spi-nor: Add calibration hook for high speed SPI
From: Ian Roberts High speed SPI flash chip operation, such as speeds greater than 50MHz, require a calibration of the data lines to determine the correct signal propagation delay. This calibration delay will vary based on flash chip, operating frequency, board trace length, and board temperature to a smaller extent. To my knowledge, JEDEC doesn't have a well defined standard for how calibration should be implemented by flash chip manufacturers. The few flash chip datasheets I have viewed from chips that do support such high speed operation implement very different methods for assisting in calibration, such as: * No provision for calibration. * Independent "data learning" commands. * Scratch data registers. * Predefined bit patterns inserted before read data contents (preamble). Thus, the simplest and most portable solution to calibrate appears to be to simply read and compare a known data pattern from the flash array. During SPI flash probe, calibration is initialized after the SFDP read, but before read command selection. At this stage, higher speeds, more advanced read commands, and additional IO lanes, and dual data rate options have not yet been enabled. Communication is most reliable at this stage to read out a pattern to then check against later. The most basic and widely supported read commands are then used to read out the data pattern. The default is to read 2 flash pages worth of data at the first address in flash. Commonly, this is where a bootloader might be located on the chip. While a bootloader is not an ideal pattern, two pages worth of data hopefully contains enough entropy to calibrate successfully. This can be further customized with two new flash chip device tree parameters: * 'calibration-offset' The flash chip address offset where the pattern data is located. * 'calibration-length' The length of pattern data. The calibration step is then called at the end of the chip probe, right after all advanced IO modes have been enabled, such as multiple IO lanes and SDR/DDR modes. Another solution to the high speed calibration issue is to perform the calibration offline and then to simply apply the calibration at boot. This skips a potentially lengthy calibration process. However, this change set also serves as an ideal hook for controller drivers to also simply apply any pre-calibrated values. Early commands in the probe process, such as RDID, RDSFDP, and RDAY may have slower operating frequencies. As, for example, the JEDEC spec only requires that RDSFDP and RDAY to support at least up to 50MHz frequency. Thus it is ideal to probe the chip at lower frequencies with more reliable IO modes, such as a low frequency with one lane at a single data rate. This patch implements: * SPI-mem API function for drivers to implement to perform calibration. * Read pattern data through reliable methods. * Call SPI-mem API calibration function with a read check function that uses probed read commands and all enabled fast IO modes. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- --- doc/device-tree-bindings/spi/spi-bus.txt | 4 + drivers/mtd/spi/Kconfig | 12 ++ drivers/mtd/spi/spi-nor-core.c | 168 +++ drivers/spi/spi-mem.c| 24 include/linux/mtd/spi-nor.h | 7 + include/spi-mem.h| 19 +++ 6 files changed, 234 insertions(+) diff --git a/doc/device-tree-bindings/spi/spi-bus.txt b/doc/device-tree-bindings/spi/spi-bus.txt index e57897ac0c..654d388cac 100644 --- a/doc/device-tree-bindings/spi/spi-bus.txt +++ b/doc/device-tree-bindings/spi/spi-bus.txt @@ -61,6 +61,10 @@ contain the following properties. used for MISO. Defaults to 1 if not present. - spi-half-duplex - (optional) Indicates that the SPI bus should wait for a header byte before reading data from the slave. +- calibration-offset - (optional) Check pattern offset location for high- + speed calibration. +- calibration-length - (optional) Check pattern length for high-speed + calibration. Some SPI controllers and devices support Dual and Quad SPI transfer mode. It allows data in SPI system transferred in 2 wires(DUAL) or 4 wires(QUAD). diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index d068b7860e..ed0335d9ba 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -127,6 +127,18 @@ config SPI_FLASH_SOFT_RESET_ON_BOOT that are not supposed to be handed to U-Boot in Octal DTR mode, even if they _do_ support the Soft Reset sequence. +config SPI_FLASH_HS_CALIB + bool "Support for high-speed SPI flash calibration" + default n + help +Modern flash chips and controllers that operate at speeds higher than +50MHz require delays
[PATCH 04/11] spi: cadence-quadspi: enable opcode extension based on command length
From: Ian Roberts
Some flash chips use dual opcodes in other modes. For example, the
Macronix MX66 requires dual opcodes for STR octal operation. Thus,
enable opcode extension based on the length of the command instead
of the DTR mode of the controller.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
---
drivers/spi/cadence_qspi_apb.c | 66 +-
1 file changed, 49 insertions(+), 17 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 34cacf1880..eb9f4ed63d 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -412,19 +412,27 @@ static int cadence_qspi_enable_dtr(struct
cadence_spi_priv *priv,
reg = readl(priv->regbase + CQSPI_REG_CONFIG);
- if (enable) {
- reg |= CQSPI_REG_CONFIG_DTR_PROTO;
+ switch (op->cmd.nbytes) {
+ case 1:
+ reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
+ break;
+ case 2:
reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
/* Set up command opcode extension. */
ret = cadence_qspi_setup_opcode_ext(priv, op, shift);
if (ret)
return ret;
- } else {
- reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
- reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
+ break;
+ default:
+ return log_msg_ret("QSPI: Invalid command length", -EINVAL);
}
+ if (enable)
+ reg |= CQSPI_REG_CONFIG_DTR_PROTO;
+ else
+ reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
+
writel(reg, priv->regbase + CQSPI_REG_CONFIG);
return 0;
@@ -465,10 +473,16 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv
*priv,
unsigned int dummy_clk;
u8 opcode;
- if (priv->dtr)
- opcode = op->cmd.opcode >> 8;
- else
+ switch (op->cmd.nbytes) {
+ case 1:
opcode = op->cmd.opcode;
+ break;
+ case 2:
+ opcode = op->cmd.opcode >> 8;
+ break;
+ default:
+ return log_msg_ret("QSPI: Invalid command length", -EINVAL);
+ }
if (opcode == CMD_4BYTE_OCTAL_READ && !priv->dtr)
opcode = CMD_4BYTE_FAST_READ;
@@ -557,10 +571,16 @@ int cadence_qspi_apb_command_write(struct
cadence_spi_priv *priv,
void *reg_base = priv->regbase;
u8 opcode;
- if (priv->dtr)
- opcode = op->cmd.opcode >> 8;
- else
+ switch (op->cmd.nbytes) {
+ case 1:
opcode = op->cmd.opcode;
+ break;
+ case 2:
+ opcode = op->cmd.opcode >> 8;
+ break;
+ default:
+ return log_msg_ret("QSPI: Invalid command length", -EINVAL);
+ }
reg |= opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
@@ -634,10 +654,16 @@ int cadence_qspi_apb_read_setup(struct cadence_spi_priv
*priv,
priv->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
- if (priv->dtr)
- opcode = op->cmd.opcode >> 8;
- else
+ switch (op->cmd.nbytes) {
+ case 1:
opcode = op->cmd.opcode;
+ break;
+ case 2:
+ opcode = op->cmd.opcode >> 8;
+ break;
+ default:
+ return log_msg_ret("QSPI: Invalid command length", -EINVAL);
+ }
rd_reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
rd_reg |= op->cmd.dtr ? CQSPI_REG_RD_INSTR_DDR_EN_MASK : 0;
@@ -804,10 +830,16 @@ int cadence_qspi_apb_write_setup(struct cadence_spi_priv
*priv,
priv->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
- if (priv->dtr)
- opcode = op->cmd.opcode >> 8;
- else
+ switch (op->cmd.nbytes) {
+ case 1:
opcode = op->cmd.opcode;
+ break;
+ case 2:
+ opcode = op->cmd.opcode >> 8;
+ break;
+ default:
+ return log_msg_ret("QSPI: Invalid command length", -EINVAL);
+ }
reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
reg |= priv->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
--
2.43.2
[PATCH 05/11] spi: cadence-quadspi: disable automatic write enable
From: Ian Roberts The spi-nor subsystem issues the write enable command manually. So this automatic feature sends duplicate commands and also introduces the possibility of erroneous writes. Disable the automatic write enable feature by default. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 72e92cc997..355919cb23 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -73,6 +73,7 @@ #define CQSPI_REG_WR_INSTR 0x08 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_WR_INSTR_WELDIS_MASK BIT(8) #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index eb9f4ed63d..176cff5338 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -842,6 +842,7 @@ int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv, } reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; + reg |= CQSPI_REG_WR_INSTR_WELDIS_MASK; reg |= priv->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; reg |= priv->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; writel(reg, priv->regbase + CQSPI_REG_WR_INSTR); -- 2.43.2
[PATCH 03/11] spi: cadence-quadspi: Enable DDR bit for DTR commands
From: Ian Roberts The Cadence octal SPI IP read instruction register requires a bit to be set to indicate if the read opcode is a compliant DDR read command. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 4 2 files changed, 5 insertions(+) diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 693474a287..72e92cc997 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -61,6 +61,7 @@ #define CQSPI_REG_RD_INSTR 0x04 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 +#define CQSPI_REG_RD_INSTR_DDR_EN_MASK BIT(10) #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB12 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB16 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index fb90532217..34cacf1880 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -446,6 +446,7 @@ int cadence_qspi_apb_command_read_setup(struct cadence_spi_priv *priv, return ret; reg = cadence_qspi_calc_rdreg(priv); + reg |= op->cmd.dtr ? CQSPI_REG_RD_INSTR_DDR_EN_MASK : 0; writel(reg, priv->regbase + CQSPI_REG_RD_INSTR); return 0; @@ -537,6 +538,7 @@ int cadence_qspi_apb_command_write_setup(struct cadence_spi_priv *priv, return ret; reg = cadence_qspi_calc_rdreg(priv); + reg |= op->cmd.dtr ? CQSPI_REG_RD_INSTR_DDR_EN_MASK : 0; writel(reg, priv->regbase + CQSPI_REG_RD_INSTR); return 0; @@ -638,6 +640,7 @@ int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv, opcode = op->cmd.opcode; rd_reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; + rd_reg |= op->cmd.dtr ? CQSPI_REG_RD_INSTR_DDR_EN_MASK : 0; rd_reg |= cadence_qspi_calc_rdreg(priv); writel(op->addr.val, priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); @@ -812,6 +815,7 @@ int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv, writel(reg, priv->regbase + CQSPI_REG_WR_INSTR); reg = cadence_qspi_calc_rdreg(priv); + reg |= op->cmd.dtr ? CQSPI_REG_RD_INSTR_DDR_EN_MASK : 0; writel(reg, priv->regbase + CQSPI_REG_RD_INSTR); writel(op->addr.val, priv->regbase + CQSPI_REG_INDIRECTWRSTARTADDR); -- 2.43.2
[PATCH 02/11] mtd: spi-nor: Octal DTR support for IS25*x
From: Ian Roberts
ISSI IS25*x series SPIflash chips are capable of Octal IO and DDR.
Add spi-nor support to enable and operate in these modes.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
---
drivers/mtd/spi/spi-nor-core.c | 78 ++
drivers/mtd/spi/spi-nor-ids.c | 6 ++-
include/linux/mtd/spi-nor.h| 6 +++
3 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index f164c3cf73..ce86e53860 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3968,6 +3968,76 @@ static struct spi_nor_fixups macronix_octal_fixups = {
};
#endif /* CONFIG_SPI_FLASH_MACRONIX */
+#ifdef CONFIG_SPI_FLASH_ISSI
+/**
+ * spi_nor_issi_octal_dtr_enable() - Enable octal DTR on ISSI flashes.
+ * @nor: pointer to a 'struct spi_nor'
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_issi_octal_dtr_enable(struct spi_nor *nor)
+{
+ struct spi_mem_op op;
+ int ret;
+ u8 regval;
+
+ nor->read_dummy = ISSI_MAX_DC;
+
+ ret = write_enable(nor);
+ if (ret)
+ return ret;
+
+ regval = SPINOR_REG_ISSI_VCR_ODDR_EN;
+ op = (struct spi_mem_op)
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_ISSI_WR_VCR, 1),
+ SPI_MEM_OP_ADDR(3, SPINOR_REG_ISSI_VCR_IOMODE, 1),
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(1, , 1));
+
+ ret = spi_mem_exec_op(nor->spi, );
+ if (ret) {
+ dev_err(nor->dev, "Failed to enable octal DTR mode\n");
+ return ret;
+ }
+
+ nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
+
+ return 0;
+}
+
+static void issi_octal_default_init(struct spi_nor *nor)
+{
+ nor->octal_dtr_enable = spi_nor_issi_octal_dtr_enable;
+}
+
+static void issi_octal_post_sfdp_fixup(struct spi_nor *nor,
+ struct spi_nor_flash_parameter *params)
+{
+ /*
+* Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when
+* SPI_NOR_OCTAL_DTR_READ flag exists.
+*/
+ if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR)
+ params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
+ nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
+
+ spi_nor_set_read_settings(>reads[SNOR_CMD_READ_8_8_8_DTR],
+ 0, 16, 0x0c, SNOR_PROTO_8_8_8_DTR);
+ spi_nor_set_pp_settings(>page_programs[SNOR_CMD_PP_8_8_8_DTR],
+ 0x12, SNOR_PROTO_8_8_8_DTR);
+
+ params->rdsr_dummy = 8;
+
+ nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;
+ nor->flags |= SNOR_F_SOFT_RESET;
+}
+
+static struct spi_nor_fixups issi_octal_dtr_fixups = {
+ .default_init = issi_octal_default_init,
+ .post_sfdp = issi_octal_post_sfdp_fixup,
+};
+#endif /* CONFIG_SPI_FLASH_ISSI */
+
/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
* @nor: pointer to a 'struct spi_nor'
*
@@ -4161,6 +4231,14 @@ void spi_nor_set_fixups(struct spi_nor *nor)
nor->fixups = _fixups;
#endif
+#if CONFIG_IS_ENABLED(SPI_FLASH_ISSI)
+ if (JEDEC_MFR(nor->info) == SNOR_MFR_ISSI) {
+ if ((nor->info->id[1] == 0x5a || nor->info->id[1] == 0x5b) &&
+ (nor->info->id[2] == 0x19 || nor->info->id[2] == 0x18))
+ nor->fixups = _octal_dtr_fixups;
+ }
+#endif
+
#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
nor->fixups = _octal_fixups;
#endif /* SPI_FLASH_MACRONIX */
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 4e83b8c94c..e3e37cd79b 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -238,8 +238,12 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25lx256", 0x9d5a19, 0, 128 * 1024, 256,
+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ
+ | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256,
- SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
SPI_NOR_4B_OPCODES) },
+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ
+ | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("is25lx512", 0x9d5a1a, 0, 64 * 1024, 1024,
SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES |
SPI_NOR_HAS_TB) },
#endif
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-no
Re: [PATCH 01/19] spi: cadence_qspi: Add support for DDR PHY mode
cadence_spi_mem_exec_op() because it would
recursively trigger itself as the calibration was not yet completed,
but as a result this does not support all of the read modes that the
device could be configured for. I think this is further reason to have
a specialized function for enabling DTR rather than triggering it on
the first DTR operation.
> +static int cadence_spi_child_pre_probe(struct udevice *bus)
> +{
> +struct spi_slave *slave = dev_get_parent_priv(bus);
> +
> +slave->bytemode = SPI_4BYTE_MODE;
> +
> +return 0;
> +}
> +
> +__weak int cadence_qspi_versal_set_dll_mode(struct udevice *dev)
> +{
> +return -ENOTSUPP;
> +}
Although it is likely that any flash supporting DTR uses 4 byte
addressing, we should not set it here.
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index faf02c7778..5895b5de09 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
Can we split the micron-specific changes into a separate patch? I
realize currently that they are tightly coupled with the calibration
implementation, but after changing the calibration implementation
perhaps this will be possible.
Some additional comments not specific to any part of the code:
How does this patch address the case when the calibrated frequency is
faster than the non-calibrated mode can run at? For example, if
spi-max-frequency is 125MHz, but single IO operation breaks down at
speeds greater than 50MHz? (This also happens on our board). Also, the
calibration algorithm doesn't appear to re-calibrate the read capture
delay register, which is required whenever the clock or IO mode
changes.
At Timesys we have a set of patches that implement DDR and PHY
calibration for the same Cadence IP that presents different solutions
to the above issues. However, our patches only support bypass mode
calibration and direct mode, because they are the only options that
work on our hardware. Would you be interested in looking at our
version and working together to create a new version of this patchset
that can support both of our platforms at once?
Thanks,
Greg
--
Greg Malysa
Timesys Corporation
Re: [PATCH] mtd: spi-nor: Add support to exit 4-byte mode
Hi Tejas,
+ Ian Roberts, my coworker has the following comments:
I do not think it is appropriate to put what appears to be use-case
specific logic into the core functionality.
Your problem statement sounds like the chip is stuck in a stateful
mode after a reset. As alternatives, I would suggest:
1) Toggle the hardware reset line for the chip.
2) If one does not exist, use SPI_FLASH_SOFT_RESET_ON_BOOT
3) Alter your recovery application set the chip back to 3B mode on exit.
As is, I also think this would cause problems for chips with existing
support. set_4byte() sends commands to the chip, which may be
unrecognized or overlap with a manufacturer's custom command and cause
unintended side effects.
On Thu, Mar 28, 2024 at 11:37 AM Tejas Bhumkar
wrote:
>
> The Kria board features a recovery application that activates
> when the FW_EN button is pressed.
> Upon power-up flash operates in 3B mode, However, the recovery
> application changes it back to 4B mode.
> Following a reset, u-boot activates the CONFIG_SPI_FLASH_BAR
> and expects the flash to be in 3B mode. However, there's no
> code to handle this configuration. to address this issue, changes
> were made to disable the 4B mode when the CONFIG_SPI_FLASH_BAR
> is enabled.
>
> Additionally, spi_nor_wait_till_ready() was included because there is
> operation that places the device in a busy state before performing
> a nor read.
>
> Signed-off-by: Tejas Bhumkar
> ---
> drivers/mtd/spi/spi-nor-core.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index f86003ca8c..47f65a4f5e 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -1464,6 +1464,9 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t
> from, size_t len,
> else
> read_len = remain_len;
> #endif
> + ret = spi_nor_wait_till_ready(nor);
> + if (ret)
> + goto read_err;
Can you elaborate on the purpose of this wait_till_ready?
>
> ret = nor->read(nor, addr, read_len, buf);
> if (ret == 0) {
> @@ -4161,6 +4164,7 @@ int spi_nor_scan(struct spi_nor *nor)
> #else
> /* Configure the BAR - discover bank cmds and read current bank */
> nor->addr_width = 3;
> + set_4byte(nor, info, 0);
> ret = read_bar(nor, info);
> if (ret < 0)
> return ret;
> --
> 2.37.6
>
Thanks,
Greg
--
Greg Malysa
Timesys Corporation
Re: [PATCH] usb: dwc2: Add in version 4xx compatibility
I'd be happy with that change. Does anyone have access to the
associated designware databook (I do not)? We could also check to see
if those four bits are all always allocated to the 2/3/4/x version
number. I can submit v2 with that change instead once we know.
On Tue, Mar 26, 2024 at 7:50 AM Marek Vasut wrote:
>
> On 3/26/24 3:32 AM, Greg Malysa wrote:
> > From: Nathan Barrett-Morrison
> >
> > This adds the Synopsys device id for version 4xx of the designware
> > IP block and extends the version check to include it to permit
> > new hardware to run. It does not add any 4xx-specific features.
> >
> > Signed-off-by: Ian Roberts
> > Signed-off-by: Greg Malysa
> > Signed-off-by: Nathan Barrett-Morrison
> >
> > ---
> >
> >
> > ---
> > drivers/usb/host/dwc2.c | 3 ++-
> > drivers/usb/host/dwc2.h | 1 +
> > 2 files changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
> > index 637eb2dd06..6fdde6a9a7 100644
> > --- a/drivers/usb/host/dwc2.c
> > +++ b/drivers/usb/host/dwc2.c
> > @@ -1180,7 +1180,8 @@ static int dwc2_init_common(struct udevice *dev,
> > struct dwc2_priv *priv)
> >snpsid >> 12 & 0xf, snpsid & 0xfff);
> >
> > if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
> > - (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
> > + (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx &&
> > + (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_4xx) {
> > dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
> >snpsid);
> > return -ENODEV;
> > diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h
> > index 6f022e33a1..f202d55eb2 100644
> > --- a/drivers/usb/host/dwc2.h
> > +++ b/drivers/usb/host/dwc2.h
> > @@ -739,6 +739,7 @@ struct dwc2_core_regs {
> > #define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET 7
> > #define DWC2_SNPSID_DEVID_VER_2xx (0x4f542 << 12)
> > #define DWC2_SNPSID_DEVID_VER_3xx (0x4f543 << 12)
> > +#define DWC2_SNPSID_DEVID_VER_4xx(0x4f544 << 12)
> > #define DWC2_SNPSID_DEVID_MASK (0xf <<
> > 12)
> > #define DWC2_SNPSID_DEVID_OFFSET12
>
> Maybe it would be better/easier/futureproof to simply check if (snpsid &
> 0x0 == 0x4f540) ?
--
Greg Malysa
Timesys Corporation
Upcoming Analog Devices SoC Support Submission
Hi Tom, I wanted to get a little bit of guidance before dumping some patches on the mailing list. I've been preparing to submit support we've developed for the Analog Devices SC5xx SoCs including both core SoC support and specific device trees and defconfigs for the eval kits available from ADI. I've submitted several small patches to touch various shared parts of U-Boot that we needed to extend to get this hardware running and to get some familiarity with using patman to format and submit things, but now I have a roughly 15k line changeset consisting of a new mach type and all of the required drivers for the system. It's broken down into a bunch of commits: one for the mach type support, one per driver we've added, and one per target board supported. What is the best way to submit this? Ideally I'd love to get feedback on individual drivers from the respective subsystem maintainers, but it seems rude to have a 20-element patch series that gets resubmitted each time feedback comes in for one component. If we break it down into separate patches for each piece, what would be the best way to ensure that all of the dependencies are merged in order? Thanks, Greg -- Greg Malysa Timesys Corporation
[PATCH] usb: dwc2: Add in version 4xx compatibility
From: Nathan Barrett-Morrison
This adds the Synopsys device id for version 4xx of the designware
IP block and extends the version check to include it to permit
new hardware to run. It does not add any 4xx-specific features.
Signed-off-by: Ian Roberts
Signed-off-by: Greg Malysa
Signed-off-by: Nathan Barrett-Morrison
---
---
drivers/usb/host/dwc2.c | 3 ++-
drivers/usb/host/dwc2.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 637eb2dd06..6fdde6a9a7 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -1180,7 +1180,8 @@ static int dwc2_init_common(struct udevice *dev, struct
dwc2_priv *priv)
snpsid >> 12 & 0xf, snpsid & 0xfff);
if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
- (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
+ (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx &&
+ (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_4xx) {
dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
snpsid);
return -ENODEV;
diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h
index 6f022e33a1..f202d55eb2 100644
--- a/drivers/usb/host/dwc2.h
+++ b/drivers/usb/host/dwc2.h
@@ -739,6 +739,7 @@ struct dwc2_core_regs {
#define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET 7
#define DWC2_SNPSID_DEVID_VER_2xx (0x4f542 << 12)
#define DWC2_SNPSID_DEVID_VER_3xx (0x4f543 << 12)
+#define DWC2_SNPSID_DEVID_VER_4xx (0x4f544 << 12)
#define DWC2_SNPSID_DEVID_MASK (0xf << 12)
#define DWC2_SNPSID_DEVID_OFFSET 12
--
2.43.2
[PATCH] mmc: Support 32-bit only ADMA on 64-bit platforms
Some arm64 platforms may include SDIO host controllers that
only support 32-bit ADMA. While the Linux kernel detects which
size is supported and adjusts the descriptor size used dynamically,
the previous u-boot implementation statically selected between the
two depending on whether DMA_ADDR_T_64BIT was defined. Because the
static selection is already in place and effective for most platforms,
this patch logically separates "64 bit addresses are used for DMA on
this platform" and "64 bit addresses are used by the SDIO host
controller for ADMA" in order to support the small number of platforms
where these statements are not equivalent.
Using 32 bits is opt-in and existing 64 bit platforms should be
unaffected by this change.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Greg Malysa
---
---
drivers/mmc/Kconfig | 18 ++
drivers/mmc/sdhci-adma.c | 2 +-
drivers/mmc/sdhci.c | 9 -
include/sdhci.h | 4 ++--
4 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index cef05790dd..4538286c64 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -495,6 +495,24 @@ config SPL_MMC_SDHCI_ADMA
This enables support for the ADMA (Advanced DMA) defined
in the SD Host Controller Standard Specification Version 3.00 in SPL.
+config MMC_SDHCI_ADMA_FORCE_32BIT
+ bool "Force 32 bit mode for ADMA on 64 bit platforms"
+ help
+ This forces SDHCI ADMA to be built for 32 bit descriptors, even
+ on a 64 bit platform where they would otherwise be assumed to
+ be 64 bits. This is necessary for certain hardware platforms
+ that are 64-bit but include only 32-bit support within the selected
+ SD host controller IP.
+
+config MMC_SDHCI_ADMA_64BIT
+ bool "Use SHDCI ADMA with 64 bit descriptors"
+ depends on !MMC_SDHCI_ADMA_FORCE_32BIT
+ default y if DMA_ADDR_T_64BIT
+ help
+ This selects 64 bit descriptors for SDHCI ADMA. It is enabled by
+ default on 64 bit systems, but can be disabled if one of these
+ systems includes 32-bit ADMA.
+
config FIXED_SDHCI_ALIGNED_BUFFER
hex "SDRAM address for fixed buffer"
depends on SPL && MVEBU_SPL_BOOT_DEVICE_MMC
diff --git a/drivers/mmc/sdhci-adma.c b/drivers/mmc/sdhci-adma.c
index 8213223d3f..474647c3fd 100644
--- a/drivers/mmc/sdhci-adma.c
+++ b/drivers/mmc/sdhci-adma.c
@@ -22,7 +22,7 @@ static void sdhci_adma_desc(struct sdhci_adma_desc *desc,
desc->len = len;
desc->reserved = 0;
desc->addr_lo = lower_32_bits(addr);
-#ifdef CONFIG_DMA_ADDR_T_64BIT
+#ifdef CONFIG_MMC_SDHCI_ADMA_64BIT
desc->addr_hi = upper_32_bits(addr);
#endif
}
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 0178ed8a11..b27ce57d96 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -900,11 +900,10 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct
sdhci_host *host,
host->adma_desc_table = sdhci_adma_init();
host->adma_addr = (dma_addr_t)host->adma_desc_table;
-#ifdef CONFIG_DMA_ADDR_T_64BIT
- host->flags |= USE_ADMA64;
-#else
- host->flags |= USE_ADMA;
-#endif
+ if (IS_ENABLED(CONFIG_MMC_SDHCI_ADMA_64BIT))
+ host->flags |= USE_ADMA64;
+ else
+ host->flags |= USE_ADMA;
#endif
if (host->quirks & SDHCI_QUIRK_REG32_RW)
host->version =
diff --git a/include/sdhci.h b/include/sdhci.h
index a1b74e3bd7..07b84d6715 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -294,7 +294,7 @@ struct sdhci_ops {
};
#define ADMA_MAX_LEN 65532
-#ifdef CONFIG_DMA_ADDR_T_64BIT
+#ifdef CONFIG_MMC_SDHCI_ADMA_64BIT
#define ADMA_DESC_LEN 16
#else
#define ADMA_DESC_LEN 8
@@ -319,7 +319,7 @@ struct sdhci_adma_desc {
u8 reserved;
u16 len;
u32 addr_lo;
-#ifdef CONFIG_DMA_ADDR_T_64BIT
+#ifdef CONFIG_MMC_SDHCI_ADMA_64BIT
u32 addr_hi;
#endif
} __packed;
--
2.43.2
[PATCH] mmc: sdhci: Fix potential ADMA descriptor table overflow
From: Ian Roberts
Change ADMA_TABLE_NO_ENTRIES to round the division up to fully
contain CONFIG_SYS_MMC_MAX_BLK_COUNT, fixing potential buffer overflow
of the ADMA descriptor table.
sdhci_prepare_adma_table() expecitily states it does _not_ check for
overflow as the descriptor table size is dependent on
CONFIG_SYS_MMC_MAX_BLK_COUNT. However, the ADMA_TABLE_NO_ENTRIES
calculation does not round up the divison, so with the current u-boot
defaults:
max_mmc_transfer = (CONFIG_SYS_MMC_MAX_BLK_COUNT * MMC_MAX_BLOCK_LEN) =
65535 * 512 = 33553920 bytes.
ADMA_TABLE_NO_ENTRIES = max_mmc_transfer / ADMA_MAX_LEN =
33553920 / 65532, which does not divide cleanly.
actual_max_transfer = ADMA_TABLE_NO_ENTRIES * ADMA_MAX_LEN = 512 *
65532 = 33552384, which is smaller than max_mmc_transfer.
This can cause sdhci_prepare_adma_table() to write one extra
descriptor, overflowing the table when a transaction larger than
actual_max_transfer is issued.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
---
---
include/sdhci.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/sdhci.h b/include/sdhci.h
index a1b74e3bd7..fbc0f0391c 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -11,6 +11,7 @@
#include
#include
+#include
#include
#include
#include
@@ -299,8 +300,8 @@ struct sdhci_ops {
#else
#define ADMA_DESC_LEN 8
#endif
-#define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
- MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN
+#define ADMA_TABLE_NO_ENTRIES DIV_ROUND_UP(CONFIG_SYS_MMC_MAX_BLK_COUNT * \
+ MMC_MAX_BLOCK_LEN, ADMA_MAX_LEN)
#define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
--
2.43.2
[PATCH] mmc: sdhci: introduce adma_write_desc() hook to struct sdhci_ops
From: Ian Roberts
Add this hook so that it can be overridden with driver specific
implementations. We also let the original sdhci_adma_write_desc()
accept so that the function can set its new value. Then export
the function so that it could be reused by driver's specific
implementations.
The above is a port of Linux kernel commit 54552e4948cbf
In addition, allow drivers to allocate their own ADMA descriptor
tables if additional space is required.
Finally, fix the assignment of adma_addr to fix compiler warning
on 64-bit platforms that still use 32-bit DMA addressing.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
---
---
drivers/mmc/fsl_esdhc.c | 2 +-
drivers/mmc/sdhci-adma.c | 41 +++-
drivers/mmc/sdhci.c | 8 +---
include/sdhci.h | 12 ++--
4 files changed, 44 insertions(+), 19 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index d50669..bd0671cc52 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -252,7 +252,7 @@ static void esdhc_setup_dma(struct fsl_esdhc_priv *priv,
struct mmc_data *data)
priv->adma_desc_table) {
debug("Using ADMA2\n");
/* prefer ADMA2 if it is available */
- sdhci_prepare_adma_table(priv->adma_desc_table, data,
+ sdhci_prepare_adma_table(NULL, priv->adma_desc_table, data,
priv->dma_addr);
adma_addr = virt_to_phys(priv->adma_desc_table);
diff --git a/drivers/mmc/sdhci-adma.c b/drivers/mmc/sdhci-adma.c
index 8213223d3f..8c38448b6a 100644
--- a/drivers/mmc/sdhci-adma.c
+++ b/drivers/mmc/sdhci-adma.c
@@ -9,9 +9,10 @@
#include
#include
-static void sdhci_adma_desc(struct sdhci_adma_desc *desc,
- dma_addr_t addr, u16 len, bool end)
+void sdhci_adma_write_desc(struct sdhci_host *host, void **next_desc,
+ dma_addr_t addr, int len, bool end)
{
+ struct sdhci_adma_desc *desc = *next_desc;
u8 attr;
attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
@@ -19,17 +20,30 @@ static void sdhci_adma_desc(struct sdhci_adma_desc *desc,
attr |= ADMA_DESC_ATTR_END;
desc->attr = attr;
- desc->len = len;
+ desc->len = len & 0x;
desc->reserved = 0;
desc->addr_lo = lower_32_bits(addr);
#ifdef CONFIG_DMA_ADDR_T_64BIT
desc->addr_hi = upper_32_bits(addr);
#endif
+
+ *next_desc += ADMA_DESC_LEN;
+}
+
+static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
+ void **desc, dma_addr_t addr,
+ int len, bool end)
+{
+ if (host && host->ops && host->ops->adma_write_desc)
+ host->ops->adma_write_desc(host, desc, addr, len, end);
+ else
+ sdhci_adma_write_desc(host, desc, addr, len, end);
}
/**
* sdhci_prepare_adma_table() - Populate the ADMA table
*
+ * @host: Pointer to the sdhci_host
* @table: Pointer to the ADMA table
* @data: Pointer to MMC data
* @addr: DMA address to write to or read from
@@ -39,25 +53,26 @@ static void sdhci_adma_desc(struct sdhci_adma_desc *desc,
* Please note, that the table size depends on CONFIG_SYS_MMC_MAX_BLK_COUNT and
* we don't have to check for overflow.
*/
-void sdhci_prepare_adma_table(struct sdhci_adma_desc *table,
- struct mmc_data *data, dma_addr_t addr)
+void sdhci_prepare_adma_table(struct sdhci_host *host,
+ struct sdhci_adma_desc *table,
+ struct mmc_data *data, dma_addr_t start_addr)
{
+ dma_addr_t addr = start_addr;
uint trans_bytes = data->blocksize * data->blocks;
- uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
- struct sdhci_adma_desc *desc = table;
- int i = desc_count;
+ void *next_desc = table;
+ int i = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
while (--i) {
- sdhci_adma_desc(desc, addr, ADMA_MAX_LEN, false);
+ __sdhci_adma_write_desc(host, _desc, addr,
+ ADMA_MAX_LEN, false);
addr += ADMA_MAX_LEN;
trans_bytes -= ADMA_MAX_LEN;
- desc++;
}
- sdhci_adma_desc(desc, addr, trans_bytes, true);
+ __sdhci_adma_write_desc(host, _desc, addr, trans_bytes, true);
- flush_cache((dma_addr_t)table,
- ROUND(desc_count * sizeof(struct sdhci_adma_desc),
+ flush_cache((phys_addr_t)table,
+ ROUND(next_desc - (void *)table,
ARCH_DMA_MINALIGN));
}
diff --git a/drivers/mmc
[PATCH v2] build: Revive and update LDR format support
LDR format files are used primarily by Analog Devices processors but may be of interest to other vendors. Previously support existed for this format as part of the U-Boot build, but it has been unmaintained and unused for a long time. In preparation for adding support for modern ADI processors that use LDR, modernize the LDR support: - Introduce CONFIG_LDR_CPU as the CPU string recognized by the LDR tool may not be the same as CONFIG_CPU - Add an SPL target that repackages u-boot-spl inside an LDR file An almost identical target for packaging u-boot into an LDR file already exists and did not need to be created. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Ian Roberts Signed-off-by: Greg Malysa --- Changes in v2: - Add HAS_LDR prerequisite to avoid prompting for LDR_CPU on unrelated platforms - Fixed accidentally moving 'source "api/Kconfig"' which is unrelated to this patch --- Kconfig | 14 ++ Makefile | 2 +- scripts/Makefile.spl | 5 + 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/Kconfig b/Kconfig index 5710934000..bccacb773a 100644 --- a/Kconfig +++ b/Kconfig @@ -715,6 +715,20 @@ config SYS_CLK_FREQ A static value for the CPU frequency. Note that if not required for a given SoC, this can be left at 0. +config HAS_LDR + bool + help + Enables building .ldr targets for U-Boot and SPL. This does not + automatically build any additional targets with make or buildman. + +config LDR_CPU + string "CPU name to be passed to LDR utility." + depends on HAS_LDR + help + Set the CPU name for the -T parameter in the LDR utility. This is + generally used on processors from Analog Devices, but may be also + be useful for other vendors. + source "api/Kconfig" endmenu# General setup diff --git a/Makefile b/Makefile index a2bc9d5903..db3272a439 100644 --- a/Makefile +++ b/Makefile @@ -1328,7 +1328,7 @@ u-boot-nodtb.bin: u-boot FORCE u-boot.ldr:u-boot $(CREATE_LDR_ENV) - $(LDR) -T $(CONFIG_CPU) -c $@ $< $(LDR_FLAGS) + $(LDR) -T $(CONFIG_LDR_CPU) -c $@ $< $(LDR_FLAGS) $(BOARD_SIZE_CHECK) # binman diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 407fc52376..58d6a452e5 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -381,6 +381,11 @@ $(obj)/$(BOARD)-spl.bin: $(obj)/u-boot-spl.bin $(objtree)/tools/mkexynosspl) $(VAR_SIZE_PARAM) $< $@ endif +$(obj)/u-boot-spl.ldr: $(obj)/u-boot-spl + $(CREATE_LDR_ENV) + $(LDR) -T $(CONFIG_LDR_CPU) -c $@ $< $(LDR_FLAGS) + $(BOARD_SIZE_CHECK) + quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ -- 2.38.2
[PATCH] build: Revive and update LDR format support
LDR format files are used primarily by Analog Devices processors but may be of interest to other vendors. Previously support existed for this format as part of the U-Boot build, but it has been unmaintained and unused for a long time. In preparation for adding support for modern ADI processors that use LDR, modernize the LDR support: - Introduce CONFIG_LDR_CPU as the CPU string recognized by the LDR tool may not be the same as CONFIG_CPU - Add an SPL target that repackages u-boot-spl inside an LDR file An almost identical target for packaging u-boot into an LDR file already exists and did not need to be updated Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Ian Roberts Signed-off-by: Greg Malysa --- Kconfig | 9 - Makefile | 2 +- scripts/Makefile.spl | 5 + 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/Kconfig b/Kconfig index 5710934000..3f3ce6054e 100644 --- a/Kconfig +++ b/Kconfig @@ -715,10 +715,17 @@ config SYS_CLK_FREQ A static value for the CPU frequency. Note that if not required for a given SoC, this can be left at 0. -source "api/Kconfig" +config LDR_CPU + string "CPU name to be passed to LDR utility." + help + Set the CPU name for the -T parameter in the LDR utility. This is + generally used on processors from Analog Devices, but may be also + be useful for other vendors. endmenu# General setup +source "api/Kconfig" + source "boot/Kconfig" source "common/Kconfig" diff --git a/Makefile b/Makefile index a2bc9d5903..db3272a439 100644 --- a/Makefile +++ b/Makefile @@ -1328,7 +1328,7 @@ u-boot-nodtb.bin: u-boot FORCE u-boot.ldr:u-boot $(CREATE_LDR_ENV) - $(LDR) -T $(CONFIG_CPU) -c $@ $< $(LDR_FLAGS) + $(LDR) -T $(CONFIG_LDR_CPU) -c $@ $< $(LDR_FLAGS) $(BOARD_SIZE_CHECK) # binman diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 407fc52376..58d6a452e5 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -381,6 +381,11 @@ $(obj)/$(BOARD)-spl.bin: $(obj)/u-boot-spl.bin $(objtree)/tools/mkexynosspl) $(VAR_SIZE_PARAM) $< $@ endif +$(obj)/u-boot-spl.ldr: $(obj)/u-boot-spl + $(CREATE_LDR_ENV) + $(LDR) -T $(CONFIG_LDR_CPU) -c $@ $< $(LDR_FLAGS) + $(BOARD_SIZE_CHECK) + quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ -- 2.38.2
