Re: [U-Boot] [PATCH V4] AT91: pio: Add PIO3 features
Hi Wolfgang and Albert, How to move on? Thanks BR, Eric On 01/31/2012 01:14 PM, Hong Xu wrote: This patch adds the support for new PIO controller introduced by some AT91 SoCs. New features include * More peripheral multiplexing * Pull-down, Schmitt trigger, Debouncer * More irq trigger mode (may be not interesting in U-Boot) Signed-off-by: Hong Xu Acked-by: Remy Bohmer --- Changes since V3 Add Acked-by from Remy Bohmer arch/arm/include/asm/arch-at91/at91_pio.h | 48 ++- drivers/gpio/at91_gpio.c | 130 +++- 2 files changed, 171 insertions(+), 7 deletions(-) [...] ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V4] AT91: pio: Add PIO3 features
This patch adds the support for new PIO controller introduced by some
AT91 SoCs.
New features include
* More peripheral multiplexing
* Pull-down, Schmitt trigger, Debouncer
* More irq trigger mode (may be not interesting in U-Boot)
Signed-off-by: Hong Xu
Acked-by: Remy Bohmer
---
Changes since V3
Add Acked-by from Remy Bohmer
arch/arm/include/asm/arch-at91/at91_pio.h | 48 ++-
drivers/gpio/at91_gpio.c | 130 +++-
2 files changed, 171 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h
b/arch/arm/include/asm/arch-at91/at91_pio.h
index 416cabf..069368d 100644
--- a/arch/arm/include/asm/arch-at91/at91_pio.h
+++ b/arch/arm/include/asm/arch-at91/at91_pio.h
@@ -4,6 +4,7 @@
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
* Copyright (C) 2009 Jens Scharsig (js_at...@scharsoft.de)
+ * Copyright (C) 2011 Hong Xu (hong...@atmel.com)
*
* Parallel I/O Controller (PIO) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
@@ -17,7 +18,6 @@
#ifndef AT91_PIO_H
#define AT91_PIO_H
-
#define AT91_ASM_PIO_RANGE 0x200
#define AT91_ASM_PIOC_ASR \
(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
@@ -66,14 +66,51 @@ typedef struct at91_port {
u32 puer; /* 0x64 Pull-up Enable Register */
u32 pusr; /* 0x68 Pad Pull-up Status Register */
u32 reserved4;
+#if defined(ATMEL_CPU_HAS_PIO3)
+ u32 abcdsr1;/* 0x70 Peripheral ABCD Select Register 1 */
+ u32 abcdsr2;/* 0x74 Peripheral ABCD Select Register 2 */
+ u32 reserved5[2];
+ u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */
+ u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */
+ u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */
+ u32 scdr; /* 0x8C SCLK Divider Debouncing Register */
+#define PIO_SCDR_DIV_MASK (0x3fff << 0) /* Slow Clock Divider Mask */
+ u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
+ u32 ppder; /* 0x94 Pad Pull-down Enable Register */
+ u32 ppdsr; /* 0x98 Pad Pull-down Status Register */
+ u32 reserved6;
+#else
u32 asr;/* 0x70 Select A Register */
u32 bsr;/* 0x74 Select B Register */
u32 absr; /* 0x78 AB Select Status Register */
u32 reserved5[9]; /* */
+#endif
u32 ower; /* 0xA0 Output Write Enable Register */
u32 owdr; /* 0xA4 Output Write Disable Register */
- u32 owsr; /* OxA8 utput Write Status Register */
+ u32 owsr; /* OxA8 Output Write Status Register */
+#if defined(ATMEL_CPU_HAS_PIO3)
+ u32 reserved7; /* */
+ u32 aimer; /* Additional Interrupt Modes Enable Register*/
+ u32 aimdr; /* Additional Interrupt Modes Disable Register*/
+ u32 aimmr; /* Additional Intterupt Modes Mask Register */
+ u32 reserved8; /* */
+ u32 esr;/* 0xC0 Edge Select Register */
+ u32 lsr;/* 0xC4 Level Select Register */
+ u32 elsr; /* 0xC8 Edge/Level Status Register */
+ u32 reserved9; /* 0xCC */
+ u32 fellsr; /* 0xD0 Falling Edge/Low Level Select Register*/
+ u32 rehlsr; /* 0xD4 Rising Edge/High Level Select Register*/
+ u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */
+ u32 reserved10; /* */
+ u32 locksr; /* 0xE0 Lock Status */
+ u32 wpmr; /* 0xE4 Write Protect Mode Register */
+ u32 wpsr; /* 0xE4 Write Protect Status Register */
+ u32 reserved11[5]; /* */
+ u32 schmitt;/* 0x100 Schmitt Trigger Register */
+ u32 reserved12[63];
+#else
u32 reserved6[85];
+#endif
} at91_port_t;
typedef union at91_pio {
@@ -94,6 +131,13 @@ typedef union at91_pio {
#ifdef CONFIG_AT91_GPIO
int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
+#if defined(ATMEL_CPU_HAS_PIO3)
+int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
+int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
+#endif
int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
int at91_set_pio_output(unsigned port, unsigned pin, int value);
diff --git a/driver
Re: [U-Boot] [PATCH v3] AT91: pio: Add PIO3 features
ping ... BR, Eric On 11/16/2011 06:47 PM, Hong Xu wrote: This patch adds the support for new PIO controller introduced by some AT91 SoCs. New features include * More peripheral multiplexing * Pull-down, Schmitt trigger, Debouncer * More irq trigger mode (may be not interesting in U-Boot) Signed-off-by: Hong Xu --- Change for v3 * CONFIG_CPU_HAS_PIO3 -> ATMEL_CPU_HAS_PIO3 PIO3 is a feature of CPU, not a configuration item arch/arm/include/asm/arch-at91/at91_pio.h | 48 ++- drivers/gpio/at91_gpio.c | 130 +++- 2 files changed, 171 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h index 416cabf..069368d 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/include/asm/arch-at91/at91_pio.h @@ -4,6 +4,7 @@ * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) SAN People [...] ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] AT91: pio: Add PIO3 features
This patch adds the support for new PIO controller introduced by some
AT91 SoCs.
New features include
* More peripheral multiplexing
* Pull-down, Schmitt trigger, Debouncer
* More irq trigger mode (may be not interesting in U-Boot)
Signed-off-by: Hong Xu
---
Change for v3
* CONFIG_CPU_HAS_PIO3 -> ATMEL_CPU_HAS_PIO3
PIO3 is a feature of CPU, not a configuration item
arch/arm/include/asm/arch-at91/at91_pio.h | 48 ++-
drivers/gpio/at91_gpio.c | 130 +++-
2 files changed, 171 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h
b/arch/arm/include/asm/arch-at91/at91_pio.h
index 416cabf..069368d 100644
--- a/arch/arm/include/asm/arch-at91/at91_pio.h
+++ b/arch/arm/include/asm/arch-at91/at91_pio.h
@@ -4,6 +4,7 @@
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
* Copyright (C) 2009 Jens Scharsig (js_at...@scharsoft.de)
+ * Copyright (C) 2011 Hong Xu (hong...@atmel.com)
*
* Parallel I/O Controller (PIO) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
@@ -17,7 +18,6 @@
#ifndef AT91_PIO_H
#define AT91_PIO_H
-
#define AT91_ASM_PIO_RANGE 0x200
#define AT91_ASM_PIOC_ASR \
(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
@@ -66,14 +66,51 @@ typedef struct at91_port {
u32 puer; /* 0x64 Pull-up Enable Register */
u32 pusr; /* 0x68 Pad Pull-up Status Register */
u32 reserved4;
+#if defined(ATMEL_CPU_HAS_PIO3)
+ u32 abcdsr1;/* 0x70 Peripheral ABCD Select Register 1 */
+ u32 abcdsr2;/* 0x74 Peripheral ABCD Select Register 2 */
+ u32 reserved5[2];
+ u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */
+ u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */
+ u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */
+ u32 scdr; /* 0x8C SCLK Divider Debouncing Register */
+#define PIO_SCDR_DIV_MASK (0x3fff << 0) /* Slow Clock Divider Mask */
+ u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
+ u32 ppder; /* 0x94 Pad Pull-down Enable Register */
+ u32 ppdsr; /* 0x98 Pad Pull-down Status Register */
+ u32 reserved6;
+#else
u32 asr;/* 0x70 Select A Register */
u32 bsr;/* 0x74 Select B Register */
u32 absr; /* 0x78 AB Select Status Register */
u32 reserved5[9]; /* */
+#endif
u32 ower; /* 0xA0 Output Write Enable Register */
u32 owdr; /* 0xA4 Output Write Disable Register */
- u32 owsr; /* OxA8 utput Write Status Register */
+ u32 owsr; /* OxA8 Output Write Status Register */
+#if defined(ATMEL_CPU_HAS_PIO3)
+ u32 reserved7; /* */
+ u32 aimer; /* Additional Interrupt Modes Enable Register*/
+ u32 aimdr; /* Additional Interrupt Modes Disable Register*/
+ u32 aimmr; /* Additional Intterupt Modes Mask Register */
+ u32 reserved8; /* */
+ u32 esr;/* 0xC0 Edge Select Register */
+ u32 lsr;/* 0xC4 Level Select Register */
+ u32 elsr; /* 0xC8 Edge/Level Status Register */
+ u32 reserved9; /* 0xCC */
+ u32 fellsr; /* 0xD0 Falling Edge/Low Level Select Register*/
+ u32 rehlsr; /* 0xD4 Rising Edge/High Level Select Register*/
+ u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */
+ u32 reserved10; /* */
+ u32 locksr; /* 0xE0 Lock Status */
+ u32 wpmr; /* 0xE4 Write Protect Mode Register */
+ u32 wpsr; /* 0xE4 Write Protect Status Register */
+ u32 reserved11[5]; /* */
+ u32 schmitt;/* 0x100 Schmitt Trigger Register */
+ u32 reserved12[63];
+#else
u32 reserved6[85];
+#endif
} at91_port_t;
typedef union at91_pio {
@@ -94,6 +131,13 @@ typedef union at91_pio {
#ifdef CONFIG_AT91_GPIO
int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
+#if defined(ATMEL_CPU_HAS_PIO3)
+int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
+int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
+#endif
int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
int at91_set_pio_output(unsi
[U-Boot] [PATCH v2] AT91: pio: Add PIO3 features
This patch adds the support for new PIO controller introduced by some
AT91 SoCs.
New features include
* More peripheral multiplexing
* Pull-down, Schmitt trigger, Debouncer
* More irq trigger mode (may be not interesting in U-Boot)
Signed-off-by: Hong Xu
---
- Correct register group definitions
- ATMEL_CPU_HAS_PIO3 -> CONFIG_CPU_HAS_PIO3
arch/arm/include/asm/arch-at91/at91_pio.h | 48 ++-
drivers/gpio/at91_gpio.c | 130 +++-
2 files changed, 171 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h
b/arch/arm/include/asm/arch-at91/at91_pio.h
index 416cabf..90a3ad6 100644
--- a/arch/arm/include/asm/arch-at91/at91_pio.h
+++ b/arch/arm/include/asm/arch-at91/at91_pio.h
@@ -4,6 +4,7 @@
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
* Copyright (C) 2009 Jens Scharsig (js_at...@scharsoft.de)
+ * Copyright (C) 2011 Hong Xu (hong...@atmel.com)
*
* Parallel I/O Controller (PIO) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
@@ -17,7 +18,6 @@
#ifndef AT91_PIO_H
#define AT91_PIO_H
-
#define AT91_ASM_PIO_RANGE 0x200
#define AT91_ASM_PIOC_ASR \
(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
@@ -66,14 +66,51 @@ typedef struct at91_port {
u32 puer; /* 0x64 Pull-up Enable Register */
u32 pusr; /* 0x68 Pad Pull-up Status Register */
u32 reserved4;
+#if defined(CONFIG_CPU_HAS_PIO3)
+ u32 abcdsr1;/* 0x70 Peripheral ABCD Select Register 1 */
+ u32 abcdsr2;/* 0x74 Peripheral ABCD Select Register 2 */
+ u32 reserved5[2];
+ u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */
+ u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */
+ u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */
+ u32 scdr; /* 0x8C SCLK Divider Debouncing Register */
+#define PIO_SCDR_DIV_MASK (0x3fff << 0) /* Slow Clock Divider Mask */
+ u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
+ u32 ppder; /* 0x94 Pad Pull-down Enable Register */
+ u32 ppdsr; /* 0x98 Pad Pull-down Status Register */
+ u32 reserved6;
+#else
u32 asr;/* 0x70 Select A Register */
u32 bsr;/* 0x74 Select B Register */
u32 absr; /* 0x78 AB Select Status Register */
u32 reserved5[9]; /* */
+#endif
u32 ower; /* 0xA0 Output Write Enable Register */
u32 owdr; /* 0xA4 Output Write Disable Register */
- u32 owsr; /* OxA8 utput Write Status Register */
+ u32 owsr; /* OxA8 Output Write Status Register */
+#if defined(CONFIG_CPU_HAS_PIO3)
+ u32 reserved7; /* */
+ u32 aimer; /* Additional Interrupt Modes Enable Register*/
+ u32 aimdr; /* Additional Interrupt Modes Disable Register*/
+ u32 aimmr; /* Additional Intterupt Modes Mask Register */
+ u32 reserved8; /* */
+ u32 esr;/* 0xC0 Edge Select Register */
+ u32 lsr;/* 0xC4 Level Select Register */
+ u32 elsr; /* 0xC8 Edge/Level Status Register */
+ u32 reserved9; /* 0xCC */
+ u32 fellsr; /* 0xD0 Falling Edge/Low Level Select Register*/
+ u32 rehlsr; /* 0xD4 Rising Edge/High Level Select Register*/
+ u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */
+ u32 reserved10; /* */
+ u32 locksr; /* 0xE0 Lock Status */
+ u32 wpmr; /* 0xE4 Write Protect Mode Register */
+ u32 wpsr; /* 0xE4 Write Protect Status Register */
+ u32 reserved11[5]; /* */
+ u32 schmitt;/* 0x100 Schmitt Trigger Register */
+ u32 reserved12[63];
+#else
u32 reserved6[85];
+#endif
} at91_port_t;
typedef union at91_pio {
@@ -94,6 +131,13 @@ typedef union at91_pio {
#ifdef CONFIG_AT91_GPIO
int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
+#if defined(CONFIG_CPU_HAS_PIO3)
+int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
+int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
+#endif
int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
int at91_set_pio_output(unsigned port, unsigned pin, int val
[U-Boot] [PATCH] AT91: pio: Add PIO3 features
This patch adds the support for new PIO controller introduced by some
AT91 SoCs.
New features include
* More peripheral multiplexing
* Pull-down, Schmitt trigger, Debouncer
* More irq trigger mode (may be not interesting in U-Boot)
Signed-off-by: Hong Xu
---
arch/arm/include/asm/arch-at91/at91_pio.h | 50 ++-
drivers/gpio/at91_gpio.c | 130 +++-
2 files changed, 172 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h
b/arch/arm/include/asm/arch-at91/at91_pio.h
index 416cabf..26e9766 100644
--- a/arch/arm/include/asm/arch-at91/at91_pio.h
+++ b/arch/arm/include/asm/arch-at91/at91_pio.h
@@ -4,6 +4,7 @@
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
* Copyright (C) 2009 Jens Scharsig (js_at...@scharsoft.de)
+ * Copyright (C) 2011 Hong Xu (hong...@atmel.com)
*
* Parallel I/O Controller (PIO) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
@@ -17,7 +18,6 @@
#ifndef AT91_PIO_H
#define AT91_PIO_H
-
#define AT91_ASM_PIO_RANGE 0x200
#define AT91_ASM_PIOC_ASR \
(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
@@ -66,14 +66,51 @@ typedef struct at91_port {
u32 puer; /* 0x64 Pull-up Enable Register */
u32 pusr; /* 0x68 Pad Pull-up Status Register */
u32 reserved4;
+#if defined(ATMEL_CPU_HAS_PIO3)
+ u32 abcdsr1;/* 0x70 Peripheral ABCD Select Register 1 */
+ u32 abcdsr2;/* 0x74 Peripheral ABCD Select Register 2 */
+ u32 reserved5[2];
+ u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */
+ u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */
+ u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */
+ u32 scdr; /* 0x8C SCLK Divider Debouncing Register */
+#define PIO_SCDR_DIV_MASK (0x3fff << 0) /* Slow Clock Divider Mask */
+ u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
+ u32 ppder; /* 0x94 Pad Pull-down Enable Register */
+ u32 ppdsr; /* 0x98 Pad Pull-down Status Register */
+ u32 reserved6;
+#else
u32 asr;/* 0x70 Select A Register */
u32 bsr;/* 0x74 Select B Register */
u32 absr; /* 0x78 AB Select Status Register */
u32 reserved5[9]; /* */
+#endif
u32 ower; /* 0xA0 Output Write Enable Register */
u32 owdr; /* 0xA4 Output Write Disable Register */
- u32 owsr; /* OxA8 utput Write Status Register */
- u32 reserved6[85];
+ u32 owsr; /* OxA8 Output Write Status Register */
+#if defined(ATMEL_CPU_HAS_PIO3)
+ u32 reserved7; /* */
+ u32 aimer; /* Additional Interrupt Modes Enable Register*/
+ u32 aimdr; /* Additional Interrupt Modes Disable Register*/
+ u32 aimmr; /* Additional Intterupt Modes Mask Register */
+ u32 reserved8; /* */
+ u32 esr;/* 0xC0 Edge Select Register */
+ u32 lsr;/* 0xC4 Level Select Register */
+ u32 elsr; /* 0xC8 Edge/Level Status Register */
+ u32 reserved9; /* 0xCC */
+ u32 fellsr; /* 0xD0 Falling Edge/Low Level Select Register*/
+ u32 rehlsr; /* 0xD4 Rising Edge/High Level Select Register*/
+ u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */
+ u32 reserved10; /* */
+ u32 locksr /* 0xE0 Lock Status */
+ u32 wpmr/* 0xE4 Write Protect Mode Register */
+ u32 wpsr/* 0xE4 Write Protect Status Register */
+ u32 reserved11[5]; /* */
+ u32 schmitt;/* 0x100 Schmitt Trigger Register */
+ u32 reserved12[7];
+#else
+ u32 reserved6[21];
+#endif
} at91_port_t;
typedef union at91_pio {
@@ -94,6 +131,13 @@ typedef union at91_pio {
#ifdef CONFIG_AT91_GPIO
int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
+#if defined(ATMEL_CPU_HAS_PIO3)
+int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
+int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
+#endif
int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
int at91_set_pio_output(unsigned port, unsigned pin, int value);
diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_
Re: [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
Hi Aneesh,
On 08/19/2011 10:20 PM, Aneesh V wrote:
> Hi Hong,
>
> On Friday 19 August 2011 02:53 PM, Hong Xu wrote:
>> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
>> into this file.
>>
>> Signed-off-by: Hong Xu
>> Tested-by: Elen Song
>> CC: Albert Aribaud
>> ---
>> Since V1
>> Modified copyright line
>> Fix for compiling warnings
>> Changed the way to use CONFIG_SYS_CACHELINE_SIZE
>> When unaligned buffer detected, emit ERROR instead of WARNING
>>
>> Do not make a common v5,v6 cache file. It seems arm946 is lack of
>> Test-and-Clean DCache operation. And maybe more differents...
>>
>> arch/arm/cpu/arm926ejs/Makefile |2 +-
>> arch/arm/cpu/arm926ejs/cache.c | 135
>> +++
>> 2 files changed, 136 insertions(+), 1 deletions(-)
>> create mode 100644 arch/arm/cpu/arm926ejs/cache.c
>>
[...]
>> +
>> +/*
>> + * The buffer range to be flushed is [start, stop)
>> + */
>> +void flush_dcache_range(unsigned long start, unsigned long stop)
>> +{
>> +cache_range_op(start, stop, FLUSH_CACHE_OP);
>> +}
>> +
>> +void flush_dcache_all(void)
>> +{
>> +/*
>> + * ARM926EJ-S Technical Reference Manual, Chap 2.3.8
>> + * Clean& Invalidate the entire DCache
>> + */
>> +asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
>> +/* Drain WB */
>> +asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
>
> While looking at the manuals for the armv5 compatibility I stumbled
> upon the following in Chapter 2.3.8. Are you sure your flush_dcache_all
> implementation is correct? I suspect the above is flushing only one
> line?
>
> "The test, clean, and invalidate DCache instruction is the same as test
> and clean DCache,
> except that when the entire cache has been cleaned, it is invalidated.
> This means that
> you can use the following loop to clean and invalidate the entire
> DCache:
>
> tci_loop: MRC p15, 0, r15, c7, c14, 3
>BNE tci_loop
> "
As stated in the manual, we can use a loop to clean and invalidate the
entire DCache.
The "asm" statement above is a loop, isn't it? ;-)
BR,
Eric
> best regards,
> Aneesh
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Re: [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
Hi Lei, On 08/19/2011 06:31 PM, Lei Wen wrote: > Hi Hong, > > On Fri, Aug 19, 2011 at 5:23 PM, Hong Xu wrote: >> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations >> into this file. >> >> Signed-off-by: Hong Xu >> Tested-by: Elen Song >> CC: Albert Aribaud >> --- >> Since V1 >> Modified copyright line >> Fix for compiling warnings >> Changed the way to use CONFIG_SYS_CACHELINE_SIZE >> When unaligned buffer detected, emit ERROR instead of WARNING >> >> Do not make a common v5,v6 cache file. It seems arm946 is lack of >> Test-and-Clean DCache operation. And maybe more differents... >> >> arch/arm/cpu/arm926ejs/Makefile |2 +- >> arch/arm/cpu/arm926ejs/cache.c | 135 >> +++ [..] >> +#include >> + >> +#define FLUSH_CACHE_OP 0 >> +#define INVALIDATE_CACHE_OP1 >> + >> +#ifndef CONFIG_SYS_CACHELINE_SIZE >> +/* >> + * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9 >> + * only b'10, aka. 32 bytes cache line len is valid >> + */ >> +#define CONFIG_SYS_CACHELINE_SIZE 32 > > I think we shouldn't make such assumption here. > You could refer to Lukasz's patch over armv7: > http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/105772 > And you also should export one method as: get_dcache_line_size(), so > that we could malloc cache aligned buffer in mmc.c. There was a long loop about this, see http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105113/focus=105137 I agree we may need something like get_dcache_line_size(). This will make driver sane if CONFIG_SYS_CACHELINE_SIZE is not defined. BR, Eric > Best regards, > Lei ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
Hi Wen, On 08/19/2011 06:17 PM, Lei Wen wrote: > Hi Hong, > > On Fri, Aug 19, 2011 at 5:23 PM, Hong Xu wrote: >> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations >> into this file. >> >> Signed-off-by: Hong Xu >> Tested-by: Elen Song >> CC: Albert Aribaud >> --- >> Since V1 >> Modified copyright line >> Fix for compiling warnings >> Changed the way to use CONFIG_SYS_CACHELINE_SIZE >> When unaligned buffer detected, emit ERROR instead of WARNING >> >> Do not make a common v5,v6 cache file. It seems arm946 is lack of >> Test-and-Clean DCache operation. And maybe more differents... >> >> arch/arm/cpu/arm926ejs/Makefile |2 +- >> arch/arm/cpu/arm926ejs/cache.c | 135 >> +++ >> 2 files changed, 136 insertions(+), 1 deletions(-) >> create mode 100644 arch/arm/cpu/arm926ejs/cache.c >> > > This patch series don't works for me. My board is also arm926ejs > based, and its configure as dkb_config; > The error message as below: > ERROR: cache_range_op op: 0 - stop address 0x1fe7c028 not aligned to > cache line size(32 bytes) > ERROR: cache_range_op op: 0 - start address 0x1fe7be30 not aligned to > cache line size(32 bytes) > ERROR: cache_range_op op: 0 - stop address 0x1fe7c030 not aligned to > cache line size(32 bytes) > ERROR: cache_range_op op: 0 - start address 0x1fe7be28 not aligned to > cache line size(32 bytes) > ERROR: cache_range_op op: 0 - stop address 0x1fe7c028 not aligned to > cache line size(32 bytes) The APIs need the buffer address passed is cache-line size aligned. You shall take the alignment into account in your driver code. Try to use memalign() or something similar in your driver code? BR, Eric > Do you have any hint for this? > > Best regards, > Lei ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3 v2] ARM: ARM1136 - Remove flush_cache from arch/arm/lib/cache.c
Hi Marek,
On 08/19/2011 05:40 PM, Marek Vasut wrote:
> On Friday, August 19, 2011 11:23:14 AM Hong Xu wrote:
>> arch/arm/lib/cache.c is cleaned and no real cache operation will be
>> defined in this file. A new file arch/arm/cpu/arm1136/cache.c is
>> created. This file will define the real cache operations.
>>
>> Signed-off-by: Hong Xu
>> Tested-by: Elen Song
>> CC: Albert Aribaud
>> ---
>> Since V2
>> Removed redundant ifdef for CONFIG_OMAP2420 || CONFIG_ARM1136
>>
>> arch/arm/cpu/arm1136/Makefile |2 +-
>> arch/arm/cpu/arm1136/cache.c | 31 +++
>> 2 files changed, 32 insertions(+), 1 deletions(-)
>> create mode 100644 arch/arm/cpu/arm1136/cache.c
>>
>> diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile
>> index 930e0d1..5b5f330 100644
>> --- a/arch/arm/cpu/arm1136/Makefile
>> +++ b/arch/arm/cpu/arm1136/Makefile
[...]
>> + */
>> +
>> +#include
>> +
>> +void flush_cache(unsigned long start, unsigned long size)
>> +{
>> +void arm1136_cache_flush(void);
>
> Whoa this void on the left side is strange ;-)
Just copied from original file. ;-)
Move it out and change to "extern void arm1136_cache_flush(void);", OK
for you?
BR,
Eric
>
>> +
>> +arm1136_cache_flush();
>> +}
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[U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
into this file.
Signed-off-by: Hong Xu
Tested-by: Elen Song
CC: Albert Aribaud
---
Since V1
Modified copyright line
Fix for compiling warnings
Changed the way to use CONFIG_SYS_CACHELINE_SIZE
When unaligned buffer detected, emit ERROR instead of WARNING
Do not make a common v5,v6 cache file. It seems arm946 is lack of
Test-and-Clean DCache operation. And maybe more differents...
arch/arm/cpu/arm926ejs/Makefile |2 +-
arch/arm/cpu/arm926ejs/cache.c | 135 +++
2 files changed, 136 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/cache.c
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 930e0d1..5b5f330 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
START = start.o
-COBJS = cpu.o
+COBJS = cpu.o cache.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
new file mode 100644
index 000..756c9b1
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2011 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+
+#define FLUSH_CACHE_OP 0
+#define INVALIDATE_CACHE_OP1
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+/*
+ * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
+ * only b'10, aka. 32 bytes cache line len is valid
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * Flush or Invalidate DCache respectively
+ */
+static void cache_range_op(unsigned long start, unsigned long stop, int op)
+{
+ unsigned long mva;
+
+ if (op > INVALIDATE_CACHE_OP) {
+ printf("ERROR: %s - Invalid cache operation, op: %d!\n",
+ __func__, op);
+ return;
+ }
+
+ mva = start;
+ if ((mva & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
+ printf("ERROR: %s op: %d - start address 0x%08lx not aligned "
+ "to cache line size(%d bytes)\n", __func__, op, start,
+ CONFIG_SYS_CACHELINE_SIZE);
+ /* Round up starting address */
+ mva = (mva | (CONFIG_SYS_CACHELINE_SIZE - 1)) + 1;
+ }
+ if ((stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
+ printf("ERROR: %s op: %d - stop address 0x%08lx not aligned "
+ "to cache line size(%d bytes)\n", __func__, op, stop,
+ CONFIG_SYS_CACHELINE_SIZE);
+ /* Round down ending address */
+ stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ }
+
+ while (mva < stop) {
+ if (op == FLUSH_CACHE_OP)
+ asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva));
+ else
+ asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva));
+
+ mva += CONFIG_SYS_CACHELINE_SIZE;
+ }
+
+ /* Drain WB if necessary */
+ if (op == FLUSH_CACHE_OP)
+ asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+/*
+ * The buffer range to be flushed is [start, stop)
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ cache_range_op(start, stop, FLUSH_CACHE_OP);
+}
+
+void flush_dcache_all(void)
+{
+ /*
+* ARM926EJ-S Technical Reference Manual, Chap 2.3.8
+* Clean & Invalidate the entire DCache
+*/
+ asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
+ /* Drain WB */
+ asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+ flush_dcache_range(start, start + size);
+}
+
+/*
+ * The buffer range to be invalidated is [start, stop)
+ */
+vo
[U-Boot] [PATCH 2/3 v2] ARM: ARM1136 - Remove flush_cache from arch/arm/lib/cache.c
arch/arm/lib/cache.c is cleaned and no real cache operation will be
defined in this file. A new file arch/arm/cpu/arm1136/cache.c is
created. This file will define the real cache operations.
Signed-off-by: Hong Xu
Tested-by: Elen Song
CC: Albert Aribaud
---
Since V2
Removed redundant ifdef for CONFIG_OMAP2420 || CONFIG_ARM1136
arch/arm/cpu/arm1136/Makefile |2 +-
arch/arm/cpu/arm1136/cache.c | 31 +++
2 files changed, 32 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/arm1136/cache.c
diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile
index 930e0d1..5b5f330 100644
--- a/arch/arm/cpu/arm1136/Makefile
+++ b/arch/arm/cpu/arm1136/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
START = start.o
-COBJS = cpu.o
+COBJS = cpu.o cache.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/arm1136/cache.c b/arch/arm/cpu/arm1136/cache.c
new file mode 100644
index 000..30aa99d
--- /dev/null
+++ b/arch/arm/cpu/arm1136/cache.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+ void arm1136_cache_flush(void);
+
+ arm1136_cache_flush();
+}
--
1.7.6
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[U-Boot] [PATCH 1/3 v2] ARM: Clean arch/arm/lib/cache.c
The default cache operations defined in arch/arm/lib/cache.c
do not perform any real cache operation, and instead a WARNING
will be emitted.
Signed-off-by: Hong Xu
Tested-by: Elen Song
CC: Albert Aribaud
---
Since V1
Modified copyright line
Used `debug' to replace `printf'
arch/arm/lib/cache.c | 58 +++--
1 files changed, 32 insertions(+), 26 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 92b61a2..ce9b712 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -1,6 +1,5 @@
/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ * (C) Copyright 2011 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -20,36 +19,43 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+#include
+#include
-/* for now: just dummy functions to satisfy the linker */
+#define EMIT_WARNING debug("WARNING: %s - CPU cache operation is not " \
+"implemented!\n", __func__)
-#include
+/*
+ * Default implementations
+ *
+ * Warn user if CPU code does not implement necessary cache functions
+ */
+void __weak flush_cache(unsigned long start, unsigned long size)
+{
+ EMIT_WARNING;
+}
-void __flush_cache(unsigned long start, unsigned long size)
+void __weak flush_dcache_all(void)
{
-#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
- void arm1136_cache_flush(void);
+ EMIT_WARNING;
+}
- arm1136_cache_flush();
-#endif
-#ifdef CONFIG_ARM926EJS
- /* test and clean, page 2-23 of arm926ejs manual */
- asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
- /* disable write buffer as well (page 2-22) */
- asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-#endif
- return;
+void __weak flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ EMIT_WARNING;
}
-void flush_cache(unsigned long start, unsigned long size)
- __attribute__((weak, alias("__flush_cache")));
-/*
- * Default implementation:
- * do a range flush for the entire range
- */
-void __flush_dcache_all(void)
+void __weak invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ EMIT_WARNING;
+}
+
+void __weak invalidate_dcache_all(void)
+{
+ EMIT_WARNING;
+}
+
+void __weak invalidate_icache_all(void)
{
- flush_cache(0, ~0);
+ EMIT_WARNING;
}
-void flush_dcache_all(void)
- __attribute__((weak, alias("__flush_dcache_all")));
--
1.7.6
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Re: [U-Boot] [PATCH 0/3] ARM: Clean arm/lib/cache.c, modify ARM1136 and ARM926 accordingly
Hi Marek, On 08/18/2011 06:51 PM, Marek Vasut wrote: > On Thursday, August 11, 2011 04:19:43 AM Hong Xu wrote: >> This series try to clean the code of arch/arm/lib/cache.c >> Move ARM1136 cache operations into cpu/arm1136/cache.c >> Add ARM926EJS cache operations into cpu/arm926ejs/cache.c > > Hi, > > any updates? Quite busy in the passed days ;-) And just turned back. V2 patches are on the way BR, Eric > > Thanks, cheers! > >> >> Hong Xu (3): >> ARM: Clean arch/arm/lib/cache.c >> ARM: ARM1136 - Remove flush_cache from arch/arm/lib/cache.c >> ARM: ARM926EJS - Add cache operations >> >> arch/arm/cpu/arm1136/Makefile |2 +- >> arch/arm/cpu/arm1136/cache.c| 33 + >> arch/arm/cpu/arm926ejs/Makefile |2 +- >> arch/arm/cpu/arm926ejs/cache.c | 142 >> +++ arch/arm/lib/cache.c| >> 55 +--- >> 5 files changed, 208 insertions(+), 26 deletions(-) >> create mode 100644 arch/arm/cpu/arm1136/cache.c >> create mode 100644 arch/arm/cpu/arm926ejs/cache.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3 v3] ARM: ARM926EJS - Add cache operations
Hi Marek,
On 08/11/2011 12:47 PM, Marek Vasut wrote:
> On Thursday, August 11, 2011 05:27:37 AM Hong Xu wrote:
>> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
>> into this file.
>>
>> Signed-off-by: Hong Xu
>> ---
>> V2:
>> Fixed a typo when CONFIG_SYS_DCACHE_OFF is defined
>> V3:
>> Undo changes in include/configs/at91sam9260ek.h
>> It's for testing purpose
>>
>> arch/arm/cpu/arm926ejs/Makefile |2 +-
>> arch/arm/cpu/arm926ejs/cache.c | 142
>> +++ 2 files changed, 143
>> insertions(+), 1 deletions(-)
>> create mode 100644 arch/arm/cpu/arm926ejs/cache.c
>>
>> diff --git a/arch/arm/cpu/arm926ejs/Makefile
>> b/arch/arm/cpu/arm926ejs/Makefile index 930e0d1..5b5f330 100644
>> --- a/arch/arm/cpu/arm926ejs/Makefile
>> +++ b/arch/arm/cpu/arm926ejs/Makefile
>> @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
>> LIB= $(obj)lib$(CPU).o
>>
>> START = start.o
>> -COBJS = cpu.o
>> +COBJS = cpu.o cache.o
>>
>> SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
>> OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
>> diff --git a/arch/arm/cpu/arm926ejs/cache.c
>> b/arch/arm/cpu/arm926ejs/cache.c new file mode 100644
>> index 000..fc321f6
>> --- /dev/null
>> +++ b/arch/arm/cpu/arm926ejs/cache.c
>> @@ -0,0 +1,142 @@
>> +/*
>> + * (C) Copyright 2002
>> + * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
>
> Again ... really ?
>
not sure...
add a new copyright line on top of it?
>> + *
>> + * See file CREDITS for list of people who contributed to this
>> + * project.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#include
>> +
>> +#define FLUSH_CACHE_OP 0
>> +#define INVALIDATE_CACHE_OP 1
>> +
>> +#ifndef CONFIG_SYS_DCACHE_OFF
>> +/*
>> + * Flush or Invalidate DCache respectively
>> + */
>> +static void cache_range_op(unsigned long start, unsigned long stop, int
>> op) +{
>> +int cache_line_len;
>> +unsigned long mva;
>> +char *func_name;
>> +
>> +if (op == FLUSH_CACHE_OP)
>> +func_name = "flush_dcache_range";
>> +else if (op == INVALIDATE_CACHE_OP)
>> +func_name = "invalidate_dcache_range";
>> +else {
>> +printf("WARNING: %s - Invalid cache operation!\n", __func__);
>> +return;
>> +}
well, looks removing it and printing the `op' code is enough.
>
> hm...
> if (op> 2)
> printf(warning);
>
> otherwise, just declare an array of strings ...
> char *name[] = { "flush", "invalidate" };
>
> and access it where needed ... printf("%s", name[OP]); ... maybe ?
>> +
>> +#ifdef CONFIG_SYS_CACHELINE_SIZE
>> +cache_line_len = CONFIG_SYS_CACHELINE_SIZE;
>> +#else
>> +/*
>> + * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
>> + * only b'10, aka. 32 bytes cache line len is valid
>> + */
>> +cache_line_len = 32;
>> +#endif
>
> Move this at the begining of the file
>
> #ifndef CONFIG_SYS...
> #define
> #endif
>
> include the comment, just modify it a bit accordingly, explaining what it does
> here. Then use CONFIG_SYS... as it'll always be defined.
>
OK, looks better.
BR,
Eric
> Otherwise looks good.
>
> I need sleep badly :-) Good night !
>
>> +mva = start;
>> +if ((mva& (cache_line_len - 1)) != 0) {
>> +printf("WARNING: %s - start address 0x%08x not aligned to"
>> +"cache line size(%d bytes)\n", func_name, start,
[...]
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Re: [U-Boot] [PATCH 2/3] ARM: ARM1136 - Remove flush_cache from arch/arm/lib/cache.c
On 08/11/2011 12:40 PM, Marek Vasut wrote:
> On Thursday, August 11, 2011 04:19:47 AM Hong Xu wrote:
>> arch/arm/lib/cache.c is cleaned and no real cache operation will be
>> defined in this file. So a new file arch/arm/cpu/arm1136/cache.c is
>> created. This file will define the real cache operations.
>>
>> Signed-off-by: Hong Xu
>> Tested-by: Elen Song
>> CC: Albert Aribaud
>> CC: Aneesh V
>> CC: Marek Vasut
>> CC: Reinhard Meyer
>> CC: Heiko Schocher
>> ---
>> arch/arm/cpu/arm1136/Makefile |2 +-
>> arch/arm/cpu/arm1136/cache.c | 33 +
>> 2 files changed, 34 insertions(+), 1 deletions(-)
>> create mode 100644 arch/arm/cpu/arm1136/cache.c
>>
>> diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile
>> index 930e0d1..5b5f330 100644
>> --- a/arch/arm/cpu/arm1136/Makefile
>> +++ b/arch/arm/cpu/arm1136/Makefile
>> @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
>> LIB= $(obj)lib$(CPU).o
>>
>> START = start.o
>> -COBJS = cpu.o
>> +COBJS = cpu.o cache.o
>>
>> SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
>> OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
>> diff --git a/arch/arm/cpu/arm1136/cache.c b/arch/arm/cpu/arm1136/cache.c
>> new file mode 100644
>> index 000..02aa266
>> --- /dev/null
>> +++ b/arch/arm/cpu/arm1136/cache.c
>> @@ -0,0 +1,33 @@
>> +/*
>> + * (C) Copyright 2002
>> + * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
>
> Really ?
not sure...
Maybe add a copyright line on top of it?
>
>> + *
>> + * See file CREDITS for list of people who contributed to this
>> + * project.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#include
>> +
>> +void flush_cache(unsigned long start, unsigned long size)
>> +{
>> +#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
>
> Hm, this is in cpu/arm1136/cache.c ... do we need the macro ?
>
> You can test if this breaks anything by MAKEALL script in uboot tree.
Thanks, I'll have a close look at it.
BR,
Eric
>> +void arm1136_cache_flush(void);
>> +
>> +arm1136_cache_flush();
>> +#endif
>> +}
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Re: [U-Boot] [PATCH 1/3] ARM: Clean arch/arm/lib/cache.c
Hi Marek,
On 08/11/2011 12:38 PM, Marek Vasut wrote:
> On Thursday, August 11, 2011 04:19:45 AM Hong Xu wrote:
>> The default cache operations defined in arch/arm/lib/cache.c
>> do not perform any real cache operation, and instead a WARNING
>> will be emitted.
>>
>> Signed-off-by: Hong Xu
>> Tested-by: Elen Song
>> CC: Albert Aribaud
>> CC: Aneesh V
>> CC: Marek Vasut
>> CC: Reinhard Meyer
>> CC: Heiko Schocher
>> ---
>> arch/arm/lib/cache.c | 55
>> - 1 files changed, 31
>> insertions(+), 24 deletions(-)
>>
>> diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
>> index 92b61a2..6af05ec 100644
>> --- a/arch/arm/lib/cache.c
>> +++ b/arch/arm/lib/cache.c
>> @@ -20,36 +20,43 @@
>>* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>>* MA 02111-1307 USA
>>*/
>> +#include
>> +#include
>>
>> -/* for now: just dummy functions to satisfy the linker */
>> +#define EMIT_WARNING printf("WARNING: %s - CPU cache operation is not " \
>> +"implemented!\n", __func__)
>
> Maybe use debug() ? Or make the emission of warning conditional, somehow I
> have
> the feeling this will make some people unhappy.
Just my feelings: It's noisy but it'll give strong message to the user
even if the DEBUG is not opened :-)
BR,
Eric
> Otherwise looks nice and clean.
>>
>> -#include
>> +/*
[...]
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[U-Boot] [PATCH 3/3 v3] ARM: ARM926EJS - Add cache operations
Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
into this file.
Signed-off-by: Hong Xu
---
V2:
Fixed a typo when CONFIG_SYS_DCACHE_OFF is defined
V3:
Undo changes in include/configs/at91sam9260ek.h
It's for testing purpose
arch/arm/cpu/arm926ejs/Makefile |2 +-
arch/arm/cpu/arm926ejs/cache.c | 142 +++
2 files changed, 143 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/cache.c
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 930e0d1..5b5f330 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
START = start.o
-COBJS = cpu.o
+COBJS = cpu.o cache.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
new file mode 100644
index 000..fc321f6
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+
+#define FLUSH_CACHE_OP 0
+#define INVALIDATE_CACHE_OP1
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * Flush or Invalidate DCache respectively
+ */
+static void cache_range_op(unsigned long start, unsigned long stop, int op)
+{
+ int cache_line_len;
+ unsigned long mva;
+ char *func_name;
+
+ if (op == FLUSH_CACHE_OP)
+ func_name = "flush_dcache_range";
+ else if (op == INVALIDATE_CACHE_OP)
+ func_name = "invalidate_dcache_range";
+ else {
+ printf("WARNING: %s - Invalid cache operation!\n", __func__);
+ return;
+ }
+
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+ cache_line_len = CONFIG_SYS_CACHELINE_SIZE;
+#else
+ /*
+* ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
+* only b'10, aka. 32 bytes cache line len is valid
+*/
+ cache_line_len = 32;
+#endif
+ mva = start;
+ if ((mva & (cache_line_len - 1)) != 0) {
+ printf("WARNING: %s - start address 0x%08x not aligned to"
+ "cache line size(%d bytes)\n", func_name, start,
+ cache_line_len);
+ /* Round up starting address */
+ mva = (mva | (cache_line_len - 1)) + 1;
+ }
+ if ((stop & (cache_line_len - 1)) != 0) {
+ printf("WARNING: %s - stop address 0x%08x not aligned to"
+ "cache line size(%d bytes)\n", func_name, stop,
+ cache_line_len);
+ /* Round down ending address */
+ stop &= ~(cache_line_len - 1);
+ }
+
+ while (mva < stop) {
+ if (op == FLUSH_CACHE_OP)
+ asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva));
+ else
+ asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva));
+
+ mva += cache_line_len;
+ }
+
+ /* Drain WB if necessary */
+ if (op == FLUSH_CACHE_OP)
+ asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+/*
+ * The buffer range to be flushed is [start, stop)
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ cache_range_op(start, stop, FLUSH_CACHE_OP);
+}
+
+void flush_dcache_all(void)
+{
+ /*
+* ARM926EJ-S Technical Reference Manual, Chap 2.3.8
+* Clean & Invalidate the entire DCache
+*/
+ asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
+ /* Drain WB */
+ asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+ flush_dcache_range(start, start + size);
+}
+
+/*
+ * The buffer range to be invalidated is [start, stop)
+
[U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
into this file.
Signed-off-by: Hong Xu
CC: Albert Aribaud
---
V2:
Fixed a typo when CONFIG_SYS_DCACHE_OFF is defined
arch/arm/cpu/arm926ejs/Makefile |2 +-
arch/arm/cpu/arm926ejs/cache.c | 142 +++
include/configs/at91sam9260ek.h |1 +
3 files changed, 144 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/cache.c
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 930e0d1..5b5f330 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
START = start.o
-COBJS = cpu.o
+COBJS = cpu.o cache.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
new file mode 100644
index 000..fc321f6
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+
+#define FLUSH_CACHE_OP 0
+#define INVALIDATE_CACHE_OP1
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * Flush or Invalidate DCache respectively
+ */
+static void cache_range_op(unsigned long start, unsigned long stop, int op)
+{
+ int cache_line_len;
+ unsigned long mva;
+ char *func_name;
+
+ if (op == FLUSH_CACHE_OP)
+ func_name = "flush_dcache_range";
+ else if (op == INVALIDATE_CACHE_OP)
+ func_name = "invalidate_dcache_range";
+ else {
+ printf("WARNING: %s - Invalid cache operation!\n", __func__);
+ return;
+ }
+
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+ cache_line_len = CONFIG_SYS_CACHELINE_SIZE;
+#else
+ /*
+* ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
+* only b'10, aka. 32 bytes cache line len is valid
+*/
+ cache_line_len = 32;
+#endif
+ mva = start;
+ if ((mva & (cache_line_len - 1)) != 0) {
+ printf("WARNING: %s - start address 0x%08x not aligned to"
+ "cache line size(%d bytes)\n", func_name, start,
+ cache_line_len);
+ /* Round up starting address */
+ mva = (mva | (cache_line_len - 1)) + 1;
+ }
+ if ((stop & (cache_line_len - 1)) != 0) {
+ printf("WARNING: %s - stop address 0x%08x not aligned to"
+ "cache line size(%d bytes)\n", func_name, stop,
+ cache_line_len);
+ /* Round down ending address */
+ stop &= ~(cache_line_len - 1);
+ }
+
+ while (mva < stop) {
+ if (op == FLUSH_CACHE_OP)
+ asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva));
+ else
+ asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva));
+
+ mva += cache_line_len;
+ }
+
+ /* Drain WB if necessary */
+ if (op == FLUSH_CACHE_OP)
+ asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+/*
+ * The buffer range to be flushed is [start, stop)
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ cache_range_op(start, stop, FLUSH_CACHE_OP);
+}
+
+void flush_dcache_all(void)
+{
+ /*
+* ARM926EJ-S Technical Reference Manual, Chap 2.3.8
+* Clean & Invalidate the entire DCache
+*/
+ asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
+ /* Drain WB */
+ asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+ flush_dcache_range(start, start + size);
+}
+
+/*
+ * The buffer range to be invalidated is [start, stop)
+ */
+void invalidate_dcach
[U-Boot] [PATCH 3/3] ARM: ARM926EJS - Add cache operations
Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
into this file.
Signed-off-by: Hong Xu
Tested-by: Elen Song
CC: Albert Aribaud
CC: Aneesh V
CC: Marek Vasut
CC: Reinhard Meyer
CC: Heiko Schocher
---
arch/arm/cpu/arm926ejs/Makefile |2 +-
arch/arm/cpu/arm926ejs/cache.c | 142 +++
2 files changed, 143 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/cache.c
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 930e0d1..5b5f330 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
START = start.o
-COBJS = cpu.o
+COBJS = cpu.o cache.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
new file mode 100644
index 000..99a73c6
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+
+#define FLUSH_CACHE_OP 0
+#define INVALIDATE_CACHE_OP1
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * Flush or Invalidate DCache respectively
+ */
+static void cache_range_op(unsigned long start, unsigned long stop, int op)
+{
+ int cache_line_len;
+ unsigned long mva;
+ char *func_name;
+
+ if (op == FLUSH_CACHE_OP)
+ func_name = "flush_dcache_range";
+ else if (op == INVALIDATE_CACHE_OP)
+ func_name = "invalidate_dcache_range";
+ else {
+ printf("WARNING: %s - Invalid cache operation!\n", __func__);
+ return;
+ }
+
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+ cache_line_len = CONFIG_SYS_CACHELINE_SIZE;
+#else
+ /*
+* ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
+* only b'10, aka. 32 bytes cache line len is valid
+*/
+ cache_line_len = 32;
+#endif
+ mva = start;
+ if ((mva & (cache_line_len - 1)) != 0) {
+ printf("WARNING: %s - start address 0x%08x not aligned to"
+ "cache line size(%d bytes)\n", func_name, start,
+ cache_line_len);
+ /* Round up starting address */
+ mva = (mva | (cache_line_len - 1)) + 1;
+ }
+ if ((stop & (cache_line_len - 1)) != 0) {
+ printf("WARNING: %s - stop address 0x%08x not aligned to"
+ "cache line size(%d bytes)\n", func_name, stop,
+ cache_line_len);
+ /* Round down ending address */
+ stop &= ~(cache_line_len - 1);
+ }
+
+ while (mva < stop) {
+ if (op == FLUSH_CACHE_OP)
+ asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva));
+ else
+ asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva));
+
+ mva += cache_line_len;
+ }
+
+ /* Drain WB if necessary */
+ if (op == FLUSH_CACHE_OP)
+ asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+/*
+ * The buffer range to be flushed is [start, stop)
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ cache_range_op(start, stop, FLUSH_CACHE_OP);
+}
+
+void flush_dcache_all(void)
+{
+ /*
+* ARM926EJ-S Technical Reference Manual, Chap 2.3.8
+* Clean & Invalidate the entire DCache
+*/
+ asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
+ /* Drain WB */
+ asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+ flush_dcache_range(start, start + size);
+}
+
+/*
+ * The buffer range to be invalidated is [start, stop)
+ */
+void invalidate_dcache_range(unsigne
[U-Boot] [PATCH 3/3] ARM: ARM926EJS - Add cache operations
Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
into this file.
Signed-off-by: Hong Xu
Tested-by: Elen Song
CC: Albert Aribaud
---
arch/arm/cpu/arm926ejs/Makefile |2 +-
arch/arm/cpu/arm926ejs/cache.c | 142 +++
2 files changed, 143 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/cache.c
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 930e0d1..5b5f330 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
START = start.o
-COBJS = cpu.o
+COBJS = cpu.o cache.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
new file mode 100644
index 000..99a73c6
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+
+#define FLUSH_CACHE_OP 0
+#define INVALIDATE_CACHE_OP1
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * Flush or Invalidate DCache respectively
+ */
+static void cache_range_op(unsigned long start, unsigned long stop, int op)
+{
+ int cache_line_len;
+ unsigned long mva;
+ char *func_name;
+
+ if (op == FLUSH_CACHE_OP)
+ func_name = "flush_dcache_range";
+ else if (op == INVALIDATE_CACHE_OP)
+ func_name = "invalidate_dcache_range";
+ else {
+ printf("WARNING: %s - Invalid cache operation!\n", __func__);
+ return;
+ }
+
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+ cache_line_len = CONFIG_SYS_CACHELINE_SIZE;
+#else
+ /*
+* ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
+* only b'10, aka. 32 bytes cache line len is valid
+*/
+ cache_line_len = 32;
+#endif
+ mva = start;
+ if ((mva & (cache_line_len - 1)) != 0) {
+ printf("WARNING: %s - start address 0x%08x not aligned to"
+ "cache line size(%d bytes)\n", func_name, start,
+ cache_line_len);
+ /* Round up starting address */
+ mva = (mva | (cache_line_len - 1)) + 1;
+ }
+ if ((stop & (cache_line_len - 1)) != 0) {
+ printf("WARNING: %s - stop address 0x%08x not aligned to"
+ "cache line size(%d bytes)\n", func_name, stop,
+ cache_line_len);
+ /* Round down ending address */
+ stop &= ~(cache_line_len - 1);
+ }
+
+ while (mva < stop) {
+ if (op == FLUSH_CACHE_OP)
+ asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva));
+ else
+ asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva));
+
+ mva += cache_line_len;
+ }
+
+ /* Drain WB if necessary */
+ if (op == FLUSH_CACHE_OP)
+ asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+/*
+ * The buffer range to be flushed is [start, stop)
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ cache_range_op(start, stop, FLUSH_CACHE_OP);
+}
+
+void flush_dcache_all(void)
+{
+ /*
+* ARM926EJ-S Technical Reference Manual, Chap 2.3.8
+* Clean & Invalidate the entire DCache
+*/
+ asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
+ /* Drain WB */
+ asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+ flush_dcache_range(start, start + size);
+}
+
+/*
+ * The buffer range to be invalidated is [start, stop)
+ */
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ cache_range_op(start, stop, INVALID
[U-Boot] [PATCH 2/3] ARM: ARM1136 - Remove flush_cache from arch/arm/lib/cache.c
arch/arm/lib/cache.c is cleaned and no real cache operation will be
defined in this file. So a new file arch/arm/cpu/arm1136/cache.c is
created. This file will define the real cache operations.
Signed-off-by: Hong Xu
Tested-by: Elen Song
CC: Albert Aribaud
CC: Aneesh V
CC: Marek Vasut
CC: Reinhard Meyer
CC: Heiko Schocher
---
arch/arm/cpu/arm1136/Makefile |2 +-
arch/arm/cpu/arm1136/cache.c | 33 +
2 files changed, 34 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/arm1136/cache.c
diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile
index 930e0d1..5b5f330 100644
--- a/arch/arm/cpu/arm1136/Makefile
+++ b/arch/arm/cpu/arm1136/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
START = start.o
-COBJS = cpu.o
+COBJS = cpu.o cache.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/arm1136/cache.c b/arch/arm/cpu/arm1136/cache.c
new file mode 100644
index 000..02aa266
--- /dev/null
+++ b/arch/arm/cpu/arm1136/cache.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
+ void arm1136_cache_flush(void);
+
+ arm1136_cache_flush();
+#endif
+}
--
1.7.6
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[U-Boot] [PATCH 2/3] ARM: ARM1136 - Remove flush_cache from arch/arm/lib/cache.c
arch/arm/lib/cache.c is cleaned and no real cache operation will be
defined in this file. So a new file arch/arm/cpu/arm1136/cache.c is
created. This file will define the real cache operations.
Signed-off-by: Hong Xu
Tested-by: Elen Song
CC: Albert Aribaud
---
arch/arm/cpu/arm1136/Makefile |2 +-
arch/arm/cpu/arm1136/cache.c | 33 +
2 files changed, 34 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/arm1136/cache.c
diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile
index 930e0d1..5b5f330 100644
--- a/arch/arm/cpu/arm1136/Makefile
+++ b/arch/arm/cpu/arm1136/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
START = start.o
-COBJS = cpu.o
+COBJS = cpu.o cache.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/arm1136/cache.c b/arch/arm/cpu/arm1136/cache.c
new file mode 100644
index 000..02aa266
--- /dev/null
+++ b/arch/arm/cpu/arm1136/cache.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
+ void arm1136_cache_flush(void);
+
+ arm1136_cache_flush();
+#endif
+}
--
1.7.6
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[U-Boot] [PATCH 1/3] ARM: Clean arch/arm/lib/cache.c
The default cache operations defined in arch/arm/lib/cache.c
do not perform any real cache operation, and instead a WARNING
will be emitted.
Signed-off-by: Hong Xu
Tested-by: Elen Song
CC: Albert Aribaud
CC: Aneesh V
CC: Marek Vasut
CC: Reinhard Meyer
CC: Heiko Schocher
---
arch/arm/lib/cache.c | 55 -
1 files changed, 31 insertions(+), 24 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 92b61a2..6af05ec 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -20,36 +20,43 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+#include
+#include
-/* for now: just dummy functions to satisfy the linker */
+#define EMIT_WARNING printf("WARNING: %s - CPU cache operation is not " \
+"implemented!\n", __func__)
-#include
+/*
+ * Default implementations
+ *
+ * Warn user if CPU code does not implement necessary cache functions
+ */
+void __weak flush_cache(unsigned long start, unsigned long size)
+{
+ EMIT_WARNING;
+}
-void __flush_cache(unsigned long start, unsigned long size)
+void __weak flush_dcache_all(void)
{
-#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
- void arm1136_cache_flush(void);
+ EMIT_WARNING;
+}
- arm1136_cache_flush();
-#endif
-#ifdef CONFIG_ARM926EJS
- /* test and clean, page 2-23 of arm926ejs manual */
- asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
- /* disable write buffer as well (page 2-22) */
- asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-#endif
- return;
+void __weak flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ EMIT_WARNING;
}
-void flush_cache(unsigned long start, unsigned long size)
- __attribute__((weak, alias("__flush_cache")));
-/*
- * Default implementation:
- * do a range flush for the entire range
- */
-void __flush_dcache_all(void)
+void __weak invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ EMIT_WARNING;
+}
+
+void __weak invalidate_dcache_all(void)
+{
+ EMIT_WARNING;
+}
+
+void __weak invalidate_icache_all(void)
{
- flush_cache(0, ~0);
+ EMIT_WARNING;
}
-void flush_dcache_all(void)
- __attribute__((weak, alias("__flush_dcache_all")));
--
1.7.6
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[U-Boot] [PATCH 1/3] ARM: Clean arch/arm/lib/cache.c
The default cache operations defined in arch/arm/lib/cache.c
do not perform any real cache operation, and instead a WARNING
will be emitted.
Signed-off-by: Hong Xu
Tested-by: Elen Song
CC: Albert Aribaud
---
arch/arm/lib/cache.c | 55 -
1 files changed, 31 insertions(+), 24 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 92b61a2..6af05ec 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -20,36 +20,43 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+#include
+#include
-/* for now: just dummy functions to satisfy the linker */
+#define EMIT_WARNING printf("WARNING: %s - CPU cache operation is not " \
+"implemented!\n", __func__)
-#include
+/*
+ * Default implementations
+ *
+ * Warn user if CPU code does not implement necessary cache functions
+ */
+void __weak flush_cache(unsigned long start, unsigned long size)
+{
+ EMIT_WARNING;
+}
-void __flush_cache(unsigned long start, unsigned long size)
+void __weak flush_dcache_all(void)
{
-#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
- void arm1136_cache_flush(void);
+ EMIT_WARNING;
+}
- arm1136_cache_flush();
-#endif
-#ifdef CONFIG_ARM926EJS
- /* test and clean, page 2-23 of arm926ejs manual */
- asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
- /* disable write buffer as well (page 2-22) */
- asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-#endif
- return;
+void __weak flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ EMIT_WARNING;
}
-void flush_cache(unsigned long start, unsigned long size)
- __attribute__((weak, alias("__flush_cache")));
-/*
- * Default implementation:
- * do a range flush for the entire range
- */
-void __flush_dcache_all(void)
+void __weak invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ EMIT_WARNING;
+}
+
+void __weak invalidate_dcache_all(void)
+{
+ EMIT_WARNING;
+}
+
+void __weak invalidate_icache_all(void)
{
- flush_cache(0, ~0);
+ EMIT_WARNING;
}
-void flush_dcache_all(void)
- __attribute__((weak, alias("__flush_dcache_all")));
--
1.7.6
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[U-Boot] [PATCH 0/3] ARM: Clean arm/lib/cache.c, modify ARM1136 and ARM926 accordingly
This series try to clean the code of arch/arm/lib/cache.c Move ARM1136 cache operations into cpu/arm1136/cache.c Add ARM926EJS cache operations into cpu/arm926ejs/cache.c Hong Xu (3): ARM: Clean arch/arm/lib/cache.c ARM: ARM1136 - Remove flush_cache from arch/arm/lib/cache.c ARM: ARM926EJS - Add cache operations arch/arm/cpu/arm1136/Makefile |2 +- arch/arm/cpu/arm1136/cache.c| 33 + arch/arm/cpu/arm926ejs/Makefile |2 +- arch/arm/cpu/arm926ejs/cache.c | 142 +++ arch/arm/lib/cache.c| 55 +--- 5 files changed, 208 insertions(+), 26 deletions(-) create mode 100644 arch/arm/cpu/arm1136/cache.c create mode 100644 arch/arm/cpu/arm926ejs/cache.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] ARM926ejs: Add routines to invalidate D-Cache
Hi Albert, On 08/10/2011 02:36 PM, Albert ARIBAUD wrote: > Hi Hong Xu, > > Le 10/08/2011 08:17, Hong Xu a écrit : > >> There are some ARM926 specific code in arch/arm/lib/cache.c; So I also >> put the stuff there. ;-) I think Albert Aribaud or the original >> contributor of cache part shall have clearer view.So, I'll keep neutral >> to hear more ideas. > > Basically, cache operations are CP15 commands which are defined for each > ARM architecture, not for each ISA, so Marek is right about the best > place for this being in arm926ejs. Actually, I think > arch/arm/lib/cache.c should only contain the weak defaults (i.e., no > real cache action) and each architecture should provide overrides to the > defaults. Currently this is almost the case, with (apart from arm926ejs > which you're already touching) only one arm1136 specific implementation > to move. > > So please move the arm926ejs specific implementations to > arch/arm/cpu/arm926ejs/cache.c as suggested by Marek, keeping only the > weak default in arch/arm/lib/cache.c. Ok, I'll manage a basic version for review. Thanks BR, Eric > > Amicalement, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] ARM926ejs: Add routines to invalidate D-Cache
Hi Marek Vasut, On 08/10/2011 01:52 PM, Marek Vasut wrote: > On Wednesday, August 10, 2011 04:49:25 AM Hong Xu wrote: >> After DMA operation, we need to maintain D-Cache coherency. >> So that the DCache must be invalidated (hence CPU will fetch >> data written by DMA controller from RAM). >> >> Tested on AT91SAM9261EK with Peripheral DMA controller. > > Hi Hong, > > one more thing, not that I want to disappoint you. Not at all ;-) To raise such discussion is not bad actually. > Try to take a look at arch/arm/cpu/armv7/cache_v7.c > > Maybe we should do the same for arm926ejs -- have > arch/arm/cpu/arm926ejs/cache.c > -- containing arm926ejs specific cache management functions. That way, > arch/arm/lib/cache.c won't become mess. > > What do you think ? Basically I'm not quite sure about the design of ARM cache part. I noticed the work for armv7, but I've thought it as a special case because armv7 cache part looks more complicated than ARM926. There are some ARM926 specific code in arch/arm/lib/cache.c; So I also put the stuff there. ;-) I think Albert Aribaud or the original contributor of cache part shall have clearer view.So, I'll keep neutral to hear more ideas. BR, Eric >> >> Signed-off-by: Hong Xu >> Tested-by: Elen Song >> CC: Albert Aribaud >> CC: Aneesh V >> CC: Marek Vasut >> CC: Reinhard Meyer >> CC: Heiko Schocher >> --- >> V2: >>Per Albert's suggestion, add invalidate_dcache_range >> >> V3: >>invalidate_dcache_range emits warning when detecting unaligned buffer >> >>invalidate_dcache_range won't clean any adjacent cache line when >> detecting unaligned buffer and only round up/down the buffer address >> >> v4: >>invalidate_dcache_range will emit clearer warning message >> >>Per Albert's suggestion, if not alighed to cache line size, round up >>start address, round down stop addres >> >>Per Marek Vasut's suggestion, use __func__ stated in C99 >> >> arch/arm/lib/cache.c | 58 >> ++ 1 files changed, 58 >> insertions(+), 0 deletions(-) >> [...] ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4] ARM926ejs: Add routines to invalidate D-Cache
After DMA operation, we need to maintain D-Cache coherency.
So that the DCache must be invalidated (hence CPU will fetch
data written by DMA controller from RAM).
Tested on AT91SAM9261EK with Peripheral DMA controller.
Signed-off-by: Hong Xu
Tested-by: Elen Song
CC: Albert Aribaud
CC: Aneesh V
CC: Marek Vasut
CC: Reinhard Meyer
CC: Heiko Schocher
---
V2:
Per Albert's suggestion, add invalidate_dcache_range
V3:
invalidate_dcache_range emits warning when detecting unaligned buffer
invalidate_dcache_range won't clean any adjacent cache line when detecting
unaligned buffer and only round up/down the buffer address
v4:
invalidate_dcache_range will emit clearer warning message
Per Albert's suggestion, if not alighed to cache line size, round up
start address, round down stop addres
Per Marek Vasut's suggestion, use __func__ stated in C99
arch/arm/lib/cache.c | 58 ++
1 files changed, 58 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 92b61a2..4c8e160 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -53,3 +53,61 @@ void __flush_dcache_all(void)
}
void flush_dcache_all(void)
__attribute__((weak, alias("__flush_dcache_all")));
+
+/*
+ * The buffer range to be invalidated is [start, stop)
+ */
+void __invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ int cache_line_len;
+ unsigned long mva;
+
+#ifdef CONFIG_ARM926EJS
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+ cache_line_len = CONFIG_SYS_CACHELINE_SIZE;
+#else
+ /*
+* ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
+* only b'10, aka. 32 bytes cache line len is valid
+*/
+ cache_line_len = 32;
+#endif
+ mva = start;
+ if ((mva & (cache_line_len - 1)) != 0) {
+ printf("WARNING: %s - start address 0x%08x not aligned to"
+ "cache line size(%d bytes)\n", __func__, start,
+ cache_line_len);
+ /* Round up starting address */
+ mva = (mva | (cache_line_len - 1)) + 1;
+ }
+ if ((stop & (cache_line_len - 1)) != 0) {
+ printf("WARNING: %s - stop address 0x%08x not aligned to"
+ "cache line size(%d bytes)\n", __func__, stop,
+ cache_line_len);
+ /* Round down ending address */
+ stop &= ~(cache_line_len - 1);
+ }
+
+ while (mva < stop) {
+ asm("mcr p15, 0, %0, c7, c6, 1" : : "r"(mva));
+ mva += cache_line_len;
+ }
+
+ /* Drain the WB */
+ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+#endif
+
+ return;
+}
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+ __attribute__((weak, alias("__invalidate_dcache_range")));
+
+void __invalidate_dcache_all(void)
+{
+#ifdef CONFIG_ARM926EJS
+ asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+#endif
+ return;
+}
+void invalidate_dcache_all(void)
+ __attribute__((weak, alias("__invalidate_dcache_all")));
--
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Re: [U-Boot] [PATCH] ARM926ejs: Add routines to invalidate D-Cache
Hi Marek Vasut,
On 08/10/2011 03:55 AM, Marek Vasut wrote:
> On Tuesday, August 09, 2011 03:57:41 AM Hong Xu wrote:
>> Hi Marek Vasut,
>>
>> On 08/09/2011 01:34 AM, Marek Vasut wrote:
[...]
>>>> printf("WARNING: %s - start address %x is not aligned\n"
>>>>
>>>>__FUNCTION__, start);
>>>
>>> __func__ is prefered in linux kernel :-)
>>
>> __func__ is C99 standard. __FUNCTION__ appears more in U-Boot. ;-)
>
> This doesn't mean it's correct ;-) "majority proof" isn't a proof really.
>
>> GCC manual says some older GCC only recognize __FUNCTION__ .
>> If we rely on GCC, it looks __FUNCTION__ will reduce troubles.
>
> Do we support such ancient versions of GCC anyway ? Just to be clear, I'm fine
> with either way, just my 2.7183 cents ;-)
Agree. Just after last reply, I reconsidered the situation in the
tearoom. __func__ looks better. ;-) I'll resend the patch soon, thanks.
BR,
Eric
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Re: [U-Boot] [PATCH] ARM926ejs: Add routines to invalidate D-Cache
Hi Marek Vasut,
On 08/09/2011 01:34 AM, Marek Vasut wrote:
> On Monday, August 08, 2011 10:01:19 AM Albert ARIBAUD wrote:
>> Hi Hong Xu,
>>
>> Le 08/08/2011 05:20, Hong Xu a écrit :
>>> After DMA operation, we need to maintain D-Cache coherency.
>>> So that the DCache must be invalidated (hence CPU will fetch
>>> data written by DMA controller from RAM).
>>>
>>> Tested on AT91SAM9261EK with Peripheral DMA controller.
>>>
>>> Signed-off-by: Hong Xu
>>> Tested-by: Elen Song
>>> CC: Albert Aribaud
>>> CC: Aneesh V
>>> CC: Reinhard Meyer
>>> CC: Heiko Schocher
>>> ---
>>>
>>> V2:
>>> Per Albert's suggestion, add invalidate_dcache_range
>>>
>>> V3:
>>> invalidate_dcache_range emits warning when detecting unaligned buffer
>>>
>>> invalidate_dcache_range won't clean any adjacent cache line when
>>> detecting unaligned buffer and only round up/down the buffer address
>>>
>>> + mva = start;
>>> + if ((mva& (cache_line_len - 1)) != 0) {
>>> + printf("WARNING: %s - unaligned buffer detected, starting "
>>
>> I'd rather have a message about "cache", not "buffer", e.g.
>>
>> printf("WARNING: %s - start address %x is not aligned\n"
>> __FUNCTION__, start);
>
> __func__ is prefered in linux kernel :-)
__func__ is C99 standard. __FUNCTION__ appears more in U-Boot. ;-)
GCC manual says some older GCC only recognize __FUNCTION__ .
If we rely on GCC, it looks __FUNCTION__ will reduce troubles.
BR,
Eric
>>
>>> + mva&= ~(cache_line_len - 1);
>>> + }
>>> + if ((stop& (cache_line_len - 1)) != 0) {
>>> + printf("WARNING: %s - unaligned buffer detected, ending "
>>> + "address: 0x%08x\n", __FUNCTION__, stop);
>>
>> Ditto.
>
> Ditto.
>
[...]
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Re: [U-Boot] [PATCH] ARM926ejs: Add routines to invalidate D-Cache
Hi Albert,
On 08/08/2011 04:01 PM, Albert ARIBAUD wrote:
> Hi Hong Xu,
>
> Le 08/08/2011 05:20, Hong Xu a écrit :
>> After DMA operation, we need to maintain D-Cache coherency.
>> So that the DCache must be invalidated (hence CPU will fetch
[...]
>> unaligned buffer and only round up/down the buffer address
>
>> + mva = start;
>> + if ((mva& (cache_line_len - 1)) != 0) {
>> + printf("WARNING: %s - unaligned buffer detected, starting "
>
> I'd rather have a message about "cache", not "buffer", e.g.
>
> printf("WARNING: %s - start address %x is not aligned\n"
> __FUNCTION__, start);
OK
>> + mva&= ~(cache_line_len - 1);
>> + }
>> + if ((stop& (cache_line_len - 1)) != 0) {
>> + printf("WARNING: %s - unaligned buffer detected, ending "
>> + "address: 0x%08x\n", __FUNCTION__, stop);
>
> Ditto.
OK
>> + stop = (stop | (cache_line_len - 1)) + 1;
>> + }
>> +
>> + while (mva< stop) {
>> + asm("mcr p15, 0, %0, c7, c6, 1" : : "r"(mva));
>> + mva += cache_line_len;
>> + }
>
> Thinking more about the degenerate case -- why not round *up* the start
> address, and round *down* the stop address, that is, *reduce* the area
> to the aligned portion rather than *expand* it into the unknown? That
> would make data in "partially owned" cache lines safe from unwanted
> invalidation. OTOH, it would not completely invalidate the caller's
> data, but at least the malfunction would appear in the faulty calling
> code, not elsewhere.
>
> Opinions?
Agree :)
BR,
Eric
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[U-Boot] [PATCH] ARM926ejs: Add routines to invalidate D-Cache
After DMA operation, we need to maintain D-Cache coherency.
So that the DCache must be invalidated (hence CPU will fetch
data written by DMA controller from RAM).
Tested on AT91SAM9261EK with Peripheral DMA controller.
Signed-off-by: Hong Xu
Tested-by: Elen Song
CC: Albert Aribaud
CC: Aneesh V
CC: Reinhard Meyer
CC: Heiko Schocher
---
V2:
Per Albert's suggestion, add invalidate_dcache_range
V3:
invalidate_dcache_range emits warning when detecting unaligned buffer
invalidate_dcache_range won't clean any adjacent cache line when detecting
unaligned buffer and only round up/down the buffer address
arch/arm/lib/cache.c | 54 ++
1 files changed, 54 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 92b61a2..9e6aa47 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -53,3 +53,57 @@ void __flush_dcache_all(void)
}
void flush_dcache_all(void)
__attribute__((weak, alias("__flush_dcache_all")));
+
+/*
+ * The buffer range to be invalidated is [start, stop)
+ */
+void __invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ int cache_line_len;
+ unsigned long mva;
+
+#ifdef CONFIG_ARM926EJS
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+ cache_line_len = CONFIG_SYS_CACHELINE_SIZE;
+#else
+ /*
+* ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
+* only b'10, aka. 32 bytes cache line len is valid
+*/
+ cache_line_len = 32;
+#endif
+ mva = start;
+ if ((mva & (cache_line_len - 1)) != 0) {
+ printf("WARNING: %s - unaligned buffer detected, starting "
+ "address: 0x%08x\n", __FUNCTION__, start);
+ mva &= ~(cache_line_len - 1);
+ }
+ if ((stop & (cache_line_len - 1)) != 0) {
+ printf("WARNING: %s - unaligned buffer detected, ending "
+ "address: 0x%08x\n", __FUNCTION__, stop);
+ stop = (stop | (cache_line_len - 1)) + 1;
+ }
+
+ while (mva < stop) {
+ asm("mcr p15, 0, %0, c7, c6, 1" : : "r"(mva));
+ mva += cache_line_len;
+ }
+
+ /* Drain the WB */
+ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+#endif
+
+ return;
+}
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+ __attribute__((weak, alias("__invalidate_dcache_range")));
+
+void __invalidate_dcache_all(void)
+{
+#ifdef CONFIG_ARM926EJS
+ asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+#endif
+ return;
+}
+void invalidate_dcache_all(void)
+ __attribute__((weak, alias("__invalidate_dcache_all")));
--
1.7.6
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Re: [U-Boot] [PATCH v2] ARM926ejs: Add routines to invalidate D-Cache
Hi Aneesh, On 08/05/2011 03:10 PM, Aneesh V wrote: > Hi Hong, Albert, > > On Friday 05 August 2011 12:16 PM, Albert ARIBAUD wrote: >> Le 05/08/2011 08:38, Hong Xu a écrit : >>> Hi Albert, >>> >>> I've tried to deal with the case that the (start, stop) is not aligned. >>> If mis-align happens, the adjacent lines will be cleaned before >>> invalidating. And from my view it's impossible for a driver to always >>> pass aligned address to invalidate_dcache_range. >> >> Why would it be impossible? If it is statically allocated it can use >> __attribute__(aligned)) and if it is dynamically aligned, it can be >> over-allocated to make sure it starts and ends at cache boundaries. >> >>> To answer your question in another email >>> >>> > How do you know the dirty data should be flushed rather than >>> invalidated? >>> >>> "Dirty" means this cache is changed by CPU but not has not been written >>> into memory or WB. If we invalidate it, data will lost. In most cases, I >>> do not see a situation why the dirty data shall not be written into >>> memory. >> >> The problem is the cases that fall outside of 'most'. This kind of issue >> tends to have effects that, when unwanted, are extremely difficult to >> link to their cause and makes for long and painful debugging. >> > > IMHO, Hong's approach is correct. If the buffer that is invalidated is > not aligned to cache-line, one cache-line at the respective boundary > may have to be flushed to make sure the invalidation doesn't affect > somebody else's memory. > > The solution is for drivers to ensure that any buffer that needs to be > invalidated is aligned to cache-line boundary at both ends. The above > approach puts this onus on the driver. I have documented the alignment > requirement in my recent patch series for fixing arm cache problems. I have not noticed the patch series. ;-) If we put the alignment burden to the driver, I'm afraid many drivers which make use of something like a DMA controller have to modify the code heavily. This sounds not good. :) BR, Eric > best regards, > Aneesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] ARM926ejs: Add routines to invalidate D-Cache
On 08/05/2011 02:46 PM, Albert ARIBAUD wrote:
> Le 05/08/2011 08:38, Hong Xu a écrit :
>> Hi Albert,
>>
>> On 08/05/2011 02:13 PM, Albert ARIBAUD wrote:
>>> Hi Hong Xu,
>>>
>>> Le 05/08/2011 06:44, Hong Xu a écrit :
>>>> After DMA operation, we need to maintain D-Cache coherency.
>>>> We need to clean cache (write back the dirty lines) and then
>>>> make the cache invalidate as well(hence CPU will fetch data
>>>> written by DMA controller from RAM).
>>>>
>>>> Tested on AT91SAM9261EK with Peripheral DMA controller.
>>>>
>>>> Signed-off-by: Hong Xu
>>>> Tested-by: Elen Song
>>>> CC: Albert Aribaud
>>>> CC: Heiko Schocher
>>
>> [...]
>>
>>>> +
>>>> +#ifdef CONFIG_SYS_CACHELINE_SIZE
>>>> + cache_line_len = CONFIG_SYS_CACHELINE_SIZE;
>>>> +#else
>>>> + cache_line_len = 32;
>>>
>>> Document magic number 32 -- for instance, indicate ARM architecture spec
>>> paragraph reference in a comment above it (and possibly emit a
>>> compile-time and/or run-time warning) -- or bail out with a compile
>>> error if CONFIG_SYS_CACHELINE_SIZE is not defined.
>>
>> ARM926EJ-S Technical Reference Manual (r0p4/r0p5) only defines one cache
>> line size, "32". From my understanding, the standard ARM926EJ-S
>> implementation shall use 32 bytes cache line size. Of course this can be
>> overwritten by CONFIG_SYS_CACHELINE_SIZE, but shall we force to define
>> it?
>>
>> Frankly I have not found a proper place to define this(aka. not using 32
>> here), for example as a Macro.
>
> As I said, I am fine with a simple comment above that '32' that says
> where this value comes from.
>
OK
>>>> +#endif
>>>> + /*
>>>> + * If start and stop are not aligned to cache-line,
>>>> + * the adjacent lines will be cleaned
>>>> + */
>>>> + if ((start& (cache_line_len - 1)) != 0)
>>>> + asm("mcr p15, 0, %0, c7, c10, 1" : : "r" (start));
>>>> + if ((stop& (cache_line_len - 1)) != 0)
>>>> + asm("mcr p15, 0, %0, c7, c10, 1" : : "r" (stop));
>>>> +
>>>> + mva = start& ~(cache_line_len - 1);
>>>> + while (mva< stop) {
>>>> + asm("mcr p15, 0, %0, c7, c6, 1" : : "r"(mva));
>>>> + mva += cache_line_len;
>>>> + }
>>>
>>> I, like Reinhard, prefer aligning start and stop and then looping
>>> through a single invalidate mcr.
>>>
>>> But I also want to make sure logs tell us anything weird with caches,
>>> and since unaligned start or stop invalidation could lead to trashing
>>> third party data, I would like the code to emit a run-time warning if
>>> that happens, like this:
>>>
>>> if ((start& (cache_line_len - 1)) != 0) {
>>> printf("WARNING: aligning start %x on start of cache line\n",
>>> start);
>>> start &= ~(cache_line_len - 1);
>>> }
>>> if ((stop& (cache_line_len - 1)) != (cache_line_len -1) ) {
>>> printf("WARNING: aligning stop %x on end of cache line\n",
>>> stop);
>>> start |= (cache_line_len - 1);
>>> }
>>
>> I've tried to deal with the case that the (start, stop) is not aligned.
>> If mis-align happens, the adjacent lines will be cleaned before
>> invalidating. And from my view it's impossible for a driver to always
>> pass aligned address to invalidate_dcache_range.
>
> Why would it be impossible? If it is statically allocated it can use
> __attribute__(aligned)) and if it is dynamically aligned, it can be
> over-allocated to make sure it starts and ends at cache boundaries.
Technically it's possible, as you mentioned. But shall we add such
restriction? Does this API initially have this alignment primitive?
>> To answer your question in another email
>>
>> > How do you know the dirty data should be flushed rather than
>> invalidated?
>>
>> "Dirty" means this cache is changed by CPU but not has not been written
>> into memory or WB. If we invalidate it, data will lost. In most cases, I
>> do not see a situation why the dirty data shall not be written into
>> memory.
>
> The problem is the cases that fall outside of 'most'. This kind of issue
> tends to have effects that, when unwanted, are extremely difficult to
> link to their cause and makes for long and painful debugging.
Well, "most" here may be a little bit confusing. Assuming a
write-through cache, how can you write data to memory and then regret? I
think you have to undo explicitly.
How about keeping cleaning the cache when mis-aligned happens and print
a WARNING?
BR,
Eric
>> BR,
>> Eric
>
> Amicalement,
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Re: [U-Boot] [PATCH v2] ARM926ejs: Add routines to invalidate D-Cache
Hi Albert,
On 08/05/2011 02:13 PM, Albert ARIBAUD wrote:
> Hi Hong Xu,
>
> Le 05/08/2011 06:44, Hong Xu a écrit :
>> After DMA operation, we need to maintain D-Cache coherency.
>> We need to clean cache (write back the dirty lines) and then
>> make the cache invalidate as well(hence CPU will fetch data
>> written by DMA controller from RAM).
>>
>> Tested on AT91SAM9261EK with Peripheral DMA controller.
>>
>> Signed-off-by: Hong Xu
>> Tested-by: Elen Song
>> CC: Albert Aribaud
>> CC: Heiko Schocher
[...]
>> +
>> +#ifdef CONFIG_SYS_CACHELINE_SIZE
>> + cache_line_len = CONFIG_SYS_CACHELINE_SIZE;
>> +#else
>> + cache_line_len = 32;
>
> Document magic number 32 -- for instance, indicate ARM architecture spec
> paragraph reference in a comment above it (and possibly emit a
> compile-time and/or run-time warning) -- or bail out with a compile
> error if CONFIG_SYS_CACHELINE_SIZE is not defined.
ARM926EJ-S Technical Reference Manual (r0p4/r0p5) only defines one cache
line size, "32". From my understanding, the standard ARM926EJ-S
implementation shall use 32 bytes cache line size. Of course this can be
overwritten by CONFIG_SYS_CACHELINE_SIZE, but shall we force to define it?
Frankly I have not found a proper place to define this(aka. not using 32
here), for example as a Macro.
>
>> +#endif
>> + /*
>> + * If start and stop are not aligned to cache-line,
>> + * the adjacent lines will be cleaned
>> + */
>> + if ((start& (cache_line_len - 1)) != 0)
>> + asm("mcr p15, 0, %0, c7, c10, 1" : : "r" (start));
>> + if ((stop& (cache_line_len - 1)) != 0)
>> + asm("mcr p15, 0, %0, c7, c10, 1" : : "r" (stop));
>> +
>> + mva = start& ~(cache_line_len - 1);
>> + while (mva< stop) {
>> + asm("mcr p15, 0, %0, c7, c6, 1" : : "r"(mva));
>> + mva += cache_line_len;
>> + }
>
> I, like Reinhard, prefer aligning start and stop and then looping
> through a single invalidate mcr.
>
> But I also want to make sure logs tell us anything weird with caches,
> and since unaligned start or stop invalidation could lead to trashing
> third party data, I would like the code to emit a run-time warning if
> that happens, like this:
>
> if ((start& (cache_line_len - 1)) != 0) {
> printf("WARNING: aligning start %x on start of cache line\n",
> start);
> start &= ~(cache_line_len - 1);
> }
> if ((stop& (cache_line_len - 1)) != (cache_line_len -1) ) {
> printf("WARNING: aligning stop %x on end of cache line\n",
> stop);
> start |= (cache_line_len - 1);
> }
I've tried to deal with the case that the (start, stop) is not aligned.
If mis-align happens, the adjacent lines will be cleaned before
invalidating. And from my view it's impossible for a driver to always
pass aligned address to invalidate_dcache_range.
To answer your question in another email
> How do you know the dirty data should be flushed rather than
invalidated?
"Dirty" means this cache is changed by CPU but not has not been written
into memory or WB. If we invalidate it, data will lost. In most cases, I
do not see a situation why the dirty data shall not be written into memory.
BR,
Eric
>
[...]
> Amicalement,
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Re: [U-Boot] [PATCH v2] ARM926ejs: Add routines to invalidate D-Cache
H Reinhard,
On 08/05/2011 01:11 PM, Reinhard Meyer wrote:
> Dear Hong Xu,
>> After DMA operation, we need to maintain D-Cache coherency.
>> We need to clean cache (write back the dirty lines) and then
>> make the cache invalidate as well(hence CPU will fetch data
>> written by DMA controller from RAM).
>>
>> Tested on AT91SAM9261EK with Peripheral DMA controller.
>>
>> Signed-off-by: Hong Xu
>> Tested-by: Elen Song
>> CC: Albert Aribaud
>> CC: Heiko Schocher
>> ---
>> Changes since v1
>> ~ Per Albert's suggestion, add invalidate_dcache_range originally defined
>> in include/common.h
>>
>> arch/arm/lib/cache.c | 46 ++
>> 1 files changed, 46 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
>> index 92b61a2..0436443 100644
>> --- a/arch/arm/lib/cache.c
>> +++ b/arch/arm/lib/cache.c
>> @@ -53,3 +53,49 @@ void __flush_dcache_all(void)
>> }
>> void flush_dcache_all(void)
>> __attribute__((weak, alias("__flush_dcache_all")));
>> +
>> +void __invalidate_dcache_range(unsigned long start, unsigned long stop)
>> +{
>> + int cache_line_len;
>> + unsigned long mva;
>> +
>> +#ifdef CONFIG_ARM926EJS
>> +
>> +#ifdef CONFIG_SYS_CACHELINE_SIZE
>> + cache_line_len = CONFIG_SYS_CACHELINE_SIZE;
>> +#else
>> + cache_line_len = 32;
>> +#endif
>> + /*
>> + * If start and stop are not aligned to cache-line,
>> + * the adjacent lines will be cleaned
>> + */
>> + if ((start& (cache_line_len - 1)) != 0)
>> + asm("mcr p15, 0, %0, c7, c10, 1" : : "r" (start));
>> + if ((stop& (cache_line_len - 1)) != 0)
>> + asm("mcr p15, 0, %0, c7, c10, 1" : : "r" (stop));
>
> Why so complicated?
In case of mis-aligned (start, stop), this is to clean the cache line,
aka. write back the potential dirty lines before successive invalidating
BR,
Eric
> How about:
> /* round down to the start of the cache line */
> start &= (cache_line_len - 1);
> /* round up to the end of the cache line */
> note: if, what I assume, the range to be invalidated is
> [start, stop) - that means stop is the first address not to be
> invalidated, the next statement is not necessary
> stop |= (cache_line_len - 1);
> while (start < stop) {
> asm("mcr p15, 0, %0, c7, c6, 1" : : "r"(start));
> start += cache_line_len;
> }
> /* Drain the WB */
> asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
>> +#endif
>
> Best Regards,
> Reinhard
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[U-Boot] [PATCH v2] ARM926ejs: Add routines to invalidate D-Cache
After DMA operation, we need to maintain D-Cache coherency.
We need to clean cache (write back the dirty lines) and then
make the cache invalidate as well(hence CPU will fetch data
written by DMA controller from RAM).
Tested on AT91SAM9261EK with Peripheral DMA controller.
Signed-off-by: Hong Xu
Tested-by: Elen Song
CC: Albert Aribaud
CC: Heiko Schocher
---
Changes since v1
~ Per Albert's suggestion, add invalidate_dcache_range originally defined
in include/common.h
arch/arm/lib/cache.c | 46 ++
1 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 92b61a2..0436443 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -53,3 +53,49 @@ void __flush_dcache_all(void)
}
void flush_dcache_all(void)
__attribute__((weak, alias("__flush_dcache_all")));
+
+void __invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ int cache_line_len;
+ unsigned long mva;
+
+#ifdef CONFIG_ARM926EJS
+
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+ cache_line_len = CONFIG_SYS_CACHELINE_SIZE;
+#else
+ cache_line_len = 32;
+#endif
+ /*
+* If start and stop are not aligned to cache-line,
+* the adjacent lines will be cleaned
+*/
+ if ((start & (cache_line_len - 1)) != 0)
+ asm("mcr p15, 0, %0, c7, c10, 1" : : "r" (start));
+ if ((stop & (cache_line_len - 1)) != 0)
+ asm("mcr p15, 0, %0, c7, c10, 1" : : "r" (stop));
+
+ mva = start & ~(cache_line_len - 1);
+ while (mva < stop) {
+ asm("mcr p15, 0, %0, c7, c6, 1" : : "r"(mva));
+ mva += cache_line_len;
+ }
+
+ /* Drain the WB */
+ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+#endif
+
+ return;
+}
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+ __attribute__((weak, alias("__invalidate_dcache_range")));
+
+void __invalidate_dcache_all(void)
+{
+#ifdef CONFIG_ARM926EJS
+ asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+#endif
+ return;
+}
+void invalidate_dcache_all(void)
+ __attribute__((weak, alias("__invalidate_dcache_all")));
--
1.7.3.3
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[U-Boot] [PATCH] ARM926ejs: Add routines to invalidate D-Cache
After DMA transfer, we need to maintain D-Cache coherency.
We need to clean cache (write back the dirty lines) and then
make the cache invalidate as well(hence CPU will fetch data
written by DMA controller from RAM).
Tested on AT91SAM9261EK with Peripheral DMA controller.
Signed-off-by: Hong Xu
Tested-by: Elen Song
CC: Heiko Schocher
CC: Albert Aribaud
---
arch/arm/lib/cache.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 92b61a2..216bde0 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -53,3 +53,13 @@ void __flush_dcache_all(void)
}
void flush_dcache_all(void)
__attribute__((weak, alias("__flush_dcache_all")));
+
+void __invalidate_dcache_all(void)
+{
+#ifdef CONFIG_ARM926EJS
+ asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+#endif
+ return;
+}
+void invalidate_dcache_all(void)
+ __attribute__((weak, alias("__invalidate_dcache_all")));
--
1.7.3.3
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Re: [U-Boot] [PATCH] AT91: Defer Dataflash access to env_relocate_spec
Hi Reinhard, On 08/03/2011 03:20 PM, Reinhard Meyer wrote: > Dear Hong Xu, > > When env_init is called, the SPI is not actually initialized in U-Boot. > > So that we can not read Dataflash for its content. > > We simply mark it OK for now, and defer the real work to > > `env_relocate_spec'. (Idealy from env_nand.c) > > > > Signed-off-by: Hong Xu > > --- > > common/env_dataflash.c | 83 > ++-- > > 1 files changed, 45 insertions(+), 38 deletions(-) > > I cannot really decide if that is a good approach. Where would be > the issue if SPI/dataflash were initialized at this point (before > relocation)? Currently the SPI is initialized in board_init which is called in board_init_r, but env_init is called in board_init_f. So actually the original code needs the SPI to be initialized before env_init, not before relocation. An alternative way is to put SPI initialization code in board_early_init_f. But I'm not sure if it's the correct way. BR, Eric > Same works well for example for I2C. > > If Wolfgang is OK with it, I can pick up this patch (once > it is agreed on the way to solve the issue). > > Best Regards, > Reinhard > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] AT91: Defer Dataflash access to env_relocate_spec
When env_init is called, the SPI is not actually initialized in U-Boot.
So that we can not read Dataflash for its content.
We simply mark it OK for now, and defer the real work to
`env_relocate_spec'. (Idealy from env_nand.c)
Signed-off-by: Hong Xu
---
common/env_dataflash.c | 83 ++--
1 files changed, 45 insertions(+), 38 deletions(-)
diff --git a/common/env_dataflash.c b/common/env_dataflash.c
index 1d57079..55534a5 100644
--- a/common/env_dataflash.c
+++ b/common/env_dataflash.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -50,11 +51,46 @@ uchar env_get_char_spec(int index)
void env_relocate_spec(void)
{
- char buf[CONFIG_ENV_SIZE];
+ ulong old_crc, new_crc = 0;
+ char *buf;
- read_dataflash(CONFIG_ENV_ADDR, CONFIG_ENV_SIZE, buf);
+ gd->env_valid = 0;
- env_import(buf, 1);
+ buf = (char *)malloc(CONFIG_ENV_SIZE);
+ if (buf == NULL) {
+ error("Can not allocate memory for env.\n");
+ goto err_mem;
+ }
+
+ AT91F_DataflashInit();
+
+ if (read_dataflash(CONFIG_ENV_ADDR + offsetof(env_t, crc),
+ sizeof(ulong), (char *)&old_crc) != DATAFLASH_OK) {
+ error("Dataflash: Failed to read original 4-bytes CRC\n");
+ goto err;
+ }
+
+ if (read_dataflash(CONFIG_ENV_ADDR + offsetof(env_t, data),
+ ENV_SIZE, buf) != DATAFLASH_OK) {
+ error("Dataflash: Failed to read env string.\n");
+ goto err;
+ }
+
+ new_crc = crc32(new_crc, (uchar *)buf, ENV_SIZE);
+
+ if (old_crc == new_crc) {
+ gd->env_addr = offsetof(env_t, data);
+ gd->env_valid = 1;
+ env_import(buf, 0);
+ goto out;
+ }
+
+err:
+ set_default_env("!bad CRC");
+out:
+ free(buf);
+err_mem:
+ return;
}
#ifdef CONFIG_ENV_OFFSET_REDUND
@@ -83,44 +119,15 @@ int saveenv(void)
/*
* Initialize environment use
*
- * We are still running from ROM, so data use is limited.
- * Use a (moderately small) buffer on the stack
+ * When env_init is called, the SPI is not actually initialized in U-Boot.
+ * So that we can not read Dataflash for its content.
+ * We simply mark it OK for now, and defer the real work to
+ * `env_relocate_spec'. (Idealy from env_nand.c)
*/
int env_init(void)
{
- ulong crc, len, new;
- unsigned off;
- uchar buf[64];
-
- if (gd->env_valid)
- return 0;
-
- AT91F_DataflashInit(); /* prepare for DATAFLASH read/write */
-
- /* read old CRC */
- read_dataflash(CONFIG_ENV_ADDR + offsetof(env_t, crc),
- sizeof(ulong), (char *)&crc);
-
- new = 0;
- len = ENV_SIZE;
- off = offsetof(env_t,data);
- while (len > 0) {
- int n = (len > sizeof(buf)) ? sizeof(buf) : len;
-
- read_dataflash(CONFIG_ENV_ADDR + off, n, (char *)buf);
-
- new = crc32 (new, buf, n);
- len -= n;
- off += n;
- }
-
- if (crc == new) {
- gd->env_addr = offsetof(env_t,data);
- gd->env_valid = 1;
- } else {
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = 0;
- }
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 1;
return 0;
}
--
1.7.3.3
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Re: [U-Boot] [STATUS] AT91: boards still broken on 02.Aug.2011
Hi Reinhard & Thomas, On 08/02/2011 09:36 PM, Reinhard Meyer wrote: > Dear Thomas Petazzoni, > > Le Tue, 02 Aug 2011 12:37:41 +, > > Reinhard Meyer a écrit : > > > > > Configuring for at91sam9m10g45ek board... > > > > For this board there are patches from Alex Waterman, sent on June, > > 30th. They fix the compilation, and they mostly work (there is an issue > > with the Ethernet device, though). > > > > Since Alex hasn't posted an updated version of his patch set since one > > month, should I take his patch set, fix the comments you made at that > > time and send an updated version ? > > > > (I have the AT91SAM9M10G45-EK platform on my desk here). > Unless Atmel NAKs this approach, I am fine with it. We're OK with this. If Thomas can fix soon, that's good. Or we'll take over and send out the fixes for Soc and board part. BR, Eric > Please re-base them on current u-boot-atmel/master and provide two > independent patches: > 1. for the SoC parts > 2. for the board itself > > Thanks, > Reinhard > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3] AT91: Small fix on AT91 USART initialization code
Before reset dbgu transmitter, we just wait TXEMPTY to drain the
transmitter register(Just in case). If not doing this, we may sometimes
see several weird characters from DBGU.
A short delay is also added to make sure the new serial settings are
settled.
Signed-off-by: Hong Xu
---
Changes since V2,
Using __udelay to avoid potential endless loop
drivers/serial/atmel_usart.c | 11 ++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index e326b2b..943ef70 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -49,17 +49,26 @@ int serial_init(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
+ /*
+* Just in case: drain transmitter register
+* 1000us is enough for baudrate >= 9600
+*/
+ if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
+ __udelay(1000);
+
writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
serial_setbrg();
- writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
| USART3_BF(USCLKS, USART3_USCLKS_MCK)
| USART3_BF(CHRL, USART3_CHRL_8)
| USART3_BF(PAR, USART3_PAR_NONE)
| USART3_BF(NBSTOP, USART3_NBSTOP_1)),
&usart->mr);
+ writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
+ /* 100us is enough for the new settings to be settled */
+ __udelay(100);
return 0;
}
--
1.7.3.3
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Re: [U-Boot] [PATCH V2] AT91: Small fix on AT91 USART initialization code
Hi Reinhard,
On 08/02/2011 05:54 PM, Reinhard Meyer wrote:
> Dear Hong Xu,
> > > > diff --git a/drivers/serial/atmel_usart.c
> b/drivers/serial/atmel_usart.c
> > > > index e326b2b..6f9c2de 100644
> > > > --- a/drivers/serial/atmel_usart.c
> > > > +++ b/drivers/serial/atmel_usart.c
> > > > @@ -49,17 +49,23 @@ int serial_init(void)
> > > > {
> > > > atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
> > > >
> > > > + /* Just in case: drain transmitter register */
> > > > + while (!(readl(&usart->csr)& USART3_BIT(TXEMPTY)))
> > > > + ;
> > > > +
> > >
> > > You still have not addressed my concern about a possible hang situation
> > > here!
> > > I rather have _some_ weird characters than an apparently dead board...
> > > When do we have the possibility of weird characters anyway?
> > > Only if a preloader makes output and transfers to u-boot before its
> output
> > > has been flushed. Any other situations?
> >
> > This is the main cause. I monitored some versions of bootstraps check
> > TXRDY before sending data to THR (Transmitter holding register). And for
> > the last character, they won't wait till the character has been sent
> > out. (And maybe there are similar places in U-Boot before calling
> > serial_init, I'm not sure)
>
> There should be no output made by u-boot BEFORE serial_init() is called!
>
> >
> > The possibility of hang, I don't think so. Reason,
> > TXEMPTY means "There are no characters in DBGU_THR and there are no
> > characters being processed by the transmitter."
>
> What if there is no Baud Clock?
> What if the USART is unconfigured or misconfigured?
>
> >
> > Theoretically this situation shall be met here. But of course a timeout
> > can be added defensively (chip goes mad? :)
> >
> > What's your opinion?
>
> Timeout is complicated at the pre-relocation level.
> What is MOST IMPORTANT at this point is that u-boot must made be able to
> print messages. Anything that could perhaps impair that should not be
> done.
> Keep the code simple and live with occasional weird characters.
> End users of a system will usually not look at the serial debug output.
> Or just use a __udelay(1000) - that should give time to drain any char
> at 9600 bit/s and above.
Agree. Actually I tried __udelay to overcome the weird character issue
firstly. And later found the TXEMPTY was not set when serial_init is
called. I'll send another patch soon (by using __udelay, simple but
useful enough :-).
Thanks
BR,
Eric
> Best Regards,
> Reinhard
>
>
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Re: [U-Boot] [PATCH V2] AT91: Small fix on AT91 USART initialization code
Hi Reinhard,
On 08/01/2011 10:39 PM, Reinhard Meyer wrote:
> Dear Hong Xu,
> > Before reset dbgu transmitter, we just wait TXEMPTY to drain the
> > transmitter register. If not doing this, we may sometimes see several
> > weird characters from DBGU.
> >
> > A short delay is also added to make sure the new serial settings are
> > settled.
> >
> > Signed-off-by: Hong Xu
> > ---
> > Change since V1:
> > - Fix comment for easy reading
> >
> > drivers/serial/atmel_usart.c | 8 +++-
> > 1 files changed, 7 insertions(+), 1 deletions(-)
> >
> > diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
> > index e326b2b..6f9c2de 100644
> > --- a/drivers/serial/atmel_usart.c
> > +++ b/drivers/serial/atmel_usart.c
> > @@ -49,17 +49,23 @@ int serial_init(void)
> > {
> > atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
> >
> > + /* Just in case: drain transmitter register */
> > + while (!(readl(&usart->csr)& USART3_BIT(TXEMPTY)))
> > + ;
> > +
>
> You still have not addressed my concern about a possible hang situation
> here!
> I rather have _some_ weird characters than an apparently dead board...
> When do we have the possibility of weird characters anyway?
> Only if a preloader makes output and transfers to u-boot before its output
> has been flushed. Any other situations?
This is the main cause. I monitored some versions of bootstraps check
TXRDY before sending data to THR (Transmitter holding register). And for
the last character, they won't wait till the character has been sent
out. (And maybe there are similar places in U-Boot before calling
serial_init, I'm not sure)
The possibility of hang, I don't think so. Reason,
TXEMPTY means "There are no characters in DBGU_THR and there are no
characters being processed by the transmitter."
Theoretically this situation shall be met here. But of course a timeout
can be added defensively (chip goes mad? :)
What's your opinion?
BR,
Eric
>
> Best Regards,
> Reinhard
>
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[U-Boot] [PATCH V2] AT91: Small fix on AT91 USART initialization code
Before reset dbgu transmitter, we just wait TXEMPTY to drain the
transmitter register. If not doing this, we may sometimes see several
weird characters from DBGU.
A short delay is also added to make sure the new serial settings are
settled.
Signed-off-by: Hong Xu
---
Change since V1:
- Fix comment for easy reading
drivers/serial/atmel_usart.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index e326b2b..6f9c2de 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -49,17 +49,23 @@ int serial_init(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
+ /* Just in case: drain transmitter register */
+ while (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
+ ;
+
writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
serial_setbrg();
- writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
| USART3_BF(USCLKS, USART3_USCLKS_MCK)
| USART3_BF(CHRL, USART3_CHRL_8)
| USART3_BF(PAR, USART3_PAR_NONE)
| USART3_BF(NBSTOP, USART3_NBSTOP_1)),
&usart->mr);
+ writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
+ /* 100us is enough for the new settings to be settled */
+ __udelay(100);
return 0;
}
--
1.7.3.3
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[U-Boot] [PATCH] AT91: Small fix on AT91 USART initialization code
Before reset dbgu transmitter, we just wait TXEMPTY to drain the
transmitter register. If not doing this, we may sometimes see several
weird characters from DBGU.
A short delay is also added to make sure the new serial settings are
settled.
Signed-off-by: Hong Xu
---
drivers/serial/atmel_usart.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index e326b2b..0d5d254 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -49,17 +49,23 @@ int serial_init(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
+ /* Just in case: drain transmitter register */
+ while (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
+ ;
+
writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
serial_setbrg();
- writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
| USART3_BF(USCLKS, USART3_USCLKS_MCK)
| USART3_BF(CHRL, USART3_CHRL_8)
| USART3_BF(PAR, USART3_PAR_NONE)
| USART3_BF(NBSTOP, USART3_NBSTOP_1)),
&usart->mr);
+ writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
+ /* __udelay(100) is enough for the new settings to be settled */
+ __udelay(100);
return 0;
}
--
1.7.3.3
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[U-Boot] [PATCH] AT91: Board fix for AT91SAM9261-EK
Fix board part of AT91SAM9261-EK according to the new scheme
Signed-off-by: Hong Xu
---
Makefile | 23 -
board/atmel/at91sam9261ek/at91sam9261ek.c | 136 +++--
board/atmel/at91sam9261ek/config.mk |1 -
board/atmel/at91sam9261ek/led.c |7 +-
boards.cfg|6 ++
include/configs/at91sam9261ek.h | 133 +++-
6 files changed, 154 insertions(+), 152 deletions(-)
delete mode 100644 board/atmel/at91sam9261ek/config.mk
diff --git a/Makefile b/Makefile
index e56fa02..cedb499 100644
--- a/Makefile
+++ b/Makefile
@@ -796,29 +796,6 @@ M5485HFE_config : unconfig
## ARM926EJ-S Systems
#
-at91sam9261ek_nandflash_config \
-at91sam9261ek_dataflash_cs0_config \
-at91sam9261ek_dataflash_cs3_config \
-at91sam9261ek_config \
-at91sam9g10ek_nandflash_config \
-at91sam9g10ek_dataflash_cs0_config \
-at91sam9g10ek_dataflash_cs3_config \
-at91sam9g10ek_config : unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring 9g10,$@)" ] ; then \
- echo "#define CONFIG_AT91SAM9G10EK 1"
>>$(obj)include/config.h ; \
- else \
- echo "#define CONFIG_AT91SAM9261EK 1"
>>$(obj)include/config.h ; \
- fi;
- @if [ "$(findstring _nandflash,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_NANDFLASH 1"
>>$(obj)include/config.h ; \
- elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_DATAFLASH_CS3 1"
>>$(obj)include/config.h ; \
- else \
- echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1"
>>$(obj)include/config.h ; \
- fi;
- @$(MKCONFIG) -n $@ -a at91sam9261ek arm arm926ejs at91sam9261ek atmel
at91
-
at91sam9263ek_norflash_config \
at91sam9263ek_norflash_boot_config \
at91sam9263ek_nandflash_config \
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c
b/board/atmel/at91sam9261ek/at91sam9261ek.c
index de5cfae..b6c7d9e 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -23,6 +23,7 @@
*/
#include
+#include
#include
#include
#include
@@ -31,7 +32,6 @@
#include
#include
#include
-#include
#include
#include
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
@@ -49,44 +49,48 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_CMD_NAND
static void at91sam9261ek_nand_hw_init(void)
{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
unsigned long csa;
/* Enable CS3 */
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA,
- csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+
+ writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
#ifdef CONFIG_AT91SAM9G10EK
- at91_sys_write(AT91_SMC_SETUP(3),
- AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3),
- AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(7) |
- AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(7));
- at91_sys_write(AT91_SMC_CYCLE(3),
- AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+ &smc->cs[3].cycle);
#else
- at91_sys_write(AT91_SMC_SETUP(3),
- AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3),
- AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
- AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
- at91_sys_write(AT91_SMC_CYCLE(3),
- AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91
[U-Boot] [PATCH] AT91: SoC fix at91sam9261_matrix.h
Fix at91sam9261_matrix.h according to the new scheme.
Signed-off-by: Hong Xu
---
.../arm/include/asm/arch-at91/at91sam9261_matrix.h | 77 +---
1 files changed, 36 insertions(+), 41 deletions(-)
diff --git a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h
b/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h
index e2bfc4b..913b4d7 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h
@@ -15,50 +15,45 @@
#ifndef AT91SAM9261_MATRIX_H
#define AT91SAM9261_MATRIX_H
-#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00)/* Master Configuration
Register */
-#defineAT91_MATRIX_RCB0(1 << 0)/*
Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#defineAT91_MATRIX_RCB1(1 << 1)/*
Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#ifndef __ASSEMBLY__
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04)/* Slave Configuration
Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08)/* Slave Configuration
Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C)/* Slave Configuration
Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10)/* Slave Configuration
Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14)/* Slave Configuration
Register 4 */
-#defineAT91_MATRIX_SLOT_CYCLE (0xff << 0) /*
Maximum Number of Allowed Cycles for a Burst */
-#defineAT91_MATRIX_DEFMSTR_TYPE(3<< 16)/*
Default Master Type */
-#defineAT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#defineAT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#defineAT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#defineAT91_MATRIX_FIXED_DEFMSTR (7<< 18)/*
Fixed Index of Default Master */
+struct at91_matrix {
+ u32 mcfg; /* Master Configuration Registers */
+ u32 scfg[5];/* Slave Configuration Registers */
+ u32 filler[6];
+ u32 ebicsa; /* EBI Chip Select Assignment Register */
+};
+#endif /* __ASSEMBLY__ */
-#define AT91_MATRIX_TCR(AT91_MATRIX + 0x24)/* TCM
Configuration Register */
-#defineAT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size
of ITCM enabled memory block */
-#defineAT91_MATRIX_ITCM_0 (0 << 0)
-#defineAT91_MATRIX_ITCM_16 (5 << 0)
-#defineAT91_MATRIX_ITCM_32 (6 << 0)
-#defineAT91_MATRIX_ITCM_64 (7 << 0)
-#defineAT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size
of DTCM enabled memory block */
-#defineAT91_MATRIX_DTCM_0 (0 << 4)
-#defineAT91_MATRIX_DTCM_16 (5 << 4)
-#defineAT91_MATRIX_DTCM_32 (6 << 4)
-#defineAT91_MATRIX_DTCM_64 (7 << 4)
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN(4 << 0)
-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30)/* EBI Chip Select
Assignment Register */
-#defineAT91_MATRIX_CS1A(1 << 1)/* Chip
Select 1 Assignment */
-#defineAT91_MATRIX_CS1A_SMC(0 << 1)
-#defineAT91_MATRIX_CS1A_SDRAMC (1 << 1)
-#defineAT91_MATRIX_CS3A(1 << 3)/* Chip
Select 3 Assignment */
-#defineAT91_MATRIX_CS3A_SMC(0 << 3)
-#defineAT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#defineAT91_MATRIX_CS4A(1 << 4)/* Chip
Select 4 Assignment */
-#defineAT91_MATRIX_CS4A_SMC(0 << 4)
-#defineAT91_MATRIX_CS4A_SMC_CF1(1 << 4)
-#defineAT91_MATRIX_CS5A(1 << 5)/* Chip
Select 5 Assignment */
-#defineAT91_MATRIX_CS5A_SMC(0 << 5)
-#defineAT91_MATRIX_CS5A_SMC_CF2(1 << 5)
-#defineAT91_MATRIX_DBPUC (1 << 8)/* Data
Bus Pull-up Configuration */
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_D
Re: [U-Boot] [PATCH 1/2 V3] AT91: Makes AT91SAM9RL SoC build correctly against u-boot-atmel/master
Hi Reinhard,
On 08/01/2011 04:00 PM, Reinhard Meyer wrote:
> Dear Hong Xu,
> > Rework for AT91SAM9RL SoC, makes it build again.
> > arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h | 121 +-
>
> When I compare at91sam9rl_matrix.h to at91sam9260_matrix.h there is only
> one subtle difference:
>
> at91sam9260_matrix.h:
>
> struct at91_matrix {
> u32 mcfg[16]; /* Master Configuration Registers */
> u32 scfg[16]; /* Slave Configuration Registers */
> u32 pras[16][2]; /* Priority Assignment Slave Registers */
> u32 mrcr; /* Master Remap Control Register */
> u32 filler[0x06];
> u32 ebicsa; /* EBI Chip Select Assignment Register */
>
> at91sam9rl_matrix.h:
>
> struct at91_matrix {
> u32 mcfg[16]; /* Master Configuration Registers */
> u32 scfg[16]; /* Slave Configuration Registers */
> u32 pras[16][2]; /* Priority Assignment Slave Registers */
> u32 mrcr; /* Master Remap Control Register */
> u32 filler[7];
> u32 ebicsa; /* EBI Chip Select Assignment Register */
> };
>
> 1. Is it really filler[7] for the 9rl - can you verify with the data
> sheet?
Confirmed. ebicsa is at 0x120 for SAM9RL, but 0x11c for SAM9260.
> 2. It seems there is a possibility to unify all those _matrix files into
> one in the future (we are not going to do this now!) ?
There are many differents among chips. For example, on SAM9260/SAM9G10
struct at91_matrix {
u32 mcfg; /* Master Configuration Registers */
u32 scfg[5];/* Slave Configuration Registers */
u32 filler[6];
u32 ebicsa; /* EBI Chip Select Assignment Register */
};
And for newer chips, some new fields are added. Can we keep current
scheme and then have a look to see whether we have an elegant way to
handle this? BTW, we're going to add some new chips soon.
Thanks.
BR,
Eric
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Re: [U-Boot] AT91: rework and fixes
Hi Reinhard, On 07/26/2011 08:59 PM, Reinhard Meyer wrote: > Dear Hong Xu, > > Hi Albert, > > > > On 07/18/2011 02:39 PM, Albert ARIBAUD wrote: > > > Hi Eric, > > > > > > Le 18/07/2011 04:52, Hong Xu a écrit : > > > > Hi Reinhard, > > > > > > > > It's a pity to see that some of the AT91 boards are planed to be > removed > > > > by Wolfgang. > > > > > > > > Several weeks ago, the patches for SAM9261/9G10 have got Acks > from you. > > > > See http://www.mail-archive.com/u-boot@lists.denx.de/msg54829.html > > > > But I don't know why it's not merged upstream. > > Now, an actual at91sam9261_devices.c and at91sam9261.h are on top of > u-boot-atmel/master. > If your board patches for az91sam9261-ek still work with that, I can > apply them again to master. OK, I'll check and resend the board fix. > > > > > > > > > For SAM9RL, the V3 patches have been sent long time ago and was > pinged. > > > > But no response any longer. > > I have changes requested there. You mean the change requests for V3 patches? I never saw them. Is it a general comments towards AT91 or specific to V3 patches? But anyway, I'd like to send the patches again in the coming days. > > > > > > > > > The similar stories are also applied for SAM9263 and SAM9M10G45. > > Changes requested as well. Ditto. [...] > > Anyway, for work reasons, there will be no extended vacation this > summer :( Sorry to hear this. > Again, the work flow, as I want it followed, is as such: > > 1. convert/fix all SoC specific files for 9263 9g45 etc. to be in line > and equivalent to the now existing files for 9260 and 9261. > (Next should be for 9263, we should be looking at existing patches to > fix that SoC). > I will NOT accept patches that do not fully implement the name schemes > laid out in 9260 and 9261. > > 2. Fix any boards to use those files AND to use relocation properly. > > 3. Make sure those build without warning or errors. > > 4. Make sure those boards still "boot" with that u-boot. > > 5. When a board has passed those tests (I cannot test point 4) the > "removal" patch for that board will not be applied. OK, the SoC fixes for 9263 and 9G45 will come firstly. Thanks. BR, Eric > Best Regards, > Reinhard > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 47/52] ARM: remove broken "at91sam9261ek" /"at91sam9g10ek" boards
Hi Albert, On 07/18/2011 02:39 PM, Albert ARIBAUD wrote: > Hi Eric, > > Le 18/07/2011 04:52, Hong Xu a écrit : > > Hi Reinhard, > > > > It's a pity to see that some of the AT91 boards are planed to be removed > > by Wolfgang. > > > > Several weeks ago, the patches for SAM9261/9G10 have got Acks from you. > > See http://www.mail-archive.com/u-boot@lists.denx.de/msg54829.html > > But I don't know why it's not merged upstream. > > > > For SAM9RL, the V3 patches have been sent long time ago and was pinged. > > But no response any longer. > > > > The similar stories are also applied for SAM9263 and SAM9M10G45. > > > > We of course need the mainline support for all SAM9 boards in U-Boot. > > But it's the time we need your plans/suggestions/NAKs/ACKs to move on. > > > > Thanks. > > Note: I'll naturally defer the decision of what to make with the AT91 > boards to Reinhard, and likewise to other ARM custodians for boards the > architecture of which falls under their 'jurisdiction'. Understand. But it looks like Reinhard has bunch of paid work at hand and he has his vocation in the near future (He mentioned this in an email towards Wolfgang's [U-Boot] [PATCH 00/52] ARM: remove broken boards). We noticed that there are several AT91 fixes in the mailing list without any response. As a suggestion, how about we setup a git branch and collect AT91 related patches during Reinhard's busy time and vocation time? If yes, can we ask for `pull request' from you? Thanks. BR, Eric ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 47/52] ARM: remove broken "at91sam9261ek" /"at91sam9g10ek" boards
Hi Reinhard, It's a pity to see that some of the AT91 boards are planed to be removed by Wolfgang. Several weeks ago, the patches for SAM9261/9G10 have got Acks from you. See http://www.mail-archive.com/u-boot@lists.denx.de/msg54829.html But I don't know why it's not merged upstream. For SAM9RL, the V3 patches have been sent long time ago and was pinged. But no response any longer. The similar stories are also applied for SAM9263 and SAM9M10G45. We of course need the mainline support for all SAM9 boards in U-Boot. But it's the time we need your plans/suggestions/NAKs/ACKs to move on. Thanks. BR, Eric On 07/18/2011 06:17 AM, Wolfgang Denk wrote: > Signed-off-by: Wolfgang Denk > Cc: Stelian Pop > Cc: Sedji Gaouaou > --- > MAINTAINERS | 2 - > MAKEALL | 2 - > Makefile | 23 --- > board/atmel/at91sam9261ek/Makefile | 56 -- > board/atmel/at91sam9261ek/at91sam9261ek.c | 292 > - > board/atmel/at91sam9261ek/config.mk | 1 - > board/atmel/at91sam9261ek/led.c | 43 - > board/atmel/at91sam9261ek/partition.c | 40 > doc/README.scrapyard | 2 + > include/configs/at91sam9261ek.h | 240 --- > 10 files changed, 2 insertions(+), 699 deletions(-) > delete mode 100644 board/atmel/at91sam9261ek/Makefile > delete mode 100644 board/atmel/at91sam9261ek/at91sam9261ek.c > delete mode 100644 board/atmel/at91sam9261ek/config.mk > delete mode 100644 board/atmel/at91sam9261ek/led.c > delete mode 100644 board/atmel/at91sam9261ek/partition.c > delete mode 100644 include/configs/at91sam9261ek.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index 9f36643..da3202f 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -630,7 +630,6 @@ Daniel Gorsulowski > otc570 ARM926EJS (AT91SAM9263 SoC) > > Sedji Gaouaou > - at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC) > at91sam9m10g45ek ARM926EJS (AT91SAM9G45 SoC) > > Simon Guinot > @@ -743,7 +742,6 @@ Manikandan Pillai > Stelian Pop > > at91sam9260ek ARM926EJS (AT91SAM9260 SoC) > - at91sam9261ek ARM926EJS (AT91SAM9261 SoC) > at91sam9263ek ARM926EJS (AT91SAM9263 SoC) > at91sam9rlek ARM926EJS (AT91SAM9RL SoC) > [...] ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2 V3] AT91: Makes AT91SAM9RL SoC build correctly against u-boot-atmel/master
Hi Wolfgang, On 06/22/2011 05:03 PM, Wolfgang Denk wrote: > Dear Hong Xu, > > In message <4e01a429.8000...@atmel.com> you wrote: > > ping ... > > > > On 06/15/2011 11:11 AM, Hong Xu wrote: > > > Rework for AT91SAM9RL SoC, makes it build again. > > > Based on the work for AT91SAM9260-EK. > > Is ther e_any_ need to quote 500+ lines of patch just for such a ping? > > Please stick to basic netiquette rules. > > See http://www.netmeister.org/news/learn2quote.html > > And never ever top post / full quote. Thanks for your reminding. BR > Thanks. > > > Wolfgang Denk > > -- > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de > I thought my people would grow tired of killing. But you were right, > they see it is easier than trading. And it has its pleasures. I feel > it myself. Like the hunt, but with richer rewards. > -- Apella, "A Private Little War", stardate 4211.8 > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] [V2] AT91: Makes AT91SAM9263 SoC build correctly against u-boot-atmel/master
ping ...
On 06/15/2011 12:51 PM, Hong Xu wrote:
> Hi Reinhard,
>
> On 06/14/2011 08:43 PM, Reinhard Meyer wrote:
> > Dear Hong Xu,
> > > Rework for AT91SAM9263 SoC, makes it build again.
> > > Based on the work for AT91SAM9260-EK.
> > >
> > > Signed-off-by: Hong Xu
> > > ---
> > > arch/arm/cpu/arm926ejs/at91/lowlevel_init.S | 2 +-
> > > arch/arm/cpu/arm926ejs/at91/timer.c | 13 ++
> > > arch/arm/include/asm/arch-at91/at91_spi.h | 2 +-
> > > arch/arm/include/asm/arch-at91/at91sam9263.h | 13 ++
> > > .../arm/include/asm/arch-at91/at91sam9263_matrix.h | 146
> > ++--
> > > arch/arm/include/asm/arch-at91/at91sam9_sdramc.h | 2 +-
> > > 6 files changed, 71 insertions(+), 107 deletions(-)
> > >
> > > diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c
> > b/arch/arm/cpu/arm926ejs/at91/timer.c
> > > index a087687..89a01ea 100644
> > > --- a/arch/arm/cpu/arm926ejs/at91/timer.c
> > > +++ b/arch/arm/cpu/arm926ejs/at91/timer.c
> > > @@ -134,3 +134,16 @@ ulong get_tbclk(void)
> > > {
> > > return gd->timer_rate_hz;
> > > }
> > > +
> > > +/*
> > > + * Reset the timer.
> > > + */
> > > +void reset_timer(void)
> > > +{
> > > + /* TODO: write this code. */
> > > +}
> > > +
> > > +void reset_timer_masked(void)
> > > +{
> > > + /* TODO: write this code. */
> > > +}
> >
> > NAK. Those functions were intentionally removed from at91/timer.c
> > quite a while ago.
> > If some other code requires them, it must be fixed there.
> > See also the discussion of the "new timer API" made recently.
> >
> > Applied (without at91/timer.c changes) to u-boot-atmel/master.
>
> Thanks for merging the AT91SAM9263 SoC part. What about [PATCH 2/2] [V2]
> AT91: Makes AT91SAM9263-EK build correctly against u-boot-atmel/master ?
>
> BR,
> Hong
>
> > Best Regards,
> > Reinhard
> >
>
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Re: [U-Boot] [PATCH 2/2 V3] AT91: Makes AT91SAM9RL-EK build correctly against u-boot-atmel/master
ping ...
On 06/15/2011 11:11 AM, Hong Xu wrote:
> Rework for AT91SAM9RL-EK, makes it build again.
> Based on the work for AT91SAM9260-EK.
>
> Signed-off-by: Hong Xu
> ---
> Makefile | 12
> board/atmel/at91sam9rlek/at91sam9rlek.c | 73 --
> board/atmel/at91sam9rlek/config.mk | 1 -
> board/atmel/at91sam9rlek/led.c | 6 ++-
> boards.cfg | 3 +
> include/configs/at91sam9rlek.h | 85 +-
> 6 files changed, 100 insertions(+), 80 deletions(-)
> delete mode 100644 board/atmel/at91sam9rlek/config.mk
>
> diff --git a/Makefile b/Makefile
> index cd328b3..4e19fed 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -785,18 +785,6 @@ at91sam9263ek_config : unconfig
> fi;
> @$(MKCONFIG) -n $@ -a at91sam9263ek arm arm926ejs at91sam9263ek atmel at91
>
> -at91sam9rlek_nandflash_config \
> -at91sam9rlek_dataflash_config \
> -at91sam9rlek_dataflash_cs0_config \
> -at91sam9rlek_config : unconfig
> - @mkdir -p $(obj)include
> - @if [ "$(findstring _nandflash,$@)" ] ; then \
> - echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
> - else \
> - echo "#define CONFIG_SYS_USE_DATAFLASH 1" >>$(obj)include/config.h ; \
> - fi;
> - @$(MKCONFIG) -n $@ -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
> -
> at91sam9m10g45ek_nandflash_config \
> at91sam9m10g45ek_dataflash_config \
> at91sam9m10g45ek_dataflash_cs0_config \
> diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c
> b/board/atmel/at91sam9rlek/at91sam9rlek.c
> index e374917..e559084 100644
> --- a/board/atmel/at91sam9rlek/at91sam9rlek.c
> +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
> @@ -23,6 +23,7 @@
> */
>
> #include
> +#include
> #include
> #include
> #include
> @@ -31,7 +32,7 @@
> #include
> #include
> #include
> -#include
> +
> #include
> #include
> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
> @@ -48,33 +49,37 @@ DECLARE_GLOBAL_DATA_PTR;
> #ifdef CONFIG_CMD_NAND
> static void at91sam9rlek_nand_hw_init(void)
> {
> + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
> + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
> + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> unsigned long csa;
>
> /* Enable CS3 */
> - csa = at91_sys_read(AT91_MATRIX_EBICSA);
> - at91_sys_write(AT91_MATRIX_EBICSA,
> - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
> + csa = readl(&matrix->ebicsa);
> + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
> +
> + writel(csa, &matrix->ebicsa);
>
> /* Configure SMC CS3 for NAND/SmartMedia */
> - at91_sys_write(AT91_SMC_SETUP(3),
> - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
> - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
> - at91_sys_write(AT91_SMC_PULSE(3),
> - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
> - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
> - at91_sys_write(AT91_SMC_CYCLE(3),
> - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
> - at91_sys_write(AT91_SMC_MODE(3),
> - AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
> - AT91_SMC_EXNWMODE_DISABLE |
> + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
> + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
> + &smc->cs[3].setup);
> + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
> + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
> + &smc->cs[3].pulse);
> + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
> + &smc->cs[3].cycle);
> + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
> + AT91_SMC_MODE_EXNW_DISABLE |
> #ifdef CONFIG_SYS_NAND_DBW_16
> - AT91_SMC_DBW_16 |
> + AT91_SMC_MODE_DBW_16 |
> #else /* CONFIG_SYS_NAND_DBW_8 */
> - AT91_SMC_DBW_8 |
> + AT91_SMC_MODE_DBW_8 |
> #endif
> - AT91_SMC_TDF_(2));
> + AT91_SMC_MODE_TDF_CYCLE(2),
> + &smc->cs[3].mode);
>
> - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
> + writel(1 << ATMEL_ID_PIOD, &pmc->pcer);
>
> /* Configure RDY/BSY */
> at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
> @@ -102,7 +107,7 @@ vidinfo_t panel_info = {
> vl_vsync_len: 1,
> vl_upper_margin:1,
> vl_lower_margin:0,
> - mmio: AT91SAM9RL_LCDC_BASE,
> + mmio: ATMEL_BASE_LCDC,
> };
>
> void lcd_enable(void)
> @@ -116,6 +121,8 @@ void lcd_disable(void)
> }
> static void at91sam9rlek_lcd_hw_init(void)
> {
> + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> +
> at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
> at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
> at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
> @@ -138,9 +145,7 @@ static void at91sam9rlek_lcd_h
Re: [U-Boot] [PATCH 1/2 V3] AT91: Makes AT91SAM9RL SoC build correctly against u-boot-atmel/master
ping ...
On 06/15/2011 11:11 AM, Hong Xu wrote:
> Rework for AT91SAM9RL SoC, makes it build again.
> Based on the work for AT91SAM9260-EK.
>
> Signed-off-by: Hong Xu
> ---
> Changes since V2
> - No at91_serial_hw_init, no CONFIG_USARTx anymore.
> - Removed SZ_* macros - though I don't have the reason found in code :)
> - Add definitions for all ATMEL_BASE_CSx
>
> Thanks!
>
> arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c | 45 ++
> arch/arm/include/asm/arch-at91/at91sam9rl.h | 177 ++--
> arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h | 121 +-
> 3 files changed, 141 insertions(+), 202 deletions(-)
>
> diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
> b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
> index 4f570f4..c2a6584 100644
> --- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
> +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
> @@ -23,77 +23,58 @@
> */
>
> #include
> +#include
> #include
> #include
> #include
> -#include
>
> void at91_serial0_hw_init(void)
> {
> - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
> + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
>
> at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */
> at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* RXD0 */
> - writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer);
> + writel(1 << ATMEL_ID_US0, &pmc->pcer);
> }
>
> void at91_serial1_hw_init(void)
> {
> - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
> + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
>
> at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */
> at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* RXD1 */
> - writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer);
> + writel(1 << ATMEL_ID_US1, &pmc->pcer);
> }
>
> void at91_serial2_hw_init(void)
> {
> - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
> + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
>
> at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */
> at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* RXD2 */
> - writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer);
> + writel(1 << ATMEL_ID_US2, &pmc->pcer);
> }
>
> -void at91_serial3_hw_init(void)
> +void at91_seriald_hw_init(void)
> {
> - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
> + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
>
> at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* DRXD */
> at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */
> - writel(1 << AT91_ID_SYS, &pmc->pcer);
> + writel(1 << ATMEL_ID_SYS, &pmc->pcer);
> }
>
> -void at91_serial_hw_init(void)
> -{
> -#ifdef CONFIG_USART0
> - at91_serial0_hw_init();
> -#endif
> -
> -#ifdef CONFIG_USART1
> - at91_serial1_hw_init();
> -#endif
> -
> -#ifdef CONFIG_USART2
> - at91_serial2_hw_init();
> -#endif
> -
> -#ifdef CONFIG_USART3 /* DBGU */
> - at91_serial3_hw_init();
> -#endif
> -}
> -
> -#ifdef CONFIG_HAS_DATAFLASH
> +#ifdef CONFIG_HAS_DATAFLASH || defined(CONFIG_ATMEL_SPI)
> void at91_spi0_hw_init(unsigned long cs_mask)
> {
> - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
> + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
>
> at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* SPI0_MISO */
> at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* SPI0_MOSI */
> at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* SPI0_SPCK */
>
> /* Enable clock */
> - writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer);
> + writel(1 << ATMEL_ID_SPI, &pmc->pcer);
>
> if (cs_mask & (1 << 0)) {
> at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
> diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h
> b/arch/arm/include/asm/arch-at91/at91sam9rl.h
> index 8eb0d4f..dfaafee 100644
> --- a/arch/arm/include/asm/arch-at91/at91sam9rl.h
> +++ b/arch/arm/include/asm/arch-at91/at91sam9rl.h
> @@ -14,117 +14,110 @@
> #ifndef AT91SAM9RL_H
> #define AT91SAM9RL_H
>
> +#define CONFIG_ARM926EJS /* ARM926EJS Core */
> +#define CONFIG_AT91FAMILY /* it's a member of AT91 */
> /*
> * Peripheral identifiers/interrupts.
> */
> -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
> -#define AT91_ID_SYS 1 /* System Controller */
> -#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
> -#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
> -#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
> -#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
> -#define AT91SAM9RL_ID_US0 6 /* USART 0 */
> -#define AT91SAM9RL_ID_US1 7 /* USART 1 */
> -#define AT91SAM9RL_ID_US2 8 /* USART 2 */
> -#define AT91SAM9RL_ID_US3 9 /* USART 3 */
> -#define AT91SAM9RL_ID_MCI
Re: [U-Boot] about at91 board in uboot
Hi Reinhard, On 06/17/2011 03:17 PM, Reinhard Meyer wrote: > Dear Lin, >> The following is the status XU Hong is reporting to me on >> u-boot-atmel/master. >> I saw it has been silent for 2 days. I don’t know if we could do something >> to help maintain all the boards. >> I will try to help allocate some of my people to handling missing parts for >> our EK. > > I send a message about 2 days ago, asking that the SoC relevant parts are > changed in a manner > consistent with the changes for the 9260, like in > at91sam9260_devices.c, at91sam9260.h, at91sam9260_matrix.h. Yes, we noticed that. And the patches we sent out are divided into 2 parts, one for SoC and one for EK (boards). We noticed the SoC part of SAM9263 has been merged, but EK part is not. I've already sent out an email about this but no response yet. For SAM9RL, V3 patches (SoC part and EK part) have been sent out days ago according to your comments. But, no response yet. We're sure we can not totally 100% understand all of your concerns. But we can talk with the code and finally reach the same point. Thanks for your understanding. BR, Hong > Once that is done, and added to u-boot-atmel/master, the board specific > patches should be rebased on that and submitted. > > Since nobody did volunteer so far, I was going to edit the SoC specific parts > and submit them, > but unfortunately that could take some time (until next week maybe, I was > going to start today > with that, but have paid work to finish as well :) ) > > I am not fond of quick and dirty solutions here, > the boards are not going to be removed with this u-boot release, > but will be after if no progress is seen - but we do have progress here - so > no need to panic. > > So lets do it in two distinct steps: > 1. fix SoCs > 2. fix boards > >> 9261 soc& ek have been merged to atmel branch. >> 9rl – v3 patches have been pushed out just now and shall be ok. >> 9263 – soc part has been merged into atmel branch. I’m asking the ek part. >> 9g45 - patches were sent by 3rd party. > > The SoC specific changes will/should be based before those patches, and will > replace the current ones. > > --- > > Original Message: > > Dear Friends, > > I have received several different patches reworking > > "at91sam*_devices.c" > > and > > "at91sam9*.h". > > Lokking at them, none of them is completely done the way the files for > at91sam9260 are done. > > Examples: > > 9260, 9263: ATMEL_ID_USART0 > 9261: ATMEL_ID_US0 > > 9260 uses the CONFIG_AT91_GPIO_PULLUP define, the others do not. > > 9261 still uses the CONFIG_USARTx defines. > > Please have a look at at91sam9260 as a reference. > > We do need a properly fixed SoC port for 9261, 9263 and the others > before individual board ports can be fixed. > > Just because there is a sudden rush to get things fixed for the next release > should NOT tempt us to get in interim versions. > > With Best Regards, > Reinhard ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] [V2] AT91: Makes AT91SAM9263 SoC build correctly against u-boot-atmel/master
Hi Reinhard,
On 06/14/2011 08:43 PM, Reinhard Meyer wrote:
> Dear Hong Xu,
> > Rework for AT91SAM9263 SoC, makes it build again.
> > Based on the work for AT91SAM9260-EK.
> >
> > Signed-off-by: Hong Xu
> > ---
> > arch/arm/cpu/arm926ejs/at91/lowlevel_init.S | 2 +-
> > arch/arm/cpu/arm926ejs/at91/timer.c | 13 ++
> > arch/arm/include/asm/arch-at91/at91_spi.h | 2 +-
> > arch/arm/include/asm/arch-at91/at91sam9263.h | 13 ++
> > .../arm/include/asm/arch-at91/at91sam9263_matrix.h | 146
> ++--
> > arch/arm/include/asm/arch-at91/at91sam9_sdramc.h | 2 +-
> > 6 files changed, 71 insertions(+), 107 deletions(-)
> >
> > diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c
> b/arch/arm/cpu/arm926ejs/at91/timer.c
> > index a087687..89a01ea 100644
> > --- a/arch/arm/cpu/arm926ejs/at91/timer.c
> > +++ b/arch/arm/cpu/arm926ejs/at91/timer.c
> > @@ -134,3 +134,16 @@ ulong get_tbclk(void)
> > {
> > return gd->timer_rate_hz;
> > }
> > +
> > +/*
> > + * Reset the timer.
> > + */
> > +void reset_timer(void)
> > +{
> > + /* TODO: write this code. */
> > +}
> > +
> > +void reset_timer_masked(void)
> > +{
> > + /* TODO: write this code. */
> > +}
>
> NAK. Those functions were intentionally removed from at91/timer.c
> quite a while ago.
> If some other code requires them, it must be fixed there.
> See also the discussion of the "new timer API" made recently.
>
> Applied (without at91/timer.c changes) to u-boot-atmel/master.
Thanks for merging the AT91SAM9263 SoC part. What about [PATCH 2/2] [V2]
AT91: Makes AT91SAM9263-EK build correctly against u-boot-atmel/master ?
BR,
Hong
> Best Regards,
> Reinhard
>
___
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[U-Boot] [PATCH 2/2 V3] AT91: Makes AT91SAM9RL-EK build correctly against u-boot-atmel/master
Rework for AT91SAM9RL-EK, makes it build again.
Based on the work for AT91SAM9260-EK.
Signed-off-by: Hong Xu
---
Makefile| 12
board/atmel/at91sam9rlek/at91sam9rlek.c | 73 --
board/atmel/at91sam9rlek/config.mk |1 -
board/atmel/at91sam9rlek/led.c |6 ++-
boards.cfg |3 +
include/configs/at91sam9rlek.h | 85 +-
6 files changed, 100 insertions(+), 80 deletions(-)
delete mode 100644 board/atmel/at91sam9rlek/config.mk
diff --git a/Makefile b/Makefile
index cd328b3..4e19fed 100644
--- a/Makefile
+++ b/Makefile
@@ -785,18 +785,6 @@ at91sam9263ek_config : unconfig
fi;
@$(MKCONFIG) -n $@ -a at91sam9263ek arm arm926ejs at91sam9263ek atmel
at91
-at91sam9rlek_nandflash_config \
-at91sam9rlek_dataflash_config \
-at91sam9rlek_dataflash_cs0_config \
-at91sam9rlek_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _nandflash,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_NANDFLASH 1"
>>$(obj)include/config.h ; \
- else \
- echo "#define CONFIG_SYS_USE_DATAFLASH 1"
>>$(obj)include/config.h ; \
- fi;
- @$(MKCONFIG) -n $@ -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
-
at91sam9m10g45ek_nandflash_config \
at91sam9m10g45ek_dataflash_config \
at91sam9m10g45ek_dataflash_cs0_config \
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c
b/board/atmel/at91sam9rlek/at91sam9rlek.c
index e374917..e559084 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -23,6 +23,7 @@
*/
#include
+#include
#include
#include
#include
@@ -31,7 +32,7 @@
#include
#include
#include
-#include
+
#include
#include
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@@ -48,33 +49,37 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_CMD_NAND
static void at91sam9rlek_nand_hw_init(void)
{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
unsigned long csa;
/* Enable CS3 */
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA,
- csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+
+ writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
- at91_sys_write(AT91_SMC_SETUP(3),
- AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3),
- AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
- AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
- at91_sys_write(AT91_SMC_CYCLE(3),
- AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
- at91_sys_write(AT91_SMC_MODE(3),
- AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
- AT91_SMC_EXNWMODE_DISABLE |
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
- AT91_SMC_DBW_16 |
+ AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
- AT91_SMC_DBW_8 |
+ AT91_SMC_MODE_DBW_8 |
#endif
- AT91_SMC_TDF_(2));
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
+ writel(1 << ATMEL_ID_PIOD, &pmc->pcer);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -102,7 +107,7 @@ vidinfo_t panel_info = {
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
- mmio: AT91SAM9RL_LCDC_BASE,
+ mmio: ATMEL_BASE_LCDC,
};
void lcd_enable(void)
@@ -116,6 +121,8 @@ void lcd_disable(void)
}
static void at91sam9rlek_lcd_hw_init(void)
{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
at91_set_A_periph(AT91_
[U-Boot] [PATCH 1/2 V3] AT91: Makes AT91SAM9RL SoC build correctly against u-boot-atmel/master
Rework for AT91SAM9RL SoC, makes it build again.
Based on the work for AT91SAM9260-EK.
Signed-off-by: Hong Xu
---
Changes since V2
- No at91_serial_hw_init, no CONFIG_USARTx anymore.
- Removed SZ_* macros - though I don't have the reason found in code :)
- Add definitions for all ATMEL_BASE_CSx
Thanks!
arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c | 45 ++
arch/arm/include/asm/arch-at91/at91sam9rl.h| 177 ++--
arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h | 121 +-
3 files changed, 141 insertions(+), 202 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
index 4f570f4..c2a6584 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
@@ -23,77 +23,58 @@
*/
#include
+#include
#include
#include
#include
-#include
void at91_serial0_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 6, 1);/* TXD0 */
at91_set_a_periph(AT91_PIO_PORTA, 7, 0);/* RXD0 */
- writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer);
+ writel(1 << ATMEL_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* RXD1 */
- writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer);
+ writel(1 << ATMEL_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* RXD2 */
- writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer);
+ writel(1 << ATMEL_ID_US2, &pmc->pcer);
}
-void at91_serial3_hw_init(void)
+void at91_seriald_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */
- writel(1 << AT91_ID_SYS, &pmc->pcer);
+ writel(1 << ATMEL_ID_SYS, &pmc->pcer);
}
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
- at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
- at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
- at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3 /* DBGU */
- at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_HAS_DATAFLASH
+#ifdef CONFIG_HAS_DATAFLASH || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* SPI0_SPCK */
/* Enable clock */
- writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer);
+ writel(1 << ATMEL_ID_SPI, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h
b/arch/arm/include/asm/arch-at91/at91sam9rl.h
index 8eb0d4f..dfaafee 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9rl.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9rl.h
@@ -14,117 +14,110 @@
#ifndef AT91SAM9RL_H
#define AT91SAM9RL_H
+#define CONFIG_ARM926EJS /* ARM926EJS Core */
+#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ0 /* Advanced Interrupt Controller (FIQ)
*/
-#define AT91_ID_SYS1 /* System Controller */
-#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
-#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
-#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
-#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
-#define AT91SAM9RL_ID_US0 6 /* USART 0 */
-#define AT91SAM9RL_ID_US1 7 /* USART 1 */
-#define AT91SAM9RL_ID_US2 8 /* USART 2 */
-#define AT91SAM9RL_ID_US3 9 /* USART 3 */
-#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card I
[U-Boot] [PATCH 2/2] [V2] AT91: Makes AT91SAM9261(9G10)-EK build correctly against u-boot-atmel/master
Rework for AT91SAM9261(9G10)-EK, makes it build again.
Based on the work for AT91SAM9260-EK.
Signed-off-by: Hong Xu
---
Makefile | 23 -
board/atmel/at91sam9261ek/at91sam9261ek.c | 136 +++--
board/atmel/at91sam9261ek/config.mk |1 -
board/atmel/at91sam9261ek/led.c |7 +-
boards.cfg|6 ++
include/configs/at91sam9261ek.h | 81 ++
6 files changed, 128 insertions(+), 126 deletions(-)
delete mode 100644 board/atmel/at91sam9261ek/config.mk
diff --git a/Makefile b/Makefile
index 1619c47..cd328b3 100644
--- a/Makefile
+++ b/Makefile
@@ -766,29 +766,6 @@ M5485HFE_config : unconfig
## ARM926EJ-S Systems
#
-at91sam9261ek_nandflash_config \
-at91sam9261ek_dataflash_cs0_config \
-at91sam9261ek_dataflash_cs3_config \
-at91sam9261ek_config \
-at91sam9g10ek_nandflash_config \
-at91sam9g10ek_dataflash_cs0_config \
-at91sam9g10ek_dataflash_cs3_config \
-at91sam9g10ek_config : unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring 9g10,$@)" ] ; then \
- echo "#define CONFIG_AT91SAM9G10EK 1"
>>$(obj)include/config.h ; \
- else \
- echo "#define CONFIG_AT91SAM9261EK 1"
>>$(obj)include/config.h ; \
- fi;
- @if [ "$(findstring _nandflash,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_NANDFLASH 1"
>>$(obj)include/config.h ; \
- elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_DATAFLASH_CS3 1"
>>$(obj)include/config.h ; \
- else \
- echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1"
>>$(obj)include/config.h ; \
- fi;
- @$(MKCONFIG) -n $@ -a at91sam9261ek arm arm926ejs at91sam9261ek atmel
at91
-
at91sam9263ek_norflash_config \
at91sam9263ek_norflash_boot_config \
at91sam9263ek_nandflash_config \
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c
b/board/atmel/at91sam9261ek/at91sam9261ek.c
index de5cfae..b6c7d9e 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -23,6 +23,7 @@
*/
#include
+#include
#include
#include
#include
@@ -31,7 +32,6 @@
#include
#include
#include
-#include
#include
#include
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
@@ -49,44 +49,48 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_CMD_NAND
static void at91sam9261ek_nand_hw_init(void)
{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
unsigned long csa;
/* Enable CS3 */
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA,
- csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+
+ writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
#ifdef CONFIG_AT91SAM9G10EK
- at91_sys_write(AT91_SMC_SETUP(3),
- AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3),
- AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(7) |
- AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(7));
- at91_sys_write(AT91_SMC_CYCLE(3),
- AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+ &smc->cs[3].cycle);
#else
- at91_sys_write(AT91_SMC_SETUP(3),
- AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3),
- AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
- AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
- at91_sys_write(AT91_SMC_CYCLE(3),
- AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SM
[U-Boot] [PATCH 1/2] [V2] AT91: Makes AT91SAM9261(9G10) SoC build correctly against u-boot-atmel/master
Rework for AT91SAM9261(9G10) SoC, makes it build again.
Based on the work for AT91SAM9260-EK.
Signed-off-by: Hong Xu
---
arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c | 45 +---
arch/arm/include/asm/arch-at91/at91_spi.h |2 +-
arch/arm/include/asm/arch-at91/at91sam9261.h |1 +
.../arm/include/asm/arch-at91/at91sam9261_matrix.h | 77 +---
4 files changed, 56 insertions(+), 69 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
index b4353ef..3db2b20 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
@@ -26,74 +26,65 @@
#include
#include
#include
-#include
+#include
void at91_serial0_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 8, 1);/* TXD0 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0);/* RXD0 */
- writel(1 << AT91SAM9261_ID_US0, &pmc->pcer);
+ writel(1 << ATMEL_ID_USART0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */
- writel(1 << AT91SAM9261_ID_US1, &pmc->pcer);
+ writel(1 << ATMEL_ID_USART1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */
- writel(1 << AT91SAM9261_ID_US2, &pmc->pcer);
+ writel(1 << ATMEL_ID_USART2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 9, 0);/* DRXD */
at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
- writel(1 << AT91_ID_SYS, &pmc->pcer);
+ writel(1 << ATMEL_ID_SYS, &pmc->pcer);
}
-void at91_serial_hw_init(void)
+void at91_seriald_hw_init(void)
{
-#ifdef CONFIG_USART0
- at91_serial0_hw_init();
-#endif
+ at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-#ifdef CONFIG_USART1
- at91_serial1_hw_init();
-#endif
+ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* DRXD */
+ at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */
-#ifdef CONFIG_USART2
- at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3 /* DBGU */
- at91_serial3_hw_init();
-#endif
+ writel(1 << ATMEL_ID_SYS, &pmc->pcer);
}
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 0, 0);/* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTA, 1, 0);/* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTA, 2, 0);/* SPI0_SPCK */
/* Enable clock */
- writel(1 << AT91SAM9261_ID_SPI0, &pmc->pcer);
+ writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
@@ -123,14 +114,14 @@ void at91_spi0_hw_init(unsigned long cs_mask)
void at91_spi1_hw_init(unsigned long cs_mask)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 31, 0); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* SPI1_SPCK */
/* Enable clock */
- writel(1 << AT91SAM9261_ID_SPI1, &pmc->pcer);
+ writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h
b/arch/arm/include/asm/arch-at91/at91_spi.h
index c520e89..afe724d 100644
--- a/arch/arm/include/asm/arch-at91/at91_spi.h
+++ b/arch/arm/include/asm/arch-at91/at91_spi.h
@@ -33,7 +33,7 @@ typedef struct at91_spi {
at91_pdc_t pdc;
} at91_spi_t;
-#ifdef CONFIG_AT91_LEGACY
+#ifdef CONFIG_ATMEL_LEGACY
#define AT91_SPI_CR
[U-Boot] [PATCH 2/2] [V2] AT91: Makes AT91SAM9263-EK build correctly against u-boot-atmel/master
Rework for AT91SAM9263-EK, makes it build again.
Based on the work for AT91SAM9260-EK.
Signed-off-by: Hong Xu
---
Makefile | 19 ---
board/atmel/at91sam9263ek/at91sam9263ek.c | 56 ---
board/atmel/at91sam9263ek/config.mk |1 -
board/atmel/at91sam9263ek/led.c | 23
boards.cfg|5 ++
include/configs/at91sam9263ek.h | 83
6 files changed, 98 insertions(+), 89 deletions(-)
delete mode 100644 board/atmel/at91sam9263ek/config.mk
diff --git a/Makefile b/Makefile
index 1619c47..c62601a 100644
--- a/Makefile
+++ b/Makefile
@@ -789,25 +789,6 @@ at91sam9g10ek_config : unconfig
fi;
@$(MKCONFIG) -n $@ -a at91sam9261ek arm arm926ejs at91sam9261ek atmel
at91
-at91sam9263ek_norflash_config \
-at91sam9263ek_norflash_boot_config \
-at91sam9263ek_nandflash_config \
-at91sam9263ek_dataflash_config \
-at91sam9263ek_dataflash_cs0_config \
-at91sam9263ek_config : unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _nandflash,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_NANDFLASH 1"
>>$(obj)include/config.h ; \
- elif [ "$(findstring norflash,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_NORFLASH 1"
>>$(obj)include/config.h ; \
- else \
- echo "#define CONFIG_SYS_USE_DATAFLASH 1"
>>$(obj)include/config.h ; \
- fi;
- @if [ "$(findstring norflash_boot,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_BOOT_NORFLASH 1"
>>$(obj)include/config.h ; \
- fi;
- @$(MKCONFIG) -n $@ -a at91sam9263ek arm arm926ejs at91sam9263ek atmel
at91
-
at91sam9rlek_nandflash_config \
at91sam9rlek_dataflash_config \
at91sam9rlek_dataflash_cs0_config \
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c
b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 91efc07..4d2937d 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -32,7 +32,8 @@
#include
#include
#include
-#include
+#include
+#include
#include
#include
#include
@@ -52,9 +53,9 @@ DECLARE_GLOBAL_DATA_PTR;
static void at91sam9263ek_nand_hw_init(void)
{
unsigned long csa;
- at91_smc_t *smc= (at91_smc_t *) AT91_SMC0_BASE;
- at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_smc_t*smc= (at91_smc_t *) ATMEL_BASE_SMC0;
+ at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
+ at91_pmc_t*pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
/* Enable CS3 */
csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
@@ -83,14 +84,14 @@ static void at91sam9263ek_nand_hw_init(void)
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
- writel(1 << AT91SAM9263_ID_PIOA | 1 << AT91SAM9263_ID_PIOCDE,
+ writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE,
&pmc->pcer);
/* Configure RDY/BSY */
- at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
@@ -98,11 +99,11 @@ static void at91sam9263ek_nand_hw_init(void)
static void at91sam9263ek_macb_hw_init(void)
{
unsigned long erstl;
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
- at91_pio_t *pio= (at91_pio_t *) AT91_PIO_BASE;
- at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
+ at91_pio_t *pio= (at91_pio_t *) ATMEL_BASE_PIO;
+ at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
/* Enable clock */
- writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
+ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
/*
* Disable pull-up on:
@@ -153,7 +154,7 @@ vidinfo_t panel_info = {
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
- mmio: AT91SAM9263_LCDC_BASE,
+ mmio: ATMEL_BASE_LCDC,
};
void lcd_enable(void)
@@ -168,7 +169,7 @@ void lcd_disable(void)
static void at91sam9263ek_lcd_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 1, 0);/* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 2, 0);/* LCDDOTCK */
@@ -193,8 +194,8 @@ static void at91sam9263ek_lcd_hw_in
[U-Boot] [PATCH 1/2] [V2] AT91: Makes AT91SAM9263 SoC build correctly against u-boot-atmel/master
Rework for AT91SAM9263 SoC, makes it build again.
Based on the work for AT91SAM9260-EK.
Signed-off-by: Hong Xu
---
arch/arm/cpu/arm926ejs/at91/lowlevel_init.S|2 +-
arch/arm/cpu/arm926ejs/at91/timer.c| 13 ++
arch/arm/include/asm/arch-at91/at91_spi.h |2 +-
arch/arm/include/asm/arch-at91/at91sam9263.h | 13 ++
.../arm/include/asm/arch-at91/at91sam9263_matrix.h | 146 ++--
arch/arm/include/asm/arch-at91/at91sam9_sdramc.h |2 +-
6 files changed, 71 insertions(+), 107 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
index 17ff0dd..d102195 100644
--- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
+++ b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
@@ -35,7 +35,7 @@
#include
#include
#include
-#ifdef CONFIG_AT91_LEGACY
+#ifdef CONFIG_ATMEL_LEGACY
#include
#endif
#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c
b/arch/arm/cpu/arm926ejs/at91/timer.c
index a087687..89a01ea 100644
--- a/arch/arm/cpu/arm926ejs/at91/timer.c
+++ b/arch/arm/cpu/arm926ejs/at91/timer.c
@@ -134,3 +134,16 @@ ulong get_tbclk(void)
{
return gd->timer_rate_hz;
}
+
+/*
+ * Reset the timer.
+ */
+void reset_timer(void)
+{
+ /* TODO: write this code. */
+}
+
+void reset_timer_masked(void)
+{
+ /* TODO: write this code. */
+}
diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h
b/arch/arm/include/asm/arch-at91/at91_spi.h
index c520e89..afe724d 100644
--- a/arch/arm/include/asm/arch-at91/at91_spi.h
+++ b/arch/arm/include/asm/arch-at91/at91_spi.h
@@ -33,7 +33,7 @@ typedef struct at91_spi {
at91_pdc_t pdc;
} at91_spi_t;
-#ifdef CONFIG_AT91_LEGACY
+#ifdef CONFIG_ATMEL_LEGACY
#define AT91_SPI_CR0x00/* Control Register */
#defineAT91_SPI_SPIEN (1 << 0) /* SPI
Enable */
diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h
b/arch/arm/include/asm/arch-at91/at91sam9263.h
index 2a1d6ee..bf9ff76 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9263.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9263.h
@@ -125,10 +125,23 @@
#define ATMEL_BASE_UHP 0x00a0 /* USB Host controller */
/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0 0x1000 /* typically NOR */
+#define ATMEL_BASE_CS1 0x2000 /* SDRAM */
+#define ATMEL_BASE_CS2 0x3000
+#define ATMEL_BASE_CS3 0x4000 /* typically NAND */
+#define ATMEL_BASE_CS4 0x5000
+#define ATMEL_BASE_CS5 0x6000
+#define ATMEL_BASE_CS6 0x7000
+#define ATMEL_BASE_CS7 0x8000
+
+/*
* Other misc defines
*/
#define ATMEL_PIO_PORTS5 /* this SoCs has 5 PIO
*/
#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
+#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
/*
* Cpu Name
diff --git a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
b/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
index 83b..3f67093 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
@@ -15,115 +15,53 @@
#ifndef AT91SAM9263_MATRIX_H
#define AT91SAM9263_MATRIX_H
-#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00)/* Master Configuration
Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04)/* Master Configuration
Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08)/* Master Configuration
Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C)/* Master Configuration
Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10)/* Master Configuration
Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14)/* Master Configuration
Register 5 */
-#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18)/* Master Configuration
Register 6 */
-#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C)/* Master Configuration
Register 7 */
-#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20)/* Master Configuration
Register 8 */
-#defineAT91_MATRIX_ULBT(7 << 0)/* Undefined
Length Burst Type */
-#defineAT91_MATRIX_ULBT_INFINITE (0 << 0)
-#defineAT91_MATRIX_ULBT_SINGLE (1 << 0)
-#defineAT91_MATRIX_ULBT_FOUR (2 << 0)
-#defineAT91_MATRIX_ULBT_EIGHT (3 << 0)
-#defineAT91_MATRIX_ULBT_SIXTEEN(4 << 0)
+#ifndef __ASSEMBLY__
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40)/* Slave Configuration
Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44)/* Slave Configuration
Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48)/* Slave Configuration
Register 2 */
-#defi
[U-Boot] [PATCH 2/2] [V2] AT91: Makes AT91SAM9RL-EK build correctly against u-boot-atmel/master
Rework for AT91SAM9RL-EK, makes it build again.
Based on the work for AT91SAM9260-EK.
Signed-off-by: Hong Xu
---
Makefile| 12 -
board/atmel/at91sam9rlek/at91sam9rlek.c | 71 +---
board/atmel/at91sam9rlek/config.mk |1 -
board/atmel/at91sam9rlek/led.c |6 ++-
boards.cfg |3 +
include/configs/at91sam9rlek.h | 77 +-
6 files changed, 95 insertions(+), 75 deletions(-)
delete mode 100644 board/atmel/at91sam9rlek/config.mk
diff --git a/Makefile b/Makefile
index 1619c47..35e9107 100644
--- a/Makefile
+++ b/Makefile
@@ -808,18 +808,6 @@ at91sam9263ek_config : unconfig
fi;
@$(MKCONFIG) -n $@ -a at91sam9263ek arm arm926ejs at91sam9263ek atmel
at91
-at91sam9rlek_nandflash_config \
-at91sam9rlek_dataflash_config \
-at91sam9rlek_dataflash_cs0_config \
-at91sam9rlek_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _nandflash,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_NANDFLASH 1"
>>$(obj)include/config.h ; \
- else \
- echo "#define CONFIG_SYS_USE_DATAFLASH 1"
>>$(obj)include/config.h ; \
- fi;
- @$(MKCONFIG) -n $@ -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
-
at91sam9m10g45ek_nandflash_config \
at91sam9m10g45ek_dataflash_config \
at91sam9m10g45ek_dataflash_cs0_config \
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c
b/board/atmel/at91sam9rlek/at91sam9rlek.c
index e374917..ad289a4 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -23,6 +23,7 @@
*/
#include
+#include
#include
#include
#include
@@ -31,7 +32,7 @@
#include
#include
#include
-#include
+
#include
#include
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@@ -48,33 +49,37 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_CMD_NAND
static void at91sam9rlek_nand_hw_init(void)
{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
unsigned long csa;
/* Enable CS3 */
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA,
- csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+
+ writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
- at91_sys_write(AT91_SMC_SETUP(3),
- AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3),
- AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
- AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
- at91_sys_write(AT91_SMC_CYCLE(3),
- AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
- at91_sys_write(AT91_SMC_MODE(3),
- AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
- AT91_SMC_EXNWMODE_DISABLE |
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
- AT91_SMC_DBW_16 |
+ AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
- AT91_SMC_DBW_8 |
+ AT91_SMC_MODE_DBW_8 |
#endif
- AT91_SMC_TDF_(2));
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
+ writel(1 << ATMEL_ID_PIOD, &pmc->pcer);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -102,7 +107,7 @@ vidinfo_t panel_info = {
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
- mmio: AT91SAM9RL_LCDC_BASE,
+ mmio: ATMEL_BASE_LCDC,
};
void lcd_enable(void)
@@ -116,6 +121,8 @@ void lcd_disable(void)
}
static void at91sam9rlek_lcd_hw_init(void)
{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
at91_set_A_periph(AT91_
[U-Boot] [PATCH 1/2] [V2] AT91: Makes AT91SAM9RL SoC build correctly against u-boot-atmel/master
Rework for AT91SAM9RL SoC, makes it build again.
Based on the work for AT91SAM9260-EK.
Signed-off-by: Hong Xu
---
arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c | 26 ++--
arch/arm/include/asm/arch-at91/at91_spi.h |2 +-
arch/arm/include/asm/arch-at91/at91sam9rl.h| 176 ++--
arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h | 121 +-
4 files changed, 141 insertions(+), 184 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
index 4f570f4..c8d19f8 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
@@ -23,45 +23,45 @@
*/
#include
+#include
#include
#include
#include
-#include
void at91_serial0_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 6, 1);/* TXD0 */
at91_set_a_periph(AT91_PIO_PORTA, 7, 0);/* RXD0 */
- writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer);
+ writel(1 << ATMEL_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* RXD1 */
- writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer);
+ writel(1 << ATMEL_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* RXD2 */
- writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer);
+ writel(1 << ATMEL_ID_US2, &pmc->pcer);
}
-void at91_serial3_hw_init(void)
+void at91_seriald_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */
- writel(1 << AT91_ID_SYS, &pmc->pcer);
+ writel(1 << ATMEL_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@@ -79,21 +79,21 @@ void at91_serial_hw_init(void)
#endif
#ifdef CONFIG_USART3 /* DBGU */
- at91_serial3_hw_init();
+ at91_seriald_hw_init();
#endif
}
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* SPI0_SPCK */
/* Enable clock */
- writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer);
+ writel(1 << ATMEL_ID_SPI, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h
b/arch/arm/include/asm/arch-at91/at91_spi.h
index c520e89..afe724d 100644
--- a/arch/arm/include/asm/arch-at91/at91_spi.h
+++ b/arch/arm/include/asm/arch-at91/at91_spi.h
@@ -33,7 +33,7 @@ typedef struct at91_spi {
at91_pdc_t pdc;
} at91_spi_t;
-#ifdef CONFIG_AT91_LEGACY
+#ifdef CONFIG_ATMEL_LEGACY
#define AT91_SPI_CR0x00/* Control Register */
#defineAT91_SPI_SPIEN (1 << 0) /* SPI
Enable */
diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h
b/arch/arm/include/asm/arch-at91/at91sam9rl.h
index 8eb0d4f..7e3a029 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9rl.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9rl.h
@@ -14,117 +14,109 @@
#ifndef AT91SAM9RL_H
#define AT91SAM9RL_H
+#define CONFIG_ARM926EJS /* ARM926EJS Core */
+#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ0 /* Advanced Interrupt Controller (FIQ)
*/
-#define AT91_ID_SYS1 /* System Controller */
-#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
-#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
-#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
-#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
-#define AT91SAM9RL
[U-Boot] [PATCH] Makes AT91SAM9261-EK build correctly against the mainline HEAD
Rework for AT91SAM9261-EK, makes it build again.
Based on the work for AT91SAM9260-EK.
Signed-off-by: voice
Signed-off-by: Hong Xu
---
Makefile | 23
arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c | 45 +++
arch/arm/include/asm/arch-at91/at91_spi.h |2 +-
arch/arm/include/asm/arch-at91/at91sam9261.h |2 +-
.../arm/include/asm/arch-at91/at91sam9261_matrix.h | 77 +--
board/atmel/at91sam9261ek/at91sam9261ek.c | 136 ++-
board/atmel/at91sam9261ek/config.mk|1 -
board/atmel/at91sam9261ek/led.c|7 +-
boards.cfg |6 +
include/configs/at91sam9261ek.h| 81 +++-
10 files changed, 184 insertions(+), 196 deletions(-)
delete mode 100644 board/atmel/at91sam9261ek/config.mk
diff --git a/Makefile b/Makefile
index dcf5d93..fedddf4 100644
--- a/Makefile
+++ b/Makefile
@@ -803,29 +803,6 @@ at91sam9xeek_config: unconfig
fi;
@$(MKCONFIG) -n $@ -a at91sam9260ek arm arm926ejs at91sam9260ek atmel
at91
-at91sam9261ek_nandflash_config \
-at91sam9261ek_dataflash_cs0_config \
-at91sam9261ek_dataflash_cs3_config \
-at91sam9261ek_config \
-at91sam9g10ek_nandflash_config \
-at91sam9g10ek_dataflash_cs0_config \
-at91sam9g10ek_dataflash_cs3_config \
-at91sam9g10ek_config : unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring 9g10,$@)" ] ; then \
- echo "#define CONFIG_AT91SAM9G10EK 1"
>>$(obj)include/config.h ; \
- else \
- echo "#define CONFIG_AT91SAM9261EK 1"
>>$(obj)include/config.h ; \
- fi;
- @if [ "$(findstring _nandflash,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_NANDFLASH 1"
>>$(obj)include/config.h ; \
- elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_DATAFLASH_CS3 1"
>>$(obj)include/config.h ; \
- else \
- echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1"
>>$(obj)include/config.h ; \
- fi;
- @$(MKCONFIG) -n $@ -a at91sam9261ek arm arm926ejs at91sam9261ek atmel
at91
-
at91sam9263ek_norflash_config \
at91sam9263ek_norflash_boot_config \
at91sam9263ek_nandflash_config \
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
index b4353ef..3db2b20 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
@@ -26,74 +26,65 @@
#include
#include
#include
-#include
+#include
void at91_serial0_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 8, 1);/* TXD0 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0);/* RXD0 */
- writel(1 << AT91SAM9261_ID_US0, &pmc->pcer);
+ writel(1 << ATMEL_ID_USART0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */
- writel(1 << AT91SAM9261_ID_US1, &pmc->pcer);
+ writel(1 << ATMEL_ID_USART1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */
- writel(1 << AT91SAM9261_ID_US2, &pmc->pcer);
+ writel(1 << ATMEL_ID_USART2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 9, 0);/* DRXD */
at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
- writel(1 << AT91_ID_SYS, &pmc->pcer);
+ writel(1 << ATMEL_ID_SYS, &pmc->pcer);
}
-void at91_serial_hw_init(void)
+void at91_seriald_hw_init(void)
{
-#ifdef CONFIG_USART0
- at91_serial0_hw_init();
-#endif
+ at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-#ifdef CONFIG_USART1
- at91_serial1_hw_init();
-#endif
+ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* DRXD */
+ at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */
-#ifdef CON
[U-Boot] [PATCH] Makes AT91SAM9263-EK build correctly against the mainline HEAD
Rework for AT91SAM9263-EK, makes it build again.
Based on the work for AT91SAM9260-EK.
Signed-off-by: Hong Xu
---
Makefile | 19 ---
arch/arm/cpu/arm926ejs/at91/lowlevel_init.S| 26 ++--
arch/arm/cpu/arm926ejs/at91/timer.c| 13 ++
arch/arm/include/asm/arch-at91/at91_matrix.h | 10 +-
arch/arm/include/asm/arch-at91/at91_pio.h | 14 +-
arch/arm/include/asm/arch-at91/at91_pmc.h | 10 +-
arch/arm/include/asm/arch-at91/at91_rstc.h |2 +-
arch/arm/include/asm/arch-at91/at91_spi.h |2 +-
arch/arm/include/asm/arch-at91/at91_wdt.h |2 +-
arch/arm/include/asm/arch-at91/at91sam9263.h |5 +
.../arm/include/asm/arch-at91/at91sam9263_matrix.h | 146 ++--
arch/arm/include/asm/arch-at91/at91sam9_sdramc.h |2 +-
arch/arm/include/asm/arch-at91/at91sam9_smc.h |2 +-
board/atmel/at91sam9263ek/at91sam9263ek.c | 51 +---
board/atmel/at91sam9263ek/config.mk|1 -
board/atmel/at91sam9263ek/led.c| 23 ++--
boards.cfg |5 +
include/configs/at91sam9263ek.h| 83 +++-
18 files changed, 190 insertions(+), 226 deletions(-)
delete mode 100644 board/atmel/at91sam9263ek/config.mk
diff --git a/Makefile b/Makefile
index dcf5d93..80867d2 100644
--- a/Makefile
+++ b/Makefile
@@ -826,25 +826,6 @@ at91sam9g10ek_config : unconfig
fi;
@$(MKCONFIG) -n $@ -a at91sam9261ek arm arm926ejs at91sam9261ek atmel
at91
-at91sam9263ek_norflash_config \
-at91sam9263ek_norflash_boot_config \
-at91sam9263ek_nandflash_config \
-at91sam9263ek_dataflash_config \
-at91sam9263ek_dataflash_cs0_config \
-at91sam9263ek_config : unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _nandflash,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_NANDFLASH 1"
>>$(obj)include/config.h ; \
- elif [ "$(findstring norflash,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_NORFLASH 1"
>>$(obj)include/config.h ; \
- else \
- echo "#define CONFIG_SYS_USE_DATAFLASH 1"
>>$(obj)include/config.h ; \
- fi;
- @if [ "$(findstring norflash_boot,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_BOOT_NORFLASH 1"
>>$(obj)include/config.h ; \
- fi;
- @$(MKCONFIG) -n $@ -a at91sam9263ek arm arm926ejs at91sam9263ek atmel
at91
-
at91sam9rlek_nandflash_config \
at91sam9rlek_dataflash_config \
at91sam9rlek_dataflash_cs0_config \
diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
index 7f7ca5e..56b5c6e 100644
--- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
+++ b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
@@ -27,7 +27,7 @@
*/
#include
-#include
+#include
#include
#include
#include
@@ -230,37 +230,37 @@ SMRDATA1:
.word CONFIG_SYS_SDRC_MDR_VAL
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
- .word AT91_SDRAM_BASE
+ .word ATMEL_BASE_CS1
.word CONFIG_SYS_SDRAM_VAL1
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
- .word AT91_SDRAM_BASE
+ .word ATMEL_BASE_CS1
.word CONFIG_SYS_SDRAM_VAL2
- .word AT91_SDRAM_BASE
+ .word ATMEL_BASE_CS1
.word CONFIG_SYS_SDRAM_VAL3
- .word AT91_SDRAM_BASE
+ .word ATMEL_BASE_CS1
.word CONFIG_SYS_SDRAM_VAL4
- .word AT91_SDRAM_BASE
+ .word ATMEL_BASE_CS1
.word CONFIG_SYS_SDRAM_VAL5
- .word AT91_SDRAM_BASE
+ .word ATMEL_BASE_CS1
.word CONFIG_SYS_SDRAM_VAL6
- .word AT91_SDRAM_BASE
+ .word ATMEL_BASE_CS1
.word CONFIG_SYS_SDRAM_VAL7
- .word AT91_SDRAM_BASE
+ .word ATMEL_BASE_CS1
.word CONFIG_SYS_SDRAM_VAL8
- .word AT91_SDRAM_BASE
+ .word ATMEL_BASE_CS1
.word CONFIG_SYS_SDRAM_VAL9
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL4
- .word AT91_SDRAM_BASE
+ .word ATMEL_BASE_CS1
.word CONFIG_SYS_SDRAM_VAL10
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL5
- .word AT91_SDRAM_BASE
+ .word ATMEL_BASE_CS1
.word CONFIG_SYS_SDRAM_VAL11
.word AT91_ASM_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL2
- .word AT91_SDRAM_BASE
+ .word ATMEL_BASE_CS1
.word CONFIG_SYS_SDRAM_VAL12
/* User reset enable*/
.word AT91_ASM_RSTC_MR
diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c
b/arch/arm/cpu/arm926ejs/at91/timer.c
index a087687..89a01ea 100644
--- a/arch/arm/cpu/arm926ejs/at91/timer.c
+++ b/arch/arm/cpu/arm926ejs/at91/timer.c
@@ -134,3 +134,16 @@ ulong get_tbclk(void)
{
return gd->timer_rate_h
[U-Boot] [PATCH] AT91: Makes AT91SAM9RL-EK build correctly against the mainline HEAD
Rework for AT91SAM9RL-EK, makes it build again.
Based on the work for AT91SAM9260-EK.
Signed-off-by: Hong Xu
---
Makefile | 12 --
arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c | 26 ++--
arch/arm/include/asm/arch-at91/at91_spi.h |2 +-
arch/arm/include/asm/arch-at91/at91sam9rl.h| 176 ++--
arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h | 121 +-
board/atmel/at91sam9rlek/at91sam9rlek.c| 71 +---
board/atmel/at91sam9rlek/config.mk |1 -
board/atmel/at91sam9rlek/led.c |6 +-
boards.cfg |3 +
include/configs/at91sam9rlek.h | 77 +
10 files changed, 236 insertions(+), 259 deletions(-)
delete mode 100644 board/atmel/at91sam9rlek/config.mk
diff --git a/Makefile b/Makefile
index dcf5d93..9cd812c 100644
--- a/Makefile
+++ b/Makefile
@@ -845,18 +845,6 @@ at91sam9263ek_config : unconfig
fi;
@$(MKCONFIG) -n $@ -a at91sam9263ek arm arm926ejs at91sam9263ek atmel
at91
-at91sam9rlek_nandflash_config \
-at91sam9rlek_dataflash_config \
-at91sam9rlek_dataflash_cs0_config \
-at91sam9rlek_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _nandflash,$@)" ] ; then \
- echo "#define CONFIG_SYS_USE_NANDFLASH 1"
>>$(obj)include/config.h ; \
- else \
- echo "#define CONFIG_SYS_USE_DATAFLASH 1"
>>$(obj)include/config.h ; \
- fi;
- @$(MKCONFIG) -n $@ -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
-
CPU9G20_128M_config \
CPU9G20_config \
CPU9260_128M_config \
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
index 4f570f4..c8d19f8 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
@@ -23,45 +23,45 @@
*/
#include
+#include
#include
#include
#include
-#include
void at91_serial0_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 6, 1);/* TXD0 */
at91_set_a_periph(AT91_PIO_PORTA, 7, 0);/* RXD0 */
- writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer);
+ writel(1 << ATMEL_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* RXD1 */
- writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer);
+ writel(1 << ATMEL_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* RXD2 */
- writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer);
+ writel(1 << ATMEL_ID_US2, &pmc->pcer);
}
-void at91_serial3_hw_init(void)
+void at91_seriald_hw_init(void)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */
- writel(1 << AT91_ID_SYS, &pmc->pcer);
+ writel(1 << ATMEL_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@@ -79,21 +79,21 @@ void at91_serial_hw_init(void)
#endif
#ifdef CONFIG_USART3 /* DBGU */
- at91_serial3_hw_init();
+ at91_seriald_hw_init();
#endif
}
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc= (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* SPI0_SPCK */
/* Enable clock */
- writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer);
+ writel(1 << ATMEL_ID_SPI, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h
b/arch/arm/include/asm/arch-at91/at91_spi.h
index c520e89..afe724d 100644
--- a/arch/arm/include/asm/arc
[U-Boot] Help on mem relocation issue when reworking on at91sam9rlek
Hi Reinhard,
I have an issue when I reworked U-Boot for AT91SAM9RL-EK.
When I choose `at91sam9rlek_nandflash', things are quite smooth.
But when I choose `at91sam9rlek_dataflash_cs0', uboot will stop
booting after `relocate_code()'.
Do you have some hints about this? Thanks a lot.
Please see below the U-Boot output,
U-Boot 2011.06-rc1-02788-g2cca47e-dirty (Jun 09 2011 - 17:48:14)
U-Boot code: 21F0 -> 21F2812C BSS: -> 21F2A920
CPU: AT91SAM9RL
Crystal frequency: 12 MHz
CPU clock: 200 MHz
Master clock : 100 MHz
monitor len: 0002A920
ramsize: 0400
TLB table at: 23ff
Top of RAM usable for U-Boot at: 23ff
LCD panel info: 240 x 320, 8 bit/pix
Reserving 76k for LCD Framebuffer at: 23fdd000
Reserving 170k for U-Boot at: 23fb2000
Reserving 180k for malloc() at: 23f85000
Reserving 24 Bytes for Board Info at: 23f84fe8
Reserving 144 Bytes for Global Data at: 23f84f58
New Stack Pointer is: 23f84f48
RAM Configuration:
Bank #0: 2000 64 MiB
relocation Offset is: 020b2000
addr_sp: 23f84f48, id: 23f84f58, addr: 23fb2000
--- U-Boot will stop here ---
--- >8 --- my temporary work is below
diff --git a/Makefile b/Makefile
index 76124e5..2bdc17b 100644
--- a/Makefile
+++ b/Makefile
@@ -808,6 +808,7 @@ at91sam9263ek_config: unconfig
fi;
@$(MKCONFIG) -n $@ -a at91sam9263ek arm arm926ejs at91sam9263ek atmel
at91
+ifdef XXX
at91sam9rlek_nandflash_config \
at91sam9rlek_dataflash_config \
at91sam9rlek_dataflash_cs0_config \
@@ -819,6 +820,7 @@ at91sam9rlek_config : unconfig
echo "#define CONFIG_SYS_USE_DATAFLASH 1"
>>$(obj)include/config.h ; \
fi;
@$(MKCONFIG) -n $@ -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
+endif
CPU9G20_128M_config \
CPU9G20_config \
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
index 4f570f4..79ca59b 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
@@ -23,10 +23,11 @@
*/
#include
+#include
#include
#include
#include
-#include
+
void at91_serial0_hw_init(void)
{
@@ -34,7 +35,7 @@ void at91_serial0_hw_init(void)
at91_set_a_periph(AT91_PIO_PORTA, 6, 1);/* TXD0 */
at91_set_a_periph(AT91_PIO_PORTA, 7, 0);/* RXD0 */
- writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer);
+ writel(1 << ATMEL_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
@@ -43,7 +44,7 @@ void at91_serial1_hw_init(void)
at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* RXD1 */
- writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer);
+ writel(1 << ATMEL_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
@@ -52,7 +53,7 @@ void at91_serial2_hw_init(void)
at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* RXD2 */
- writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer);
+ writel(1 << ATMEL_ID_US2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
@@ -61,7 +62,7 @@ void at91_serial3_hw_init(void)
at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */
- writel(1 << AT91_ID_SYS, &pmc->pcer);
+ writel(1 << ATMEL_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@@ -93,7 +94,7 @@ void at91_spi0_hw_init(unsigned long cs_mask)
at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* SPI0_SPCK */
/* Enable clock */
- writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer);
+ writel(1 << ATMEL_ID_SPI, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h
b/arch/arm/include/asm/arch-at91/at91sam9rl.h
index 8eb0d4f..e36282e 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9rl.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9rl.h
@@ -14,35 +14,37 @@
#ifndef AT91SAM9RL_H
#define AT91SAM9RL_H
+#define CONFIG_ARM926EJS /* ARM926EJS Core */
+#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ0 /* Advanced Interrupt Controller (FIQ)
*/
-#define AT91_ID_SYS1 /* System Controller */
-#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
-#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
-#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
-#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
-#define AT91SAM9RL_ID_US0 6 /* USART 0 */
-#define AT91SAM9RL_ID_US1 7 /* USART 1 */
-#define AT91SAM9RL_ID_US2 8 /* USART 2 */
-#define AT
Re: [U-Boot] Fwd: [STATUS] WARNING: huge ARM board removal pending
Hi Reinhard, On 06/07/2011 04:18 PM, Reinhard Meyer wrote: > Dear Xu, Hong, >> Dear Reinhard, >> >> We just noticed the warning from Wolfgang Denk about the status of the ARM >> boards. > > See http://article.gmane.org/gmane.comp.boot-loaders.u-boot/100918 >> >> There're quite a lot of AT91 boards listed. We're going to focus on > > fixing the current issues to let MAKEALL happy. :-) >> >> I know exactly your great work on AT91 and AVR32. The rework you're > > doing is quite excellent. We of course want to sync with what you have > > done. Could you please describe us the starting point we can begin with? > > Do you have special things which we can help? And so on ... >> >> Thanks a lot. > > If there are SoC specific files to be adapted, they should be adapted > as done in 9260. > > Board specific files should be looking like those of at91sam9260-ek. > > Remove fixed boards from the global Makefile and add them to boards.cfg. > > I'll put the fix for at91sam9260*-ek on u-boot-atmel/master in the next hours, > you can have a look at it - or look at the patch I posted yesterday for it. OK, very nice. I'm just worried because I can not compile at91sam9260ek on u-boot-atmel/master and u-boot-atmel/next 3 hrs ago. So, we're waiting for your work on sam9260 and take it as a starting point for other boards. > Two notes: > 1. please limit line length in e-Mails to 80 or less - I had to manually > break your mail to be able to read it. > > 2. please post to the u-boot mailing list as well No problem. BR, Eric > Best Regards, > > Reinhard ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] [NAND] Add board_nand_init_tail to give board module a chance to init after NAND chip is scaned.
Sometimes, board module needs to know some information about the NAND
chip e.g. page size to continue it's initialization. This short patch
give board module a chance to continue its initialization after the
NAND chip is scaned.
best regards,
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index e44470e..f795d2e 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -41,6 +41,10 @@ static const char default_nand_name[] = "nand";
extern int board_nand_init(struct nand_chip *nand);
+int __board_nand_init_tail(struct nand_chip *nand) { return 0; }
+int inline board_nand_init_tail (struct nand_chip *) __attribute__
+ ((weak, alias("__board_nand_init_tail")));
+
static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand,
ulong base_addr)
{
@@ -48,7 +52,7 @@ static void nand_init_chip(struct mtd_info *mtd,
struct nand_chip *nand,
nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
if (board_nand_init(nand) == 0) {
- if (nand_scan(mtd, 1) == 0) {
+ if ((nand_scan(mtd, 1) == 0) && (board_nand_init_tail(nand) ==
0)) {
if (!mtd->name)
mtd->name = (char *)default_nand_name;
} else
___
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