[PATCH] phy: rockchip: inno-hdmi: Fix missing readl base addr
inno_poll passes the reg offset that is used by readl_poll_sleep_timeout
without any base addr.
Fix it.
Bug:
inno_hdmi_phy phy@ff43: Pre-PLL locking failed
inno_hdmi_phy phy@ff43: PHY: Failed to power on phy@ff43: -110.
failed to power on phy (ret=-110)
inno_hdmi_phy phy@ff43: Pre-PLL locking failed
inno_hdmi_phy phy@ff43: PHY: Failed to power on phy@ff43: -110.
failed to power on phy (ret=-110)
Fixes: aa2271184603 ("phy: rockchip: Add Rockchip INNO HDMI PHY driver")
Suggested-by: Jonas Karlman
Signed-off-by: Jagan Teki
---
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index 3bb1a254ff..7459779dff 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -432,8 +432,8 @@ static inline void inno_update_bits(struct inno_hdmi_phy
*inno, u8 reg,
inno_write(inno, reg, tmp);
}
-#define inno_poll(reg, val, cond, sleep_us, timeout_us) \
- readl_poll_sleep_timeout((reg) * 4, val, cond, sleep_us, timeout_us)
+#define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \
+ readl_poll_sleep_timeout((inno)->regs + ((reg) * 4), val, cond,
sleep_us, timeout_us)
static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno,
unsigned long rate)
@@ -575,7 +575,7 @@ inno_hdmi_phy_rk3328_clk_set_rate(struct phy *phy,
inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
/* Wait for Pre-PLL lock */
- ret = inno_poll(0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS,
+ ret = inno_poll(inno, 0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS,
1000, 1);
if (ret) {
dev_err(phy->dev, "Pre-PLL locking failed\n");
@@ -674,7 +674,7 @@ inno_hdmi_phy_rk3328_power_on(struct phy *phy,
RK3328_TMDS_DRIVER_ENABLE);
/* Wait for post PLL lock */
- ret = inno_poll(0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS,
+ ret = inno_poll(inno, 0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS,
1000, 1);
if (ret) {
dev_err(phy->dev, "Post-PLL locking failed\n");
--
2.34.1
Re: [PATCH v2 2/3] rockchip: rk3328: Enable ARMv8 crypto extensions
On Mon, 22 Apr 2024 at 01:40, Jonas Karlman wrote: > > The RK3328 SoC support ARMv8 Cryptography Extensions and use of the > ARMv8 crypto extensions help speed up FIT checksum validation in SPL. > > Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto > extensions for SHA256 when validating checksum of FIT images. > > Also imply OF_LIVE to help speed up init of U-Boot proper. > > Signed-off-by: Jonas Karlman > --- > v2: No change, rebase on latest master bransh > --- > arch/arm/mach-rockchip/Kconfig | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig > index ee0f338995b9..651ecfe9b8fd 100644 > --- a/arch/arm/mach-rockchip/Kconfig > +++ b/arch/arm/mach-rockchip/Kconfig > @@ -180,8 +180,11 @@ config ROCKCHIP_RK3328 > select SUPPORT_TPL > select TPL > select TPL_NEEDS_SEPARATE_STACK if TPL > + imply ARMV8_CRYPTO > + imply ARMV8_SET_SMPEN This blocks the access of PLL registers. U-Boot 2024.07-rc4-00052-gfe2ce09a07-dirty (Jun 19 2024 - 00:43:40 +0530) Model: Firefly roc-rk3328-cc DRAM: 1 GiB (effective 1022 MiB) PMIC: RK8050 (on=0x40, off=0x00) Core: 241 devices, 29 uclasses, devicetree: separate MMC: mmc@ff50: 1, mmc@ff52: 0 Loading Environment from MMC... Reading from MMC(1)... *** Warning - bad CRC, using default environment inno_hdmi_phy phy@ff43: Pre-PLL locking failed inno_hdmi_phy phy@ff43: PHY: Failed to power on phy@ff43: -110. failed to power on phy (ret=-110) inno_hdmi_phy phy@ff43: Pre-PLL locking failed inno_hdmi_phy phy@ff43: PHY: Failed to power on phy@ff43: -110. failed to power on phy (ret=-110) In:serial,usbkbd Out: serial,vidconsole Err: serial,vidconsole Model: Firefly roc-rk3328-cc Net: eth0: ethernet@ff54 Jagan.
Re: [PATCH 2/2] rockchip: rk3588-edgeble: Add USB OTG support
On Mon, 27 May 2024 at 14:17, Quentin Schulz wrote:
>
> Hi Jagan,
>
> On 5/27/24 8:39 AM, Jagan Teki wrote:
> > Add support for USB OTG with UMS to program eMMC.
> >
> > Add it for Edgeble NCM6A, NCM6B.
> >
> > Signed-off-by: Jagan Teki
> > ---
> > .../dts/rk3588-edgeble-neu6a-io-u-boot.dtsi| 18 ++
> > .../dts/rk3588-edgeble-neu6b-io-u-boot.dtsi| 18 ++
> > configs/neu6a-io-rk3588_defconfig | 9 +
> > configs/neu6b-io-rk3588_defconfig | 9 +
> > 4 files changed, 54 insertions(+)
> >
> > diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
> > b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
> > index 88f3f7eee2..534d9f8a2c 100644
> > --- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
> > +++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
> > @@ -15,3 +15,21 @@
> > bus-width = <4>;
> > status = "okay";
> > };
> > +
> > + {
> > + status = "okay";
> > +};
> > +
> > +_otg {
> > + status = "okay";
> > +};
> > +
> > +_phy0 {
> > + status = "okay";
> > +};
> > +
> > +_host0_xhci {
> > + dr_mode = "peripheral";
> > + maximum-speed = "high-speed";
> > + status = "okay";
> > +};
> > diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
> > b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
> > index 289578803e..b3d17a60ce 100644
> > --- a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
> > +++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
> > @@ -15,3 +15,21 @@
> > bus-width = <4>;
> > status = "okay";
> > };
> > +
> > + {
> > + status = "okay";
> > +};
> > +
> > +_otg {
> > + status = "okay";
> > +};
> > +
> > +_phy0 {
> > + status = "okay";
> > +};
> > +
> > +_host0_xhci {
> > + dr_mode = "peripheral";
> > + maximum-speed = "high-speed";
> > + status = "okay";
> > +};
>
> I don't see those patches in v6.10-rc1. Have you sent those to upstream
> already? I assume we should cherry-pick patches in dts/upstream instead
> of piling stuff up in u-boot.dtsis. This should also bring the patches
> in rk3588(s).dtsi to add the missing bits for USB support we currently
> have in rk3588*-u-boot.dtsi?
These are -u-boot.dtsi and nothing to do with dts/upstream and can be
removed or reconfigured once we sync the DT from Linux.
Jagan.
[PATCH 2/2] rockchip: rk3588-edgeble: Add USB OTG support
Add support for USB OTG with UMS to program eMMC.
Add it for Edgeble NCM6A, NCM6B.
Signed-off-by: Jagan Teki
---
.../dts/rk3588-edgeble-neu6a-io-u-boot.dtsi| 18 ++
.../dts/rk3588-edgeble-neu6b-io-u-boot.dtsi| 18 ++
configs/neu6a-io-rk3588_defconfig | 9 +
configs/neu6b-io-rk3588_defconfig | 9 +
4 files changed, 54 insertions(+)
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
index 88f3f7eee2..534d9f8a2c 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
@@ -15,3 +15,21 @@
bus-width = <4>;
status = "okay";
};
+
+ {
+ status = "okay";
+};
+
+_otg {
+ status = "okay";
+};
+
+_phy0 {
+ status = "okay";
+};
+
+_host0_xhci {
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
index 289578803e..b3d17a60ce 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
@@ -15,3 +15,21 @@
bus-width = <4>;
status = "okay";
};
+
+ {
+ status = "okay";
+};
+
+_otg {
+ status = "okay";
+};
+
+_phy0 {
+ status = "okay";
+};
+
+_host0_xhci {
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ status = "okay";
+};
diff --git a/configs/neu6a-io-rk3588_defconfig
b/configs/neu6a-io-rk3588_defconfig
index ac281e6539..6e50d06458 100644
--- a/configs/neu6a-io-rk3588_defconfig
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -24,6 +24,7 @@ CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_ATF=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
@@ -33,6 +34,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
@@ -42,6 +44,8 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
@@ -49,4 +53,9 @@ CONFIG_BAUDRATE=150
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_ERRNO_STR=y
diff --git a/configs/neu6b-io-rk3588_defconfig
b/configs/neu6b-io-rk3588_defconfig
index c01e5fb0d0..f2eb650f19 100644
--- a/configs/neu6b-io-rk3588_defconfig
+++ b/configs/neu6b-io-rk3588_defconfig
@@ -24,6 +24,7 @@ CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_ATF=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
@@ -33,6 +34,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
@@ -42,6 +44,8 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
@@ -49,4 +53,9 @@ CONFIG_BAUDRATE=150
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_ERRNO_STR=y
--
2.34.1
[PATCH 1/2] arm64: dts: rockchip: Fix spl-boot-order for edgeble-ncm6b
Edgeble NCM6B SoM has built-in eMMC so make sdhci has first boot
priority.
Fix it for NCM6A, NCM6B SoM.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi | 6 +-
arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi | 11 ++-
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
index dd0058262b..88f3f7eee2 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
@@ -6,12 +6,8 @@
#include "rk3588-u-boot.dtsi"
/ {
- aliases {
- mmc0 =
- };
-
chosen {
- u-boot,spl-boot-order =
+ u-boot,spl-boot-order = "same-as-spl", ,
};
};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
index a45b3f5e86..289578803e 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
@@ -6,11 +6,12 @@
#include "rk3588j-u-boot.dtsi"
/ {
- aliases {
- mmc0 =
- };
-
chosen {
- u-boot,spl-boot-order =
+ u-boot,spl-boot-order = "same-as-spl", ,
};
};
+
+ {
+ bus-width = <4>;
+ status = "okay";
+};
--
2.34.1
Re: [PATCH] mtd: spi-nor-ids: Add Puya Semiconductor chips description
On Mon, Feb 26, 2024 at 3:56 PM Dmitry Dunaev wrote: > > Added support for the Puya Semiconductor chips. > > The datasheet can be found here: > https://www.puyasemi.com/h_xilie715.html > > Signed-off-by: Dmitry Dunaev > --- Applied to u-boot-spi/master
Re: [PATCH v11 0/8] spi-nor: Add parallel and stacked memories support
On Fri, May 24, 2024 at 8:56 PM Tom Rini wrote: > > On Fri, May 24, 2024 at 04:09:00PM +0200, Michal Simek wrote: > > > > > > On 5/7/24 17:48, Tom Rini wrote: > > > On Tue, May 07, 2024 at 04:15:14AM +, Abbarapu, Venkatesh wrote: > > > > > > > + Tom Rini > > > > > > > > Do you have any comments for this series? > > > > > > Seems likely fine. Jagan, do you have time to put this in a PR for > > > -next? Thanks. > > > > No reaction for quite a long time. Can you take it directly to next branch? > > Or do you want me to send you pull request to get this to regression and see > > if this breaks someone else? > > I will (am now) taking a look directly, thanks for the reminder and your > patience. Will clear this weekend, if not if you are already on it. let me know. Jagan,
Re: [PATCH] mtd: spi-nor-ids: Add Puya Semiconductor chips description
On Mon, Feb 26, 2024 at 3:56 PM Dmitry Dunaev wrote: > > Added support for the Puya Semiconductor chips. > > The datasheet can be found here: > https://www.puyasemi.com/h_xilie715.html > > Signed-off-by: Dmitry Dunaev > --- Reviewed-by: Jagan Teki
Re: [PATCH] mtd: spi-nor: Clear Winbond SR3 WPS bit on boot
On Mon, Mar 4, 2024 at 9:46 PM Marek Vasut wrote: > > Some Winbond SPI NORs have special SR3 register which is > used among other things to control whether non-standard > "Individual Block/Sector Write Protection" (WPS bit) > locking scheme is activated. This non-standard locking > scheme is not supported by either U-Boot or Linux SPI > NOR stack so make sure it is disabled, otherwise the > SPI NOR may appear locked for no obvious reason. > > This SR3 WPS appears e.g. on W25Q16FW which has the same ID as > W25Q16DW, but the W25Q16DW does not implement the SR3 WPS bit. > > Signed-off-by: Marek Vasut > --- Applied to u-boot-spi/master
Re: [PATCH v3 00/17] video: dw_hdmi: Support Vendor PHY
Hi Anatolij, On Mon, Feb 19, 2024 at 5:19 PM Jagan Teki wrote: > > Hi Anatolij, > > On Wed, Jan 17, 2024 at 1:22 PM Jagan Teki wrote: > > > > From: Jagan Teki > > > > Unlike RK3399, Sunxi/Meson DW HDMI the new Rockchip SoC Rk3328 would > > support external vendor PHY with DW HDMI chip. > > > > Support this vendor PHY by adding new platform PHY ops via DW HDMI > > driver and call the respective generic phy from platform driver code. > > > > This series tested in RK3328 with 1080p (1920x1080) resolution. > > > > Patch 0001/0005: Support Vendor PHY > > Patch 0006/0008: VOP extension for win, dsp offsets > > Patch 0009/0010: RK3328 VOP, HDMI clocks > > Patch 0011: Rockchip Inno HDMI PHY > > Patch 0012: RK3328 HDMI driver > > Patch 0013: RK3328 VOP driver > > Patch 0014/0017: Enable HDMI Out for RK3328 > > > > Changes for v3: > > - updated phy_ops logic > > - tested in BPI-M64 > > - updated handoff logic for rk3328 > > > > Changes for v2: > > - Use proper cfg function for meson > > - Add VOP cleanup code. > > - Add DCLK get rate > > > > Linux VOP/HDMI out issues seems resolved with explicit WIN0 disable. > > > > Any inputs? > > Jagan. > > > > Jagan Teki (17): > > video: rockchip: hdmi: Detect hpd after controller init > > video: dw_hdmi: Add Vendor PHY handling > > video: dw_hdmi: Extend the HPD detection > > video: dw_hdmi: Add read_hpd hook > > video: dw_hdmi: Add setup_hpd hook > > video: rockchip: vop: Simplify rkvop_enable > > video: rockchip: vop: Add win offset support > > video: rockchip: vop: Add dsp offset support > > clk: rockchip: rk3328: Add VOP clk support > > clk: rk3328: Add get hdmiphy clock > > phy: rockchip: Add Rockchip INNO HDMI PHY driver > > video: rockchip: Add rk3328 hdmi support > > video: rockchip: Add rk3328 vop support > > ARM: dts: rk3328: Enable VOP for bootph-all > > rockchip: Enable preconsole for rk3328 > > configs: evb-rk3328: Enable vidconsole for rk3328 > > configs: Enable HDMI Out for ROC-RK3328-CC > > Any comments on this? Or is it okay if I send a PR for this? Any update? Jagan.
Re: [PATCH v3 14/17] ARM: dts: rk3328: Enable VOP for bootph-all
Hi Jonas,
On Mon, Feb 19, 2024 at 10:51 PM Jonas Karlman wrote:
>
> Hi Jagan,
>
> On 2024-01-17 08:51, Jagan Teki wrote:
> > Model: Firefly roc-rk3328-cc
> > DRAM: 1 GiB (effective 1022 MiB)
> > Video device 'vop@ff37' cannot allocate frame buffer memory -ensure the
> > device is set up before relocation
> > Error binding driver 'rockchip_rk3328_vop': -28
> > Some drivers failed to bind
> > initcall sequence 3ffcd5e8 failed at call 0021a5c4 (err=-28)
> > ### ERROR ### Please RESET the board ###
> >
> > Signed-off-by: Jagan Teki
> > ---
> > Changes for v3, v2:
> > - none
> >
> > arch/arm/dts/rk3328-u-boot.dtsi | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/dts/rk3328-u-boot.dtsi
> > b/arch/arm/dts/rk3328-u-boot.dtsi
> > index a9f2536de2..5258fec566 100644
> > --- a/arch/arm/dts/rk3328-u-boot.dtsi
> > +++ b/arch/arm/dts/rk3328-u-boot.dtsi
> > @@ -68,3 +68,7 @@
> > {
> > bootph-all;
> > };
> > +
> > + {
> > + bootph-all;
>
> bootph-some-ram is better, TPL or SPL does not need or use the vop node.
>
> I am working on a cleanup series for rk3399 and that series will include
> a change from bootph-all to bootph-some-ram of vop nodes on rk3399.
Sure, we can even update the same later as these were in the ML from
months ago. I will mark them as well.
Jagan.
Re: [PATCH v3 00/17] video: dw_hdmi: Support Vendor PHY
Hi Anatolij, On Wed, Jan 17, 2024 at 1:22 PM Jagan Teki wrote: > > From: Jagan Teki > > Unlike RK3399, Sunxi/Meson DW HDMI the new Rockchip SoC Rk3328 would > support external vendor PHY with DW HDMI chip. > > Support this vendor PHY by adding new platform PHY ops via DW HDMI > driver and call the respective generic phy from platform driver code. > > This series tested in RK3328 with 1080p (1920x1080) resolution. > > Patch 0001/0005: Support Vendor PHY > Patch 0006/0008: VOP extension for win, dsp offsets > Patch 0009/0010: RK3328 VOP, HDMI clocks > Patch 0011: Rockchip Inno HDMI PHY > Patch 0012: RK3328 HDMI driver > Patch 0013: RK3328 VOP driver > Patch 0014/0017: Enable HDMI Out for RK3328 > > Changes for v3: > - updated phy_ops logic > - tested in BPI-M64 > - updated handoff logic for rk3328 > > Changes for v2: > - Use proper cfg function for meson > - Add VOP cleanup code. > - Add DCLK get rate > > Linux VOP/HDMI out issues seems resolved with explicit WIN0 disable. > > Any inputs? > Jagan. > > Jagan Teki (17): > video: rockchip: hdmi: Detect hpd after controller init > video: dw_hdmi: Add Vendor PHY handling > video: dw_hdmi: Extend the HPD detection > video: dw_hdmi: Add read_hpd hook > video: dw_hdmi: Add setup_hpd hook > video: rockchip: vop: Simplify rkvop_enable > video: rockchip: vop: Add win offset support > video: rockchip: vop: Add dsp offset support > clk: rockchip: rk3328: Add VOP clk support > clk: rk3328: Add get hdmiphy clock > phy: rockchip: Add Rockchip INNO HDMI PHY driver > video: rockchip: Add rk3328 hdmi support > video: rockchip: Add rk3328 vop support > ARM: dts: rk3328: Enable VOP for bootph-all > rockchip: Enable preconsole for rk3328 > configs: evb-rk3328: Enable vidconsole for rk3328 > configs: Enable HDMI Out for ROC-RK3328-CC Any comments on this? Or is it okay if I send a PR for this? Jagan.
Re: [PATCH v10 4/8] spi: spi-uclass: Read chipselect and restrict capabilities
On Tue, Jan 30, 2024 at 10:15 AM Venkatesh Yadav Abbarapu wrote: > > From: Ashok Reddy Soma > > Read chipselect properties from DT which are populated using 'reg' > property and save it in plat->cs[] array for later use. > > Also read multi chipselect capability which is used for > parallel-memories and return errors if they are passed on using DT but > driver is not capable of handling it. Why would the SPI controller need to know about multi chip select capabilities of one slave time called spi flash. We need a way to abstract the slave capabilities from the controller point-of-view. Jagan.
Pull request: u-boot-spi/master
Hi Tom, Please pull this PR. Summary: - Support Infineon S28HS02GT (Takahiro) CI: - https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/19467 thanks, Jagan. The following changes since commit 526a865fe4fea59fb2638726c26e39557eb97fdd: Merge branch 'master-cleanup' of https://source.denx.de/u-boot/custodians/u-boot-sh (2024-01-27 20:43:20 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-spi master for you to fetch changes up to 16dd10951015183f87b8202b8d4c8617da4f6d44: mtd: spi-nor-ids: Add Infineon(Cypress) s28hs02gt ID (2024-01-29 19:34:17 +0530) Maksim Kiselev (1): spi: dw: add check for Rx FIFO overflow Ssunk (1): mtd: spi: spi-nor-ids: Add more XM25Q series chips Takahiro Kuwano (9): mtd: spi-nor-core: Clean up macros for Infineon(Cypress) S25 and S28 mtd: spi-nor-core: Consolidate non-uniform erase helpers for S25 and S28 mtd: spi-nor-core: Rework spansion_read_any_reg() to support Octal DTR mode mtd: spi-nor-core: Use CLPEF(0x82) as alternative to CLSR(0x30) for S25 and S28 mtd: spi-nor-core: Rework s25_mdp_ready() to support Octal DTR mode mtd: spi-nor-core: Consolidate setup() hook for Infineon(Cypress) S25 and S28 mtd: spi-nor-core: Consolidate post_bfpt_fixup() for Infineon(Cypress) S25 and S28 mtd: spi-nor-core: Rework spi_nor_cypress_octal_dtr_enable() mtd: spi-nor-ids: Add Infineon(Cypress) s28hs02gt ID Tejas Bhumkar (2): mtd: spi-nor-ids: Add is25lx512 chip spi: cadence_qspi: Address the comparison failure for 0-8 bytes of data drivers/mtd/spi/spi-nor-core.c| 224 +++--- drivers/mtd/spi/spi-nor-ids.c | 7 ++ drivers/spi/cadence_ospi_versal.c | 3 - drivers/spi/cadence_qspi.h| 4 + drivers/spi/cadence_qspi_apb.c| 3 + drivers/spi/designware_spi.c | 18 ++- include/linux/mtd/spi-nor.h | 14 +-- 7 files changed, 119 insertions(+), 154 deletions(-)
Re: [PATCH v2 07/11] mtd: spi: renesas: Add R8A779H0 V4M support
On Sun, Jan 28, 2024 at 9:25 PM Marek Vasut wrote: > > From: Hai Pham > > Support RPC SPI on R8A779H0 V4M SoC. > > Reviewed-by: Paul Barker > Signed-off-by: Hai Pham > --- > Cc: Jagan Teki > Cc: Paul Barker > --- Reviewed-by: Jagan Teki
Re: [PATCH v2 07/11] mtd: spi: renesas: Add R8A779H0 V4M support
On Mon, Jan 29, 2024 at 6:57 PM Marek Vasut wrote: > > On 1/29/24 12:52, Jagan Teki wrote: > > On Sun, Jan 28, 2024 at 9:25 PM Marek Vasut > > wrote: > >> > >> From: Hai Pham > >> > >> Support RPC SPI on R8A779H0 V4M SoC. > >> > >> Reviewed-by: Paul Barker > >> Signed-off-by: Hai Pham > >> --- > >> Cc: Jagan Teki > >> Cc: Paul Barker > >> --- > > > > Applied to u-boot-spi/master > > I don't think this will build without 06/11 macro addition, so I'll pull > this via u-boot-sh tree if that's OK with you ? > > I could use a RB though . Yeah. Got the runner failure. Please proceed to pick this vi -sh Thanks, Jagan.
Re: [PATCH v2 00/30] Fix issues with QSPI and OSPI compare failures
On Wed, Dec 6, 2023 at 3:02 PM Tejas Bhumkar wrote: > > A set of patches has been developed to resolve concerns regarding data > integrity failures in QSPI and OSPI for the Versal, Versal NET, Zynq, > and ZynqMP platforms. > > The series has undergone testing with flashes on the default setup, > and comprehensive testing is currently underway to test the series > with all available flash parts. > > These patches are built upon the v5 series, which can be found at the > following link: > https://lore.kernel.org/all/20231201031839.239567-1-venkatesh.abbar...@amd.com/ > > Changes in v2: > - Removed the SPI_NOR_HAS_TB flag for gd25lx256e and is25wx256 flashes > since it already exists in a tree. > > Algapally Santosh Sagar (1): > mtd: spi-nor-ids: Add support for W25Q02NW > > Ashok Reddy Soma (10): > mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes > mtd: spi-nor: Add support for cross die read in dual flash > configuration > mtd: spi-nor: Enable DTR octal flash program > mtd: spi-nor: Send write disable cmd after every write enable > mtd: spi-nor: Check SNOR_F_IO_MODE_EN_VOLATILE only if SFDP is enabled > spi: cadence_qspi: Set tshsl_ns to at least one sclk_ns > spi: cadence_qspi: Clean up registers in init > spi: cadence_qspi: Initialize read and write watermark registers > spi: cadence_qspi: Enable ECO bit for higher frequencies > spi: cadence_qspi: Write aligned byte length to ahbbase > > T Karthik Reddy (9): > mtd: spi-nor: Add config to enable flash DTR > mtd: spi-nor-core: Set dummy buswidth equal to data buswidth > spi: mtd: Use split reads if multi-die flag is set > mtd: spi-nor: program quad enable bit for winbond flashes > spi: cadence_qspi: Setup ddr mode in cadence qspi driver > spi: cadence-qspi: Switch SDR/DTR using SPI_FLASH_DTR_ENABLE config > spi: cadence_ospi_versal: ospi ddr changes in cadence ospi versal > driver > spi: cadence_qspi: Add spi mem dtr support ops > mtd: spi-nor: Add block protection support for micron flashes > > Tejas Bhumkar (5): > arm64: versal: Enable defconfig for Micron octal flashes > mtd: spi-nor: Update erase operation function > spi: cadence_qspi: Fix versal ospi indirect write timed out issue > arm64: versal: Enable soft reset support for xspi flashes > arm64: versal: Enable octal DTR mode > > Venkatesh Yadav Abbarapu (5): > mtd: spi-nor: Update block protection flags for flash parts > mtd: spi-nor: Add support for locking on Macronix nor flashes > mtd: spi-nor: Add support for locking on ISSI nor flashes > mtd: spi-nor: Add support for locking on GIGADEVICE nor flashes > mtd: spi-nor: Add support for locking on Spansion nor flashes Look like there are 3 or more topics are covered in single patch set, please break them and send separate series. Jagan
Re: [PATCH v2 01/30] mtd: spi-nor: Add config to enable flash DTR
On Sun, Dec 31, 2023 at 11:27 PM Bhumkar, Tejas Arvind wrote: > > [AMD Official Use Only - General] > > Hi Jagan, > > > -Original Message- > > From: Jagan Teki > > Sent: Wednesday, December 20, 2023 1:00 PM > > To: Bhumkar, Tejas Arvind > > Cc: u-boot@lists.denx.de; joe.hershber...@ni.com; rfried@gmail.com; > > Simek, Michal ; vigne...@ti.com; g...@xilinx.com; T > > Karthik Reddy > > Subject: Re: [PATCH v2 01/30] mtd: spi-nor: Add config to enable flash DTR > > > > Caution: This message originated from an External Source. Use proper caution > > when opening attachments, clicking links, or responding. > > > > > > On Wed, Dec 6, 2023 at 3:02 PM Tejas Bhumkar > > wrote: > > > > > > From: T Karthik Reddy > > > > > > The spi-nor framework will set up the flash parameters by reading the > > > flash id table flags, which include cmd opcodes, address width, dummy > > > bytes, and bus width. In case, flash supports octal DTR mode and the > > > controller does not support the DTR. There is no process to switch > > > back to SDR mode. > > > To avoid this issue, create a Kconfig option SPI_FLASH_DTR_ENABLE to > > > explicitly specify to enable/disable flash DTR support. > > > This config is disabled by default. > > > > We cannot control controller fixup in flash, DTR read based on the DTR flag > > I don't > > think adding extra CONFIG to hack the controller with impact is. > [Tejas] : By default, this configuration is set to Disabled. It serves as a > convenient option for operating the flash > between SDR and DDR without requiring any adjustments to the nor-id > table flags. This look like controller hack to me, may be a clear negotiation b/w controller and flag might have proper solution. Jagan.
Re: [PATCH v2 9/9] mtd: spi-nor-ids: Add Infineon(Cypress) s28hs02gt ID
On Fri, Dec 22, 2023 at 11:17 AM wrote: > > From: Takahiro Kuwano > > Infineon(Cypress) S28HS02GT is 1.8V, 2Gb (256MB) NOR Flash memory with > Octal interface. It is a dual-die package parts and has same features > with existing S28 series. > > Signed-off-by: Takahiro Kuwano > --- Reviewed-by: Jagan Teki
Re: [PATCH v2 8/9] mtd: spi-nor-core: Rework spi_nor_cypress_octal_dtr_enable()
On Fri, Dec 22, 2023 at 11:16 AM wrote: > > From: Takahiro Kuwano > > Enabling Octal DTR mode in multi-die package parts requires reister setup > for each die. That can be done by simple for-loop. write_enable() takes > effect to all die at once so we can call it before the loop. Besides we > can replace spi_mem_exec_op() calls with spansion_read/write_any_reg(). > And finally, we must mask CFR2V[7:4] when changing dummy cycles, as > CFR2V[7] indicates current addressing mode and that should be 1 (4-byte > address mode) for multi-die package parts. > > Signed-off-by: Takahiro Kuwano > --- Reviewed-by: Jagan Teki
Re: [PATCH v2 7/9] mtd: spi-nor-core: Consolidate post_bfpt_fixup() for Infineon(Cypress) S25 and S28
On Fri, Dec 22, 2023 at 11:16 AM wrote: > > From: Takahiro Kuwano > > s28hx_t_post_bfpt_fixup() fixes erase opcode, erase size, and page size. > s25_post_bfpt_fixup() is doing same thing including multi-die support. > We can consolidate s28hx_t_post_bfpt_fixup() and s25_post_bfpt_fixup() > into one named s25_s28_post_bfpt_fixup(). > > In s25_s28_post_bfpt_fixup(), set_4byte() is called to force the device to > be 4-byte addressing mode. In S28HS02GT datasheet, the B7 opcode is missing > but it works actually (confirmed). > > Signed-off-by: Takahiro Kuwano > --- Reviewed-by: Jagan Teki
Re: [PATCH v2 6/9] mtd: spi-nor-core: Consolidate setup() hook for Infineon(Cypress) S25 and S28
On Fri, Dec 22, 2023 at 11:16 AM wrote: > > From: Takahiro Kuwano > > s28hx_t_setup() only checks sector layout setting. To support multi-die > package parts like S28HS02GT, it needs to check device size and assign > ready() hook for multi-die package parts. These are covered in s25_setup() > so we can consolidate s28hx_t_setup() and s25_setup() into one named > s25_s28_setup(). > > spi_nor_wait_till_ready() at the beginning of s28hx_t_setup() can be > removed since there is no op that makes device busy state before setup. > > Signed-off-by: Takahiro Kuwano > --- Reviewed-by: Jagan Teki
Re: [PATCH v2 5/9] mtd: spi-nor-core: Rework s25_mdp_ready() to support Octal DTR mode
On Fri, Dec 22, 2023 at 11:16 AM wrote: > > From: Takahiro Kuwano > > s25_mdp_ready() handles status polling for multi-die package parts that > requires to read and check status register for each die. To support > S28HS02GT(dual-die package with Octal DTR support), rename function and > use nor->rdsr_dummy in octal DTR mode. > > Signed-off-by: Takahiro Kuwano > --- Reviewed-by: Jagan Teki
Re: [PATCH v2 4/9] mtd: spi-nor-core: Use CLPEF(0x82) as alternative to CLSR(0x30) for S25 and S28
On Fri, Dec 22, 2023 at 11:16 AM wrote: > > From: Takahiro Kuwano > > Infineon(Cypress) S28Hx-T family does not support legacy CLSR(0x30) opcode. > Instead, it supports CLPEF(0x82) which has the same functionality as CLSR. > spansion_sr_ready() is for multi-die package parts including S28HS02GT, so > we need to use CLPEF instead of CLSR. > > This change does not affect to S25x02GT which uses spansion_sr_ready() as > S25Hx-T family also supports CLPEF(0x82) as well as CLSR(0x30). > > Signed-off-by: Takahiro Kuwano > --- Reviewed-by: Jagan Teki
Re: [PATCH v2 3/9] mtd: spi-nor-core: Rework spansion_read_any_reg() to support Octal DTR mode
On Fri, Dec 22, 2023 at 11:16 AM wrote: > > From: Takahiro Kuwano > > In Infineon multi-die package parts, we need to use Read Any Register op > to read status register in 2nd or further die. Infineon S28HS02GT is > dual-die package and supports Octal DTR interface. To support this, > spansion_read_any_reg() needs to be reworked. Implementation is similar > to existing read_sr() that already supports Octal DTR mode. > > Signed-off-by: Takahiro Kuwano > --- Reviewed-by: Jagan Teki
Re: [PATCH v2 2/9] mtd: spi-nor-core: Consolidate non-uniform erase helpers for S25 and S28
On Fri, Dec 22, 2023 at 11:16 AM wrote: > > From: Takahiro Kuwano > > s25_erase_non_uniform() and s28hx_t_erase_uniform() support hybrid sector > layout (32 x 4KB sectors overlaid at bottom address) and doing same thing. > Consolidate them into single helper named s25_s28_erase_non_uniform(). > > Signed-off-by: Takahiro Kuwano > --- Reviewed-by: Jagan Teki
Re: [PATCH v2 1/9] mtd: spi-nor-core: Clean up macros for Infineon(Cypress) S25 and S28
On Fri, Dec 22, 2023 at 11:16 AM wrote: > > From: Takahiro Kuwano > > Some macro definitions used in Infineon(Cypress) S25 and S28 series are > redundant and some have inconsistent prefix. This patch removes > redundant ones and renames some to have same prefix as others. > > Signed-off-by: Takahiro Kuwano > --- Reviewed-by: Jagan Teki
Re: [PATCH] Add XMC XM25QH128C/XM25QH256C/XM25QU256C/XM25QH512C/XM25QU512C site: https://www.xmcwh.com/site/product
On Tue, Jan 16, 2024 at 11:09 AM Ssunk wrote: > > Signed-off-by: Kankan Sun > --- Applied to u-boot-spi/master
Re: [PATCH v2] spi: cadence_qspi: Address the comparison failure for 0-8 bytes of data
On Sun, Jan 28, 2024 at 12:08 PM Tejas Bhumkar wrote: > > The current implementation encounters issues when testing data ranging > from 0 to 8 bytes. This was confirmed through testing with both ISSI > (IS25WX256) and Micron (MT35XU02G) Flash exclusively in SDR mode. > > Upon investigation, it was observed that utilizing the > "SPI_NOR_OCTAL_READ" flag and attempting to read less than 8 bytes in > STIG mode results in a read failure, leading to a compare test failure. > > To resolve this issue, the CMD_4BYTE_FAST_READ opcode is now utilized > instead of CMD_4BYTE_OCTAL_READ, specifically in SDR mode. > > This is based on patch series: > https://lore.kernel.org/all/cover.1701853668.git.tejas.arvind.bhum...@amd.com/ > > Signed-off-by: Tejas Bhumkar > --- Applied to u-boot-spi/master
Re: [PATCH] mtd: spinand: Add support for XTX XT26xxxDxxxxx
On Tue, Dec 26, 2023 at 1:28 PM Bruce Suen wrote: > > Add Support XTX Technology XT26G01DX, XT26G11DX, XT26Q01DX, > XT26G02DX, XT26G12DX, XT26Q02DX, XT26G04DX, and > XT26Q04DX SPI NAND. > > These are 3V/1.8V 1G/2G/4Gbit serial SLC NAND flash device with on-die > ECC(8bit strength per 512bytes). > > Datasheet Links: > - http://www.xtxtech.com/download/?AId=458 > - http://www.xtxtech.com/download/?AId=495 > > Signed-off-by: Bruce Suen > --- This won't apply on my spi tree, maybe some out-of-master changes are stopping. Jagan.
Re: [PATCH] mtd: spi-nor: ids: Add is25lx512 chip
On Wed, Dec 27, 2023 at 9:58 PM Tejas Bhumkar wrote: > > Added support for the ISSI OSPI flash part IS25LX512M. > Initial testing was performed on the Tenzing-se1 board using > SDR mode, covering basic erase, write, and readback operations. > > Signed-off-by: Tejas Bhumkar > --- Applied to u-boot-spi/master
Re: [PATCH v2 07/11] mtd: spi: renesas: Add R8A779H0 V4M support
On Sun, Jan 28, 2024 at 9:25 PM Marek Vasut wrote: > > From: Hai Pham > > Support RPC SPI on R8A779H0 V4M SoC. > > Reviewed-by: Paul Barker > Signed-off-by: Hai Pham > --- > Cc: Jagan Teki > Cc: Paul Barker > --- Applied to u-boot-spi/master
Re: [PATCH v2] spi: dw: add check for Rx FIFO overflow
On Thu, Dec 21, 2023 at 3:43 PM Maksim Kiselev wrote: > > If even one byte is lost due to Rx FIFO overflow then we will never > exit the read loop. Because the (priv->rx != priv->rx_end) condition will > be always true. > > Let's check if Rx FIFO overflow occurred and exit the read loop > in this case. > > Signed-off-by: Maksim Kiselev > --- Applied to u-boot-spi/master
Re: Black and White Artifact on BMP (24BPP) logo during boot
Hi Kever, On Thu, Jan 18, 2024 at 9:09 AM Kever Yang wrote: > > Hi Jagan, > > Have you check the memory area, does it maybe overlap with other > area? eg. heap, stack, malloc area and etc. Start with GD all memory map seems proper before and after relocation. I did load U-Boot proper of rockchip with mainline and vice-versa. The issue persists. Jagan.
[PATCH v3 17/17] configs: Enable HDMI Out for ROC-RK3328-CC
U-Boot 2024.01-00901-g75d07e0e6e-dirty (Jan 17 2024 - 12:50:56 +0530) Model: Firefly roc-rk3328-cc DRAM: 4 GiB PMIC: RK8050 (on=0x40, off=0x00) Core: 236 devices, 26 uclasses, devicetree: separate MMC: mmc@ff50: 1, mmc@ff52: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment In:serial,usbkbd Out: serial,vidconsole Err: serial,vidconsole Model: Firefly roc-rk3328-cc Net: eth0: ethernet@ff54 Hit any key to stop autoboot: 0 => dm tree Class Index Probed DriverName --- root 0 [ + ] root_driver root_driver firmware 0 [ ] psci |-- psci clk 0 [ + ] fixed_clock |-- xin24m syscon0 [ + ] rockchip_rk3328_grf |-- syscon@ff10 serial0 [ + ] ns16550_serial|-- serial@ff13 i2c 0 [ + ] rockchip_rk3066_i2c |-- i2c@ff16 pmic 0 [ + ] rockchip_rk805| `-- pmic@18 sysreset 0 [ ] rk8xx_sysreset| |-- rk8xx_sysreset regulator 0 [ + ] rk8xx_buck| |-- DCDC_REG1 regulator 1 [ + ] rk8xx_buck| |-- DCDC_REG2 regulator 2 [ + ] rk8xx_buck| |-- DCDC_REG3 regulator 3 [ + ] rk8xx_buck| |-- DCDC_REG4 regulator 4 [ + ] rk8xx_ldo | |-- LDO_REG1 regulator 5 [ + ] rk8xx_ldo | |-- LDO_REG2 regulator 6 [ + ] rk8xx_ldo | `-- LDO_REG3 video 0 [ + ] rk3328_vop|-- vop@ff37 vidconsole0 [ + ] vidconsole0 | `-- vop@ff37.vidconsole0 display 0 [ + ] rk3328_hdmi_rockchip |-- hdmi@ff3c phy 0 [ + ] inno_hdmi_phy |-- phy@ff43 clk 1 [ + ] rockchip_rk3328_cru |-- clock-controller@ff44 sysreset 1 [ ] rockchip_sysreset | |-- sysreset reset 0 [ + ] rockchip_reset| `-- reset Signed-off-by: Jagan Teki --- Changes for v3, v2: - none configs/roc-cc-rk3328_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 4ac3c9403b..4eef9016dc 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -79,6 +79,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_HDMI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y @@ -114,6 +115,10 @@ CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y -- 2.25.1
[PATCH v3 16/17] configs: evb-rk3328: Enable vidconsole for rk3328
Enable video console for Rockchip RK3328. Signed-off-by: Jagan Teki --- Changes for v3, v2: - none include/configs/evb_rk3328.h| 5 + include/configs/rk3328_common.h | 1 + 2 files changed, 6 insertions(+) diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h index d10e5b1d2e..c985080f7b 100644 --- a/include/configs/evb_rk3328.h +++ b/include/configs/evb_rk3328.h @@ -6,6 +6,11 @@ #ifndef __EVB_RK3328_H #define __EVB_RK3328_H +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + #include #endif diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index e920ec7e5d..2c40674b22 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -26,6 +26,7 @@ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ "boot_targets=" BOOT_TARGETS "\0" #endif -- 2.25.1
[PATCH v3 15/17] rockchip: Enable preconsole for rk3328
Enable and set the start address of pre-console buffer for RK3328. Signed-off-by: Jagan Teki --- Changes for v3, v2: - none arch/arm/mach-rockchip/Kconfig | 1 + common/Kconfig | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b577a911e7..60f403fe74 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -179,6 +179,7 @@ config ROCKCHIP_RK3328 select SUPPORT_TPL select TPL select TPL_NEEDS_SEPARATE_STACK if TPL + imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_SDRAM_COMMON imply SPL_ROCKCHIP_COMMON_BOARD diff --git a/common/Kconfig b/common/Kconfig index 0283701f1d..5e3070e925 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -231,7 +231,7 @@ config PRE_CON_BUF_ADDR default 0x2f00 if ARCH_SUNXI && MACH_SUN9I default 0x4f00 if ARCH_SUNXI && !MACH_SUN9I default 0x0f00 if ROCKCHIP_RK3288 - default 0x0f20 if ROCKCHIP_RK3399 + default 0x0f20 if ROCKCHIP_RK3399 || ROCKCHIP_RK3328 help This sets the start address of the pre-console buffer. This must be in available memory and is accessed before relocation and -- 2.25.1
[PATCH v3 14/17] ARM: dts: rk3328: Enable VOP for bootph-all
Model: Firefly roc-rk3328-cc
DRAM: 1 GiB (effective 1022 MiB)
Video device 'vop@ff37' cannot allocate frame buffer memory -ensure the
device is set up before relocation
Error binding driver 'rockchip_rk3328_vop': -28
Some drivers failed to bind
initcall sequence 3ffcd5e8 failed at call 0021a5c4 (err=-28)
### ERROR ### Please RESET the board ###
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
arch/arm/dts/rk3328-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index a9f2536de2..5258fec566 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -68,3 +68,7 @@
{
bootph-all;
};
+
+ {
+ bootph-all;
+};
--
2.25.1
[PATCH v3 13/17] video: rockchip: Add rk3328 vop support
From: Jagan Teki
Add support for Rockchip RK3328 VOP.
Require VOP cleanup before handoff to Linux by writing reset values to
WIN registers. Without this Linux VOP trigger page fault as below
[0.752016] Loading compiled-in X.509 certificates
[0.787796] inno_hdmi_phy_rk3328_clk_recalc_rate: parent 2400
[0.788391] inno-hdmi-phy ff43.phy: inno_hdmi_phy_rk3328_clk_recalc_rate
rate 14850 vco 14850
[0.798353] rockchip-drm display-subsystem: bound ff37.vop (ops
vop_component_ops)
[0.799403] dwhdmi-rockchip ff3c.hdmi: supply avdd-0v9 not found, using
dummy regulator
[0.800288] rk_iommu ff373f00.iommu: Enable stall request timed out, status:
0x4b
[0.801131] dwhdmi-rockchip ff3c.hdmi: supply avdd-1v8 not found, using
dummy regulator
[0.802056] rk_iommu ff373f00.iommu: Disable paging request timed out,
status: 0x4b
[0.803233] dwhdmi-rockchip ff3c.hdmi: Detected HDMI TX controller
v2.11a with HDCP (inno_dw_hdmi_phy2)
[0.805355] dwhdmi-rockchip ff3c.hdmi: registered DesignWare HDMI I2C
bus driver
[0.808769] rockchip-drm display-subsystem: bound ff3c.hdmi (ops
dw_hdmi_rockchip_ops)
[0.810869] [drm] Initialized rockchip 1.0.0 20140818 for display-subsystem
on minor 0
Signed-off-by: Jagan Teki
---
Changes for v3:
- Add WIN0 disable at remove
Changes for v2:
- Add VOP cleanup
- Update commit
drivers/video/rockchip/Makefile | 1 +
drivers/video/rockchip/rk3328_vop.c | 83 +
2 files changed, 84 insertions(+)
create mode 100644 drivers/video/rockchip/rk3328_vop.c
diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
index 4991303c73..f55beceebf 100644
--- a/drivers/video/rockchip/Makefile
+++ b/drivers/video/rockchip/Makefile
@@ -6,6 +6,7 @@
ifdef CONFIG_VIDEO_ROCKCHIP
obj-y += rk_vop.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o
+obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o
obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
diff --git a/drivers/video/rockchip/rk3328_vop.c
b/drivers/video/rockchip/rk3328_vop.c
new file mode 100644
index 00..55233f19ee
--- /dev/null
+++ b/drivers/video/rockchip/rk3328_vop.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include
+#include
+#include
+#include "rk_vop.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void rk3328_set_pin_polarity(struct udevice *dev,
+ enum vop_modes mode, u32 polarity)
+{
+ struct rk_vop_priv *priv = dev_get_priv(dev);
+ struct rk3288_vop *regs = priv->regs;
+
+ switch (mode) {
+ case VOP_MODE_HDMI:
+ clrsetbits_le32(>dsp_ctrl1,
+ M_RK3399_DSP_HDMI_POL,
+ V_RK3399_DSP_HDMI_POL(polarity));
+ break;
+ default:
+ debug("%s: unsupported output mode %x\n", __func__, mode);
+ }
+}
+
+static int rk3328_vop_probe(struct udevice *dev)
+{
+ /* Before relocation we don't need to do anything */
+ if (!(gd->flags & GD_FLG_RELOC))
+ return 0;
+
+ return rk_vop_probe(dev);
+}
+
+static int rk3328_vop_remove(struct udevice *dev)
+{
+ struct rk_vop_priv *priv = dev_get_priv(dev);
+ struct rk3288_vop *regs = priv->regs;
+ struct rk3288_vop *win_regs = priv->regs + priv->win_offset;
+
+ /* FIXME: Explicit disabling of WIN0 is needed to avoid iommu
+* page-fault in Linux, better handling of iommu-address in
+* Linux might drop this.
+*/
+ clrbits_le32(_regs->win0_ctrl0, M_WIN0_EN);
+ writel(0x01, >reg_cfg_done);
+
+ return 0;
+}
+
+struct rkvop_driverdata rk3328_driverdata = {
+ .dsp_offset = 0x490,
+ .win_offset = 0xd0,
+ .features = VOP_FEATURE_OUTPUT_10BIT,
+ .set_pin_polarity = rk3328_set_pin_polarity,
+};
+
+static const struct udevice_id rk3328_vop_ids[] = {
+ {
+ .compatible = "rockchip,rk3328-vop",
+ .data = (ulong)_driverdata
+ },
+ { /* sentile */ }
+};
+
+static const struct video_ops rk3328_vop_ops = {
+};
+
+U_BOOT_DRIVER(rk3328_vop) = {
+ .name = "rk3328_vop",
+ .id = UCLASS_VIDEO,
+ .of_match = rk3328_vop_ids,
+ .ops= _vop_ops,
+ .bind = rk_vop_bind,
+ .probe = rk3328_vop_probe,
+ .remove = rk3328_vop_remove,
+ .priv_auto = sizeof(struct rk_vop_priv),
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
+};
--
2.25.1
[PATCH v3 12/17] video: rockchip: Add rk3328 hdmi support
From: Jagan Teki
Add Rockchip RK3328 HDMI Out driver.
Signed-off-by: Jagan Teki
---
Changes for v3:
- drop data
Changes for v2:
- none
drivers/video/rockchip/Makefile | 1 +
drivers/video/rockchip/rk3328_hdmi.c | 126 +++
drivers/video/rockchip/rk_hdmi.h | 3 +
3 files changed, 130 insertions(+)
create mode 100644 drivers/video/rockchip/rk3328_hdmi.c
diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
index 8128289cc8..4991303c73 100644
--- a/drivers/video/rockchip/Makefile
+++ b/drivers/video/rockchip/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o
obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
obj-hdmi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_hdmi.o
+obj-hdmi-$(CONFIG_ROCKCHIP_RK3328) += rk3328_hdmi.o
obj-hdmi-$(CONFIG_ROCKCHIP_RK3399) += rk3399_hdmi.o
obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o $(obj-hdmi-y)
obj-mipi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_mipi.o
diff --git a/drivers/video/rockchip/rk3328_hdmi.c
b/drivers/video/rockchip/rk3328_hdmi.c
new file mode 100644
index 00..763669c09b
--- /dev/null
+++ b/drivers/video/rockchip/rk3328_hdmi.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "rk_hdmi.h"
+
+#define RK3328_IO_3V_DOMAIN (7 << (9 + 16))
+#define RK3328_IO_5V_DOMAIN ((7 << 9) | (3 << (9 + 16)))
+#define RK3328_IO_DDC_IN_MSK ((3 << 10) | (3 << (10 + 16)))
+#define RK3328_IO_CTRL_BY_HDMI ((1 << 13) | (1 << (13 + 16)))
+
+static int rk3328_hdmi_enable(struct udevice *dev, int panel_bpp,
+ const struct display_timing *edid)
+{
+ struct rk_hdmi_priv *priv = dev_get_priv(dev);
+
+ return dw_hdmi_enable(>hdmi, edid);
+}
+
+static int rk3328_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint pixclock)
+{
+ struct rk_hdmi_priv *priv = container_of(hdmi, struct rk_hdmi_priv,
hdmi);
+ int ret;
+
+ ret = generic_phy_init(>phy);
+ if (ret) {
+ printf("failed to init phy (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = generic_phy_power_on(>phy);
+ if (ret) {
+ printf("failed to power on phy (ret=%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void rk3328_dw_hdmi_setup_hpd(struct dw_hdmi *hdmi)
+{
+ struct rk_hdmi_priv *priv = container_of(hdmi, struct rk_hdmi_priv,
hdmi);
+ struct rk3328_grf_regs *grf = priv->grf;
+
+ writel(RK3328_IO_DDC_IN_MSK, >soc_con[2]);
+ writel(RK3328_IO_CTRL_BY_HDMI, >soc_con[3]);
+}
+
+static void rk3328_dw_hdmi_read_hpd(struct dw_hdmi *hdmi, bool hpd_status)
+{
+ struct rk_hdmi_priv *priv = container_of(hdmi, struct rk_hdmi_priv,
hdmi);
+ struct rk3328_grf_regs *grf = priv->grf;
+
+ if (hpd_status)
+ writel(RK3328_IO_5V_DOMAIN, >soc_con[4]);
+ else
+ writel(RK3328_IO_3V_DOMAIN, >soc_con[4]);
+}
+
+static const struct dw_hdmi_phy_ops dw_hdmi_rk3328_phy_ops = {
+ .phy_set = rk3328_dw_hdmi_phy_cfg,
+ .setup_hpd = rk3328_dw_hdmi_setup_hpd,
+ .read_hpd = rk3328_dw_hdmi_read_hpd,
+};
+
+static int rk3328_hdmi_of_to_plat(struct udevice *dev)
+{
+ struct rk_hdmi_priv *priv = dev_get_priv(dev);
+ struct dw_hdmi *hdmi = >hdmi;
+
+ hdmi->i2c_clk_high = 0x71;
+ hdmi->i2c_clk_low = 0x76;
+
+ rk_hdmi_of_to_plat(dev);
+
+ hdmi->ops = _hdmi_rk3328_phy_ops;
+
+ return 0;
+}
+
+static int rk3328_hdmi_probe(struct udevice *dev)
+{
+ struct rk_hdmi_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = generic_phy_get_by_name(dev, "hdmi", >phy);
+ if (ret) {
+ printf("failed to get hdmi phy\n");
+ return ret;
+ };
+
+ ret = rk_hdmi_probe(dev);
+ if (ret) {
+ printf("failed to probe rk hdmi\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct dm_display_ops rk3328_hdmi_ops = {
+ .read_edid = rk_hdmi_read_edid,
+ .enable = rk3328_hdmi_enable,
+};
+
+static const struct udevice_id rk3328_hdmi_ids[] = {
+ { .compatible = "rockchip,rk3328-dw-hdmi" },
+ { }
+};
+
+U_BOOT_DRIVER(rk3328_hdmi_rockchip) = {
+ .name = "rk3328_hdmi_rockchip",
+ .id = UCLASS_DISPLAY,
+ .of_match = rk3328_hdmi_ids,
+ .ops = _hdmi_ops,
+ .of_to_plat = rk3328_hdmi_of_to_plat,
+ .probe = rk3328_hdmi_probe,
+ .priv_auto = sizeof(struct rk_hdmi_priv),
+};
diff --git a/drivers/video/rockchip/rk_hdmi.h b/drivers/video/rockchip/rk_hdmi.h
index 200db
[PATCH v3 11/17] phy: rockchip: Add Rockchip INNO HDMI PHY driver
From: Jagan Teki Add Rockchip INNO HDMI PHY driver for RK3328. Reference from linux-next phy-rockchip-inno-hdmi driver. Signed-off-by: Jagan Teki --- Changes for v3, v2: - none drivers/phy/rockchip/Kconfig | 7 + drivers/phy/rockchip/Makefile | 1 + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 885 ++ 3 files changed, 893 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 0247d93ab4..80128335d5 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -12,6 +12,13 @@ config PHY_ROCKCHIP_INNO_DSIDPHY help Support for Rockchip MIPI DPHY with Innosilicon IP block. +config PHY_ROCKCHIP_INNO_HDMI + bool "Rockchip INNO HDMI PHY Driver" + depends on ARCH_ROCKCHIP + select PHY + help + Enable this to support the Rockchip Innosilicon HDMI PHY. + config PHY_ROCKCHIP_INNO_USB2 bool "Rockchip INNO USB2PHY Driver" depends on ARCH_ROCKCHIP diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index 7fdbd10797..0420017425 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -3,6 +3,7 @@ # Copyright (C) 2020 Amarula Solutions(India) # +obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE)+= phy-rockchip-pcie.o diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c new file mode 100644 index 00..3bb1a254ff --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -0,0 +1,885 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Rockchip Innosilicon HDMI PHY + * + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define UPDATE(x, h, l)(((x) << (l)) & GENMASK((h), (l))) + +/* REG: 0x01 */ +#define RK3328_BYPASS_RXSENSE_EN BIT(2) +#define RK3328_BYPASS_POWERON_EN BIT(1) +#define RK3328_BYPASS_PLLPD_EN BIT(0) +/* REG: 0x02 */ +#define RK3328_INT_POL_HIGHBIT(7) +#define RK3328_BYPASS_PDATA_EN BIT(4) +#define RK3328_PDATA_ENBIT(0) +/* REG:0x05 */ +#define RK3328_INT_TMDS_CLK(x) UPDATE(x, 7, 4) +#define RK3328_INT_TMDS_D2(x) UPDATE(x, 3, 0) +/* REG:0x07 */ +#define RK3328_INT_TMDS_D1(x) UPDATE(x, 7, 4) +#define RK3328_INT_TMDS_D0(x) UPDATE(x, 3, 0) +/* for all RK3328_INT_TMDS_*, ESD_DET as defined in 0xc8-0xcb */ +#define RK3328_INT_AGND_LOW_PULSE_LOCKED BIT(3) +#define RK3328_INT_RXSENSE_LOW_PULSE_LOCKEDBIT(2) +#define RK3328_INT_VSS_AGND_ESD_DETBIT(1) +#define RK3328_INT_AGND_VSS_ESD_DETBIT(0) +/* REG: 0xa0 */ +#define RK3328_PCLK_VCO_DIV_5_MASK BIT(1) +#define RK3328_PCLK_VCO_DIV_5(x) UPDATE(x, 1, 1) +#define RK3328_PRE_PLL_POWER_DOWN BIT(0) +/* REG: 0xa1 */ +#define RK3328_PRE_PLL_PRE_DIV_MASKGENMASK(5, 0) +#define RK3328_PRE_PLL_PRE_DIV(x) UPDATE(x, 5, 0) +/* REG: 0xa2 */ +/* unset means center spread */ +#define RK3328_SPREAD_SPECTRUM_MOD_DOWNBIT(7) +#define RK3328_SPREAD_SPECTRUM_MOD_DISABLE BIT(6) +#define RK3328_PRE_PLL_FRAC_DIV_DISABLEUPDATE(3, 5, 4) +#define RK3328_PRE_PLL_FB_DIV_11_8_MASKGENMASK(3, 0) +#define RK3328_PRE_PLL_FB_DIV_11_8(x) UPDATE((x) >> 8, 3, 0) +/* REG: 0xa3 */ +#define RK3328_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) +/* REG: 0xa4*/ +#define RK3328_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(1, 0) +#define RK3328_PRE_PLL_TMDSCLK_DIV_C(x)UPDATE(x, 1, 0) +#define RK3328_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(3, 2) +#define RK3328_PRE_PLL_TMDSCLK_DIV_B(x)UPDATE(x, 3, 2) +#define RK3328_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(5, 4) +#define RK3328_PRE_PLL_TMDSCLK_DIV_A(x)UPDATE(x, 5, 4) +/* REG: 0xa5 */ +#define RK3328_PRE_PLL_PCLK_DIV_B_SHIFT5 +#define RK3328_PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5) +#define RK3328_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5) +#define RK3328_PRE_PLL_PCLK_DIV_A_MASK
[PATCH v3 10/17] clk: rk3328: Add get hdmiphy clock
From: Jagan Teki
Add support to get the hdmiphy clock for RK3328 PCLK_HDMIPHY.
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
drivers/clk/rockchip/clk_rk3328.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3328.c
b/drivers/clk/rockchip/clk_rk3328.c
index ee7edb9d10..5bb9238abb 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -179,6 +179,10 @@ enum {
CLK_I2C3_DIV_CON_SHIFT = 8,
CLK_I2C2_PLL_SEL_SHIFT = 7,
CLK_I2C2_DIV_CON_SHIFT = 0,
+
+ /* CLKSEL_CON40 */
+ CLK_HDMIPHY_DIV_CON_SHIFT = 3,
+ CLK_HDMIPHY_DIV_CON_MASK= 0x7 << CLK_HDMIPHY_DIV_CON_SHIFT,
};
#define VCO_MAX_KHZ(3200 * (MHz / KHz))
@@ -661,6 +665,16 @@ static ulong rk3328_vop_set_clk(struct rk3328_clk_priv
*priv,
}
#endif
+static ulong rk3328_hdmiphy_get_clk(struct rk3328_cru *cru)
+{
+ u32 div, con;
+
+ con = readl(>clksel_con[40]);
+ div = (con & CLK_HDMIPHY_DIV_CON_MASK) >> CLK_HDMIPHY_DIV_CON_SHIFT;
+
+ return DIV_TO_RATE(GPLL_HZ, div);
+}
+
static ulong rk3328_clk_get_rate(struct clk *clk)
{
struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
@@ -690,6 +704,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
case SCLK_SPI:
rate = rk3328_spi_get_clk(priv->cru);
break;
+ case PCLK_HDMIPHY:
+ rate = rk3328_hdmiphy_get_clk(priv->cru);
+ break;
default:
return -ENOENT;
}
--
2.25.1
[PATCH v3 09/17] clk: rockchip: rk3328: Add VOP clk support
From: Jagan Teki
VOP get and set clock would needed for VOP drivers.
Add support for it.
Signed-off-by: Jagan Teki
---
Changes for v3:
- none
Changes for v2:
- Add DCLK get rate
.../include/asm/arch-rockchip/cru_rk3328.h| 34 +++
drivers/clk/rockchip/clk_rk3328.c | 88 ++-
2 files changed, 120 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
index 226744d67d..4ad1d33e05 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
@@ -62,6 +62,40 @@ check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
enum apll_frequencies {
APLL_816_MHZ,
APLL_600_MHZ,
+
+ /* CRU_CLK_SEL37_CON */
+ ACLK_VIO_PLL_SEL_CPLL = 0,
+ ACLK_VIO_PLL_SEL_GPLL = 1,
+ ACLK_VIO_PLL_SEL_HDMIPHY= 2,
+ ACLK_VIO_PLL_SEL_USB480M= 3,
+ ACLK_VIO_PLL_SEL_SHIFT = 6,
+ ACLK_VIO_PLL_SEL_MASK = 3 << ACLK_VIO_PLL_SEL_SHIFT,
+ ACLK_VIO_DIV_CON_SHIFT = 0,
+ ACLK_VIO_DIV_CON_MASK = 0x1f << ACLK_VIO_DIV_CON_SHIFT,
+ HCLK_VIO_DIV_CON_SHIFT = 8,
+ HCLK_VIO_DIV_CON_MASK = 0x1f << HCLK_VIO_DIV_CON_SHIFT,
+
+ /* CRU_CLK_SEL39_CON */
+ ACLK_VOP_PLL_SEL_CPLL = 0,
+ ACLK_VOP_PLL_SEL_GPLL = 1,
+ ACLK_VOP_PLL_SEL_HDMIPHY= 2,
+ ACLK_VOP_PLL_SEL_USB480M= 3,
+ ACLK_VOP_PLL_SEL_SHIFT = 6,
+ ACLK_VOP_PLL_SEL_MASK = 3 << ACLK_VOP_PLL_SEL_SHIFT,
+ ACLK_VOP_DIV_CON_SHIFT = 0,
+ ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
+
+ /* CRU_CLK_SEL40_CON */
+ DCLK_LCDC_PLL_SEL_GPLL = 0,
+ DCLK_LCDC_PLL_SEL_CPLL = 1,
+ DCLK_LCDC_PLL_SEL_SHIFT = 0,
+ DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT,
+ DCLK_LCDC_SEL_HDMIPHY = 0,
+ DCLK_LCDC_SEL_PLL = 1,
+ DCLK_LCDC_SEL_SHIFT = 1,
+ DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT,
+ DCLK_LCDC_DIV_CON_SHIFT = 8,
+ DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT,
};
void rk3328_configure_cpu(struct rk3328_cru *cru,
diff --git a/drivers/clk/rockchip/clk_rk3328.c
b/drivers/clk/rockchip/clk_rk3328.c
index ef97381f0e..ee7edb9d10 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -581,6 +581,86 @@ static ulong rk3328_spi_set_clk(struct rk3328_cru *cru,
uint hz)
return rk3328_spi_get_clk(cru);
}
+#ifndef CONFIG_SPL_BUILD
+static ulong rk3328_vop_get_clk(struct rk3328_clk_priv *priv, ulong clk_id)
+{
+ struct rk3328_cru *cru = priv->cru;
+ u32 div, con, parent;
+
+ switch (clk_id) {
+ case ACLK_VOP_PRE:
+ con = readl(>clksel_con[39]);
+ div = (con & ACLK_VOP_DIV_CON_MASK) >> ACLK_VOP_DIV_CON_SHIFT;
+ parent = GPLL_HZ;
+ break;
+ case ACLK_VIO_PRE:
+ con = readl(>clksel_con[37]);
+ div = (con & ACLK_VIO_DIV_CON_MASK) >> ACLK_VIO_DIV_CON_SHIFT;
+ parent = GPLL_HZ;
+ break;
+ case DCLK_LCDC:
+ con = readl(>clksel_con[40]);
+ div = (con & DCLK_LCDC_DIV_CON_MASK) >> DCLK_LCDC_DIV_CON_SHIFT;
+ parent = GPLL_HZ;
+ break;
+ default:
+ printf("%s: Unsupported vop get clk#%ld\n", __func__, clk_id);
+ return -ENOENT;
+ }
+
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3328_vop_set_clk(struct rk3328_clk_priv *priv,
+ ulong clk_id, uint hz)
+{
+ struct rk3328_cru *cru = priv->cru;
+ int src_clk_div;
+ u32 con, parent;
+
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);
+ assert(src_clk_div - 1 < 31);
+
+ switch (clk_id) {
+ case ACLK_VOP_PRE:
+ rk_clrsetreg(>clksel_con[39],
+ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
+ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
+(src_clk_div - 1) << ACLK_VOP_DIV_CON_SHIFT);
+ break;
+ case ACLK_VIO_PRE:
+ rk_clrsetreg(>clksel_con[37],
+ACLK_VIO_PLL_SEL_MASK | ACLK_VIO_DIV_CON_MASK,
+ACLK_VIO_PLL_SEL_CPLL << ACLK_VIO_PLL_SEL_SHIFT |
+(src_clk_div - 1) << ACLK_VIO_DIV_CON_SHIFT);
+ break;
+ case DCLK_LCDC:
+ con = readl(>clksel_con[40]);
+ con = (con & DCLK_LCDC_SEL_M
[PATCH v3 08/17] video: rockchip: vop: Add dsp offset support
From: Jagan Teki
Unlike RK3399, RK3288 the Newer Rockchip SoC's like RK3328 have
different offsets for dsp registers.
Group the dsp register set via dsp_regs pointers so that dsp_offset
would point the dsp_regs to access for any changes in the offset value.
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
drivers/video/rockchip/rk_vop.c | 14 --
drivers/video/rockchip/rk_vop.h | 2 ++
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index b719a4e4ea..acc02e5d7c 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -165,6 +165,7 @@ static void rkvop_mode_set(struct udevice *dev,
{
struct rk_vop_priv *priv = dev_get_priv(dev);
struct rk3288_vop *regs = priv->regs;
+ struct rk3288_vop *dsp_regs = priv->regs + priv->dsp_offset;
struct rkvop_driverdata *data =
(struct rkvop_driverdata *)dev_get_driver_data(dev);
@@ -198,27 +199,27 @@ static void rkvop_mode_set(struct udevice *dev,
writel(V_HSYNC(hsync_len) |
V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
- >dsp_htotal_hs_end);
+ _regs->dsp_htotal_hs_end);
writel(V_HEAP(hsync_len + hback_porch + hactive) |
V_HASP(hsync_len + hback_porch),
- >dsp_hact_st_end);
+ _regs->dsp_hact_st_end);
writel(V_VSYNC(vsync_len) |
V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
- >dsp_vtotal_vs_end);
+ _regs->dsp_vtotal_vs_end);
writel(V_VAEP(vsync_len + vback_porch + vactive)|
V_VASP(vsync_len + vback_porch),
- >dsp_vact_st_end);
+ _regs->dsp_vact_st_end);
writel(V_HEAP(hsync_len + hback_porch + hactive) |
V_HASP(hsync_len + hback_porch),
- >post_dsp_hact_info);
+ _regs->post_dsp_hact_info);
writel(V_VAEP(vsync_len + vback_porch + vactive)|
V_VASP(vsync_len + vback_porch),
- >post_dsp_vact_info);
+ _regs->post_dsp_vact_info);
writel(0x01, >reg_cfg_done); /* enable reg config */
}
@@ -452,6 +453,7 @@ int rk_vop_probe(struct udevice *dev)
priv->regs = dev_read_addr_ptr(dev);
priv->win_offset = ops->win_offset;
+ priv->dsp_offset = ops->dsp_offset;
/*
* Try all the ports until we find one that works. In practice this
diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h
index 909f5602e5..eba68d87c4 100644
--- a/drivers/video/rockchip/rk_vop.h
+++ b/drivers/video/rockchip/rk_vop.h
@@ -12,6 +12,7 @@ struct rk_vop_priv {
void *grf;
void *regs;
int win_offset;
+ int dsp_offset;
};
enum vop_features {
@@ -20,6 +21,7 @@ enum vop_features {
struct rkvop_driverdata {
int win_offset;
+ int dsp_offset;
/* configuration */
u32 features;
/* block-specific setters/getters */
--
2.25.1
[PATCH v3 07/17] video: rockchip: vop: Add win offset support
From: Jagan Teki
Unlike RK3399, RK3288 the Newer Rockchip SoC's like RK3328 have
different offsets for win registers.
Group the win register set via win_regs pointers so that win_offset
would point the win_regs to access for any changes in the offset value.
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
drivers/video/rockchip/rk_vop.c | 22 +-
drivers/video/rockchip/rk_vop.h | 2 ++
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index 158ba7cbf6..b719a4e4ea 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -46,6 +46,7 @@ static void rkvop_enable(struct udevice *dev, ulong fbbase,
{
struct rk_vop_priv *priv = dev_get_priv(dev);
struct rk3288_vop *regs = priv->regs;
+ struct rk3288_vop *win_regs = priv->regs + priv->win_offset;
u32 lb_mode;
u32 rgb_mode;
u32 hactive = edid->hactive.typ;
@@ -53,32 +54,32 @@ static void rkvop_enable(struct udevice *dev, ulong fbbase,
int ret;
writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
- >win0_act_info);
+ _regs->win0_act_info);
writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
- >win0_dsp_st);
+ _regs->win0_dsp_st);
writel(V_DSP_WIDTH(hactive - 1) |
V_DSP_HEIGHT(vactive - 1),
- >win0_dsp_info);
+ _regs->win0_dsp_info);
- clrsetbits_le32(>win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
+ clrsetbits_le32(_regs->win0_color_key, M_WIN0_KEY_EN |
M_WIN0_KEY_COLOR,
V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
switch (fb_bits_per_pixel) {
case 16:
rgb_mode = RGB565;
- writel(V_RGB565_VIRWIDTH(hactive), >win0_vir);
+ writel(V_RGB565_VIRWIDTH(hactive), _regs->win0_vir);
break;
case 24:
rgb_mode = RGB888;
- writel(V_RGB888_VIRWIDTH(hactive), >win0_vir);
+ writel(V_RGB888_VIRWIDTH(hactive), _regs->win0_vir);
break;
case 32:
default:
rgb_mode = ARGB;
- writel(V_ARGB888_VIRWIDTH(hactive), >win0_vir);
+ writel(V_ARGB888_VIRWIDTH(hactive), _regs->win0_vir);
break;
}
@@ -91,12 +92,12 @@ static void rkvop_enable(struct udevice *dev, ulong fbbase,
else
lb_mode = LB_RGB_1280X8;
- clrsetbits_le32(>win0_ctrl0,
+ clrsetbits_le32(_regs->win0_ctrl0,
M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
V_WIN0_EN(1));
- writel(fbbase, >win0_yrgb_mst);
+ writel(fbbase, _regs->win0_yrgb_mst);
writel(0x01, >reg_cfg_done); /* enable reg config */
ret = reset_assert(dclk_rst);
@@ -415,6 +416,8 @@ int rk_vop_probe(struct udevice *dev)
{
struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct rk_vop_priv *priv = dev_get_priv(dev);
+ struct rkvop_driverdata *ops =
+ (struct rkvop_driverdata *)dev_get_driver_data(dev);
int ret = 0;
ofnode port, node;
struct reset_ctl ahb_rst;
@@ -448,6 +451,7 @@ int rk_vop_probe(struct udevice *dev)
#endif
priv->regs = dev_read_addr_ptr(dev);
+ priv->win_offset = ops->win_offset;
/*
* Try all the ports until we find one that works. In practice this
diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h
index 0528fb23f5..909f5602e5 100644
--- a/drivers/video/rockchip/rk_vop.h
+++ b/drivers/video/rockchip/rk_vop.h
@@ -11,6 +11,7 @@
struct rk_vop_priv {
void *grf;
void *regs;
+ int win_offset;
};
enum vop_features {
@@ -18,6 +19,7 @@ enum vop_features {
};
struct rkvop_driverdata {
+ int win_offset;
/* configuration */
u32 features;
/* block-specific setters/getters */
--
2.25.1
[PATCH v3 06/17] video: rockchip: vop: Simplify rkvop_enable
From: Jagan Teki
Get the regs from priv pointer instead of passing it an argument.
This would simplify the code and better readability.
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
drivers/video/rockchip/rk_vop.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index c514e2a0e4..158ba7cbf6 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -39,11 +39,13 @@ enum vop_pol {
DCLK_INVERT= 3
};
-static void rkvop_enable(struct udevice *dev, struct rk3288_vop *regs, ulong
fbbase,
+static void rkvop_enable(struct udevice *dev, ulong fbbase,
int fb_bits_per_pixel,
const struct display_timing *edid,
struct reset_ctl *dclk_rst)
{
+ struct rk_vop_priv *priv = dev_get_priv(dev);
+ struct rk3288_vop *regs = priv->regs;
u32 lb_mode;
u32 rgb_mode;
u32 hactive = edid->hactive.typ;
@@ -243,9 +245,7 @@ static void rkvop_mode_set(struct udevice *dev,
static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
{
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
- struct rk_vop_priv *priv = dev_get_priv(dev);
int vop_id, remote_vop_id;
- struct rk3288_vop *regs = priv->regs;
struct display_timing timing;
struct udevice *disp;
int ret;
@@ -380,7 +380,7 @@ static int rk_display_init(struct udevice *dev, ulong
fbbase, ofnode ep_node)
return ret;
}
- rkvop_enable(dev, regs, fbbase, 1 << l2bpp, , _rst);
+ rkvop_enable(dev, fbbase, 1 << l2bpp, , _rst);
ret = display_enable(disp, 1 << l2bpp, );
if (ret)
--
2.25.1
[PATCH v3 05/17] video: dw_hdmi: Add setup_hpd hook
From: Jagan Teki
Add support for DW HDMI Setup HPD status.
Signed-off-by: Jagan Teki
---
Changes for v3:
- check hdmi->ops
Changes for v2:
- none
drivers/video/dw_hdmi.c | 3 +++
include/dw_hdmi.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index 989b7ab2db..ab4811cfc7 100644
--- a/drivers/video/dw_hdmi.c
+++ b/drivers/video/dw_hdmi.c
@@ -1061,4 +1061,7 @@ void dw_hdmi_init(struct dw_hdmi *hdmi)
/* enable i2c client nack % arbitration error irq */
hdmi_write(hdmi, ~0x44, HDMI_I2CM_CTLINT);
+
+ if (hdmi->ops && hdmi->ops->setup_hpd)
+ hdmi->ops->setup_hpd(hdmi);
}
diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
index a1f0e64507..f4d66edace 100644
--- a/include/dw_hdmi.h
+++ b/include/dw_hdmi.h
@@ -539,6 +539,7 @@ struct dw_hdmi;
struct dw_hdmi_phy_ops {
int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
void (*read_hpd)(struct dw_hdmi *hdmi, bool hdp_status);
+ void (*setup_hpd)(struct dw_hdmi *hdmi);
};
struct dw_hdmi {
--
2.25.1
[PATCH v3 04/17] video: dw_hdmi: Add read_hpd hook
From: Jagan Teki
Add support for DW HDMI Read HPD status.
Signed-off-by: Jagan Teki
---
Changes for v3:
- check hdmi->ops
Changes for v2:
- none
drivers/video/dw_hdmi.c | 3 +++
include/dw_hdmi.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index 3a3b9b7a21..989b7ab2db 100644
--- a/drivers/video/dw_hdmi.c
+++ b/drivers/video/dw_hdmi.c
@@ -946,6 +946,9 @@ int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi)
return -ENODEV;
}
+ if (hdmi->ops && hdmi->ops->read_hpd)
+ hdmi->ops->read_hpd(hdmi, true);
+
return 0;
}
diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
index ba2ce5ea7f..a1f0e64507 100644
--- a/include/dw_hdmi.h
+++ b/include/dw_hdmi.h
@@ -538,6 +538,7 @@ struct dw_hdmi;
struct dw_hdmi_phy_ops {
int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
+ void (*read_hpd)(struct dw_hdmi *hdmi, bool hdp_status);
};
struct dw_hdmi {
--
2.25.1
[PATCH v3 03/17] video: dw_hdmi: Extend the HPD detection
From: Jagan Teki
HPD detection on some DW HDMIdesigned SoC's would need to read and
setup the HPD status explicitly.
So, extend the HPD detection code by adding the dw_hdmi_detect_hpd
function and move the default detection code caller there.
The new read and setup hdp will integrate the same function in
later patches.
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
drivers/video/dw_hdmi.c | 13 +
drivers/video/rockchip/rk_hdmi.c| 8 +++-
drivers/video/sunxi/sunxi_dw_hdmi.c | 8 +++-
include/dw_hdmi.h | 1 +
4 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index 4914ba6146..3a3b9b7a21 100644
--- a/drivers/video/dw_hdmi.c
+++ b/drivers/video/dw_hdmi.c
@@ -936,6 +936,19 @@ int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi)
return -1;
}
+int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi)
+{
+ int ret;
+
+ ret = dw_hdmi_phy_wait_for_hpd(hdmi);
+ if (ret < 0) {
+ debug("hdmi can not get hpd signal\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
void dw_hdmi_phy_init(struct dw_hdmi *hdmi)
{
/* enable phy i2cm done irq */
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index d5b5a529d2..16f6303513 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -114,11 +114,9 @@ int rk_hdmi_probe(struct udevice *dev)
dw_hdmi_init(hdmi);
dw_hdmi_phy_init(hdmi);
- ret = dw_hdmi_phy_wait_for_hpd(hdmi);
- if (ret < 0) {
- debug("hdmi can not get hpd signal\n");
- return -1;
- }
+ ret = dw_hdmi_detect_hpd(hdmi);
+ if (ret < 0)
+ return ret;
return 0;
}
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c
b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 986e69d66b..a5e8d39e98 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -358,11 +358,9 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
sunxi_dw_hdmi_phy_init(>hdmi);
- ret = dw_hdmi_phy_wait_for_hpd(>hdmi);
- if (ret < 0) {
- debug("hdmi can not get hpd signal\n");
- return -1;
- }
+ ret = dw_hdmi_detect_hpd(>hdmi);
+ if (ret < 0)
+ return ret;
dw_hdmi_init(>hdmi);
diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
index 17bdd2dbf9..ba2ce5ea7f 100644
--- a/include/dw_hdmi.h
+++ b/include/dw_hdmi.h
@@ -562,5 +562,6 @@ void dw_hdmi_phy_init(struct dw_hdmi *hdmi);
int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid);
int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size);
void dw_hdmi_init(struct dw_hdmi *hdmi);
+int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi);
#endif
--
2.25.1
[PATCH v3 02/17] video: dw_hdmi: Add Vendor PHY handling
From: Jagan Teki
DW HDMI support Vendor PHY like Rockchip RK3328 Inno HDMI PHY.
Extend the vendor phy handling by adding platform phy hooks.
Signed-off-by: Jagan Teki
---
Changes for v3:
- drop data
- assign ops directly
Changes for v2:
- fix meson cfg
drivers/video/dw_hdmi.c | 10 +-
drivers/video/meson/meson_dw_hdmi.c | 6 +-
drivers/video/rockchip/rk_hdmi.c| 1 -
drivers/video/sunxi/sunxi_dw_hdmi.c | 6 +-
include/dw_hdmi.h | 8 +++-
5 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index c4fbb18294..4914ba6146 100644
--- a/drivers/video/dw_hdmi.c
+++ b/drivers/video/dw_hdmi.c
@@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct
display_timing *edid)
hdmi_av_composer(hdmi, edid);
- ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
+ ret = hdmi->ops->phy_set(hdmi, edid->pixelclock.typ);
if (ret)
return ret;
@@ -1009,10 +1009,18 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct
display_timing *edid)
return 0;
}
+static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
+ .phy_set = dw_hdmi_phy_cfg,
+};
+
void dw_hdmi_init(struct dw_hdmi *hdmi)
{
uint ih_mute;
+ /* hook Synopsys PHYs ops */
+ if (!hdmi->ops)
+ hdmi->ops = _hdmi_synopsys_phy_ops;
+
/*
* boot up defaults are:
* hdmi_ih_mute = 0x03 (disabled)
diff --git a/drivers/video/meson/meson_dw_hdmi.c
b/drivers/video/meson/meson_dw_hdmi.c
index 5db01904b5..259af1b457 100644
--- a/drivers/video/meson/meson_dw_hdmi.c
+++ b/drivers/video/meson/meson_dw_hdmi.c
@@ -375,6 +375,10 @@ static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi)
return -ETIMEDOUT;
}
+static const struct dw_hdmi_phy_ops dw_hdmi_meson_phy_ops = {
+ .phy_set = meson_dw_hdmi_phy_init,
+};
+
static int meson_dw_hdmi_probe(struct udevice *dev)
{
struct meson_dw_hdmi *priv = dev_get_priv(dev);
@@ -397,7 +401,7 @@ static int meson_dw_hdmi_probe(struct udevice *dev)
priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
- priv->hdmi.phy_set = meson_dw_hdmi_phy_init;
+ priv->hdmi.ops = _hdmi_meson_phy_ops;
if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
priv->hdmi.reg_io_width = 1;
else {
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index b75a174489..d5b5a529d2 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -90,7 +90,6 @@ int rk_hdmi_of_to_plat(struct udevice *dev)
/* hdmi->i2c_clk_{high,low} are set up by the SoC driver */
hdmi->reg_io_width = 4;
- hdmi->phy_set = dw_hdmi_phy_cfg;
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c
b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 0324a050d0..986e69d66b 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -369,6 +369,10 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
return 0;
}
+static const struct dw_hdmi_phy_ops dw_hdmi_sunxi_phy_ops = {
+ .phy_set = sunxi_dw_hdmi_phy_cfg,
+};
+
static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
{
struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
@@ -379,7 +383,7 @@ static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
hdmi->i2c_clk_high = 0xd8;
hdmi->i2c_clk_low = 0xfe;
hdmi->reg_io_width = 1;
- hdmi->phy_set = sunxi_dw_hdmi_phy_cfg;
+ hdmi->ops = _hdmi_sunxi_phy_ops;
ret = reset_get_bulk(dev, >resets);
if (ret)
diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
index 8acae3839f..17bdd2dbf9 100644
--- a/include/dw_hdmi.h
+++ b/include/dw_hdmi.h
@@ -534,6 +534,12 @@ struct hdmi_data_info {
struct hdmi_vmode video_mode;
};
+struct dw_hdmi;
+
+struct dw_hdmi_phy_ops {
+ int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
+};
+
struct dw_hdmi {
ulong ioaddr;
const struct hdmi_mpll_config *mpll_cfg;
@@ -543,8 +549,8 @@ struct dw_hdmi {
u8 reg_io_width;
struct hdmi_data_info hdmi_data;
struct udevice *ddc_bus;
+ const struct dw_hdmi_phy_ops *ops;
- int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset);
u8 (*read_reg)(struct dw_hdmi *hdmi, int offset);
};
--
2.25.1
[PATCH v3 01/17] video: rockchip: hdmi: Detect hpd after controller init
From: Jagan Teki
HDP is a hardware connector event, so detect the same once the
controller and attached PHY initialization are done.
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
drivers/video/rockchip/rk_hdmi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 8dcd4d5964..b75a174489 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -112,14 +112,14 @@ int rk_hdmi_probe(struct udevice *dev)
struct dw_hdmi *hdmi = >hdmi;
int ret;
+ dw_hdmi_init(hdmi);
+ dw_hdmi_phy_init(hdmi);
+
ret = dw_hdmi_phy_wait_for_hpd(hdmi);
if (ret < 0) {
debug("hdmi can not get hpd signal\n");
return -1;
}
- dw_hdmi_init(hdmi);
- dw_hdmi_phy_init(hdmi);
-
return 0;
}
--
2.25.1
[PATCH v3 00/17] video: dw_hdmi: Support Vendor PHY
From: Jagan Teki Unlike RK3399, Sunxi/Meson DW HDMI the new Rockchip SoC Rk3328 would support external vendor PHY with DW HDMI chip. Support this vendor PHY by adding new platform PHY ops via DW HDMI driver and call the respective generic phy from platform driver code. This series tested in RK3328 with 1080p (1920x1080) resolution. Patch 0001/0005: Support Vendor PHY Patch 0006/0008: VOP extension for win, dsp offsets Patch 0009/0010: RK3328 VOP, HDMI clocks Patch 0011: Rockchip Inno HDMI PHY Patch 0012: RK3328 HDMI driver Patch 0013: RK3328 VOP driver Patch 0014/0017: Enable HDMI Out for RK3328 Changes for v3: - updated phy_ops logic - tested in BPI-M64 - updated handoff logic for rk3328 Changes for v2: - Use proper cfg function for meson - Add VOP cleanup code. - Add DCLK get rate Linux VOP/HDMI out issues seems resolved with explicit WIN0 disable. Any inputs? Jagan. Jagan Teki (17): video: rockchip: hdmi: Detect hpd after controller init video: dw_hdmi: Add Vendor PHY handling video: dw_hdmi: Extend the HPD detection video: dw_hdmi: Add read_hpd hook video: dw_hdmi: Add setup_hpd hook video: rockchip: vop: Simplify rkvop_enable video: rockchip: vop: Add win offset support video: rockchip: vop: Add dsp offset support clk: rockchip: rk3328: Add VOP clk support clk: rk3328: Add get hdmiphy clock phy: rockchip: Add Rockchip INNO HDMI PHY driver video: rockchip: Add rk3328 hdmi support video: rockchip: Add rk3328 vop support ARM: dts: rk3328: Enable VOP for bootph-all rockchip: Enable preconsole for rk3328 configs: evb-rk3328: Enable vidconsole for rk3328 configs: Enable HDMI Out for ROC-RK3328-CC arch/arm/dts/rk3328-u-boot.dtsi | 4 + .../include/asm/arch-rockchip/cru_rk3328.h| 34 + arch/arm/mach-rockchip/Kconfig| 1 + common/Kconfig| 2 +- configs/roc-cc-rk3328_defconfig | 5 + drivers/clk/rockchip/clk_rk3328.c | 105 ++- drivers/phy/rockchip/Kconfig | 7 + drivers/phy/rockchip/Makefile | 1 + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 885 ++ drivers/video/dw_hdmi.c | 29 +- drivers/video/meson/meson_dw_hdmi.c | 6 +- drivers/video/rockchip/Makefile | 2 + drivers/video/rockchip/rk3328_hdmi.c | 126 +++ drivers/video/rockchip/rk3328_vop.c | 83 ++ drivers/video/rockchip/rk_hdmi.c | 11 +- drivers/video/rockchip/rk_hdmi.h | 3 + drivers/video/rockchip/rk_vop.c | 44 +- drivers/video/rockchip/rk_vop.h | 4 + drivers/video/sunxi/sunxi_dw_hdmi.c | 14 +- include/configs/evb_rk3328.h | 5 + include/configs/rk3328_common.h | 1 + include/dw_hdmi.h | 11 +- 22 files changed, 1345 insertions(+), 38 deletions(-) create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c create mode 100644 drivers/video/rockchip/rk3328_hdmi.c create mode 100644 drivers/video/rockchip/rk3328_vop.c -- 2.25.1
Re: [PATCH V6 00/10] Update SPL splashscreen framework for AM62x
Hi Nikhil, On Tue, Jul 18, 2023 at 2:27 PM Nikhil M Jain wrote: > > This patch series aims at updating SPL splashscreen framework for AM62x. > > This patch series depends on > https://lore.kernel.org/u-boot/20230504225829.2537050-1-...@chromium.org/ > > This series: > - Fixes compilation issues in case splash related configs are not > defined in SPL. > - Does page table setup, dram initialisation and dcache enabling in > one function call spl_enable_dcache. > - Allows passing of framebuffer from spl to u-boot, eliminating flicker. > > V6: > - Add patch [1] from Samuel Dionne-Riel fixing CMD_BMP/BMP dependecy. > > V5: > - Change A53 SPL DDR layout from ASCII table to tabular format. > > V4: > - Fix commit message. > - Introduce patch defining DDR layout in A53 SPL. > - Add Reviewed-by tags. > > V3: > - Fix spacing issues. > - Add Reviewed-by tag. > - Replace #if with if in patch > common: spl: spl: Remove video driver > - Add link to updated memory map. > > V2: > - Update cover letter. > - Fix commit message. > > [1]: > https://patchwork.ozlabs.org/project/uboot/patch/20230709231810.633044-1-sam...@dionne-riel.com/ > > Nikhil M Jain (9): > common: spl: spl: Update stack pointer address > arch: arm: mach-k3: common: Return a pointer after setting page table > board: ti: am62x: evm: Update function calls for splash screen > include: video: Reserve video using blob > common: board_f: Pass frame buffer info from SPL to u-boot > drivers: video: Kconfig: Add config remove video > common: spl: spl: Remove video driver > configs: am62x_evm_a53: Add bloblist address > doc: board: ti: am62x_sk: Add A53 SPL DDR layout > > Samuel Dionne-Riel (1): > common: Kconfig: Fix CMD_BMP/BMP dependency I'm trying to use this to print splash in SPL. Look like the SPL video is not initialized in a general way like U-Boot proper does via board_f.c in reserve_video() correct? do you have your board code to initialize the video for SPL? Jagan.
Re: [PATCH v2 02/17] video: dw_hdmi: Add Vendor PHY handling
Hi Neil,
On Tue, Dec 19, 2023 at 5:21 PM Jagan Teki wrote:
>
> On Tue, Dec 19, 2023 at 2:34 PM Neil Armstrong
> wrote:
> >
> > On 18/12/2023 20:10, Jagan Teki wrote:
> > > From: Jagan Teki
> > >
> > > DW HDMI support Vendor PHY like Rockchip RK3328 Inno HDMI PHY.
> > >
> > > Extend the vendor phy handling by adding platform phy hooks.
> > >
> > > Signed-off-by: Jagan Teki
> > > ---
> > > Changes for v2:
> > > - fix meson cfg
> > >
> > > drivers/video/dw_hdmi.c | 29 +++-
> > > drivers/video/meson/meson_dw_hdmi.c | 11 ++-
> > > drivers/video/rockchip/rk3399_hdmi.c | 8 +++-
> > > drivers/video/rockchip/rk_hdmi.c | 2 +-
> > > drivers/video/sunxi/sunxi_dw_hdmi.c | 11 ++-
> > > include/dw_hdmi.h| 14 +-
> > > 6 files changed, 69 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
> > > index c4fbb18294..ea12a09407 100644
> > > --- a/drivers/video/dw_hdmi.c
> > > +++ b/drivers/video/dw_hdmi.c
> > > @@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct
> > > display_timing *edid)
> > >
> > > hdmi_av_composer(hdmi, edid);
> > >
> > > - ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
> > > + ret = hdmi->ops->phy_set(hdmi, edid->pixelclock.typ);
> > > if (ret)
> > > return ret;
> > >
> > > @@ -1009,10 +1009,37 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const
> > > struct display_timing *edid)
> > > return 0;
> > > }
> > >
> > > +static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
> > > + .phy_set = dw_hdmi_phy_cfg,
> > > +};
> > > +
> > > +static void dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
> > > +{
> > > + if (!hdmi->data)
> > > + return;
> > > +
> > > + /* hook Synopsys PHYs ops */
> > > + if (!hdmi->data->phy_force_vendor) {
> > > + hdmi->ops = _hdmi_synopsys_phy_ops;
> > > + return;
> > > + }
> > > +
> > > + /* Vendor HDMI PHYs must assign phy_ops in plat_data */
> > > + if (!hdmi->data->phy_ops) {
> > > + printf("Unsupported Vendor HDMI phy_ops\n");
> > > + return;
> > > + }
> > > +
> > > + /* hook Vendor HDMI PHYs ops */
> > > + hdmi->ops = hdmi->data->phy_ops;
> >
> > Sorry but I still don't understand why you need phy_force_vendor & phy_ops,
> > this code clearly fails if you have phy_force_vendor=true && phy_ops=NULL,
> > so drop phy_force_vendor and simply use phy_ops if != NULL, and since it's
> > the only element of dw_hdmi_plat_data, drop dw_hdmi_plat_data and pass
> > dw_hdmi_phy_ops directly in the dw_hdmi struct.
> >
> > So in dw_hdmi_detect_phy(), if hdmi->ops is NULL, set it to
> > dw_hdmi_synopsys_phy_ops.
>
> Let me elaborate more.
>
> DW HDMI IP must have phy ops. It never be NULL. Either it uses
> 1. Internal PHY via DW called them Synopsys PHYs ops - for example, rk3399
> 2. Vendor PHY via vendor phy meson, sunxi, rk3328
>
> For case 1) phy_force_vendor is false so it uses dw_hdmi_synopsys_phy_ops
> For case 2) phy_force_vendor is true so it uses dw_hdmi_plat_data phy ops
>
> dw_hdmi_detect_phy assigns internal phy ops first and then vendor phy
> ops based on phy_force_vendor flag.
>
> If we remove dw_hdmi_plat_data how can we assign or differentiate two
> types of phy ops hooks? can you explain?
Let me know if you have any comments on this. I'm sending V3 would
probably hit in MW.
Thanks,
Jagan.
Re: Re: [PATCH v2 13/17] video: rockchip: Add rk3328 vop support
Hi Andy,
On Tue, Dec 19, 2023 at 2:17 PM Andy Yan wrote:
>
>
>
> Hi Jaqan，
> 在 2023-12-19 15:42:26，"Jagan Teki" 写道：
> >Hi Andy,
> >
> >On Tue, Dec 19, 2023 at 6:50 AM Andy Yan wrote:
> >>
> >>
> >> Hi Jaqan：
> >>
> >> At 2023-12-19 03:11:10, "Jagan Teki" wrote:
> >> >From: Jagan Teki
> >> >
> >> >Add support for Rockchip RK3328 VOP.
> >> >
> >> >Require VOP cleanup before handoff to Linux by writing reset values to
> >> >WIN registers. Without this Linux VOP trigger page fault as below
> >> >[0.752016] Loading compiled-in X.509 certificates
> >> >[0.787796] inno_hdmi_phy_rk3328_clk_recalc_rate: parent 2400
> >> >[0.788391] inno-hdmi-phy ff43.phy:
> >> >inno_hdmi_phy_rk3328_clk_recalc_rate rate 14850 vco 14850
> >> >[0.798353] rockchip-drm display-subsystem: bound ff37.vop (ops
> >> >vop_component_ops)
> >> >[0.799403] dwhdmi-rockchip ff3c.hdmi: supply avdd-0v9 not found,
> >> >using dummy regulator
> >> >[0.800288] rk_iommu ff373f00.iommu: Enable stall request timed out,
> >> >status: 0x4b
> >> >[0.801131] dwhdmi-rockchip ff3c.hdmi: supply avdd-1v8 not found,
> >> >using dummy regulator
> >> >[0.802056] rk_iommu ff373f00.iommu: Disable paging request timed out,
> >> >status: 0x4b
> >> >[0.803233] dwhdmi-rockchip ff3c.hdmi: Detected HDMI TX controller
> >> >v2.11a with HDCP (inno_dw_hdmi_phy2)
> >> >[0.805355] dwhdmi-rockchip ff3c.hdmi: registered DesignWare HDMI
> >> >I2C bus driver
> >> >[0.808769] rockchip-drm display-subsystem: bound ff3c.hdmi (ops
> >> >dw_hdmi_rockchip_ops)
> >> >[0.810869] [drm] Initialized rockchip 1.0.0 20140818 for
> >> >display-subsystem on minor 0
> >> >
> >> >Signed-off-by: Jagan Teki
> >> >---
> >> >Changes for v2:
> >> >- Add VOP cleanup
> >> >- Update commit
> >> >
> >> > drivers/video/rockchip/Makefile | 1 +
> >> > drivers/video/rockchip/rk3328_vop.c | 83 +
> >> > 2 files changed, 84 insertions(+)
> >> > create mode 100644 drivers/video/rockchip/rk3328_vop.c
> >> >
> >> >diff --git a/drivers/video/rockchip/Makefile
> >> >b/drivers/video/rockchip/Makefile
> >> >index 4991303c73..f55beceebf 100644
> >> >--- a/drivers/video/rockchip/Makefile
> >> >+++ b/drivers/video/rockchip/Makefile
> >> >@@ -6,6 +6,7 @@
> >> > ifdef CONFIG_VIDEO_ROCKCHIP
> >> > obj-y += rk_vop.o
> >> > obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o
> >> >+obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o
> >> > obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o
> >> > obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
> >> > obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
> >> >diff --git a/drivers/video/rockchip/rk3328_vop.c
> >> >b/drivers/video/rockchip/rk3328_vop.c
> >> >new file mode 100644
> >> >index 00..a4da3a91e8
> >> >--- /dev/null
> >> >+++ b/drivers/video/rockchip/rk3328_vop.c
> >> >@@ -0,0 +1,83 @@
> >> >+// SPDX-License-Identifier: GPL-2.0+
> >> >+/*
> >> >+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
> >> >+ */
> >> >+
> >> >+#include
> >> >+#include
> >> >+#include
> >> >+#include "rk_vop.h"
> >> >+
> >> >+DECLARE_GLOBAL_DATA_PTR;
> >> >+
> >> >+static void rk3328_set_pin_polarity(struct udevice *dev,
> >> >+ enum vop_modes mode, u32 polarity)
> >> >+{
> >> >+ struct rk_vop_priv *priv = dev_get_priv(dev);
> >> >+ struct rk3288_vop *regs = priv->regs;
> >> >+
> >> >+ switch (mode) {
> >> >+ case VOP_MODE_HDMI:
> >> >+ clrsetbits_le32(>dsp_ctrl1,
> >> >+ M_RK3399_DSP_HDMI_POL,
> >> >+ V_RK3399_DSP_HDMI_POL(polarity));
> >> >+ break;
> >> >+ default:
> >> >+ debug("%s: unsupported output mode %x\n", __func__, mode);
> >> >+ }
> >
Re: [PATCH v2 01/30] mtd: spi-nor: Add config to enable flash DTR
On Wed, Dec 6, 2023 at 3:02 PM Tejas Bhumkar wrote: > > From: T Karthik Reddy > > The spi-nor framework will set up the flash parameters by > reading the flash id table flags, which include cmd opcodes, > address width, dummy bytes, and bus width. In case, flash > supports octal DTR mode and the controller does not support > the DTR. There is no process to switch back to SDR mode. > To avoid this issue, create a Kconfig option SPI_FLASH_DTR_ENABLE > to explicitly specify to enable/disable flash DTR support. > This config is disabled by default. We cannot control controller fixup in flash, DTR read based on the DTR flag I don't think adding extra CONFIG to hack the controller with impact is. Jagan,
Re: [PATCH v1] spi: dw: add check for Rx FIFO overflow
On Mon, Dec 18, 2023 at 11:01 PM Maxim Kiselev wrote: > > Hello Jagan, > > пн, 18 дек. 2023 г. в 14:28, Jagan Teki : > > > > On Tue, Oct 17, 2023 at 12:35 PM Maksim Kiselev > > wrote: > > > > > > If even one byte is lost due to Rx FIFO overflow then we will never > > > exit the read loop. Because the (priv->rx != priv->rx_end) condition will > > > be always true. > > > > > > Let's check if Rx FIFO overflow occurred and exit the read loop > > > in this case. > > > > > > Signed-off-by: Maksim Kiselev > > > --- > > > drivers/spi/designware_spi.c | 24 +--- > > > 1 file changed, 21 insertions(+), 3 deletions(-) > > > > > > diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c > > > index 1c7d0ca310..0f443bff8e 100644 > > > --- a/drivers/spi/designware_spi.c > > > +++ b/drivers/spi/designware_spi.c > > > @@ -111,6 +111,15 @@ > > > #define SR_TX_ERR BIT(5) > > > #define SR_DCOLBIT(6) > > > > > > +/* Bit fields in ISR, IMR, RISR, 7 bits */ > > > +#define DW_SPI_INT_MASKGENMASK(5, 0) > > > +#define DW_SPI_INT_TXEIBIT(0) > > > +#define DW_SPI_INT_TXOIBIT(1) > > > +#define DW_SPI_INT_RXUIBIT(2) > > > +#define DW_SPI_INT_RXOIBIT(3) > > > +#define DW_SPI_INT_RXFIBIT(4) > > > +#define DW_SPI_INT_MSTIBIT(5) > > > > Why do we need unused macros? > > Actually DW_SPI_INT_RXOI is used. As for the other bits in DW_SPI_RISR, > I decided to add them all to match a Linux driver. > > We already have a lot of unused macro in this driver (ex. definitions > for bits in CTRLR0_FRF, > CTRLR0_MODE regs and so on). > > So, what's a problem with adding the DW_SPI_RISR bits? I'm not fond of unused change in the particular patch, better to send the updated one with used bits. Jagan.
Re: [PATCH v2 02/17] video: dw_hdmi: Add Vendor PHY handling
On Tue, Dec 19, 2023 at 2:34 PM Neil Armstrong
wrote:
>
> On 18/12/2023 20:10, Jagan Teki wrote:
> > From: Jagan Teki
> >
> > DW HDMI support Vendor PHY like Rockchip RK3328 Inno HDMI PHY.
> >
> > Extend the vendor phy handling by adding platform phy hooks.
> >
> > Signed-off-by: Jagan Teki
> > ---
> > Changes for v2:
> > - fix meson cfg
> >
> > drivers/video/dw_hdmi.c | 29 +++-
> > drivers/video/meson/meson_dw_hdmi.c | 11 ++-
> > drivers/video/rockchip/rk3399_hdmi.c | 8 +++-
> > drivers/video/rockchip/rk_hdmi.c | 2 +-
> > drivers/video/sunxi/sunxi_dw_hdmi.c | 11 ++-
> > include/dw_hdmi.h| 14 +-
> > 6 files changed, 69 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
> > index c4fbb18294..ea12a09407 100644
> > --- a/drivers/video/dw_hdmi.c
> > +++ b/drivers/video/dw_hdmi.c
> > @@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct
> > display_timing *edid)
> >
> > hdmi_av_composer(hdmi, edid);
> >
> > - ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
> > + ret = hdmi->ops->phy_set(hdmi, edid->pixelclock.typ);
> > if (ret)
> > return ret;
> >
> > @@ -1009,10 +1009,37 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const
> > struct display_timing *edid)
> > return 0;
> > }
> >
> > +static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
> > + .phy_set = dw_hdmi_phy_cfg,
> > +};
> > +
> > +static void dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
> > +{
> > + if (!hdmi->data)
> > + return;
> > +
> > + /* hook Synopsys PHYs ops */
> > + if (!hdmi->data->phy_force_vendor) {
> > + hdmi->ops = _hdmi_synopsys_phy_ops;
> > + return;
> > + }
> > +
> > + /* Vendor HDMI PHYs must assign phy_ops in plat_data */
> > + if (!hdmi->data->phy_ops) {
> > + printf("Unsupported Vendor HDMI phy_ops\n");
> > + return;
> > + }
> > +
> > + /* hook Vendor HDMI PHYs ops */
> > + hdmi->ops = hdmi->data->phy_ops;
>
> Sorry but I still don't understand why you need phy_force_vendor & phy_ops,
> this code clearly fails if you have phy_force_vendor=true && phy_ops=NULL,
> so drop phy_force_vendor and simply use phy_ops if != NULL, and since it's
> the only element of dw_hdmi_plat_data, drop dw_hdmi_plat_data and pass
> dw_hdmi_phy_ops directly in the dw_hdmi struct.
>
> So in dw_hdmi_detect_phy(), if hdmi->ops is NULL, set it to
> dw_hdmi_synopsys_phy_ops.
Let me elaborate more.
DW HDMI IP must have phy ops. It never be NULL. Either it uses
1. Internal PHY via DW called them Synopsys PHYs ops - for example, rk3399
2. Vendor PHY via vendor phy meson, sunxi, rk3328
For case 1) phy_force_vendor is false so it uses dw_hdmi_synopsys_phy_ops
For case 2) phy_force_vendor is true so it uses dw_hdmi_plat_data phy ops
dw_hdmi_detect_phy assigns internal phy ops first and then vendor phy
ops based on phy_force_vendor flag.
If we remove dw_hdmi_plat_data how can we assign or differentiate two
types of phy ops hooks? can you explain?
Thanks,
Jagan.
Re: [PATCH v2 13/17] video: rockchip: Add rk3328 vop support
Hi Andy,
On Tue, Dec 19, 2023 at 6:50 AM Andy Yan wrote:
>
>
> Hi Jaqan：
>
> At 2023-12-19 03:11:10, "Jagan Teki" wrote:
> >From: Jagan Teki
> >
> >Add support for Rockchip RK3328 VOP.
> >
> >Require VOP cleanup before handoff to Linux by writing reset values to
> >WIN registers. Without this Linux VOP trigger page fault as below
> >[0.752016] Loading compiled-in X.509 certificates
> >[0.787796] inno_hdmi_phy_rk3328_clk_recalc_rate: parent 2400
> >[0.788391] inno-hdmi-phy ff43.phy:
> >inno_hdmi_phy_rk3328_clk_recalc_rate rate 14850 vco 14850
> >[0.798353] rockchip-drm display-subsystem: bound ff37.vop (ops
> >vop_component_ops)
> >[0.799403] dwhdmi-rockchip ff3c.hdmi: supply avdd-0v9 not found,
> >using dummy regulator
> >[0.800288] rk_iommu ff373f00.iommu: Enable stall request timed out,
> >status: 0x4b
> >[0.801131] dwhdmi-rockchip ff3c.hdmi: supply avdd-1v8 not found,
> >using dummy regulator
> >[0.802056] rk_iommu ff373f00.iommu: Disable paging request timed out,
> >status: 0x4b
> >[0.803233] dwhdmi-rockchip ff3c.hdmi: Detected HDMI TX controller
> >v2.11a with HDCP (inno_dw_hdmi_phy2)
> >[0.805355] dwhdmi-rockchip ff3c.hdmi: registered DesignWare HDMI I2C
> >bus driver
> >[0.808769] rockchip-drm display-subsystem: bound ff3c.hdmi (ops
> >dw_hdmi_rockchip_ops)
> >[0.810869] [drm] Initialized rockchip 1.0.0 20140818 for
> >display-subsystem on minor 0
> >
> >Signed-off-by: Jagan Teki
> >---
> >Changes for v2:
> >- Add VOP cleanup
> >- Update commit
> >
> > drivers/video/rockchip/Makefile | 1 +
> > drivers/video/rockchip/rk3328_vop.c | 83 +
> > 2 files changed, 84 insertions(+)
> > create mode 100644 drivers/video/rockchip/rk3328_vop.c
> >
> >diff --git a/drivers/video/rockchip/Makefile
> >b/drivers/video/rockchip/Makefile
> >index 4991303c73..f55beceebf 100644
> >--- a/drivers/video/rockchip/Makefile
> >+++ b/drivers/video/rockchip/Makefile
> >@@ -6,6 +6,7 @@
> > ifdef CONFIG_VIDEO_ROCKCHIP
> > obj-y += rk_vop.o
> > obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o
> >+obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o
> > obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o
> > obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
> > obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
> >diff --git a/drivers/video/rockchip/rk3328_vop.c
> >b/drivers/video/rockchip/rk3328_vop.c
> >new file mode 100644
> >index 00..a4da3a91e8
> >--- /dev/null
> >+++ b/drivers/video/rockchip/rk3328_vop.c
> >@@ -0,0 +1,83 @@
> >+// SPDX-License-Identifier: GPL-2.0+
> >+/*
> >+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
> >+ */
> >+
> >+#include
> >+#include
> >+#include
> >+#include "rk_vop.h"
> >+
> >+DECLARE_GLOBAL_DATA_PTR;
> >+
> >+static void rk3328_set_pin_polarity(struct udevice *dev,
> >+ enum vop_modes mode, u32 polarity)
> >+{
> >+ struct rk_vop_priv *priv = dev_get_priv(dev);
> >+ struct rk3288_vop *regs = priv->regs;
> >+
> >+ switch (mode) {
> >+ case VOP_MODE_HDMI:
> >+ clrsetbits_le32(>dsp_ctrl1,
> >+ M_RK3399_DSP_HDMI_POL,
> >+ V_RK3399_DSP_HDMI_POL(polarity));
> >+ break;
> >+ default:
> >+ debug("%s: unsupported output mode %x\n", __func__, mode);
> >+ }
> >+}
> >+
> >+static int rk3328_vop_probe(struct udevice *dev)
> >+{
> >+ /* Before relocation we don't need to do anything */
> >+ if (!(gd->flags & GD_FLG_RELOC))
> >+ return 0;
> >+
> >+ return rk_vop_probe(dev);
> >+}
> >+
> >+static int rk3328_vop_remove(struct udevice *dev)
> >+{
> >+ struct rk_vop_priv *priv = dev_get_priv(dev);
> >+ struct rk3288_vop *regs = priv->regs;
> >+ struct rk3288_vop *win_regs = priv->regs + priv->win_offset;
> >+
> >+ /* write reset values */
> >+ writel(0xef013f, _regs->win0_act_info);
> >+ writel(0xef013f, _regs->win0_dsp_info);
> >+ writel(0xa000a, _regs->win0_dsp_st);
> >+ writel(0x0, _regs->win0_yrgb_mst);
> >+ writel(0x01, >reg_cfg_done);
> >+
> >+ return 0;
> >+}
>
> I think this just workaround Linux iommu page fault by luck。
> The reset value（what you called it is）your write just let win0 read a
> 320x240 rectangular from address 0 and display it at next frame（maybe 16ms
> later if your
> current display is run at 60HZ）。
>
> 1. we don't know what content is at address 0, so you will see something
> strange on your monitor.
> 2. there is no guarantee that address 0 is really readable（maybe a security
> memory space， or maybe
> it is not a valid address）， this may cause another issue that not easy to
> detect。
Okay. Can you suggest any proper way to clean up VOP? All these reset
values are referred to as per the TRM and read before enabling the
video.
Thanks,
Jagan.
[PATCH v2 17/17] configs: Enable HDMI Out for ROC-RK3328-CC
U-Boot 2024.01-rc4-00053-gb9f7cafdd9-dirty (Dec 11 2023 - 13:18:15 +0530) Model: Firefly roc-rk3328-cc DRAM: 1 GiB (effective 1022 MiB) PMIC: RK8050 (on=0x40, off=0x00) Core: 236 devices, 26 uclasses, devicetree: separate MMC: mmc@ff50: 1, mmc@ff52: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment tmdsclock = 14850; chipversion = 1 In:serial Out: vidconsole Err: vidconsole Model: Firefly roc-rk3328-cc Net: eth0: ethernet@ff54 Hit any key to stop autoboot: 0 => dm tree Class Index Probed DriverName --- root 0 [ + ] root_driver root_driver firmware 0 [ ] psci |-- psci clk 0 [ + ] fixed_clock |-- xin24m syscon0 [ + ] rockchip_rk3328_grf |-- syscon@ff10 serial0 [ + ] ns16550_serial|-- serial@ff13 i2c 0 [ + ] rockchip_rk3066_i2c |-- i2c@ff16 pmic 0 [ + ] rockchip_rk805| `-- pmic@18 sysreset 0 [ ] rk8xx_sysreset| |-- rk8xx_sysreset regulator 0 [ + ] rk8xx_buck| |-- DCDC_REG1 regulator 1 [ + ] rk8xx_buck| |-- DCDC_REG2 regulator 2 [ + ] rk8xx_buck| |-- DCDC_REG3 regulator 3 [ + ] rk8xx_buck| |-- DCDC_REG4 regulator 4 [ + ] rk8xx_ldo | |-- LDO_REG1 regulator 5 [ + ] rk8xx_ldo | |-- LDO_REG2 regulator 6 [ + ] rk8xx_ldo | `-- LDO_REG3 video 0 [ + ] rk3328_vop|-- vop@ff37 vidconsole0 [ + ] vidconsole0 | `-- vop@ff37.vidconsole0 display 0 [ + ] rk3328_hdmi_rockchip |-- hdmi@ff3c phy 0 [ + ] inno_hdmi_phy |-- phy@ff43 clk 1 [ + ] rockchip_rk3328_cru |-- clock-controller@ff44 sysreset 1 [ ] rockchip_sysreset | |-- sysreset reset 0 [ + ] rockchip_reset| `-- reset Signed-off-by: Jagan Teki --- Changes for v2: - none configs/roc-cc-rk3328_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 4ac3c9403b..4eef9016dc 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -79,6 +79,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_HDMI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y @@ -114,6 +115,10 @@ CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y -- 2.25.1
[PATCH v2 16/17] configs: evb-rk3328: Enable vidconsole for rk3328
Enable video console for Rockchip RK3328. Signed-off-by: Jagan Teki --- Changes for v2: - none include/configs/evb_rk3328.h| 5 + include/configs/rk3328_common.h | 1 + 2 files changed, 6 insertions(+) diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h index d10e5b1d2e..c985080f7b 100644 --- a/include/configs/evb_rk3328.h +++ b/include/configs/evb_rk3328.h @@ -6,6 +6,11 @@ #ifndef __EVB_RK3328_H #define __EVB_RK3328_H +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + #include #endif diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index e920ec7e5d..2c40674b22 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -26,6 +26,7 @@ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ "boot_targets=" BOOT_TARGETS "\0" #endif -- 2.25.1
[PATCH v2 15/17] rockchip: Enable preconsole for rk3328
Enable and set the start address of pre-console buffer for RK3328. Signed-off-by: Jagan Teki --- Changes for v2: - none arch/arm/mach-rockchip/Kconfig | 1 + common/Kconfig | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b577a911e7..60f403fe74 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -179,6 +179,7 @@ config ROCKCHIP_RK3328 select SUPPORT_TPL select TPL select TPL_NEEDS_SEPARATE_STACK if TPL + imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_SDRAM_COMMON imply SPL_ROCKCHIP_COMMON_BOARD diff --git a/common/Kconfig b/common/Kconfig index 0f54819519..093ebfbd1e 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -208,7 +208,7 @@ config PRE_CON_BUF_ADDR default 0x2f00 if ARCH_SUNXI && MACH_SUN9I default 0x4f00 if ARCH_SUNXI && !MACH_SUN9I default 0x0f00 if ROCKCHIP_RK3288 - default 0x0f20 if ROCKCHIP_RK3399 + default 0x0f20 if ROCKCHIP_RK3399 || ROCKCHIP_RK3328 help This sets the start address of the pre-console buffer. This must be in available memory and is accessed before relocation and -- 2.25.1
[PATCH v2 14/17] ARM: dts: rk3328: Enable VOP for bootph-all
Model: Firefly roc-rk3328-cc
DRAM: 1 GiB (effective 1022 MiB)
Video device 'vop@ff37' cannot allocate frame buffer memory -ensure the
device is set up before relocation
Error binding driver 'rockchip_rk3328_vop': -28
Some drivers failed to bind
initcall sequence 3ffcd5e8 failed at call 0021a5c4 (err=-28)
### ERROR ### Please RESET the board ###
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
arch/arm/dts/rk3328-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index a9f2536de2..5258fec566 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -68,3 +68,7 @@
{
bootph-all;
};
+
+ {
+ bootph-all;
+};
--
2.25.1
[PATCH v2 13/17] video: rockchip: Add rk3328 vop support
From: Jagan Teki
Add support for Rockchip RK3328 VOP.
Require VOP cleanup before handoff to Linux by writing reset values to
WIN registers. Without this Linux VOP trigger page fault as below
[0.752016] Loading compiled-in X.509 certificates
[0.787796] inno_hdmi_phy_rk3328_clk_recalc_rate: parent 2400
[0.788391] inno-hdmi-phy ff43.phy: inno_hdmi_phy_rk3328_clk_recalc_rate
rate 14850 vco 14850
[0.798353] rockchip-drm display-subsystem: bound ff37.vop (ops
vop_component_ops)
[0.799403] dwhdmi-rockchip ff3c.hdmi: supply avdd-0v9 not found, using
dummy regulator
[0.800288] rk_iommu ff373f00.iommu: Enable stall request timed out, status:
0x4b
[0.801131] dwhdmi-rockchip ff3c.hdmi: supply avdd-1v8 not found, using
dummy regulator
[0.802056] rk_iommu ff373f00.iommu: Disable paging request timed out,
status: 0x4b
[0.803233] dwhdmi-rockchip ff3c.hdmi: Detected HDMI TX controller
v2.11a with HDCP (inno_dw_hdmi_phy2)
[0.805355] dwhdmi-rockchip ff3c.hdmi: registered DesignWare HDMI I2C
bus driver
[0.808769] rockchip-drm display-subsystem: bound ff3c.hdmi (ops
dw_hdmi_rockchip_ops)
[0.810869] [drm] Initialized rockchip 1.0.0 20140818 for display-subsystem
on minor 0
Signed-off-by: Jagan Teki
---
Changes for v2:
- Add VOP cleanup
- Update commit
drivers/video/rockchip/Makefile | 1 +
drivers/video/rockchip/rk3328_vop.c | 83 +
2 files changed, 84 insertions(+)
create mode 100644 drivers/video/rockchip/rk3328_vop.c
diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
index 4991303c73..f55beceebf 100644
--- a/drivers/video/rockchip/Makefile
+++ b/drivers/video/rockchip/Makefile
@@ -6,6 +6,7 @@
ifdef CONFIG_VIDEO_ROCKCHIP
obj-y += rk_vop.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o
+obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o
obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
diff --git a/drivers/video/rockchip/rk3328_vop.c
b/drivers/video/rockchip/rk3328_vop.c
new file mode 100644
index 00..a4da3a91e8
--- /dev/null
+++ b/drivers/video/rockchip/rk3328_vop.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include
+#include
+#include
+#include "rk_vop.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void rk3328_set_pin_polarity(struct udevice *dev,
+ enum vop_modes mode, u32 polarity)
+{
+ struct rk_vop_priv *priv = dev_get_priv(dev);
+ struct rk3288_vop *regs = priv->regs;
+
+ switch (mode) {
+ case VOP_MODE_HDMI:
+ clrsetbits_le32(>dsp_ctrl1,
+ M_RK3399_DSP_HDMI_POL,
+ V_RK3399_DSP_HDMI_POL(polarity));
+ break;
+ default:
+ debug("%s: unsupported output mode %x\n", __func__, mode);
+ }
+}
+
+static int rk3328_vop_probe(struct udevice *dev)
+{
+ /* Before relocation we don't need to do anything */
+ if (!(gd->flags & GD_FLG_RELOC))
+ return 0;
+
+ return rk_vop_probe(dev);
+}
+
+static int rk3328_vop_remove(struct udevice *dev)
+{
+ struct rk_vop_priv *priv = dev_get_priv(dev);
+ struct rk3288_vop *regs = priv->regs;
+ struct rk3288_vop *win_regs = priv->regs + priv->win_offset;
+
+ /* write reset values */
+ writel(0xef013f, _regs->win0_act_info);
+ writel(0xef013f, _regs->win0_dsp_info);
+ writel(0xa000a, _regs->win0_dsp_st);
+ writel(0x0, _regs->win0_yrgb_mst);
+ writel(0x01, >reg_cfg_done);
+
+ return 0;
+}
+
+struct rkvop_driverdata rk3328_driverdata = {
+ .dsp_offset = 0x490,
+ .win_offset = 0xd0,
+ .features = VOP_FEATURE_OUTPUT_10BIT,
+ .set_pin_polarity = rk3328_set_pin_polarity,
+};
+
+static const struct udevice_id rk3328_vop_ids[] = {
+ {
+ .compatible = "rockchip,rk3328-vop",
+ .data = (ulong)_driverdata
+ },
+ { /* sentile */ }
+};
+
+static const struct video_ops rk3328_vop_ops = {
+};
+
+U_BOOT_DRIVER(rk3328_vop) = {
+ .name = "rk3328_vop",
+ .id = UCLASS_VIDEO,
+ .of_match = rk3328_vop_ids,
+ .ops= _vop_ops,
+ .bind = rk_vop_bind,
+ .probe = rk3328_vop_probe,
+ .remove = rk3328_vop_remove,
+ .priv_auto = sizeof(struct rk_vop_priv),
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
+};
--
2.25.1
[PATCH v2 12/17] video: rockchip: Add rk3328 hdmi support
From: Jagan Teki
Add Rockchip RK3328 HDMI Out driver.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/video/rockchip/Makefile | 1 +
drivers/video/rockchip/rk3328_hdmi.c | 131 +++
drivers/video/rockchip/rk_hdmi.h | 3 +
3 files changed, 135 insertions(+)
create mode 100644 drivers/video/rockchip/rk3328_hdmi.c
diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
index 8128289cc8..4991303c73 100644
--- a/drivers/video/rockchip/Makefile
+++ b/drivers/video/rockchip/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o
obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
obj-hdmi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_hdmi.o
+obj-hdmi-$(CONFIG_ROCKCHIP_RK3328) += rk3328_hdmi.o
obj-hdmi-$(CONFIG_ROCKCHIP_RK3399) += rk3399_hdmi.o
obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o $(obj-hdmi-y)
obj-mipi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_mipi.o
diff --git a/drivers/video/rockchip/rk3328_hdmi.c
b/drivers/video/rockchip/rk3328_hdmi.c
new file mode 100644
index 00..23624699ba
--- /dev/null
+++ b/drivers/video/rockchip/rk3328_hdmi.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "rk_hdmi.h"
+
+#define RK3328_IO_3V_DOMAIN (7 << (9 + 16))
+#define RK3328_IO_5V_DOMAIN ((7 << 9) | (3 << (9 + 16)))
+#define RK3328_IO_DDC_IN_MSK ((3 << 10) | (3 << (10 + 16)))
+#define RK3328_IO_CTRL_BY_HDMI ((1 << 13) | (1 << (13 + 16)))
+
+static int rk3328_hdmi_enable(struct udevice *dev, int panel_bpp,
+ const struct display_timing *edid)
+{
+ struct rk_hdmi_priv *priv = dev_get_priv(dev);
+
+ return dw_hdmi_enable(>hdmi, edid);
+}
+
+static int rk3328_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint pixclock)
+{
+ struct rk_hdmi_priv *priv = container_of(hdmi, struct rk_hdmi_priv,
hdmi);
+ int ret;
+
+ ret = generic_phy_init(>phy);
+ if (ret) {
+ printf("failed to init phy (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = generic_phy_power_on(>phy);
+ if (ret) {
+ printf("failed to power on phy (ret=%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void rk3328_dw_hdmi_setup_hpd(struct dw_hdmi *hdmi)
+{
+ struct rk_hdmi_priv *priv = container_of(hdmi, struct rk_hdmi_priv,
hdmi);
+ struct rk3328_grf_regs *grf = priv->grf;
+
+ writel(RK3328_IO_DDC_IN_MSK, >soc_con[2]);
+ writel(RK3328_IO_CTRL_BY_HDMI, >soc_con[3]);
+}
+
+static void rk3328_dw_hdmi_read_hpd(struct dw_hdmi *hdmi, bool hpd_status)
+{
+ struct rk_hdmi_priv *priv = container_of(hdmi, struct rk_hdmi_priv,
hdmi);
+ struct rk3328_grf_regs *grf = priv->grf;
+
+ if (hpd_status)
+ writel(RK3328_IO_5V_DOMAIN, >soc_con[4]);
+ else
+ writel(RK3328_IO_3V_DOMAIN, >soc_con[4]);
+}
+
+static const struct dw_hdmi_phy_ops dw_hdmi_rk3328_phy_ops = {
+ .phy_set = rk3328_dw_hdmi_phy_cfg,
+ .setup_hpd = rk3328_dw_hdmi_setup_hpd,
+ .read_hpd = rk3328_dw_hdmi_read_hpd,
+};
+
+static const struct dw_hdmi_plat_data dw_hdmi_rk3328_plat_data = {
+ .phy_force_vendor = true,
+ .phy_ops = _hdmi_rk3328_phy_ops,
+};
+
+static int rk3328_hdmi_of_to_plat(struct udevice *dev)
+{
+ struct rk_hdmi_priv *priv = dev_get_priv(dev);
+ struct dw_hdmi *hdmi = >hdmi;
+
+ hdmi->i2c_clk_high = 0x71;
+ hdmi->i2c_clk_low = 0x76;
+
+ rk_hdmi_of_to_plat(dev);
+
+ hdmi->data = _hdmi_rk3328_plat_data;
+
+ return 0;
+}
+
+static int rk3328_hdmi_probe(struct udevice *dev)
+{
+ struct rk_hdmi_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = generic_phy_get_by_name(dev, "hdmi", >phy);
+ if (ret) {
+ printf("failed to get hdmi phy\n");
+ return ret;
+ };
+
+ ret = rk_hdmi_probe(dev);
+ if (ret) {
+ printf("failed to probe rk hdmi\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct dm_display_ops rk3328_hdmi_ops = {
+ .read_edid = rk_hdmi_read_edid,
+ .enable = rk3328_hdmi_enable,
+};
+
+static const struct udevice_id rk3328_hdmi_ids[] = {
+ { .compatible = "rockchip,rk3328-dw-hdmi" },
+ { }
+};
+
+U_BOOT_DRIVER(rk3328_hdmi_rockchip) = {
+ .name = "rk3328_hdmi_rockchip",
+ .id = UCLASS_DISPLAY,
+ .of_match = rk3328_hdmi_ids,
+ .ops = _hdmi_ops,
+ .of_to_plat = rk3328_hdmi_of_to_plat,
+ .probe = rk3328_hdmi_probe,
+ .priv_auto =
[PATCH v2 11/17] phy: rockchip: Add Rockchip INNO HDMI PHY driver
From: Jagan Teki Add Rockchip INNO HDMI PHY driver for RK3328. Reference from linux-next phy-rockchip-inno-hdmi driver. Signed-off-by: Jagan Teki --- Changes for v2: - none drivers/phy/rockchip/Kconfig | 7 + drivers/phy/rockchip/Makefile | 1 + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 885 ++ 3 files changed, 893 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 0247d93ab4..80128335d5 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -12,6 +12,13 @@ config PHY_ROCKCHIP_INNO_DSIDPHY help Support for Rockchip MIPI DPHY with Innosilicon IP block. +config PHY_ROCKCHIP_INNO_HDMI + bool "Rockchip INNO HDMI PHY Driver" + depends on ARCH_ROCKCHIP + select PHY + help + Enable this to support the Rockchip Innosilicon HDMI PHY. + config PHY_ROCKCHIP_INNO_USB2 bool "Rockchip INNO USB2PHY Driver" depends on ARCH_ROCKCHIP diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index 7fdbd10797..0420017425 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -3,6 +3,7 @@ # Copyright (C) 2020 Amarula Solutions(India) # +obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE)+= phy-rockchip-pcie.o diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c new file mode 100644 index 00..3bb1a254ff --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -0,0 +1,885 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Rockchip Innosilicon HDMI PHY + * + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define UPDATE(x, h, l)(((x) << (l)) & GENMASK((h), (l))) + +/* REG: 0x01 */ +#define RK3328_BYPASS_RXSENSE_EN BIT(2) +#define RK3328_BYPASS_POWERON_EN BIT(1) +#define RK3328_BYPASS_PLLPD_EN BIT(0) +/* REG: 0x02 */ +#define RK3328_INT_POL_HIGHBIT(7) +#define RK3328_BYPASS_PDATA_EN BIT(4) +#define RK3328_PDATA_ENBIT(0) +/* REG:0x05 */ +#define RK3328_INT_TMDS_CLK(x) UPDATE(x, 7, 4) +#define RK3328_INT_TMDS_D2(x) UPDATE(x, 3, 0) +/* REG:0x07 */ +#define RK3328_INT_TMDS_D1(x) UPDATE(x, 7, 4) +#define RK3328_INT_TMDS_D0(x) UPDATE(x, 3, 0) +/* for all RK3328_INT_TMDS_*, ESD_DET as defined in 0xc8-0xcb */ +#define RK3328_INT_AGND_LOW_PULSE_LOCKED BIT(3) +#define RK3328_INT_RXSENSE_LOW_PULSE_LOCKEDBIT(2) +#define RK3328_INT_VSS_AGND_ESD_DETBIT(1) +#define RK3328_INT_AGND_VSS_ESD_DETBIT(0) +/* REG: 0xa0 */ +#define RK3328_PCLK_VCO_DIV_5_MASK BIT(1) +#define RK3328_PCLK_VCO_DIV_5(x) UPDATE(x, 1, 1) +#define RK3328_PRE_PLL_POWER_DOWN BIT(0) +/* REG: 0xa1 */ +#define RK3328_PRE_PLL_PRE_DIV_MASKGENMASK(5, 0) +#define RK3328_PRE_PLL_PRE_DIV(x) UPDATE(x, 5, 0) +/* REG: 0xa2 */ +/* unset means center spread */ +#define RK3328_SPREAD_SPECTRUM_MOD_DOWNBIT(7) +#define RK3328_SPREAD_SPECTRUM_MOD_DISABLE BIT(6) +#define RK3328_PRE_PLL_FRAC_DIV_DISABLEUPDATE(3, 5, 4) +#define RK3328_PRE_PLL_FB_DIV_11_8_MASKGENMASK(3, 0) +#define RK3328_PRE_PLL_FB_DIV_11_8(x) UPDATE((x) >> 8, 3, 0) +/* REG: 0xa3 */ +#define RK3328_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) +/* REG: 0xa4*/ +#define RK3328_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(1, 0) +#define RK3328_PRE_PLL_TMDSCLK_DIV_C(x)UPDATE(x, 1, 0) +#define RK3328_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(3, 2) +#define RK3328_PRE_PLL_TMDSCLK_DIV_B(x)UPDATE(x, 3, 2) +#define RK3328_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(5, 4) +#define RK3328_PRE_PLL_TMDSCLK_DIV_A(x)UPDATE(x, 5, 4) +/* REG: 0xa5 */ +#define RK3328_PRE_PLL_PCLK_DIV_B_SHIFT5 +#define RK3328_PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5) +#define RK3328_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5) +#define RK3328_PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0
[PATCH v2 10/17] clk: rk3328: Add get hdmiphy clock
From: Jagan Teki
Add support to get the hdmiphy clock for RK3328 PCLK_HDMIPHY.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/clk/rockchip/clk_rk3328.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3328.c
b/drivers/clk/rockchip/clk_rk3328.c
index ee7edb9d10..5bb9238abb 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -179,6 +179,10 @@ enum {
CLK_I2C3_DIV_CON_SHIFT = 8,
CLK_I2C2_PLL_SEL_SHIFT = 7,
CLK_I2C2_DIV_CON_SHIFT = 0,
+
+ /* CLKSEL_CON40 */
+ CLK_HDMIPHY_DIV_CON_SHIFT = 3,
+ CLK_HDMIPHY_DIV_CON_MASK= 0x7 << CLK_HDMIPHY_DIV_CON_SHIFT,
};
#define VCO_MAX_KHZ(3200 * (MHz / KHz))
@@ -661,6 +665,16 @@ static ulong rk3328_vop_set_clk(struct rk3328_clk_priv
*priv,
}
#endif
+static ulong rk3328_hdmiphy_get_clk(struct rk3328_cru *cru)
+{
+ u32 div, con;
+
+ con = readl(>clksel_con[40]);
+ div = (con & CLK_HDMIPHY_DIV_CON_MASK) >> CLK_HDMIPHY_DIV_CON_SHIFT;
+
+ return DIV_TO_RATE(GPLL_HZ, div);
+}
+
static ulong rk3328_clk_get_rate(struct clk *clk)
{
struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
@@ -690,6 +704,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
case SCLK_SPI:
rate = rk3328_spi_get_clk(priv->cru);
break;
+ case PCLK_HDMIPHY:
+ rate = rk3328_hdmiphy_get_clk(priv->cru);
+ break;
default:
return -ENOENT;
}
--
2.25.1
[PATCH v2 09/17] clk: rockchip: rk3328: Add VOP clk support
From: Jagan Teki
VOP get and set clock would needed for VOP drivers.
Add support for it.
Signed-off-by: Jagan Teki
---
Changes for v2:
- Add DCLK get rate
.../include/asm/arch-rockchip/cru_rk3328.h| 34 +++
drivers/clk/rockchip/clk_rk3328.c | 88 ++-
2 files changed, 120 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
index 226744d67d..4ad1d33e05 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
@@ -62,6 +62,40 @@ check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
enum apll_frequencies {
APLL_816_MHZ,
APLL_600_MHZ,
+
+ /* CRU_CLK_SEL37_CON */
+ ACLK_VIO_PLL_SEL_CPLL = 0,
+ ACLK_VIO_PLL_SEL_GPLL = 1,
+ ACLK_VIO_PLL_SEL_HDMIPHY= 2,
+ ACLK_VIO_PLL_SEL_USB480M= 3,
+ ACLK_VIO_PLL_SEL_SHIFT = 6,
+ ACLK_VIO_PLL_SEL_MASK = 3 << ACLK_VIO_PLL_SEL_SHIFT,
+ ACLK_VIO_DIV_CON_SHIFT = 0,
+ ACLK_VIO_DIV_CON_MASK = 0x1f << ACLK_VIO_DIV_CON_SHIFT,
+ HCLK_VIO_DIV_CON_SHIFT = 8,
+ HCLK_VIO_DIV_CON_MASK = 0x1f << HCLK_VIO_DIV_CON_SHIFT,
+
+ /* CRU_CLK_SEL39_CON */
+ ACLK_VOP_PLL_SEL_CPLL = 0,
+ ACLK_VOP_PLL_SEL_GPLL = 1,
+ ACLK_VOP_PLL_SEL_HDMIPHY= 2,
+ ACLK_VOP_PLL_SEL_USB480M= 3,
+ ACLK_VOP_PLL_SEL_SHIFT = 6,
+ ACLK_VOP_PLL_SEL_MASK = 3 << ACLK_VOP_PLL_SEL_SHIFT,
+ ACLK_VOP_DIV_CON_SHIFT = 0,
+ ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
+
+ /* CRU_CLK_SEL40_CON */
+ DCLK_LCDC_PLL_SEL_GPLL = 0,
+ DCLK_LCDC_PLL_SEL_CPLL = 1,
+ DCLK_LCDC_PLL_SEL_SHIFT = 0,
+ DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT,
+ DCLK_LCDC_SEL_HDMIPHY = 0,
+ DCLK_LCDC_SEL_PLL = 1,
+ DCLK_LCDC_SEL_SHIFT = 1,
+ DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT,
+ DCLK_LCDC_DIV_CON_SHIFT = 8,
+ DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT,
};
void rk3328_configure_cpu(struct rk3328_cru *cru,
diff --git a/drivers/clk/rockchip/clk_rk3328.c
b/drivers/clk/rockchip/clk_rk3328.c
index ef97381f0e..ee7edb9d10 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -581,6 +581,86 @@ static ulong rk3328_spi_set_clk(struct rk3328_cru *cru,
uint hz)
return rk3328_spi_get_clk(cru);
}
+#ifndef CONFIG_SPL_BUILD
+static ulong rk3328_vop_get_clk(struct rk3328_clk_priv *priv, ulong clk_id)
+{
+ struct rk3328_cru *cru = priv->cru;
+ u32 div, con, parent;
+
+ switch (clk_id) {
+ case ACLK_VOP_PRE:
+ con = readl(>clksel_con[39]);
+ div = (con & ACLK_VOP_DIV_CON_MASK) >> ACLK_VOP_DIV_CON_SHIFT;
+ parent = GPLL_HZ;
+ break;
+ case ACLK_VIO_PRE:
+ con = readl(>clksel_con[37]);
+ div = (con & ACLK_VIO_DIV_CON_MASK) >> ACLK_VIO_DIV_CON_SHIFT;
+ parent = GPLL_HZ;
+ break;
+ case DCLK_LCDC:
+ con = readl(>clksel_con[40]);
+ div = (con & DCLK_LCDC_DIV_CON_MASK) >> DCLK_LCDC_DIV_CON_SHIFT;
+ parent = GPLL_HZ;
+ break;
+ default:
+ printf("%s: Unsupported vop get clk#%ld\n", __func__, clk_id);
+ return -ENOENT;
+ }
+
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3328_vop_set_clk(struct rk3328_clk_priv *priv,
+ ulong clk_id, uint hz)
+{
+ struct rk3328_cru *cru = priv->cru;
+ int src_clk_div;
+ u32 con, parent;
+
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);
+ assert(src_clk_div - 1 < 31);
+
+ switch (clk_id) {
+ case ACLK_VOP_PRE:
+ rk_clrsetreg(>clksel_con[39],
+ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
+ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
+(src_clk_div - 1) << ACLK_VOP_DIV_CON_SHIFT);
+ break;
+ case ACLK_VIO_PRE:
+ rk_clrsetreg(>clksel_con[37],
+ACLK_VIO_PLL_SEL_MASK | ACLK_VIO_DIV_CON_MASK,
+ACLK_VIO_PLL_SEL_CPLL << ACLK_VIO_PLL_SEL_SHIFT |
+(src_clk_div - 1) << ACLK_VIO_DIV_CON_SHIFT);
+ break;
+ case DCLK_LCDC:
+ con = readl(>clksel_con[40]);
+ con = (con & DCLK_LCDC_SEL_MASK) >&
[PATCH v2 08/17] video: rockchip: vop: Add dsp offset support
From: Jagan Teki
Unlike RK3399, RK3288 the Newer Rockchip SoC's like RK3328 have
different offsets for dsp registers.
Group the dsp register set via dsp_regs pointers so that dsp_offset
would point the dsp_regs to access for any changes in the offset value.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/video/rockchip/rk_vop.c | 14 --
drivers/video/rockchip/rk_vop.h | 2 ++
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index b719a4e4ea..acc02e5d7c 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -165,6 +165,7 @@ static void rkvop_mode_set(struct udevice *dev,
{
struct rk_vop_priv *priv = dev_get_priv(dev);
struct rk3288_vop *regs = priv->regs;
+ struct rk3288_vop *dsp_regs = priv->regs + priv->dsp_offset;
struct rkvop_driverdata *data =
(struct rkvop_driverdata *)dev_get_driver_data(dev);
@@ -198,27 +199,27 @@ static void rkvop_mode_set(struct udevice *dev,
writel(V_HSYNC(hsync_len) |
V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
- >dsp_htotal_hs_end);
+ _regs->dsp_htotal_hs_end);
writel(V_HEAP(hsync_len + hback_porch + hactive) |
V_HASP(hsync_len + hback_porch),
- >dsp_hact_st_end);
+ _regs->dsp_hact_st_end);
writel(V_VSYNC(vsync_len) |
V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
- >dsp_vtotal_vs_end);
+ _regs->dsp_vtotal_vs_end);
writel(V_VAEP(vsync_len + vback_porch + vactive)|
V_VASP(vsync_len + vback_porch),
- >dsp_vact_st_end);
+ _regs->dsp_vact_st_end);
writel(V_HEAP(hsync_len + hback_porch + hactive) |
V_HASP(hsync_len + hback_porch),
- >post_dsp_hact_info);
+ _regs->post_dsp_hact_info);
writel(V_VAEP(vsync_len + vback_porch + vactive)|
V_VASP(vsync_len + vback_porch),
- >post_dsp_vact_info);
+ _regs->post_dsp_vact_info);
writel(0x01, >reg_cfg_done); /* enable reg config */
}
@@ -452,6 +453,7 @@ int rk_vop_probe(struct udevice *dev)
priv->regs = dev_read_addr_ptr(dev);
priv->win_offset = ops->win_offset;
+ priv->dsp_offset = ops->dsp_offset;
/*
* Try all the ports until we find one that works. In practice this
diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h
index 909f5602e5..eba68d87c4 100644
--- a/drivers/video/rockchip/rk_vop.h
+++ b/drivers/video/rockchip/rk_vop.h
@@ -12,6 +12,7 @@ struct rk_vop_priv {
void *grf;
void *regs;
int win_offset;
+ int dsp_offset;
};
enum vop_features {
@@ -20,6 +21,7 @@ enum vop_features {
struct rkvop_driverdata {
int win_offset;
+ int dsp_offset;
/* configuration */
u32 features;
/* block-specific setters/getters */
--
2.25.1
[PATCH v2 07/17] video: rockchip: vop: Add win offset support
From: Jagan Teki
Unlike RK3399, RK3288 the Newer Rockchip SoC's like RK3328 have
different offsets for win registers.
Group the win register set via win_regs pointers so that win_offset
would point the win_regs to access for any changes in the offset value.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/video/rockchip/rk_vop.c | 22 +-
drivers/video/rockchip/rk_vop.h | 2 ++
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index 158ba7cbf6..b719a4e4ea 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -46,6 +46,7 @@ static void rkvop_enable(struct udevice *dev, ulong fbbase,
{
struct rk_vop_priv *priv = dev_get_priv(dev);
struct rk3288_vop *regs = priv->regs;
+ struct rk3288_vop *win_regs = priv->regs + priv->win_offset;
u32 lb_mode;
u32 rgb_mode;
u32 hactive = edid->hactive.typ;
@@ -53,32 +54,32 @@ static void rkvop_enable(struct udevice *dev, ulong fbbase,
int ret;
writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
- >win0_act_info);
+ _regs->win0_act_info);
writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
- >win0_dsp_st);
+ _regs->win0_dsp_st);
writel(V_DSP_WIDTH(hactive - 1) |
V_DSP_HEIGHT(vactive - 1),
- >win0_dsp_info);
+ _regs->win0_dsp_info);
- clrsetbits_le32(>win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
+ clrsetbits_le32(_regs->win0_color_key, M_WIN0_KEY_EN |
M_WIN0_KEY_COLOR,
V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
switch (fb_bits_per_pixel) {
case 16:
rgb_mode = RGB565;
- writel(V_RGB565_VIRWIDTH(hactive), >win0_vir);
+ writel(V_RGB565_VIRWIDTH(hactive), _regs->win0_vir);
break;
case 24:
rgb_mode = RGB888;
- writel(V_RGB888_VIRWIDTH(hactive), >win0_vir);
+ writel(V_RGB888_VIRWIDTH(hactive), _regs->win0_vir);
break;
case 32:
default:
rgb_mode = ARGB;
- writel(V_ARGB888_VIRWIDTH(hactive), >win0_vir);
+ writel(V_ARGB888_VIRWIDTH(hactive), _regs->win0_vir);
break;
}
@@ -91,12 +92,12 @@ static void rkvop_enable(struct udevice *dev, ulong fbbase,
else
lb_mode = LB_RGB_1280X8;
- clrsetbits_le32(>win0_ctrl0,
+ clrsetbits_le32(_regs->win0_ctrl0,
M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
V_WIN0_EN(1));
- writel(fbbase, >win0_yrgb_mst);
+ writel(fbbase, _regs->win0_yrgb_mst);
writel(0x01, >reg_cfg_done); /* enable reg config */
ret = reset_assert(dclk_rst);
@@ -415,6 +416,8 @@ int rk_vop_probe(struct udevice *dev)
{
struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct rk_vop_priv *priv = dev_get_priv(dev);
+ struct rkvop_driverdata *ops =
+ (struct rkvop_driverdata *)dev_get_driver_data(dev);
int ret = 0;
ofnode port, node;
struct reset_ctl ahb_rst;
@@ -448,6 +451,7 @@ int rk_vop_probe(struct udevice *dev)
#endif
priv->regs = dev_read_addr_ptr(dev);
+ priv->win_offset = ops->win_offset;
/*
* Try all the ports until we find one that works. In practice this
diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h
index 0528fb23f5..909f5602e5 100644
--- a/drivers/video/rockchip/rk_vop.h
+++ b/drivers/video/rockchip/rk_vop.h
@@ -11,6 +11,7 @@
struct rk_vop_priv {
void *grf;
void *regs;
+ int win_offset;
};
enum vop_features {
@@ -18,6 +19,7 @@ enum vop_features {
};
struct rkvop_driverdata {
+ int win_offset;
/* configuration */
u32 features;
/* block-specific setters/getters */
--
2.25.1
[PATCH v2 06/17] video: rockchip: vop: Simplify rkvop_enable
From: Jagan Teki
Get the regs from priv pointer instead of passing it an argument.
This would simplify the code and better readability.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/video/rockchip/rk_vop.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index c514e2a0e4..158ba7cbf6 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -39,11 +39,13 @@ enum vop_pol {
DCLK_INVERT= 3
};
-static void rkvop_enable(struct udevice *dev, struct rk3288_vop *regs, ulong
fbbase,
+static void rkvop_enable(struct udevice *dev, ulong fbbase,
int fb_bits_per_pixel,
const struct display_timing *edid,
struct reset_ctl *dclk_rst)
{
+ struct rk_vop_priv *priv = dev_get_priv(dev);
+ struct rk3288_vop *regs = priv->regs;
u32 lb_mode;
u32 rgb_mode;
u32 hactive = edid->hactive.typ;
@@ -243,9 +245,7 @@ static void rkvop_mode_set(struct udevice *dev,
static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
{
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
- struct rk_vop_priv *priv = dev_get_priv(dev);
int vop_id, remote_vop_id;
- struct rk3288_vop *regs = priv->regs;
struct display_timing timing;
struct udevice *disp;
int ret;
@@ -380,7 +380,7 @@ static int rk_display_init(struct udevice *dev, ulong
fbbase, ofnode ep_node)
return ret;
}
- rkvop_enable(dev, regs, fbbase, 1 << l2bpp, , _rst);
+ rkvop_enable(dev, fbbase, 1 << l2bpp, , _rst);
ret = display_enable(disp, 1 << l2bpp, );
if (ret)
--
2.25.1
[PATCH v2 05/17] video: dw_hdmi: Add setup_hpd hook
From: Jagan Teki
Add support for DW HDMI Setup HPD status.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/video/dw_hdmi.c | 3 +++
include/dw_hdmi.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index 172e6b45a6..3e0e20e59b 100644
--- a/drivers/video/dw_hdmi.c
+++ b/drivers/video/dw_hdmi.c
@@ -1080,4 +1080,7 @@ void dw_hdmi_init(struct dw_hdmi *hdmi)
/* enable i2c client nack % arbitration error irq */
hdmi_write(hdmi, ~0x44, HDMI_I2CM_CTLINT);
+
+ if (hdmi->ops->setup_hpd)
+ hdmi->ops->setup_hpd(hdmi);
}
diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
index d6de472cee..9a44b9e90c 100644
--- a/include/dw_hdmi.h
+++ b/include/dw_hdmi.h
@@ -539,6 +539,7 @@ struct dw_hdmi;
struct dw_hdmi_phy_ops {
int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
void (*read_hpd)(struct dw_hdmi *hdmi, bool hdp_status);
+ void (*setup_hpd)(struct dw_hdmi *hdmi);
};
struct dw_hdmi_plat_data {
--
2.25.1
[PATCH v2 04/17] video: dw_hdmi: Add read_hpd hook
From: Jagan Teki
Add support for DW HDMI Read HPD status.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/video/dw_hdmi.c | 3 +++
include/dw_hdmi.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index 0a597206f0..172e6b45a6 100644
--- a/drivers/video/dw_hdmi.c
+++ b/drivers/video/dw_hdmi.c
@@ -946,6 +946,9 @@ int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi)
return -ENODEV;
}
+ if (hdmi->ops->read_hpd)
+ hdmi->ops->read_hpd(hdmi, true);
+
return 0;
}
diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
index 756560e092..d6de472cee 100644
--- a/include/dw_hdmi.h
+++ b/include/dw_hdmi.h
@@ -538,6 +538,7 @@ struct dw_hdmi;
struct dw_hdmi_phy_ops {
int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
+ void (*read_hpd)(struct dw_hdmi *hdmi, bool hdp_status);
};
struct dw_hdmi_plat_data {
--
2.25.1
[PATCH v2 03/17] video: dw_hdmi: Extend the HPD detection
From: Jagan Teki
HPD detection on some DW HDMIdesigned SoC's would need to read and
setup the HPD status explicitly.
So, extend the HPD detection code by adding the dw_hdmi_detect_hpd
function and move the default detection code caller there.
The new read and setup hdp will integrate the same function in
later patches.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/video/dw_hdmi.c | 13 +
drivers/video/rockchip/rk_hdmi.c| 8 +++-
drivers/video/sunxi/sunxi_dw_hdmi.c | 8 +++-
include/dw_hdmi.h | 1 +
4 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index ea12a09407..0a597206f0 100644
--- a/drivers/video/dw_hdmi.c
+++ b/drivers/video/dw_hdmi.c
@@ -936,6 +936,19 @@ int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi)
return -1;
}
+int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi)
+{
+ int ret;
+
+ ret = dw_hdmi_phy_wait_for_hpd(hdmi);
+ if (ret < 0) {
+ debug("hdmi can not get hpd signal\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
void dw_hdmi_phy_init(struct dw_hdmi *hdmi)
{
/* enable phy i2cm done irq */
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index e34f532cd6..8a65f2440e 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -115,11 +115,9 @@ int rk_hdmi_probe(struct udevice *dev)
dw_hdmi_init(hdmi);
dw_hdmi_phy_init(hdmi);
- ret = dw_hdmi_phy_wait_for_hpd(hdmi);
- if (ret < 0) {
- debug("hdmi can not get hpd signal\n");
- return -1;
- }
+ ret = dw_hdmi_detect_hpd(hdmi);
+ if (ret < 0)
+ return ret;
return 0;
}
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c
b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 4b67a1614e..513276d812 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -358,11 +358,9 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
sunxi_dw_hdmi_phy_init(>hdmi);
- ret = dw_hdmi_phy_wait_for_hpd(>hdmi);
- if (ret < 0) {
- debug("hdmi can not get hpd signal\n");
- return -1;
- }
+ ret = dw_hdmi_detect_hpd(>hdmi);
+ if (ret < 0)
+ return ret;
dw_hdmi_init(>hdmi);
diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
index 4ad8b39f84..756560e092 100644
--- a/include/dw_hdmi.h
+++ b/include/dw_hdmi.h
@@ -568,5 +568,6 @@ void dw_hdmi_phy_init(struct dw_hdmi *hdmi);
int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid);
int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size);
void dw_hdmi_init(struct dw_hdmi *hdmi);
+int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi);
#endif
--
2.25.1
[PATCH v2 02/17] video: dw_hdmi: Add Vendor PHY handling
From: Jagan Teki
DW HDMI support Vendor PHY like Rockchip RK3328 Inno HDMI PHY.
Extend the vendor phy handling by adding platform phy hooks.
Signed-off-by: Jagan Teki
---
Changes for v2:
- fix meson cfg
drivers/video/dw_hdmi.c | 29 +++-
drivers/video/meson/meson_dw_hdmi.c | 11 ++-
drivers/video/rockchip/rk3399_hdmi.c | 8 +++-
drivers/video/rockchip/rk_hdmi.c | 2 +-
drivers/video/sunxi/sunxi_dw_hdmi.c | 11 ++-
include/dw_hdmi.h| 14 +-
6 files changed, 69 insertions(+), 6 deletions(-)
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index c4fbb18294..ea12a09407 100644
--- a/drivers/video/dw_hdmi.c
+++ b/drivers/video/dw_hdmi.c
@@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct
display_timing *edid)
hdmi_av_composer(hdmi, edid);
- ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
+ ret = hdmi->ops->phy_set(hdmi, edid->pixelclock.typ);
if (ret)
return ret;
@@ -1009,10 +1009,37 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct
display_timing *edid)
return 0;
}
+static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
+ .phy_set = dw_hdmi_phy_cfg,
+};
+
+static void dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
+{
+ if (!hdmi->data)
+ return;
+
+ /* hook Synopsys PHYs ops */
+ if (!hdmi->data->phy_force_vendor) {
+ hdmi->ops = _hdmi_synopsys_phy_ops;
+ return;
+ }
+
+ /* Vendor HDMI PHYs must assign phy_ops in plat_data */
+ if (!hdmi->data->phy_ops) {
+ printf("Unsupported Vendor HDMI phy_ops\n");
+ return;
+ }
+
+ /* hook Vendor HDMI PHYs ops */
+ hdmi->ops = hdmi->data->phy_ops;
+}
+
void dw_hdmi_init(struct dw_hdmi *hdmi)
{
uint ih_mute;
+ dw_hdmi_detect_phy(hdmi);
+
/*
* boot up defaults are:
* hdmi_ih_mute = 0x03 (disabled)
diff --git a/drivers/video/meson/meson_dw_hdmi.c
b/drivers/video/meson/meson_dw_hdmi.c
index 5db01904b5..d0d878b6af 100644
--- a/drivers/video/meson/meson_dw_hdmi.c
+++ b/drivers/video/meson/meson_dw_hdmi.c
@@ -375,6 +375,15 @@ static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi)
return -ETIMEDOUT;
}
+static const struct dw_hdmi_phy_ops dw_hdmi_meson_phy_ops = {
+ .phy_set = meson_dw_hdmi_phy_init,
+};
+
+static const struct dw_hdmi_plat_data dw_hdmi_meson_plat_data = {
+ .phy_force_vendor = true,
+ .phy_ops = _hdmi_meson_phy_ops,
+};
+
static int meson_dw_hdmi_probe(struct udevice *dev)
{
struct meson_dw_hdmi *priv = dev_get_priv(dev);
@@ -397,7 +406,7 @@ static int meson_dw_hdmi_probe(struct udevice *dev)
priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
- priv->hdmi.phy_set = meson_dw_hdmi_phy_init;
+ priv->hdmi.data = _hdmi_meson_plat_data;
if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
priv->hdmi.reg_io_width = 1;
else {
diff --git a/drivers/video/rockchip/rk3399_hdmi.c
b/drivers/video/rockchip/rk3399_hdmi.c
index 3041360c6e..b32139a8a6 100644
--- a/drivers/video/rockchip/rk3399_hdmi.c
+++ b/drivers/video/rockchip/rk3399_hdmi.c
@@ -64,8 +64,14 @@ static const struct dm_display_ops rk3399_hdmi_ops = {
.enable = rk3399_hdmi_enable,
};
+static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
+};
+
static const struct udevice_id rk3399_hdmi_ids[] = {
- { .compatible = "rockchip,rk3399-dw-hdmi" },
+ {
+ .compatible = "rockchip,rk3399-dw-hdmi",
+ .data = (ulong)_hdmi_drv_data
+ },
{ }
};
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index b75a174489..e34f532cd6 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -83,6 +83,7 @@ int rk_hdmi_of_to_plat(struct udevice *dev)
struct rk_hdmi_priv *priv = dev_get_priv(dev);
struct dw_hdmi *hdmi = >hdmi;
+ hdmi->data = (const struct dw_hdmi_plat_data *)dev_get_driver_data(dev);
hdmi->ioaddr = (ulong)dev_read_addr(dev);
hdmi->mpll_cfg = rockchip_mpll_cfg;
hdmi->phy_cfg = rockchip_phy_config;
@@ -90,7 +91,6 @@ int rk_hdmi_of_to_plat(struct udevice *dev)
/* hdmi->i2c_clk_{high,low} are set up by the SoC driver */
hdmi->reg_io_width = 4;
- hdmi->phy_set = dw_hdmi_phy_cfg;
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c
b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 0324a050d0..4b67a1614e 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi
[PATCH v2 01/17] video: rockchip: hdmi: Detect hpd after controller init
From: Jagan Teki
HDP is a hardware connector event, so detect the same once the
controller and attached PHY initialization are done.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/video/rockchip/rk_hdmi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 8dcd4d5964..b75a174489 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -112,14 +112,14 @@ int rk_hdmi_probe(struct udevice *dev)
struct dw_hdmi *hdmi = >hdmi;
int ret;
+ dw_hdmi_init(hdmi);
+ dw_hdmi_phy_init(hdmi);
+
ret = dw_hdmi_phy_wait_for_hpd(hdmi);
if (ret < 0) {
debug("hdmi can not get hpd signal\n");
return -1;
}
- dw_hdmi_init(hdmi);
- dw_hdmi_phy_init(hdmi);
-
return 0;
}
--
2.25.1
[PATCH v2 00/17] video: dw_hdmi: Support Vendor PHY
From: Jagan Teki Unlike RK3399, Sunxi/Meson DW HDMI the new Rockchip SoC Rk3328 would support external vendor PHY with DW HDMI chip. Support this vendor PHY by adding new platform PHY ops via DW HDMI driver and call the respective generic phy from platform driver code. This series tested in RK3328 with 1080p (1920x1080) resolution. Patch 0001/0005: Support Vendor PHY Patch 0006/0008: VOP extension for win, dsp offsets Patch 0009/0010: RK3328 VOP, HDMI clocks Patch 0011: Rockchip Inno HDMI PHY Patch 0012: RK3328 HDMI driver Patch 0013: RK3328 VOP driver Patch 0014/0017: Enable HDMI Out for RK3328 Changes for v2: - Use proper cfg function for meson - Add VOP cleanup code. - Add DCLK get rate Linux VOP/HDMI out issues seems resolved with explicit VOP cleanup. V1: https://patchwork.ozlabs.org/project/uboot/cover/20231211085939.5478-1-ja...@amarulasolutions.com/ Any inputs? Jagan. Jagan Teki (17): video: rockchip: hdmi: Detect hpd after controller init video: dw_hdmi: Add Vendor PHY handling video: dw_hdmi: Extend the HPD detection video: dw_hdmi: Add read_hpd hook video: dw_hdmi: Add setup_hpd hook video: rockchip: vop: Simplify rkvop_enable video: rockchip: vop: Add win offset support video: rockchip: vop: Add dsp offset support clk: rockchip: rk3328: Add VOP clk support clk: rk3328: Add get hdmiphy clock phy: rockchip: Add Rockchip INNO HDMI PHY driver video: rockchip: Add rk3328 hdmi support video: rockchip: Add rk3328 vop support ARM: dts: rk3328: Enable VOP for bootph-all rockchip: Enable preconsole for rk3328 configs: evb-rk3328: Enable vidconsole for rk3328 configs: Enable HDMI Out for ROC-RK3328-CC arch/arm/dts/rk3328-u-boot.dtsi | 4 + .../include/asm/arch-rockchip/cru_rk3328.h| 34 + arch/arm/mach-rockchip/Kconfig| 1 + common/Kconfig| 2 +- configs/roc-cc-rk3328_defconfig | 5 + drivers/clk/rockchip/clk_rk3328.c | 105 ++- drivers/phy/rockchip/Kconfig | 7 + drivers/phy/rockchip/Makefile | 1 + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 885 ++ drivers/video/dw_hdmi.c | 48 +- drivers/video/meson/meson_dw_hdmi.c | 11 +- drivers/video/rockchip/Makefile | 2 + drivers/video/rockchip/rk3328_hdmi.c | 131 +++ drivers/video/rockchip/rk3328_vop.c | 83 ++ drivers/video/rockchip/rk3399_hdmi.c | 8 +- drivers/video/rockchip/rk_hdmi.c | 12 +- drivers/video/rockchip/rk_hdmi.h | 3 + drivers/video/rockchip/rk_vop.c | 44 +- drivers/video/rockchip/rk_vop.h | 4 + drivers/video/sunxi/sunxi_dw_hdmi.c | 19 +- include/configs/evb_rk3328.h | 5 + include/configs/rk3328_common.h | 1 + include/dw_hdmi.h | 17 +- 23 files changed, 1393 insertions(+), 39 deletions(-) create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c create mode 100644 drivers/video/rockchip/rk3328_hdmi.c create mode 100644 drivers/video/rockchip/rk3328_vop.c -- 2.25.1
Re: [PATCH 00/17] video: dw_hdmi: Support Vendor PHY
On Mon, Dec 18, 2023 at 7:23 PM Robin Murphy wrote: > > On 2023-12-15 7:13 am, Kever Yang wrote: > > Hi Jagan, > > > > On 2023/12/15 14:36, Jagan Teki wrote: > >> Hi Heiko/Kerver/Anatoloj, > >> > >> On Mon, Dec 11, 2023 at 2:30 PM Jagan Teki > >> wrote: > >>> Unlike RK3399, Sunxi/Meson DW HDMI the new Rockchip SoC Rk3328 would > >>> support external vendor PHY with DW HDMI chip. > >>> > >>> Support this vendor PHY by adding new platform PHY ops via DW HDMI > >>> driver and call the respective generic phy from platform driver code. > >>> > >>> This series tested in RK3328 with 1080p (1920x1080) resolution. > >>> > >>> Patch 0001/0005: Support Vendor PHY > >>> Patch 0006/0008: VOP extension for win, dsp offsets > >>> Patch 0009/0010: RK3328 VOP, HDMI clocks > >>> Patch 0011: Rockchip Inno HDMI PHY > >>> Patch 0012: RK3328 HDMI driver > >>> Patch 0013: RK3328 VOP driver > >>> Patch 0014/0017: Enable HDMI Out for RK3328 > >>> > >>> Importent: > >>> One pontential issues is that Linux HDMI out on RK3328 has effected by > >>> this patchset as I wouldn't find any relation or clue. > >>> > >>> [0.752016] Loading compiled-in X.509 certificates > >>> [0.787796] inno_hdmi_phy_rk3328_clk_recalc_rate: parent 2400 > >>> [0.788391] inno-hdmi-phy ff43.phy: > >>> inno_hdmi_phy_rk3328_clk_recalc_rate rate 14850 vco 14850 > >>> [0.798353] rockchip-drm display-subsystem: bound ff37.vop > >>> (ops vop_component_ops) > >>> [0.799403] dwhdmi-rockchip ff3c.hdmi: supply avdd-0v9 not > >>> found, using dummy regulator > >>> [0.800288] rk_iommu ff373f00.iommu: Enable stall request timed > >>> out, status: 0x4b > >>> [0.801131] dwhdmi-rockchip ff3c.hdmi: supply avdd-1v8 not > >>> found, using dummy regulator > >>> [0.802056] rk_iommu ff373f00.iommu: Disable paging request timed > >>> out, status: 0x4b > >>> [0.803233] dwhdmi-rockchip ff3c.hdmi: Detected HDMI TX > >>> controller v2.11a with HDCP (inno_dw_hdmi_phy2) > >>> [0.805355] dwhdmi-rockchip ff3c.hdmi: registered DesignWare > >>> HDMI I2C bus driver > >>> [0.808769] rockchip-drm display-subsystem: bound ff3c.hdmi > >>> (ops dw_hdmi_rockchip_ops) > >>> [0.810869] [drm] Initialized rockchip 1.0.0 20140818 for > >>> display-subsystem on minor 0 > >>> > >>> The only way I can use Linux HDMI by disabling IOMMU or support > >>> disable-iommu link for RK3328 via DT [1]. > >>> > >>> [1] https://www.spinics.net/lists/devicetree/msg605124.html > >> Is anyone aware of this issue? I did post the patches for Linux IOMMU > >> but seems not a proper solution. Any suggestions? > > > > I'm not expert in HDMI/VOP, so I can't provide a suitable solution in > > the kernel, > > > > but here is the reason why we need patch to workaround the issue in the > > kernel: > > > > - The VOP driver working in U-Boot is non-IOMMU mode, and the VOP access > > DDR by physical address; > > > > - The VOP driver working in kernel with IOMMU enabled(by default), the > > VOP access DDR with virtual address(by IOMMU); > > > > - The VOP is keep working in kernel before kernel VOP driver is enabled, > > and the IOMMU driver will be enabled by > > > > the Linux PM framework, since the IOMMU is not correctly configured > > at this point, the VOP will access unknown > > > > space(the original physical address in U-Boot) convert by IOMMU; > > > > So we need to disable the IOMMU temporary in kernel startup before VOP > > driver is enabled. > > If U-Boot isn't handing off an active framebuffer, then it should be > U-Boot's responsibility to stop the VOP before it exits; if on the other > hand it is, then it can now use the "iommu-addresses" DT property (see > the reserved-memory schema) on the framebuffer region, and we should > just need a bit of work in the IOMMU driver to ensure that is respected > during the period between the IOMMU initialising and the Linux VOP > driver subsequently taking over (i.e. so it won't get stuck on an > unexpected page fault as seems to be happening above). The IOMMU aspect > of that ought to be fairly straightforward; the trickier part might be > the runtime PM aspect to ensure the IOMMU doesn't let itself go idle and > actually turn anything off during that period. I also still think that > doing the full rk_iommu_disable() upon runtime suspend is wrong, but > that's more of a thing which confounds the underlying issue here, rather > than being the problem in itself. Thanks for your comments. Okay, keeping the Linux IOMMU issue aside I think whatever change that u-boot makes on VOP has to clear it before handoff to Linux - so clearing the VOP registers during handoff seems working. I only wonder why it happens only on RK3328 (RK3399 and RK3288 seem fine). I will post the next version with VOP clear during handoff. Thanks, Jagan.
Re: [PATCH 13/17] video: rockchip: Add rk3328 vop support
Please don't top-post. On Sun, Dec 17, 2023 at 4:15 AM Johan Jonker wrote: > > Hi Jagan, > > In your patch U-boot users must add a new file for each new Rockchip SoC. > > With the VOP2 introduction the VOP1 structures and functions are > frozen/stabilized. > > My proposal would be to use a file simular to Linux rockchip_vop_reg.c and > port it to U-boot as is done in the manufacturer tree. > > Together with a simple basic rockchip_vop.c to start with. > > Not sure if we need a kind of DRM frame work. > > Question: What do the U-boot maintainers think of this DRM implementation in > use by Rockchip. Is that a route that useful for mainline? > > Let me know your ideas. Yes, I got your point-based rockchip-bsp tree of DRM. Technically it wouldn't required as we have created this structure before and more likely the new RK SoCs like RK3568, RK3588 are working on this tree as well. Why do we need DRM framework as long as this seems suitable? Jagan.
Re: [PATCH] spi: dw: Use controller clock rate as maximum frequency
On Wed, Oct 25, 2023 at 1:20 PM Kunihiko Hayashi
wrote:
>
> Currently the controller driver has maximum frequency in plat->frequency
> that is specified by "spi-max-frequency" DT property in the controller
> node. This is special to U-Boot and doesn't exist to Linux.
>
> spi {
> spi-max-frequency = ;
> };
>
> Usually the frequency should be specified by "spi-max-frequency" at the
> slave device node.
>
> spi {
> slave {
> spi-max-frequency = ;
> };
> };
>
> The final maximum frequency is set to the smaller value of the controller
> node (A) and the slave device node (B).
>
> Currently, if the property in the controller node is omitted, the default
> frequency is fixed at 500kHz. Even if the controller and the slave device
> allow the higher frequency than 500kHz, the maximum frequency can't exceed
> 500kHz.
>
> The upper limit of the maximum frequency should be determined by the clock
> rate of the controller clock. And this patch determines the maximum
> frequency based on the clock rate if the controller node property isn't
> specified.
>
> Signed-off-by: Kunihiko Hayashi
> ---
Applied to u-boot-spi/master
Re: [PATCH v2] mtd: spi-nor: Add IS25LP02G flash support
On Mon, Dec 4, 2023 at 2:23 PM Venkatesh Yadav Abbarapu wrote: > > Add support for ISSI 256MB flash IS25LP02G. This part supports 4byte > opcodes. It also supports dual and quad read. > > Signed-off-by: Sreekanth Sunnam > Signed-off-by: Venkatesh Yadav Abbarapu > --- > Changes in v2: > - Fixed the name to Sreekanth Sunnam. > --- Applied to u-boot-spi/master
Re: [PATCH] mtd: spi-nor: Update block protection flags for ospi flash parts
On Mon, Nov 6, 2023 at 10:55 AM Venkatesh Yadav Abbarapu wrote: > > Updating the block protection flags for Gigadevice gd25lx256e and > ISSI is25wx256 OSPI flash parts. > > Signed-off-by: Venkatesh Yadav Abbarapu > --- Applied to u-boot-spi/master
Re: [PATCH] mtd: spi-nor: Add support for Macronix flash part
On Thu, Dec 14, 2023 at 10:06 PM Tejas Bhumkar wrote: > > Added support for Macronix OSPI flash parts MX25UM51345G > and MX66UM2G45G, with initial testing conducted on the > Tenzing-se1 board using STR mode for basic erase, write, > and readback operations. > > Signed-off-by: Tejas Bhumkar > --- Applied to u-boot-spi/master
Re: [PATCH] mtd: spinand: Add support for XTX XT26xxxDxxxxx
On Thu, Oct 19, 2023 at 8:51 AM Bruce Suen wrote: > > Add Support XTX Technology XT26G01DX, XT26G11DX, XT26Q01DX, > XT26G02DX, XT26G12DX, XT26Q02DX, XT26G04DX, and > XT26Q04DX SPI NAND. > > These are 3V/1.8V 1G/2G/4Gbit serial SLC NAND flash device with on-die > ECC(8bit strength per 512bytes). > > Datasheet Links: > - http://www.xtxtech.com/download/?AId=458 > - http://www.xtxtech.com/download/?AId=495 > > Signed-off-by: Bruce Suen > --- Can you rebase and send on top of master? This won't apply. Jagan.
Re: [PATCH v1] spi: dw: add check for Rx FIFO overflow
On Tue, Oct 17, 2023 at 12:35 PM Maksim Kiselev wrote: > > If even one byte is lost due to Rx FIFO overflow then we will never > exit the read loop. Because the (priv->rx != priv->rx_end) condition will > be always true. > > Let's check if Rx FIFO overflow occurred and exit the read loop > in this case. > > Signed-off-by: Maksim Kiselev > --- > drivers/spi/designware_spi.c | 24 +--- > 1 file changed, 21 insertions(+), 3 deletions(-) > > diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c > index 1c7d0ca310..0f443bff8e 100644 > --- a/drivers/spi/designware_spi.c > +++ b/drivers/spi/designware_spi.c > @@ -111,6 +111,15 @@ > #define SR_TX_ERR BIT(5) > #define SR_DCOLBIT(6) > > +/* Bit fields in ISR, IMR, RISR, 7 bits */ > +#define DW_SPI_INT_MASKGENMASK(5, 0) > +#define DW_SPI_INT_TXEIBIT(0) > +#define DW_SPI_INT_TXOIBIT(1) > +#define DW_SPI_INT_RXUIBIT(2) > +#define DW_SPI_INT_RXOIBIT(3) > +#define DW_SPI_INT_RXFIBIT(4) > +#define DW_SPI_INT_MSTIBIT(5) Why do we need unused macros? Jagan.
Re: [PATCH] mtd: spi: flash_is_unlocked return values fix
On Fri, Oct 27, 2023 at 9:22 PM Stanislav Bolshakov wrote: > > In accordance with the name of the function 'flash_is_unlocked()', > it is implied that the return value will be either 'true' or 'false'. > Moreover, calling this function from other parts of the program is > based precisely on this fact. The value of the pointer to the actual > called function 'flash_is_unlocked()' depends on the memory manufacturer > and can be stm_is_unlocked() or sst26_is_unlocked(). These two > functions have inconsistent return values. This patch fixes this > inconsistency. Missing s-o-b
Pull request: u-boot-spi/master [for-next]
Hi Tom, Please pull this PR for next. Summary: - spi_nor_read_sfdp_dma_unsafe (Vaishnav) - w25q01/02 (Jim) CI: https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/18995 thanks, Jagan. The following changes since commit 2f0282922b2c458eea7f85c500a948a587437b63: Prepare v2024.01-rc4 (2023-12-04 13:46:56 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-spi master for you to fetch changes up to 959a4a0838acf7ef733e000d1304cea6711b8945: spi: cadence-quadspi: Fix error message on stuck busy state (2023-12-14 23:56:19 +0530) Bruce Suen (1): mtd: spi-nor-ids: add support for xtx XT55Q02G Godfrey Mwangi (1): mtd: spi-nor: Add MT25QU128AB params Igor Prusov (1): mtd: spinand: add support for ESMT F50x1G41LB Jan Kiszka (1): spi: cadence-quadspi: Fix error message on stuck busy state Jim Liu (1): mtd: spi-nor: add flash model w25q01/02 support Jit Loon Lim (1): mtd: spi-nor: Add MT25U01G part number for SPI NOR Flash Jonas Karlman (1): mtd: spi-nor: Add support for Silicon Kaiser sk25lp128 Teik Heng Chong (1): drivers: mtd: spi: Add support for GD55LB02GEBIR SPI NOR flash Udit Kumar (1): spi: cadence_qspi: Select flash subnode at runtime Vaishnav Achath (1): mtd: spi-nor-core: Implement spi_nor_read_sfdp_dma_unsafe() for sfdp parse William Zhang (1): spi: bcm63xx-hsspi: Fix compiler warning drivers/mtd/nand/spi/Makefile | 3 +- drivers/mtd/nand/spi/core.c| 1 + drivers/mtd/nand/spi/esmt.c| 137 + drivers/mtd/spi/Kconfig| 5 ++ drivers/mtd/spi/spi-nor-core.c | 34 +- drivers/mtd/spi/spi-nor-ids.c | 23 +++ drivers/spi/bcm63xx_hsspi.c| 2 +- drivers/spi/cadence_qspi.c | 7 ++- drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 3 +- include/linux/mtd/spinand.h| 1 + 11 files changed, 210 insertions(+), 7 deletions(-) create mode 100644 drivers/mtd/nand/spi/esmt.c
Re: [PATCH 00/17] video: dw_hdmi: Support Vendor PHY
Hi Heiko/Kerver/Anatoloj, On Mon, Dec 11, 2023 at 2:30 PM Jagan Teki wrote: > > Unlike RK3399, Sunxi/Meson DW HDMI the new Rockchip SoC Rk3328 would > support external vendor PHY with DW HDMI chip. > > Support this vendor PHY by adding new platform PHY ops via DW HDMI > driver and call the respective generic phy from platform driver code. > > This series tested in RK3328 with 1080p (1920x1080) resolution. > > Patch 0001/0005: Support Vendor PHY > Patch 0006/0008: VOP extension for win, dsp offsets > Patch 0009/0010: RK3328 VOP, HDMI clocks > Patch 0011: Rockchip Inno HDMI PHY > Patch 0012: RK3328 HDMI driver > Patch 0013: RK3328 VOP driver > Patch 0014/0017: Enable HDMI Out for RK3328 > > Importent: > One pontential issues is that Linux HDMI out on RK3328 has effected by > this patchset as I wouldn't find any relation or clue. > > [0.752016] Loading compiled-in X.509 certificates > [0.787796] inno_hdmi_phy_rk3328_clk_recalc_rate: parent 2400 > [0.788391] inno-hdmi-phy ff43.phy: > inno_hdmi_phy_rk3328_clk_recalc_rate rate 14850 vco 14850 > [0.798353] rockchip-drm display-subsystem: bound ff37.vop (ops > vop_component_ops) > [0.799403] dwhdmi-rockchip ff3c.hdmi: supply avdd-0v9 not found, > using dummy regulator > [0.800288] rk_iommu ff373f00.iommu: Enable stall request timed out, > status: 0x4b > [0.801131] dwhdmi-rockchip ff3c.hdmi: supply avdd-1v8 not found, > using dummy regulator > [0.802056] rk_iommu ff373f00.iommu: Disable paging request timed out, > status: 0x4b > [0.803233] dwhdmi-rockchip ff3c.hdmi: Detected HDMI TX controller > v2.11a with HDCP (inno_dw_hdmi_phy2) > [0.805355] dwhdmi-rockchip ff3c.hdmi: registered DesignWare HDMI I2C > bus driver > [0.808769] rockchip-drm display-subsystem: bound ff3c.hdmi (ops > dw_hdmi_rockchip_ops) > [0.810869] [drm] Initialized rockchip 1.0.0 20140818 for > display-subsystem on minor 0 > > The only way I can use Linux HDMI by disabling IOMMU or support > disable-iommu link for RK3328 via DT [1]. > > [1] https://www.spinics.net/lists/devicetree/msg605124.html Is anyone aware of this issue? I did post the patches for Linux IOMMU but seems not a proper solution. Any suggestions? Thanks, Jagan.
Re: [PATCH] spi: cadence-quadspi: Fix error message on stuck busy state
On Mon, Oct 30, 2023 at 9:50 PM Jan Kiszka wrote: > > From: Jan Kiszka > > We are not iterating CQSPI_REG_RETRY, we are waiting 'timeout' ms, since > day 1. > > Signed-off-by: Jan Kiszka > --- Applied to u-boot-spi/master
Re: [PATCH] mtd: spi-nor-ids: add support for xtx XT55Q02G
On Wed, Oct 18, 2023 at 9:08 AM Bruce Suen wrote: > > Add support for XTX XT55Q02G(1.8V,2Gbit). > > Signed-off-by: Bruce Suen > --- Applied to u-boot-spi/master
Re: [PATCH v2 1/1] mtd: spinand: add support for ESMT F50x1G41LB
On Wed, Oct 18, 2023 at 12:59 AM Igor Prusov wrote: > > Adaptation of Linux commit d74c36480a67 > > This patch adds support for ESMT F50L1G41LB and F50D1G41LB. > It seems that ESMT likes to use random JEDEC ID from other vendors. > Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from > Micron. For this reason, the ESMT entry is named esmt_c8 with explicit > JEDEC ID in variable name. > > Datasheets: > https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50L1G41LB(2M).pdf > https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50D1G41LB(2M).pdf > > Signed-off-by: Igor Prusov > Signed-off-by: Chuanhong Guo > Signed-off-by: Martin Kurbanov > Signed-off-by: Dmitry Rokosov > Tested-by: Martin Kurbanov > --- Applied to u-boot-spi/master
Re: [PATCH v1] drivers: mtd: spi: Add support for GD55LB02GEBIR SPI NOR flash
On Fri, Aug 4, 2023 at 7:56 AM Jit Loon Lim wrote: > > From: Teik Heng Chong > > Add Support for GigaDevice GD55LB02GEBIR SPI NOR flash as QSPI > configuration flash > > Signed-off-by: Teik Heng Chong > --- Applied to u-boot-spi/master
Re: [PATCH v1] drivers: spi: Add MT25U01G part number for SPI NOR Flash
On Fri, Aug 4, 2023 at 7:57 AM Jit Loon Lim wrote: > > MT25QU01 OPN with 4B OPCODE support is currently not supported in > source code and the driver reuses the definition for "n25q00a" > which has the same silicon ID but is a slower part. > > Adding mt25u01g definition to the source code to support a faster > read response for MT25QU01 QSPI NOR Flash device. > > Signed-off-by: Jit Loon Lim > --- Applied u-boot-spi/master
Re: [PATCH] drivers: mtd: Add MT25QU128AB params
On Sat, Aug 5, 2023 at 2:05 AM wrote: > > From: Godfrey Mwangi > > Add Micron MT25QU128AB flash. > > Signed-off-by: Godfrey Mwangi > --- Applied u-boot-spi/master
Re: [PATCH v2] spi: cadence_qspi: Select flash subnode at runtime
On Tue, Sep 12, 2023 at 3:20 PM Udit Kumar wrote: > > Currently spi driver gets flash parameter from first subnode. > > Few boards have more than one flash with different parameters > and selection of flash is done by on board switch settings. > In such case, uboot needs to be recompiled with updated > device tree to align with board switch settings. > > This patch allows to select flash node at runtime. > > Boards those are supporting multiple flashes > needs to implement cadence_qspi_get_subnode function and return correct > flash node. > > Cc: Apurva Nandan > Signed-off-by: Udit Kumar > Reviewed-by: Neha Malcom Francis > --- Applied to u-boot-spi/master
Re: [PATCH v1] spi: spi-nor-ids: add flash model w25q01/02 support
On Tue, Sep 26, 2023 at 2:40 PM Jim Liu wrote: > > add flash w25q01jv, w25q01jvfim and w25q02jv support > > Signed-off-by: Jim Liu > --- Applied to u-boot-spi/master
Re: [PATCH 02/17] video: dw_hdmi: Add Vendor PHY handling
Hi Simon,
On Thu, Dec 14, 2023 at 1:21 AM Simon Glass wrote:
>
> Hi Jagan,
>
> On Mon, 11 Dec 2023 at 02:00, Jagan Teki wrote:
> >
> > From: Jagan Teki
> >
> > DW HDMI support Vendor PHY like Rockchip RK3328 Inno HDMI PHY.
> >
> > Extend the vendor phy handling by adding platform phy hooks.
> >
> > Signed-off-by: Jagan Teki
> > ---
> > drivers/video/dw_hdmi.c | 29 +++-
> > drivers/video/meson/meson_dw_hdmi.c | 11 ++-
> > drivers/video/rockchip/rk3399_hdmi.c | 8 +++-
> > drivers/video/rockchip/rk_hdmi.c | 2 +-
> > drivers/video/sunxi/sunxi_dw_hdmi.c | 11 ++-
> > include/dw_hdmi.h| 14 +-
> > 6 files changed, 69 insertions(+), 6 deletions(-)
> >
>
> Isn't there a PHY framework we should use in U-Boot?
Yes, the driver is using generic PHY.
>
> Regards,
> Sim on
>
> > diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
> > index c4fbb18294..ea12a09407 100644
> > --- a/drivers/video/dw_hdmi.c
> > +++ b/drivers/video/dw_hdmi.c
> > @@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct
> > display_timing *edid)
> >
> > hdmi_av_composer(hdmi, edid);
> >
> > - ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
> > + ret = hdmi->ops->phy_set(hdmi, edid->pixelclock.typ);
> > if (ret)
> > return ret;
> >
> > @@ -1009,10 +1009,37 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const
> > struct display_timing *edid)
> > return 0;
> > }
> >
> > +static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
> > + .phy_set = dw_hdmi_phy_cfg,
> > +};
> > +
> > +static void dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
> > +{
> > + if (!hdmi->data)
> > + return;
> > +
> > + /* hook Synopsys PHYs ops */
> > + if (!hdmi->data->phy_force_vendor) {
> > + hdmi->ops = _hdmi_synopsys_phy_ops;
> > + return;
> > + }
> > +
> > + /* Vendor HDMI PHYs must assign phy_ops in plat_data */
> > + if (!hdmi->data->phy_ops) {
> > + printf("Unsupported Vendor HDMI phy_ops\n");
> > + return;
> > + }
> > +
> > + /* hook Vendor HDMI PHYs ops */
> > + hdmi->ops = hdmi->data->phy_ops;
> > +}
> > +
> > void dw_hdmi_init(struct dw_hdmi *hdmi)
> > {
> > uint ih_mute;
> >
> > + dw_hdmi_detect_phy(hdmi);
> > +
> > /*
> > * boot up defaults are:
> > * hdmi_ih_mute = 0x03 (disabled)
> > diff --git a/drivers/video/meson/meson_dw_hdmi.c
> > b/drivers/video/meson/meson_dw_hdmi.c
> > index 5db01904b5..63ca3ac52e 100644
> > --- a/drivers/video/meson/meson_dw_hdmi.c
> > +++ b/drivers/video/meson/meson_dw_hdmi.c
> > @@ -375,6 +375,15 @@ static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi)
> > return -ETIMEDOUT;
> > }
> >
> > +static const struct dw_hdmi_phy_ops dw_hdmi_meson_phy_ops = {
> > + .phy_set = meson_dw_hdmi_phy_cfg,
> > +};
> > +
> > +static const struct dw_hdmi_plat_data dw_hdmi_meson_plat_data = {
> > + .phy_force_vendor = true,
> > + .phy_ops = _hdmi_meson_phy_ops,
> > +};
> > +
> > static int meson_dw_hdmi_probe(struct udevice *dev)
> > {
> > struct meson_dw_hdmi *priv = dev_get_priv(dev);
> > @@ -397,7 +406,7 @@ static int meson_dw_hdmi_probe(struct udevice *dev)
> >
> > priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
> > priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
> > - priv->hdmi.phy_set = meson_dw_hdmi_phy_init;
> > + priv->hdmi.data = _hdmi_meson_plat_data;
> > if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
> > priv->hdmi.reg_io_width = 1;
> > else {
> > diff --git a/drivers/video/rockchip/rk3399_hdmi.c
> > b/drivers/video/rockchip/rk3399_hdmi.c
> > index 3041360c6e..b32139a8a6 100644
> > --- a/drivers/video/rockchip/rk3399_hdmi.c
> > +++ b/drivers/video/rockchip/rk3399_hdmi.c
> > @@ -64,8 +64,14 @@ static const struct dm_display_ops rk3399_hdmi_ops = {
> > .enable = rk3399_hdmi_enable,
> > };
> >
> > +static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
> > +};
Re: [PATCH v2] mtd: spi-nor: Add IS25LP02G flash support
On Wed, Dec 13, 2023 at 9:19 PM Michal Simek wrote:
>
>
>
> On 12/4/23 09:52, Venkatesh Yadav Abbarapu wrote:
> > Add support for ISSI 256MB flash IS25LP02G. This part supports 4byte
> > opcodes. It also supports dual and quad read.
> >
> > Signed-off-by: Sreekanth Sunnam
> > Signed-off-by: Venkatesh Yadav Abbarapu
> > ---
> > Changes in v2:
> > - Fixed the name to Sreekanth Sunnam.
> > ---
> > drivers/mtd/spi/spi-nor-ids.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> > index 3cb132dcff..9a73198227 100644
> > --- a/drivers/mtd/spi/spi-nor-ids.c
> > +++ b/drivers/mtd/spi/spi-nor-ids.c
> > @@ -217,6 +217,8 @@ const struct flash_info spi_nor_ids[] = {
> > SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048,
> > SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > + { INFO("is25lp02g", 0x9d6022, 0, 64 * 1024, 4096,
> > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
> > { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
> > { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64,
>
> Jagan/Tom: Do you want to take it? Or should I take it via my tree?
Picked on my tree.
Jagan.
Re: [PATCH] mtd: spi-nor-core: Implement spi_nor_read_sfdp_dma_unsafe() for sfdp parse
On Tue, Dec 12, 2023 at 7:34 PM Tom Rini wrote: > > On Sun, Jul 10, 2022 at 11:07:41AM +0530, Jagan Teki wrote: > > On Fri, Jun 3, 2022 at 12:31 PM Vaishnav Achath wrote: > > > > > > During SFDP header parse and BFPT parse, structures in stack are used > > > to perform spi_nor_read_sfdp() which expects a dma-safe buffer. > > > > > > This commit introduces spi_nor_read_sfdp_dma_unsafe() to wrap > > > spi_nor_read_sfdp() using a kmalloc'ed bounce buffer which is > > > the same implementation in Linux (drivers/mtd/spi-nor/sfdp.c). > > > > > > Signed-off-by: Vaishnav Achath > > > --- > > > > Applied to u-boot-spi/master > > Where did this end up? Thanks. I have CI, will send PR. soon. Jagan.
Re: [PATCH 02/17] video: dw_hdmi: Add Vendor PHY handling
On Mon, Dec 11, 2023 at 2:38 PM Neil Armstrong
wrote:
>
> On 11/12/2023 09:59, Jagan Teki wrote:
> > From: Jagan Teki
> >
> > DW HDMI support Vendor PHY like Rockchip RK3328 Inno HDMI PHY.
> >
> > Extend the vendor phy handling by adding platform phy hooks.
> >
> > Signed-off-by: Jagan Teki
> > ---
> > drivers/video/dw_hdmi.c | 29 +++-
> > drivers/video/meson/meson_dw_hdmi.c | 11 ++-
> > drivers/video/rockchip/rk3399_hdmi.c | 8 +++-
> > drivers/video/rockchip/rk_hdmi.c | 2 +-
> > drivers/video/sunxi/sunxi_dw_hdmi.c | 11 ++-
> > include/dw_hdmi.h| 14 +-
> > 6 files changed, 69 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
> > index c4fbb18294..ea12a09407 100644
> > --- a/drivers/video/dw_hdmi.c
> > +++ b/drivers/video/dw_hdmi.c
> > @@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct
> > display_timing *edid)
> >
> > hdmi_av_composer(hdmi, edid);
> >
> > - ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
> > + ret = hdmi->ops->phy_set(hdmi, edid->pixelclock.typ);
> > if (ret)
> > return ret;
> >
> > @@ -1009,10 +1009,37 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const
> > struct display_timing *edid)
> > return 0;
> > }
> >
> > +static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
> > + .phy_set = dw_hdmi_phy_cfg,
> > +};
> > +
> > +static void dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
> > +{
> > + if (!hdmi->data)
> > + return;
> > +
> > + /* hook Synopsys PHYs ops */
> > + if (!hdmi->data->phy_force_vendor) {
> > + hdmi->ops = _hdmi_synopsys_phy_ops;
> > + return;
> > + }
> > +
> > + /* Vendor HDMI PHYs must assign phy_ops in plat_data */
> > + if (!hdmi->data->phy_ops) {
> > + printf("Unsupported Vendor HDMI phy_ops\n");
> > + return;
> > + }
> > +
> > + /* hook Vendor HDMI PHYs ops */
> > + hdmi->ops = hdmi->data->phy_ops;
> > +}
> > +
> > void dw_hdmi_init(struct dw_hdmi *hdmi)
> > {
> > uint ih_mute;
> >
> > + dw_hdmi_detect_phy(hdmi);
> > +
> > /*
> >* boot up defaults are:
> >* hdmi_ih_mute = 0x03 (disabled)
> > diff --git a/drivers/video/meson/meson_dw_hdmi.c
> > b/drivers/video/meson/meson_dw_hdmi.c
> > index 5db01904b5..63ca3ac52e 100644
> > --- a/drivers/video/meson/meson_dw_hdmi.c
> > +++ b/drivers/video/meson/meson_dw_hdmi.c
> > @@ -375,6 +375,15 @@ static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi)
> > return -ETIMEDOUT;
> > }
> >
> > +static const struct dw_hdmi_phy_ops dw_hdmi_meson_phy_ops = {
> > + .phy_set = meson_dw_hdmi_phy_cfg,
>
> Pretty sure this should be meson_dw_hdmi_phy_init
Correct, I will update this.
>
> > +};
> > +
> > +static const struct dw_hdmi_plat_data dw_hdmi_meson_plat_data = {
> > + .phy_force_vendor = true,
> > + .phy_ops = _hdmi_meson_phy_ops,
> > +};
> > +
> > static int meson_dw_hdmi_probe(struct udevice *dev)
> > {
> > struct meson_dw_hdmi *priv = dev_get_priv(dev);
> > @@ -397,7 +406,7 @@ static int meson_dw_hdmi_probe(struct udevice *dev)
> >
> > priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
> > priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
> > - priv->hdmi.phy_set = meson_dw_hdmi_phy_init;
> > + priv->hdmi.data = _hdmi_meson_plat_data;
> > if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
> > priv->hdmi.reg_io_width = 1;
> > else {
> > diff --git a/drivers/video/rockchip/rk3399_hdmi.c
> > b/drivers/video/rockchip/rk3399_hdmi.c
> > index 3041360c6e..b32139a8a6 100644
> > --- a/drivers/video/rockchip/rk3399_hdmi.c
> > +++ b/drivers/video/rockchip/rk3399_hdmi.c
> > @@ -64,8 +64,14 @@ static const struct dm_display_ops rk3399_hdmi_ops = {
> > .enable = rk3399_hdmi_enable,
> > };
> >
> > +static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
> > +};
> > +
> > static const struct udevice_id rk3399_hdmi_ids[] = {
> > - { .compatible = "rockchip,rk3399-dw-hdmi" },
>
