[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 5024a96db8ea6ff2e814f4599af9e5faf09296b7: Subtree merge tag 'v6.10-dts' of devicetree-rebasing repo [1] into dts/upstream (2024-07-20 11:15:22 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to dd3cd9eecc9846e7c37a97c9755d2a83fb995cbb: Revert "riscv: dts: jh7110: Enable PLL node in SPL" (2024-07-22 15:42:07 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/21724 Andreas Schwab (1): board: sifive: unmatched: remove extra space in fdtfile value Heinrich Schuchardt (2): riscv: add RISC-V fields to bdinfo command riscv: semihosting: correct alignment Leo Yu-Chi Liang (1): Revert "riscv: dts: jh7110: Enable PLL node in SPL" arch/riscv/dts/jh7110-u-boot.dtsi| 4 arch/riscv/lib/Makefile | 1 + arch/riscv/lib/bdinfo.c | 18 ++ arch/riscv/lib/semihosting.S | 2 +- board/sifive/unmatched/unmatched.env | 2 +- 5 files changed, 21 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/lib/bdinfo.c Best regards, Leo
Re: [PATCH] riscv: dts: jh7110: Enable PLL node in SPL
On Thu, Jul 11, 2024 at 12:55:05PM -0700, E Shattow wrote:
> [EXTERNAL MAIL]
>
> Ping. This regression still exists and is now in stable release.
> Should we revert this change or how must it be fixed?
>
> -E
>
Hi all,
I think I could revert this commit for now
if we cannot find the root cause and solution right away.
Best regards,
Leo
> On Sat, Apr 20, 2024 at 3:56 AM E Shattow wrote:
> >
> > On Fri, Apr 19, 2024 at 5:51 PM Bo Gan wrote:
> > >
> > ...snip...
> > >
> > > If without the change (reverted), can you read/write the same SD media in
> > > U-boot
> > > proper? (U-boot proper will switch BUS_ROOT to PLL2).
> >
> > I tested again this change in commit e6b7aeef, before this change in
> > parent commit e6b7aeef~, af04f37a HEAD from today 19th Apr 2024 (which
> > due to not matching EEPROM product_id will be in the fall-through case
> > of board/starfive/visionfive2/spl.c), af04f37a with applied patchset
> > "board: starfive: add Milk-V Mars CM support" from 15th Apr 2024, and
> > af04f37a reverting changes from e6b7aeef also with applied patchset
> > "board: starfive: add Milk-V Mars CM support" from 15th Apr 2024.
> >
> > In all builds is OpenSBI at commit d4d2582e HEAD from today 19 Apr 2024.
> >
> > For each build tested per vendor Milk-V the Mars CM Lite (SD Card only
> > non-eMMC) has pinmux of GPIO22 instead of GPIO62:
> >
> > -- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > @@ -233,7 +233,7 @@
> >
> > mmc0_pins: mmc0-pins {
> > mmc0-pins-rest {
> > - pinmux = > + pinmux = > GPOEN_ENABLE, GPI_NONE)>;
> > bias-pull-up;
> > drive-strength = <12>;
> >
> > U-Boot config is simply starfive_visionfive2_defconfig.
> >
> > Results are as follows.
> >
> > StarFive # mac
> > EEPROM INFO
> > Vendor : MILK-V
> > Product full SN: MARC-V10-2340-D004E000-06DF
> > data version: 0x2
> > PCB revision: 0xc1
> > BOM revision: A
> > Ethernet MAC0 address: 6c:cf:39:00:83:11
> > Ethernet MAC1 address: 6c:cf:39:00:83:12
> > EEPROM INFO
> >
> > e6b7aeef: 2GB microSD (no speed class markings)
> > af04f37a: 2GB microSD (no speed class markings)
> > af04f37a with Mars CM patchset: 2GB microSD (no speed class markings)
> > StarFive # mmc rescan ; mmc info
> > unable to select a mode
> > unable to select a mode
> >
> > e6b7aeef~: 2GB microSD (no speed class markings)
> > af04f37a revert e6b7aeef with Mars CM patchset: 2GB microSD (no speed
> > class markings)
> > StarFive # mmc rescan ; mmc info
> > Device: mmc@1601
> > Manufacturer ID: 1c
> > OEM: 5356
> > Name: USD
> > Bus Speed: 5000
> > Mode: SD High Speed (50MHz)
> > Rd Block Len: 512
> > SD version 2.0
> > High Capacity: No
> > Capacity: 1.9 GiB
> > Bus Width: 1-bit
> > Erase Group Size: 512 Bytes
> >
> > e6b7aeef: 8GB microSD Class 4
> > e6b7aeef~: 8GB microSD Class 4
> > af04f37a: 8GB microSD Class 4
> > af04f37a with Mars CM patchset: 8GB microSD Class 4
> > af04f37a revert e6b7aeef with Mars CM patchset: 8GB microSD Class 4
> > StarFive # mmc rescan ; mmc info
> > Device: mmc@1601
> > Manufacturer ID: 2
> > OEM: 544d
> > Name: SA08G
> > Bus Speed: 5000
> > Mode: SD High Speed (50MHz)
> > Rd Block Len: 512
> > SD version 3.0
> > High Capacity: Yes
> > Capacity: 7.4 GiB
> > Bus Width: 1-bit
> > Erase Group Size: 512 Bytes
> >
> > e6b7aeef: 8GB microSD Class 10
> > e6b7aeef~: 8GB microSD Class 10
> > af04f37a: 8GB microSD Class 10
> > af04f37a with Mars CM patchset: 8GB microSD Class 10
> > af04f37a revert e6b7aeef with Mars CM patchset: 8GB microSD Class 10
> > StarFive # mmc rescan ; mmc info
> > Device: mmc@1601
> > Manufacturer ID: 74
> > OEM: 4a60
> > Name: USD
> > Bus Speed: 5000
> > Mode: SD High Speed (50MHz)
> > Rd Block Len: 512
> > SD version 3.0
> > High Capacity: Yes
> > Capacity: 7.5 GiB
> > Bus Width: 1-bit
> > Erase Group Size: 512 Bytes
> >
> > e6b7aeef: 32GB microSD Class 10 A1 U1 HC1
> > e6b7aeef~: 32GB microSD Class 10 A1 U1 HC1
> > af04f37a: 32GB microSD Class 10 A1 U1 HC1
> > af04f37a with Mars CM patchset: 32GB microSD Class 10 A1 U1 HC1
> > af04f37a revert e6b7aeef with Mars CM patchset: 32GB microSD Class 10 A1 U1
> > HC1
> > StarFive # mmc rescan ; mmc info
> > Device: mmc@1601
> > Manufacturer ID: 3
> > OEM: 5344
> > Name: SC32G
> > Bus Speed: 5000
> > Mode: SD High Speed (50MHz)
> > Rd Block Len: 512
> > SD version 3.0
> > High Capacity: Yes
> > Capacity: 29.7 GiB
> > Bus Width: 1-bit
> > Erase Group Size: 512 Bytes
> >
> > e6b7aeef: 200GB microSD Class 10 A1 U1 XC1
> > e6b7aeef~: 200GB microSD Class 10 A1 U1 XC1
> > af04f37a: 200GB microSD Class 10 A1 U1 XC1
> > af04f37a with Mars CM patchset: 200GB microSD Class 10 A1 U1 XC1
> > af04f37a revert e6b7aeef with Mars CM patchset: 200GB microSD Class 10 A1
> > U1 XC1
> > StarFive #
Re: [PATCH] board: sifive: unmatched: remove extra space in fdtfile value
On Mon, Jun 24, 2024 at 11:46:58AM +0200, Andreas Schwab wrote:
> Fixes: 44a792c994 ("riscv: sifive: unmatched: migrate to text environment")
> Signed-off-by: Andreas Schwab
> ---
> board/sifive/unmatched/unmatched.env | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 1/1] riscv: semihosting: correct alignment
On Wed, Jun 19, 2024 at 05:22:52PM +0200, Heinrich Schuchardt wrote:
> Commit 7400d34ba992 ("riscv: semihosting: replace inline assembly with
> assembly file") reduced the alignment of function smh_trap().
>
> As described in the "RISC-V Semihosting" specification [1] the ssli,
> ebreak, and srai statements must all reside in the same memory page.
>
> [1] RISC-V Semihosting, Version 0.4, 12th June 2024
> https://github.com/riscv-non-isa/riscv-semihosting
>
> Fixes: 7400d34ba992 ("riscv: semihosting: replace inline assembly with
> assembly file")
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/riscv/lib/semihosting.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 1/1] riscv: add RISC-V fields to bdinfo command
On Fri, Jun 07, 2024 at 10:41:17AM +0200, Heinrich Schuchardt wrote: > The firmware invoking main U-Boot uses > > * a0 to pass the boot hart > * a1 to pass a device-tree > > Let the bdinfo command print this information, e.g. > > boot hart = 0x001b > firmware fdt= 0x87e0 > > The firmware fdt field will only be printed if it is non-zero. > > Signed-off-by: Heinrich Schuchardt > --- > arch/riscv/lib/Makefile | 1 + > arch/riscv/lib/bdinfo.c | 18 ++ > 2 files changed, 19 insertions(+) > create mode 100644 arch/riscv/lib/bdinfo.c Reviewed-by: Leo Yu-Chi Liang
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 46ff00bea5dd2dd247d5e2fdadbf5dcf8653cd9a: Merge tag 'tpm-master-27052024' of https://source.denx.de/u-boot/custodians/u-boot-tpm (2024-05-27 08:56:02 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 1d29c718b7ba09807f8060796d9c21772e3c1b52: andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND (2024-05-30 16:01:13 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20920 - board: fix support for icicle - board: support Star64 board - andes: minor fixes - riscv: deprecate cache enablement in start.S Conor Dooley (2): board: microchip: icicle: correct type for node offset board: microchip: icicle: make both ethernets optional H Bell (2): board: starfive: support Pine64 Star64 board board: starfive: support Pine64 Star64 board Leo Yu-Chi Liang (3): andes: l2 cache driver: fixes typos and cctl status riscv: remove cache enablement in start.S andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND arch/riscv/cpu/andes/cache.c | 4 +- arch/riscv/cpu/start.S| 4 - arch/riscv/include/asm/arch-andes/csr.h | 2 +- board/microchip/mpfs_icicle/mpfs_icicle.c | 25 +-- board/starfive/visionfive2/spl.c | 89 ++ board/starfive/visionfive2/starfive_visionfive2.c | 4 + doc/board/starfive/index.rst | 1 + doc/board/starfive/pine64_star64.rst | 201 ++ drivers/cache/cache-andes-l2.c| 8 +- 9 files changed, 310 insertions(+), 28 deletions(-) create mode 100644 doc/board/starfive/pine64_star64.rst Best regards, Leo
Re: [PATCH v1 2/2] board: microchip: icicle: make both ethernets optional
On Wed, May 15, 2024 at 04:04:31PM +0100, Conor Dooley wrote: > From: Conor Dooley > > A given AMP configuration for a board may make either one, or neither > of, the ethernet ports available to U-Boot. The Icicle's init code will > fail if mac1 is not present, so move it to the optional approach taken > for mac0. > > Signed-off-by: Conor Dooley > --- > board/microchip/mpfs_icicle/mpfs_icicle.c | 23 +++ > 1 file changed, 7 insertions(+), 16 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v1 1/2] board: microchip: icicle: correct type for node offset
On Wed, May 15, 2024 at 04:04:30PM +0100, Conor Dooley wrote:
> From: Conor Dooley
>
> Node offsets returned by libfdt can contain negative error numbers, so
> the variable type should be "int". As things stand, if the ethernet
> nodes are not found in the early init callback, the if (node < 0) tests
> pass and the code errors out while trying to set the local-mac-address
> for a non-existent node.
>
> Fixes: 64413e1b7c ("riscv: Add Microchip MPFS Icicle Kit support")
> Signed-off-by: Conor Dooley
> ---
> board/microchip/mpfs_icicle/mpfs_icicle.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang
[GIT PULL] u-boot-riscv/master
Hi Tom,
The following changes since commit c8ffd1356d42223cbb8c86280a083cc3c93e6426:
Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"
(2024-05-13 09:15:51 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 2b8dc36b4c515979da330a96d9fcc9bbbe5385fa:
andes: Unify naming policy for Andes related source (2024-05-14 18:50:47
+0800)
CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20690
- RISC-V: Add NULL check after parsing compatible string
- Board: Add Milk-V Mars CM board
- Andes: Unify naming policy
Hanyuan Zhao (1):
riscv: add NULL check before calling strlen in the riscv cpu's get_desc()
Heinrich Schuchardt (6):
board: starfive: function to read eMMC size
board: add support for Milk-V Mars CM
doc: Milk-V Mars CM and Milk-V Mars CM Lite
configs: visionfive2: enable SPL_YMODEM_SUPPORT
starfive: add mac vendor sub-command
riscv: simplify backtrace report
Leo Yu-Chi Liang (1):
andes: Unify naming policy for Andes related source
arch/riscv/Kconfig | 4 +-
arch/riscv/cpu/{andesv5 => andes}/Kconfig | 4 +-
arch/riscv/cpu/{andesv5 => andes}/Makefile | 0
arch/riscv/cpu/{andesv5 => andes}/cache.c | 12 +-
arch/riscv/cpu/{andesv5 => andes}/cpu.c| 0
arch/riscv/cpu/{andesv5 => andes}/spl.c| 0
arch/riscv/include/asm/arch-jh7110/eeprom.h| 7 +
arch/riscv/lib/interrupts.c| 16 +-
board/{AndesTech => andestech}/ae350/Kconfig | 6 +-
board/{AndesTech => andestech}/ae350/MAINTAINERS | 2 +-
board/{AndesTech => andestech}/ae350/Makefile | 0
board/{AndesTech => andestech}/ae350/ae350.c | 2 +-
board/starfive/visionfive2/Kconfig | 9 +
board/starfive/visionfive2/spl.c | 28 ++-
board/starfive/visionfive2/starfive_visionfive2.c | 11 +-
.../starfive/visionfive2/visionfive2-i2c-eeprom.c | 43 -
configs/starfive_visionfive2_defconfig | 1 +
doc/board/{AndesTech => andestech}/adp-ag101p.rst | 0
doc/board/{AndesTech => andestech}/ae350.rst | 0
doc/board/{AndesTech => andestech}/index.rst | 0
doc/board/index.rst| 2 +-
doc/board/starfive/index.rst | 3 +-
doc/board/starfive/milk-v_mars_cm.rst | 193 +
drivers/cache/Kconfig | 6 +-
drivers/cache/Makefile | 2 +-
drivers/cache/{cache-v5l2.c => cache-andes-l2.c} | 40 ++---
drivers/cpu/riscv_cpu.c| 2 +-
27 files changed, 337 insertions(+), 56 deletions(-)
rename arch/riscv/cpu/{andesv5 => andes}/Kconfig (91%)
rename arch/riscv/cpu/{andesv5 => andes}/Makefile (100%)
rename arch/riscv/cpu/{andesv5 => andes}/cache.c (90%)
rename arch/riscv/cpu/{andesv5 => andes}/cpu.c (100%)
rename arch/riscv/cpu/{andesv5 => andes}/spl.c (100%)
rename board/{AndesTech => andestech}/ae350/Kconfig (91%)
rename board/{AndesTech => andestech}/ae350/MAINTAINERS (95%)
rename board/{AndesTech => andestech}/ae350/Makefile (100%)
rename board/{AndesTech => andestech}/ae350/ae350.c (99%)
rename doc/board/{AndesTech => andestech}/adp-ag101p.rst (100%)
rename doc/board/{AndesTech => andestech}/ae350.rst (100%)
rename doc/board/{AndesTech => andestech}/index.rst (100%)
create mode 100644 doc/board/starfive/milk-v_mars_cm.rst
rename drivers/cache/{cache-v5l2.c => cache-andes-l2.c} (84%)
Best regards,
Leo
Re: [PATCH 1/1] riscv: add NULL check before calling strlen in the riscv cpu's get_desc()
On Mon, May 06, 2024 at 05:10:06PM +0800, Hanyuan Zhao wrote: > Without the NULL check, if the devicetree that u-boot loads does not have a > compatible property then a store access fault will be raised and force the > machine to reset, due to the NULL pointer we passed to strlen. This commit > adds this check and will return -ENOSPC to indicate the get_desc failed. > > Signed-off-by: Hanyuan Zhao > --- > drivers/cpu/riscv_cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 1/1] riscv: simplify backtrace report
On Tue, May 14, 2024 at 07:51:42AM +0200, Heinrich Schuchardt wrote: > * We already have a header 'backtrace', there is no need to repeat the > word backtrace on every line. > * Add a blank line before the backtrace section of the crash report for > improved readability. > * If U-Boot is compiled without backtrace, there is no need to write a > message at all. > * Avoid #ifdef. We prefer functions to always be compiled and let > the linker remove them if not needed. > * Foresee 3 digits for the backtrace index. > > For testing the 'exception' command can be used. > > Signed-off-by: Heinrich Schuchardt > --- > arch/riscv/lib/interrupts.c | 16 +--- > 1 file changed, 5 insertions(+), 11 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v3 2/2] board: starfive: Rename spl_soc_init() to spl_dram_init()
On Thu, May 02, 2024 at 08:06:43AM +0200, Lukas Funke wrote: > [EXTERNAL MAIL] > > On 24.04.2024 13:01, Heinrich Schuchardt wrote: > > On 24.04.24 09:43, lukas.funke-...@weidmueller.com wrote: > > > From: Lukas Funke > > > > > > Rename spl_soc_init() to spl_dram_init() because the generic function > > > name does not reflect what the function actually does. Also > > > spl_dram_init() is commonly used for dram initialization and should be > > > called from board_init_f(). > > > > > > Signed-off-by: Lukas Funke > > > > Reviewed-by: Heinrich Schuchardt > Any objection on this one? Hi Lukas, This patch has been merged to u-boot-riscv. Thanks! Best regards, Leo
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit ff0de1f0557ed7d2dab47ba976a37347a1fdc432: Merge patch series "Update PHYTEC SOM Detection" (2024-04-29 10:56:05 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 19b762cf83f68b9d9a1f14e75d75781cedf4049f: board: starfive: Rename spl_soc_init() to spl_dram_init() (2024-05-02 00:01:18 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20596 - RISC-V: cmd: Add SBI implementation ID and extension ID - Board: Rename spl_soc_init to spl_dram_init - Board: milkv_duo: Add SPI NOR flash, Ethernet, Sysreset support Heinrich Schuchardt (2): cmd: sbi: add Supervisor Software Events extension cmd: sbi: add coreboot and oreboot implementation IDs Kongyang Liu (10): mmc: cv1800b: Add transmit tap delay config to fix write error sysreset: cv1800b: Add sysreset driver for cv1800b SoC board: sophgo: milkv_duo: Bind sysreset driver configs: milkv_duo: Add sysreset configs board: milkv_duo: Add init code for Milk-V Duo ethernet riscv: dts: sophgo: Add ethernet node configs: milkv_duo: Add ethernet configs spi: cv1800b: Add spi nor flash controller driver for cv1800b SoC riscv: dts: sophgo: Add spi nor flash controller node configs: milkv_duo: Add spi nor configs Lukas Funke (2): board: sifive: Rename spl_soc_init() to spl_dram_init() board: starfive: Rename spl_soc_init() to spl_dram_init() Yu Chien Peter Lin (1): riscv: andesv5: Set default cache line size to 64-bytes arch/riscv/cpu/andesv5/Kconfig | 1 + arch/riscv/cpu/fu540/spl.c | 2 +- arch/riscv/cpu/fu740/spl.c | 2 +- arch/riscv/cpu/jh7110/spl.c | 2 +- arch/riscv/dts/cv1800b-milkv-duo.dts | 18 ++ arch/riscv/dts/cv18xx.dtsi | 40 arch/riscv/include/asm/arch-fu540/spl.h | 2 +- arch/riscv/include/asm/arch-fu740/spl.h | 2 +- arch/riscv/include/asm/arch-jh7110/spl.h | 2 +- arch/riscv/include/asm/sbi.h | 1 + board/sifive/unleashed/spl.c | 4 +- board/sifive/unmatched/spl.c | 4 +- board/sophgo/milkv_duo/Makefile | 3 +- board/sophgo/milkv_duo/board.c | 10 + board/sophgo/milkv_duo/ethernet.c| 79 board/sophgo/milkv_duo/ethernet.h| 11 ++ board/starfive/visionfive2/spl.c | 4 +- cmd/riscv/sbi.c | 3 + configs/milkv_duo_defconfig | 10 + drivers/mmc/cv1800b_sdhci.c | 4 +- drivers/net/designware.c | 1 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/cv1800b_spif.c | 321 +++ drivers/sysreset/Kconfig | 5 + drivers/sysreset/Makefile| 1 + drivers/sysreset/sysreset_cv1800b.c | 64 ++ 27 files changed, 591 insertions(+), 14 deletions(-) create mode 100644 board/sophgo/milkv_duo/ethernet.c create mode 100644 board/sophgo/milkv_duo/ethernet.h create mode 100644 drivers/spi/cv1800b_spif.c create mode 100644 drivers/sysreset/sysreset_cv1800b.c Best regards, Leo
Re: [PATCH 1/3] sysreset: cv1800b: Add sysreset driver for cv1800b SoC
On Tue, Apr 16, 2024 at 03:52:38PM +0800, Kongyang Liu wrote: > Add sysreset driver for cv1800b SoC > > Signed-off-by: Kongyang Liu > --- > > drivers/sysreset/Kconfig| 5 +++ > drivers/sysreset/Makefile | 1 + > drivers/sysreset/sysreset_cv1800b.c | 64 + > 3 files changed, 70 insertions(+) > create mode 100644 drivers/sysreset/sysreset_cv1800b.c Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 2/3] board: sophgo: milkv_duo: Bind sysreset driver
On Tue, Apr 16, 2024 at 03:52:39PM +0800, Kongyang Liu wrote: > Bind cv1800b sysreset driver for Sophgo Milk-V Duo board in board_init > function. > > Signed-off-by: Kongyang Liu > --- > > board/sophgo/milkv_duo/board.c | 4 > 1 file changed, 4 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 3/3] configs: milkv_duo: Add sysreset configs
On Tue, Apr 16, 2024 at 03:52:40PM +0800, Kongyang Liu wrote: > Add sysreset configs as well as poweroff and reset commands for Sophgo > Milk-V Duo board. > > Signed-off-by: Kongyang Liu > --- > > configs/milkv_duo_defconfig | 3 +++ > 1 file changed, 3 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH] riscv: andesv5: Set default cache line size to 64-bytes
On Thu, Apr 11, 2024 at 05:29:45PM +0800, Yu Chien Peter Lin wrote: > The instruction and data cache line sizes of Andes core > are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so > the SYS_CACHELINE_SIZE is enabled with a default value. > > Signed-off-by: Yu Chien Peter Lin > --- > arch/riscv/cpu/andesv5/Kconfig | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v2 2/3] riscv: dts: sophgo: Add ethernet node
On Sat, Apr 20, 2024 at 03:00:28PM +0800, Kongyang Liu wrote: > Add ethernet node for cv1800b SoC > > Signed-off-by: Kongyang Liu > --- > > Changes in v2: > - Change compatible > - Add clocks and interrupt properties. > > arch/riscv/dts/cv1800b-milkv-duo.dts | 7 ++- > arch/riscv/dts/cv18xx.dtsi | 23 +++ > 2 files changed, 29 insertions(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 1/3] spi: cv1800b: Add spi nor flash controller driver for cv1800b SoC
On Sat, Apr 20, 2024 at 03:08:23PM +0800, Kongyang Liu wrote: > Add spi nor flash controller driver for cv1800b SoC > > Signed-off-by: Kongyang Liu > --- > > drivers/spi/Kconfig| 8 + > drivers/spi/Makefile | 1 + > drivers/spi/cv1800b_spif.c | 321 + > 3 files changed, 330 insertions(+) > create mode 100644 drivers/spi/cv1800b_spif.c Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 2/3] riscv: dts: sophgo: Add spi nor flash controller node
On Sat, Apr 20, 2024 at 03:08:24PM +0800, Kongyang Liu wrote: > Add spi nor flash controller node for cv18xx SoCs > > Signed-off-by: Kongyang Liu > --- > > arch/riscv/dts/cv1800b-milkv-duo.dts | 13 + > arch/riscv/dts/cv18xx.dtsi | 17 + > 2 files changed, 30 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 3/3] configs: milkv_duo: Add spi nor configs
On Sat, Apr 20, 2024 at 03:08:25PM +0800, Kongyang Liu wrote: > Add configs related to spi nor flash for Sophgo Milk-V Duo board > > Signed-off-by: Kongyang Liu > --- > > configs/milkv_duo_defconfig | 3 +++ > 1 file changed, 3 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 2/2] cmd: sbi: add coreboot and oreboot implementation IDs
On Wed, Apr 17, 2024 at 04:01:28PM +0200, Heinrich Schuchardt wrote: > Let the sbi command detect the coreboot and oreboot SBI Implementation IDs > defined in SBI specification v2.0. > > Signed-off-by: Heinrich Schuchardt > --- > cmd/riscv/sbi.c | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 1/2] cmd: sbi: add Supervisor Software Events extension
On Wed, Apr 17, 2024 at 04:01:27PM +0200, Heinrich Schuchardt wrote: > OpenSBI has implemented the Supervisor Software Events Extension. > Allow detecting it in the sbi command. > > Signed-off-by: Heinrich Schuchardt > --- > arch/riscv/include/asm/sbi.h | 1 + > cmd/riscv/sbi.c | 1 + > 2 files changed, 2 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v3 1/2] board: sifive: Rename spl_soc_init() to spl_dram_init()
On Wed, Apr 24, 2024 at 09:43:38AM +0200, lukas.funke-...@weidmueller.com wrote: > From: Lukas Funke > > Rename spl_soc_init() to spl_dram_init() because the generic function > name does not reflect what the function actually does. Also > spl_dram_init() is commonly used for dram initialization and should be > called from board_init_f(). > > Signed-off-by: Lukas Funke > --- > > (no changes since v1) > > arch/riscv/cpu/fu540/spl.c | 2 +- > arch/riscv/cpu/fu740/spl.c | 2 +- > arch/riscv/include/asm/arch-fu540/spl.h | 2 +- > arch/riscv/include/asm/arch-fu740/spl.h | 2 +- > board/sifive/unleashed/spl.c| 4 ++-- > board/sifive/unmatched/spl.c| 4 ++-- > 6 files changed, 8 insertions(+), 8 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: RISC-V u-boot unable to boot QEMU using '-cpu max'
On Mon, Apr 22, 2024 at 04:43:59PM -0300, Daniel Henrique Barboza wrote:
> [EXTERNAL MAIL]
>
> Hi,
>
> In QEMU we have a 'max' type CPU that implements (almost) all extensions that
> QEMU
> is able to emulate. Recently, in QEMU commit 249e0905d05, we bumped the
> extensions
> for this CPU.
>
> And after this commit this CPU is now unable to boot a guest using upstream
> u-boot. Here's the error being thrown:
>
> qemu-system-riscv64 \
> -machine virt -nographic -m 8G -smp 8 \
> -cpu max -kernel uboot.elf (...)
> (...)
>
> initcall sequence 8027c3e8 failed at call 8021259e (err=-28)
> ### ERROR ### Please RESET the board ###
>
>
> I can get the guest to boot if I disable the following extensions from the
> 'max' CPU:
>
> -cpu max,zfbfmin=false,zvfbfmin=false,zvfbfwma=false
>
> Due to QEMU extension dependencies I'm not able to disable these
> individually. What I can
> say is that u-boot isn't playing ball to at least one of them.
>
> Is this an u-boot bug? Up to this point I was assuming that u-boot would
> silently ignore
> hart extensions that it doesn't support.
Hi Daniel,
Which u-boot version are you using?
I think this issue is fixed by the following patch set sent by Conor.
f39b1b77d8 riscv: support extension probing using riscv, isa-extensions
b90edde701 riscv: don't read riscv, isa in the riscv cpu's get_desc()
I've tested and can reproduce the issue you mentioned if these two patches are
reverted.
Could you try with the lastest u-boot master branch again?
For reference, my testing commands are as follows:
1. cd ${u-boot} && make qemu-riscv64_defconfig && make -j`nproc`
2. ./${qemu}/build/qemu-system-riscv64 -nographic -machine virt -cpu max -bios
u-boot.bin -m 8G -smp 8
- u-boot branch (commit): master (38ea74d6d5c0 "Prepare v2024.07-rc1")
- qemu branch (commit): master (62dbe54c24db "Update version for v9.0.0-rc4
release")
Best regards,
Leo
>
>
> Thanks,
>
>
> Daniel
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 069d07396e30aa9be396c1dd3fc158ac199e6843: Merge tag 'efi-2024-07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi (2024-04-08 14:33:59 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to c1f78a4f632276bb4d77f8c79fe203709a9fa397: doc: describe Milk-V Mars board (2024-04-09 11:30:37 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20256 - RISC-V: Support backtrace and improve isa extension parsing - cpu: Add cv1800b SoC support - board: Add Milk-V Mars board support - board: Add Milk-V Duo SD card support Ben Dooks (1): riscv: add backtrace support Conor Dooley (2): riscv: don't read riscv, isa in the riscv cpu's get_desc() riscv: support extension probing using riscv, isa-extensions Heinrich Schuchardt (7): riscv: starfive: MMC card detect riscv: do not set default fdt for VisionFive 2 eeprom: starfive: function get_product_id_from_eeprom() riscv: set fdtfile on Milk-V Mars board: starfive: support Milk-V Mars board riscv: starfive: avoid including common.h doc: describe Milk-V Mars board Kongyang Liu (5): riscv: cpu: cv1800b: Add support for cv1800b SoC riscv: cache: Implement dcache for cv1800b mmc: cv1800b: Add sdhci driver support for cv1800b SoC riscv: dts: sophgo: Add clk node and sdhci node configs: milkv_duo: Add SD card configs Łukasz Stelmach (1): riscv: Move virtio scan to board_late_init() arch/riscv/Kconfig | 22 arch/riscv/Makefile| 4 + arch/riscv/cpu/cpu.c | 60 +++ arch/riscv/cpu/cv1800b/Kconfig | 12 +++ arch/riscv/cpu/cv1800b/Makefile| 7 ++ arch/riscv/cpu/cv1800b/cache.c | 45 arch/riscv/cpu/cv1800b/cpu.c | 9 ++ arch/riscv/cpu/cv1800b/dram.c | 21 arch/riscv/cpu/start.S | 1 + arch/riscv/dts/cv1800b-milkv-duo.dts | 8 ++ arch/riscv/dts/cv1800b.dtsi| 4 + arch/riscv/dts/cv18xx.dtsi | 22 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +- arch/riscv/include/asm/arch-jh7110/eeprom.h| 9 ++ arch/riscv/lib/interrupts.c| 35 +++ board/emulation/qemu-riscv/qemu-riscv.c| 12 +-- board/sophgo/milkv_duo/Kconfig | 4 +- board/starfive/visionfive2/spl.c | 100 +++--- board/starfive/visionfive2/starfive_visionfive2.c | 48 ++--- .../starfive/visionfive2/visionfive2-i2c-eeprom.c | 9 +- configs/milkv_duo_defconfig| 10 ++ configs/starfive_visionfive2_defconfig | 1 - doc/board/starfive/index.rst | 1 + doc/board/starfive/milk-v_mars.rst | 111 doc/board/starfive/visionfive2.rst | 18 drivers/cpu/riscv_cpu.c| 8 +- drivers/mmc/Kconfig| 13 +++ drivers/mmc/Makefile | 1 + drivers/mmc/cv1800b_sdhci.c| 116 + 29 files changed, 649 insertions(+), 64 deletions(-) create mode 100644 arch/riscv/cpu/cv1800b/Kconfig create mode 100644 arch/riscv/cpu/cv1800b/Makefile create mode 100644 arch/riscv/cpu/cv1800b/cache.c create mode 100644 arch/riscv/cpu/cv1800b/cpu.c create mode 100644 arch/riscv/cpu/cv1800b/dram.c create mode 100644 doc/board/starfive/milk-v_mars.rst create mode 100644 drivers/mmc/cv1800b_sdhci.c Best regards, Leo
Re: [PATCH v3 4/6] board: starfive: support Milk-V Mars board
On Tue, Apr 02, 2024 at 10:49:10AM +0200, Heinrich Schuchardt wrote: > The differences between the Milk-V Mars board and the VisionFive 2 board > are small enough that we can support both using the same U-Boot build. > > * The model and compatible property are taken from proposed Linux patches. > * The EEPROM is atmel,24c02 according to the vendor U-Boot. > * The second Ethernet port is not available. > > usb@1010 does not exist in U-Boot yet. So we don't have to reflect > differences in usage here. > > Signed-off-by: Heinrich Schuchardt > --- > For the mmc card-detect a separate patch has been created: > https://lore.kernel.org/u-boot/20240328214615.21501-1-heinrich.schucha...@canonical.com/ > > v3: > Replace misplaced starfive_verb[i] by milk_v_mars[i]. > v2: > do not overwrite /soc/i2c@1205/eeprom@50/compatible > --- > board/starfive/visionfive2/spl.c | 99 > 1 file changed, 87 insertions(+), 12 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v3 6/6] doc: describe Milk-V Mars board
On Tue, Apr 02, 2024 at 10:49:12AM +0200, Heinrich Schuchardt wrote: > Add instructions to build U-Boot for the Milk-V Mars board > > Signed-off-by: Heinrich Schuchardt > --- > v3: > no change > v2: > describe how to preset fdtfile > --- > doc/board/starfive/index.rst | 1 + > doc/board/starfive/milk-v_mars.rst | 111 + > 2 files changed, 112 insertions(+) > create mode 100644 doc/board/starfive/milk-v_mars.rst Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v3 1/6] riscv: do not set default fdt for VisionFive 2
On Tue, Apr 02, 2024 at 10:49:07AM +0200, Heinrich Schuchardt wrote: > Currently in set_fdtfile() we set the value of environment variable fdtfile > unconditionally. The implies that a value in the environment will be > ignored. > > With the patch environment variable fdtfile will only be set if it does not > yet exist. This requires that CONFIG_DEFAULT_FDT_FILE is not set. > > Now the user can either set and save fdtfile interactively or in the U-Boot > configuration to overrule the device-tree name chosen based on the > hardware in set_fdtfile(). > > Reported-by: E Shattow > Signed-off-by: Heinrich Schuchardt > --- > v3: > Rephrase last added sentence in doc/board/starfive/visionfive2.rst > v2: > new patch > --- > .../visionfive2/starfive_visionfive2.c | 4 > configs/starfive_visionfive2_defconfig | 1 - > doc/board/starfive/visionfive2.rst | 18 ++ > 3 files changed, 22 insertions(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v2] riscv: Move virtio scan to board_late_init()
On Thu, Mar 28, 2024 at 10:58:24AM +0100, Łukasz Stelmach wrote: > [EXTERNAL MAIL] > > When virtio_init() gets called from board_init() PCI isn't ready. Thus, > virtio-over-PCI (e.g. network interfaces) devices can't be detected and > used without additional `virtio scan` scan in the shell or a script. > > Signed-off-by: Łukasz Stelmach > --- > Changes since v1: > - remove virtio_init() call from board_init() > - select BOARD_LATE_INIT for TARGET_QEMU_VIRT > > arch/riscv/Kconfig | 1 + > board/emulation/qemu-riscv/qemu-riscv.c | 12 ++-- > 2 files changed, 7 insertions(+), 6 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: [[PATCH v2]] riscv: add backtrace support
On Tue, Sep 05, 2023 at 01:12:53PM +0100, Ben Dooks wrote: > When debugging, it is useful to have a backtrace to find > out what is in the call stack as the previous function (RA) > may not have been the culprit. > > Since this adds size to the build, do not add it by default > and avoid putting it in the SPL build if not needed. > > Signed-off-by: Ben Dooks > --- > v2: > - back to codethink email as sifive account is now gone > - add option to build SPL with frame pointer > (as suggested by Bo Gan > --- > arch/riscv/Kconfig | 20 > arch/riscv/Makefile | 4 > arch/riscv/cpu/start.S | 1 + > arch/riscv/lib/interrupts.c | 35 +++ > 4 files changed, 60 insertions(+) Tested-by: Leo Yu-Chi Liang
Re: [PATCH v1 2/2] riscv: support extension probing using riscv, isa-extensions
On Mon, Mar 18, 2024 at 03:16:03PM +, Conor Dooley wrote: > From: Conor Dooley > > A new property has been added, with an extensive rationale at [1], that > can be used in place of "riscv,isa" to indicate what extensions are > supported by a given platform that is a list of strings rather than a > single string. There are some differences between the new property, > "riscv,isa-extensions" and the incumbent "riscv,isa" - chief among them > for the sake of parsing being the list of strings, as opposed to a > string. Another advantage is strictly defined meanings for each string > in a dt-binding, rather than deriving meaning from RVI standards. This > will likely to some divergence over time, but U-Boot's current use of > extension detection is very limited - there are just four callsites of > supports_extension() in mainline U-Boot. > > These checks are limited to two checks for FPU support and two checks > for "s" and "u". "s" and "u" are not supported by the new property, but > they were also not permitted in "riscv,isa". These checks are only > meaningful (or run) in M-Mode, in which case supports_extension() does > not parse the devicetree anyway. > > Add support for the new property in U-Boot, prioritising it, before > falling back to the, now deprecated, "riscv,isa" property if it is not > present. > > Signed-off-by: Conor Dooley > --- > I moved the kernel devicetrees to use the new properties, I'd do the > same here, but I'd rather just move things to use dt-rebasing instead, > where possible. > --- > arch/riscv/cpu/cpu.c | 56 +++- > 1 file changed, 35 insertions(+), 21 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v1 1/2] riscv: don't read riscv, isa in the riscv cpu's get_desc()
On Mon, Mar 18, 2024 at 03:16:02PM +, Conor Dooley wrote: > From: Conor Dooley > > cpu_get_desc() for the RISC-V CPU currently reads "riscv,isa" to get > the description, but it is no longer a required property and cannot be > assummed to always be present, as the new "riscv,isa-extensions" and > "riscv,isa-base" properties may be present instead. > > On RISC-V, cpu_get_desc() has two main uses - firstly providing an > informational name for the CPU for smbios or at boot with > DISPLAY_CPUINFO etc and secondly it forms the basis of ISA extension > detection in supports_extension() as it returns (a portion of) an ISA > string. > > cpu_get_desc() returns a string, which aligned with "riscv,isa" but > the new property is a list of strings. Rather than add support for > the list of strings property, which would require creating an isa > string from "riscv,isa-extensions", modify the RISC-V CPU's > implementaion of cpu_get_desc() return the first compatible as the > cpu description instead. This may be fine for the informational cases, > but it would break extension dtection, given supports_extension() > expects cpu_get_desc() to return an ISA string. > > Call dev_read_string() directly in supports_extension() to get the > contents of "riscv,isa" so that extension detection remains functional. > As a knock-on affect of this change, extension detection is no longer > broken for long ISA strings. Previously if the ISA string exceeded the > 32 element array that supports_extension() passed to cpu_get_desc(), > it would return ENOSPC and no extensions would be detected. > This bug probably had no impact as U-Boot does not currently do anything > meaningful with the results of supports_extension() and most SoCs > supported by U-Boot don't have anywhere near that complex of an ISA > string. The QEMU virt machine's CPUs do however, so extension detection > doesn't work there. > > Signed-off-by: Conor Dooley > --- > I'm not really sure if I am happy with this patch - people could > definitely have got use out of the cpu info printout of the ISA string > before this patch - they'd have seen something like > CPU: rv64imafdc > at boot, but now they will see > CPU: sifive,u74 > If it really is desired, cpu_get_desc() could be made to assemble > an isa string out of "riscv,isa-extensions", but I think it's always > gonna be a bit flawed, since that string can run to almost arbitrary > length now - one I saw for a CPU last week was 320 characters long > and these things are only going to grow. > --- > arch/riscv/cpu/cpu.c| 12 +++- > drivers/cpu/riscv_cpu.c | 8 > 2 files changed, 11 insertions(+), 9 deletions(-) LGTM! reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v2 4/6] board: starfive: support Milk-V Mars board
Hi Heinrich, On Wed, Mar 27, 2024 at 12:03:01PM +0100, Heinrich Schuchardt wrote: > [EXTERNAL MAIL] > > On 24.03.24 16:00, Aurelien Jarno wrote: > > On 2024-03-21 19:11, Heinrich Schuchardt wrote: > > > The differences between the Milk-V Mars board and the VisionFive 2 board > > > are small enough that we can support both using the same U-Boot build. > > > > > > * The model and compatible property are taken from proposed Linux patches. > > > * The EEPROM is atmel,24c02 according to the vendor U-Boot. > > > * The second Ethernet port is not available. > > > > From the device tree that have been submitted to the kernel [1] it seems > > another difference is that there is a CD gpio for mmc1. > > Yes, the Mars board has > > cd-gpios = < 41 GPIO_ACTIVE_LOW>; > > while the VisionFive 2 has > >broken-cd; > > We could add the cd-gpios to the VF2 dts and then set broken-cd in > spl_fdt_fixup_*(). > > What I would really like to understand from the reviewers is if the > approach with patching the device-tree is what we are targeting for. > > Or should we try to keep the device-trees in sync with Linux, package > all JH7110 device-trees into the FIT image and in SPL choose the > device-tree from the fit image and only patch the memory size. > > The device-tree for the Milk-V CM module differs a lot in GPIO routing. > I am not sure that patching the VF2 device-tree is future proof. I think we could patch the VF2 device-tree currently with this few differeces, and create a new device tree for Milk-V Mars CM module if patching the VF2 device tree is too much of an effort. Does this sound reasonable ? Do you have any preference over which scheme we should use ? Best regards, Leo > > Best regards > > Heinrich > > > > > > From the schematics, it also seems that the usb0 port is not in > > peripheral mode, but in host mode. That said on the submitted kernel > > device tree it seems simply disabled. > > > > Aurelien > > > > [1] > > https://lore.kernel.org/linux-kernel/20240131132600.4067-2-jszh...@kernel.org/T/ > > >
Re: [PATCH v2 4/6] board: starfive: support Milk-V Mars board
Hi Heinrich,
On Thu, Mar 21, 2024 at 07:11:47PM +0100, Heinrich Schuchardt wrote:
> The differences between the Milk-V Mars board and the VisionFive 2 board
> are small enough that we can support both using the same U-Boot build.
>
> * The model and compatible property are taken from proposed Linux patches.
> * The EEPROM is atmel,24c02 according to the vendor U-Boot.
> * The second Ethernet port is not available.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v2:
> do not overwrite /soc/i2c@1205/eeprom@50/compatible
>
> ---
> board/starfive/visionfive2/spl.c | 99
> 1 file changed, 87 insertions(+), 12 deletions(-)
>
> diff --git a/board/starfive/visionfive2/spl.c
> b/board/starfive/visionfive2/spl.c
> index 1b49945d11b..e0e33cb37ba 100644
> --- a/board/starfive/visionfive2/spl.c
> +++ b/board/starfive/visionfive2/spl.c
> @@ -67,6 +87,49 @@ static const struct starfive_vf2_pro starfive_verb[] = {
> "tx-internal-delay-ps", "0"},
> };
>
> +void spl_fdt_fixup_mars(void *fdt)
> +{
> + static const char compat[] = "milkv,mars\0starfive,jh7110";
> + u32 phandle;
> + u8 i;
> + int offset;
> + int ret;
> +
> + fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat,
> sizeof(compat));
> + fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
> +"Milk-V Mars");
> +
> + /* gmac0 */
> + offset = fdt_path_offset(fdt, "/soc/clock-controller@1700");
> + phandle = fdt_get_phandle(fdt, offset);
> + offset = fdt_path_offset(fdt, "/soc/ethernet@1603");
> +
> + fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
> + fdt_appendprop_u32(fdt, offset, "assigned-clocks",
> JH7110_AONCLK_GMAC0_TX);
> + fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
> + fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
> +JH7110_AONCLK_GMAC0_RMII_RTX);
> +
> + /* gmac1 */
> + fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@1604"),
> +"status", "disabled");
> +
> + for (i = 0; i < ARRAY_SIZE(milk_v_mars); i++) {
> + offset = fdt_path_offset(fdt, milk_v_mars[i].path);
> +
> + if (starfive_verb[i].value)
Should this be milk_v_mars[i].value ?
> + ret = fdt_setprop_u32(fdt, offset, milk_v_mars[i].name,
> + dectoul(milk_v_mars[i].value,
> NULL));
> + else
> + ret = fdt_setprop_empty(fdt, offset,
> milk_v_mars[i].name);
> +
> + if (ret) {
> + pr_err("%s set prop %s fail.\n", __func__,
> milk_v_mars[i].name);
> + break;
> + }
> + }
> +}
> +
Re: [PATCH v2 3/6] riscv: set fdtfile on Milk-V Mars
On Thu, Mar 21, 2024 at 07:11:46PM +0100, Heinrich Schuchardt wrote: > Set environment variable fdtfile to the correct value for the Milk-V Mars > board. > > Signed-off-by: Heinrich Schuchardt > --- > v2: > rebase patch > --- > .../visionfive2/starfive_visionfive2.c| 43 +-- > 1 file changed, 30 insertions(+), 13 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v2 5/6] riscv: starfive: avoid including common.h
On Thu, Mar 21, 2024 at 07:11:48PM +0100, Heinrich Schuchardt wrote: > The usage of common.h is deprecated. Remove it from board files. > > Signed-off-by: Heinrich Schuchardt > --- > v2: > no change > --- > board/starfive/visionfive2/spl.c| 1 - > board/starfive/visionfive2/starfive_visionfive2.c | 1 - > board/starfive/visionfive2/visionfive2-i2c-eeprom.c | 1 - > 3 files changed, 3 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v2 2/6] eeprom: starfive: function get_product_id_from_eeprom()
On Thu, Mar 21, 2024 at 07:11:45PM +0100, Heinrich Schuchardt wrote: > Export a function get_product_id_from_eeprom() to read the product ID. > This value can be used for fixing up the device-tree on JH7110 based > products. > > Signed-off-by: Heinrich Schuchardt > --- > v2: > no change > --- > arch/riscv/include/asm/arch-jh7110/eeprom.h | 9 + > board/starfive/visionfive2/visionfive2-i2c-eeprom.c | 8 > 2 files changed, 17 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v2 1/6] riscv: do not set default fdt for VisionFive 2
On Thu, Mar 21, 2024 at 07:11:44PM +0100, Heinrich Schuchardt wrote: > Currently in set_fdtfile() we set the value of environment variable fdtfile > unconditionally. The implies that a value in the environment will be > ignored. > > With the patch environment variable fdtfile will only be set if it does not > yet exist. This requires that CONFIG_DEFAULT_FDT_FILE is not set. > > Now the user can either set and save fdtfile interactively or in the U-Boot > configuration to overrule the device-tree name chosen based on the > hardware in set_fdtfile(). > > Reported-by: E Shattow > Signed-off-by: Heinrich Schuchardt > --- > v2: > new patch > --- > .../visionfive2/starfive_visionfive2.c | 4 > configs/starfive_visionfive2_defconfig | 1 - > doc/board/starfive/visionfive2.rst | 18 ++ > 3 files changed, 22 insertions(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit dde373bde392c38649c8c4420e0c98ef8d38d9dc: Prepare v2024.04-rc5 (2024-03-25 21:56:50 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 0cfe1bc6ed9b322d2b03ded3175ac5de3ed2b784: spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR (2024-03-26 17:31:24 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20075 - Fix RISC-V falcon mode booting issue Randolph (1): spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR common/spl/spl_opensbi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Best regards, Leo
Re: [PATCH] spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR
On Fri, Mar 22, 2024 at 07:36:37PM +0800, Randolph wrote: > When Falcon Mode is enabled on RISC-V, use CONFIG_VAL > to check PAYLOAD_ARGS_ADDR, not CONFIG_IS_ENABLED. > > Signed-off-by: Randolph > --- > common/spl/spl_opensbi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Tested-by: Leo Yu-Chi Liang
Re: [PATCH] riscv: Repeat virtio scan
Hi Łukasz,
On Mon, Feb 19, 2024 at 01:41:39PM +0100, Łukasz Stelmach wrote:
> The first time virtio_init() gets called from board_init() PCI isn't
> ready. Thus any virtio-over-PCI (e.g. network interfaces) devices can't
> be detected and used without additional `virtio scan` scan in the shell
> or a script.
>
> Signed-off-by: Łukasz Stelmach
> ---
> The patch works for my but:
>
> a) maybe virtio_init() should called only from board_init() the same
>way as on ARM?
> b) can a repeated virtio_init() break already detected/initialized
>devices?
>
A repeated virtio_init() call would not break the already probed devices.
But we should prevent this redundancy by moving the virtio_init() call to
board_late_init() like what this commit[1] does for ARM.
Could you send a v2 to move the virtio_init() into board_late_init() ?
[1]
https://patchwork.ozlabs.org/project/uboot/patch/20201230135712.5289-3-sughosh.g...@linaro.org/
e1ee06dde7 ("qemu: arm: Initialise virtio devices in board_late_init")
Best regards,
Leo
> board/emulation/qemu-riscv/qemu-riscv.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/board/emulation/qemu-riscv/qemu-riscv.c
> b/board/emulation/qemu-riscv/qemu-riscv.c
> index 181abbbf97d..567b9dc6170 100644
> --- a/board/emulation/qemu-riscv/qemu-riscv.c
> +++ b/board/emulation/qemu-riscv/qemu-riscv.c
> @@ -46,6 +46,9 @@ int board_late_init(void)
> if (CONFIG_IS_ENABLED(USB_KEYBOARD))
> usb_init();
>
> + /* Repeat virtio scan to detect PCI attached virtio devices. */
> + virtio_init();
> +
> return 0;
> }
>
Re: [PATCH v2 1/3] mmc: cv1800b: Add sdhci driver support for cv1800b SoC
On Sun, Mar 10, 2024 at 01:51:55AM +0800, Kongyang Liu wrote: > Add sdhci driver for cv1800b SoC. > > Signed-off-by: Kongyang Liu > --- > > Changes in v2: > - Refactored and simplified some of the code. > > drivers/mmc/Kconfig | 13 > drivers/mmc/Makefile| 1 + > drivers/mmc/cv1800b_sdhci.c | 116 > 3 files changed, 130 insertions(+) > create mode 100644 drivers/mmc/cv1800b_sdhci.c Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v2 3/3] configs: milkv_duo: Add SD card configs
On Sun, Mar 10, 2024 at 01:51:57AM +0800, Kongyang Liu wrote: > Add configs related to sdhci and mmc for Sophgo Milk-V Duo board > > Signed-off-by: Kongyang Liu > --- > > (no changes since v1) > > configs/milkv_duo_defconfig | 10 ++ > 1 file changed, 10 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 3/3] configs: milkv_duo: Add ethernet configs
On Sun, Mar 10, 2024 at 01:56:46PM +0800, Kongyang Liu wrote: > Add configs related to ethernet and ethernet boot command for Sophgo Milk-V > Duo board > > Signed-off-by: Kongyang Liu > --- > > configs/milkv_duo_defconfig | 4 > 1 file changed, 4 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 2/3] riscv: dts: sophgo: Add ethernet node
On Sun, Mar 10, 2024 at 01:56:45PM +0800, Kongyang Liu wrote: > Add ethernet node for cv1800b SoC > > Signed-off-by: Kongyang Liu > --- > > arch/riscv/dts/cv18xx.dtsi | 6 ++ > 1 file changed, 6 insertions(+) Hi KongYang, Will there be a patch adding this ethernet node for kernel as well ? Best regards, Leo
Re: [PATCH 1/3] board: milkv_duo: Add init code for Milk-V Duo ethernet
On Sun, Mar 10, 2024 at 01:56:44PM +0800, Kongyang Liu wrote: > Initialize register in cv1800b ethernet phy to make it compatible with > generic phy driver > > Signed-off-by: Kongyang Liu > --- > > board/sophgo/milkv_duo/Makefile | 3 +- > board/sophgo/milkv_duo/board.c| 4 ++ > board/sophgo/milkv_duo/ethernet.c | 79 +++ > board/sophgo/milkv_duo/ethernet.h | 11 + > drivers/net/designware.c | 1 + > 5 files changed, 97 insertions(+), 1 deletion(-) > create mode 100644 board/sophgo/milkv_duo/ethernet.c > create mode 100644 board/sophgo/milkv_duo/ethernet.h Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v2 2/2] riscv: cache: Implement dcache for cv1800b
On Sun, Mar 10, 2024 at 12:54:57AM +0800, Kongyang Liu wrote: > Add dcache operations invalidate_dcache_range and flush_dcache_range for > cv1800b. > > Signed-off-by: Kongyang Liu > --- > > (no changes since v1) > > arch/riscv/cpu/cv1800b/Makefile | 1 + > arch/riscv/cpu/cv1800b/cache.c | 45 + > 2 files changed, 46 insertions(+) > create mode 100644 arch/riscv/cpu/cv1800b/cache.c Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v2 1/2] riscv: cpu: cv1800b: Add support for cv1800b SoC
On Sun, Mar 10, 2024 at 12:54:56AM +0800, Kongyang Liu wrote: > Add Sophgo cv1800b SoC to support RISC-V arch. > > Signed-off-by: Kongyang Liu > --- > > Changes in v2: > - Remove duplicate code in function cleanup_before_linux > > arch/riscv/Kconfig | 1 + > arch/riscv/cpu/cv1800b/Kconfig | 12 > arch/riscv/cpu/cv1800b/Makefile | 6 ++ > arch/riscv/cpu/cv1800b/cpu.c| 9 + > arch/riscv/cpu/cv1800b/dram.c | 21 + > board/sophgo/milkv_duo/Kconfig | 4 ++-- > 6 files changed, 51 insertions(+), 2 deletions(-) > create mode 100644 arch/riscv/cpu/cv1800b/Kconfig > create mode 100644 arch/riscv/cpu/cv1800b/Makefile > create mode 100644 arch/riscv/cpu/cv1800b/cpu.c > create mode 100644 arch/riscv/cpu/cv1800b/dram.c Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v2 2/3] riscv: dts: sophgo: Add clk node and sdhci node
On Sun, Mar 10, 2024 at 01:51:56AM +0800, Kongyang Liu wrote: > Add clk node and sdhci node for cv18xx SoCs according to patches from Linux > kernel. > > clk: > https://lore.kernel.org/all/ia1pr20mb4953f9ad6792013b54636f05bb...@ia1pr20mb4953.namprd20.prod.outlook.com/ > sdhci: https://lore.kernel.org/all/20240217144826.3944-1-jszh...@kernel.org/ > > Signed-off-by: Kongyang Liu > --- > > Changes in v2: > - Sync device tree with ptaches from Linux kernel > > arch/riscv/dts/cv1800b-milkv-duo.dts | 8 > arch/riscv/dts/cv1800b.dtsi | 4 > arch/riscv/dts/cv18xx.dtsi | 22 ++ > 3 files changed, 34 insertions(+) Reviewed-by: Leo Yu-Chi Liang
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit f3c979dd0053c082d2df170446923e7ce5edbc2d: Prepare v2024.04-rc4 (2024-03-11 13:11:46 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 544af8207c69829b1697f3aa5dd682a299a6dea4: board: starfive: maintainer: Add visionfive2 PCIe driver (2024-03-12 14:36:13 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19910 * riscv: lib: improve extension detection * riscv: sbi: fix display format and global variable storage * sifive: fu740: reduce DDR speed * board: starfive vf2: switch to standard boot and fix DTS Bo Gan (1): riscv: dts: jh7110: Enable PLL node in SPL Conor Dooley (1): riscv: cpu: improve multi-letter extension detection in supports_extension() Heinrich Schuchardt (3): serial: move sbi_dbcn_available to .data section cmd: sbi: Correctly display unknown implementation IDs cmd: sbi: formatting PolarFire Hart Software Services version Leon M. Busch-George (1): riscv: dts: jh7110: fix indentation Minda Chen (2): board: starfive: Update maintainer of VisionFive v2 board board: starfive: maintainer: Add visionfive2 PCIe driver Nam Cao (1): starfive: visionfive2: switch to standard boot Thomas Perrot (1): riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s arch/riscv/cpu/cpu.c | 22 -- arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +- .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 2 +- arch/riscv/dts/jh7110-u-boot.dtsi | 4 board/starfive/visionfive2/MAINTAINERS | 3 ++- cmd/riscv/sbi.c| 3 ++- configs/starfive_visionfive2_defconfig | 2 +- drivers/serial/serial_sbi.c| 2 +- include/configs/starfive-visionfive2.h | 14 +- 9 files changed, 29 insertions(+), 25 deletions(-) Best regards, Leo
Re: [PATCH] starfive: visionfive2: switch to standard boot
On Wed, Feb 21, 2024 at 01:00:14PM +0100, Nam Cao wrote: > Distro boot scripts are deprecated. Use standard boot instead. > > Signed-off-by: Nam Cao > --- > configs/starfive_visionfive2_defconfig | 2 +- > include/configs/starfive-visionfive2.h | 14 +- > 2 files changed, 2 insertions(+), 14 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH] riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s
On Thu, Feb 22, 2024 at 03:52:03PM +0100, thomas.per...@bootlin.com wrote: > From: Thomas Perrot > > It appears that there is some timing marginality either in the > board layout or the SoC that results in occasional data corruption > on some boards. > We observed this issue on some of the new HiFive Unmatched RevB > boards during volume production as well as some of the original > HiFive Unmatched boards from 2021 in our possession. This means > that there are other boards out there that might have the issue > too. > > We have done some limited testing with DDR4 at 1600MT/s and > faulty boards (failing at 1866MT/s) passed. > We plan further testing after we procure a temperature chamber. > > Signed-off-by: Thomas Perrot > --- > arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH] riscv: dts: jh7110: Enable PLL node in SPL
On Tue, Mar 05, 2024 at 07:00:11PM -0800, Bo Gan wrote: > Previously PLL node was missing from SPL dts. This caused BUS_ROOT > to stay on OSC clock (24Mhz). As a result, all peripherals have to > run at a much lower frequency, and loading from sdcard/emmc is slow. > Thus, enabling PLL node in dts to fix this. > > Signed-off-by: Bo Gan > --- > arch/riscv/dts/jh7110-u-boot.dtsi | 4 > 1 file changed, 4 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v1 2/2] board: starfive: maintainer: Add visionfive2 PCIe driver
On Fri, Mar 08, 2024 at 02:53:36PM +0800, Minda Chen wrote: > Add PCIe driver file to visionfive2 board MAINTAINERS list. > > Signed-off-by: Minda Chen > --- > board/starfive/visionfive2/MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v1 1/2] board: starfive: Update maintainer of VisionFive v2 board
On Fri, Mar 08, 2024 at 02:53:35PM +0800, Minda Chen wrote: > Update the maintainer of Starfive VisionFive v2 board. > > Signed-off-by: Minda Chen > --- > board/starfive/visionfive2/MAINTAINERS | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH] riscv: dts: jh7110: fix indentation
On Mon, Mar 04, 2024 at 09:51:47PM +0100, Leon M. Busch-George wrote: > From: "Leon M. Busch-George" > > Signed-off-by: Leon M. Busch-George > --- > arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 28760ce8640ff6266bd1c1c568a4a231576f3919: Merge tag 'clk-2024.04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-clk (2024-01-30 07:54:28 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 6882255ac3107c58e1153311df8a8270087f8cb3: riscv: dts: starfive: add regulator device (2024-01-31 16:52:53 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19505 * Add RISC-V falcon mode documentation * Add Clang build support * Add cmd to detect Debug Trigger Extension support * Add PWM setting for Unmatched board * Add Milk-V Duo board support * Add new device node and enable new config option for VisionFive2 board * Add second virtio device for RISC-V QEMU Aurelien Jarno (3): board: starfive: handle compatible property in dynamic DT configuration riscv: qemu: enable booting on a second virtio device configs: visionfive2: Disable ENV_IS_NOWHERE Heinrich Schuchardt (1): cmd: sbi: add support for Debug Trigger Extension Kongyang Liu (3): riscv: dts: sophgo: add basic device tree for Milk-V Duo board riscv: sophgo: milkv_duo: initial support added doc: sophgo: milkv_duo: document Milk-V Duo board Lukasz Tekieli (2): net: phy: motorcomm: configure pad drive strength register board: visionfive2: configure PHY pad drive strength Nam Cao (2): riscv: dts: jh7110: add power management unit controller node riscv: dts: starfive: add regulator device Randolph (3): doc: falcon: riscv: Falcon Mode boot on RISC-V spl: riscv: falcon: move fdt blob to specified address configs: andes: add the fdt blob copy address for SPL Vincent Chen (1): board: sifive: spl: Initialized the PWM setting in the SPL stage kleines Filmröllchen (1): riscv: Support building with Clang arch/riscv/Kconfig | 4 + arch/riscv/config.mk | 2 +- arch/riscv/dts/Makefile | 1 + arch/riscv/dts/cv1800b-milkv-duo.dts | 38 + arch/riscv/dts/cv1800b.dtsi | 18 +++ arch/riscv/dts/cv18xx.dtsi | 192 +++ arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 5 + arch/riscv/dts/jh7110.dtsi | 6 + arch/riscv/include/asm/arch-fu740/eeprom.h | 15 ++ arch/riscv/include/asm/sbi.h | 1 + board/AndesTech/ae350/ae350.c| 25 --- board/sifive/unmatched/spl.c | 52 ++ board/sophgo/milkv_duo/Kconfig | 28 board/sophgo/milkv_duo/MAINTAINERS | 6 + board/sophgo/milkv_duo/Makefile | 5 + board/sophgo/milkv_duo/board.c | 9 ++ board/starfive/visionfive2/spl.c | 12 ++ cmd/riscv/sbi.c | 1 + common/spl/Kconfig | 2 +- common/spl/spl_opensbi.c | 15 ++ configs/ae350_rv32_falcon_defconfig | 1 + configs/ae350_rv32_falcon_xip_defconfig | 1 + configs/ae350_rv64_falcon_defconfig | 1 + configs/ae350_rv64_falcon_xip_defconfig | 1 + configs/milkv_duo_defconfig | 23 +++ configs/starfive_visionfive2_defconfig | 1 - doc/board/index.rst | 1 + doc/board/sophgo/index.rst | 8 + doc/board/sophgo/milkv_duo.rst | 64 doc/develop/falcon.rst | 158 +++ drivers/net/phy/motorcomm.c | 130 +++ include/configs/milkv_duo.h | 12 ++ include/configs/qemu-riscv.h | 1 + 33 files changed, 811 insertions(+), 28 deletions(-) create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts create mode 100644 arch/riscv/dts/cv1800b.dtsi create mode 100644 arch/riscv/dts/cv18xx.dtsi create mode 100644 arch/riscv/include/asm/arch-fu740/eeprom.h create mode 100644 board/sophgo/milkv_duo/Kconfig create mode 100644 board/sophgo/milkv_duo/MAINTAINERS create mode 100644 board/sophgo/milkv_duo/Makefile create mode 100644 board/sophgo/milkv_duo/board.c create mode 100644 configs/milkv_duo_defconfig create mode 100644 doc/board/sophgo/index.rst create mode 100644 doc/board/sophgo/milkv_duo.rst create mode 100644 include/configs/milkv_duo.h Best regards, Leo
Re: [PATCH v2 2/2] riscv: dts: starfive: add regulator device
On Mon, Jan 29, 2024 at 09:43:09AM +0100, Nam Cao wrote: > Add the axp15060 regulator device. OpenSBI uses this device to perform > board reset and shutdown. > > Signed-off-by: Nam Cao > --- > v2: "stf,axp15060-regulator" -> "x-powers,axp15060" to match Linux. > > arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 5 + > 1 file changed, 5 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v2 1/2] riscv: dts: jh7110: add power management unit controller node
On Mon, Jan 29, 2024 at 09:43:08AM +0100, Nam Cao wrote: > JH7110 has a power management unit controller node. Add this node. > > This device is used by OpenSBI during board reset/shutdown. > > Signed-off-by: Nam Cao > --- > arch/riscv/dts/jh7110.dtsi | 6 ++ > 1 file changed, 6 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 2/2] board: visionfive2: configure PHY pad drive strength
On Sun, Jan 28, 2024 at 08:22:48PM +0100, Lukasz Tekieli wrote: > Configure the pad drive strength register for both PHYs. > The values correspond to what can be found in the Linux DTS > for VisionFive2 v1.3b. > > Pad drive strength configuration is required for the phy0 to work correctly > with 100Mbit links. > > Signed-off-by: Lukasz Tekieli > --- > board/starfive/visionfive2/spl.c | 8 > 1 file changed, 8 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 1/2] net: phy: motorcomm: configure pad drive strength register
On Sun, Jan 28, 2024 at 08:22:47PM +0100, Lukasz Tekieli wrote: > This ports the pad drive strength register configuration which can be > already found in the Linux driver for this PHY. > > Signed-off-by: Lukasz Tekieli > --- > drivers/net/phy/motorcomm.c | 130 > 1 file changed, 130 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v4 3/3] doc: sophgo: milkv_duo: document Milk-V Duo board
On Sun, Jan 28, 2024 at 03:05:26PM +0800, Kongyang Liu wrote: > Add document for Milk-V Duo board which based on Sophgo's CV1800B SoC. > > Signed-off-by: Kongyang Liu > --- > > (no changes since v3) > > Changes in v3: > - Add brief description of the procedure to run u-boot-dtb.bin > > doc/board/index.rst| 1 + > doc/board/sophgo/index.rst | 8 + > doc/board/sophgo/milkv_duo.rst | 64 ++ > 3 files changed, 73 insertions(+) > create mode 100644 doc/board/sophgo/index.rst > create mode 100644 doc/board/sophgo/milkv_duo.rst Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v4 2/3] riscv: sophgo: milkv_duo: initial support added
On Sun, Jan 28, 2024 at 03:05:25PM +0800, Kongyang Liu wrote: > Add support for Sophgo's Milk-V Duo board, only minimal device tree and > serial console are enabled, and it can boot via vendor first stage > bootloader. > > Signed-off-by: Kongyang Liu > --- > > (no changes since v3) > > Changes in v3: > - Enable EFI loader > > Changes in v2: > - Fold the defconfig patch to first patch > - Remove unnecessary environment settings of consoledev and baudrate in > config > > arch/riscv/Kconfig | 4 > board/sophgo/milkv_duo/Kconfig | 28 > board/sophgo/milkv_duo/MAINTAINERS | 6 ++ > board/sophgo/milkv_duo/Makefile| 5 + > board/sophgo/milkv_duo/board.c | 9 + > configs/milkv_duo_defconfig| 23 +++ > include/configs/milkv_duo.h| 12 > 7 files changed, 87 insertions(+) > create mode 100644 board/sophgo/milkv_duo/Kconfig > create mode 100644 board/sophgo/milkv_duo/MAINTAINERS > create mode 100644 board/sophgo/milkv_duo/Makefile > create mode 100644 board/sophgo/milkv_duo/board.c > create mode 100644 configs/milkv_duo_defconfig > create mode 100644 include/configs/milkv_duo.h Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v4 1/3] riscv: dts: sophgo: add basic device tree for Milk-V Duo board
On Sun, Jan 28, 2024 at 03:05:24PM +0800, Kongyang Liu wrote: > Import device tree from Linux kernel to add basic support for CPU, PLIC, > UART and Timer. The name cv1800b in the filename represent the chip used > on Milk-V Duo board. > > Signed-off-by: Kongyang Liu > --- > > Changes in v4: > - Sync dts files with Linux kernel > > Changes in v3: > - Swap patch 1 and 2 duo to dependency of defconfig and device tree > > arch/riscv/dts/Makefile | 1 + > arch/riscv/dts/cv1800b-milkv-duo.dts | 38 ++ > arch/riscv/dts/cv1800b.dtsi | 18 +++ > arch/riscv/dts/cv18xx.dtsi | 192 +++ > 4 files changed, 249 insertions(+) > create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts > create mode 100644 arch/riscv/dts/cv1800b.dtsi > create mode 100644 arch/riscv/dts/cv18xx.dtsi Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH] configs: visionfive2: Disable ENV_IS_NOWHERE
On Sat, Jan 27, 2024 at 02:48:45PM +0100, Aurelien Jarno wrote:
> The VisionFive 2 board supports saving the u-boot environment settings
> are saved to on-board SPI flash. However the defconfig enables both
> ENV_IS_NOWHERE and ENV_IS_IN_SPI_FLASH, preventing the "saveenv" command
> to work. Fix that by disabling ENV_IS_NOWHERE.
>
> Fixes: 7d79bed00c9e ("configs: starfive: Enable environment in SPI flash
> support")
>
> Reported-by: E Shattow
> Signed-off-by: Aurelien Jarno
> ---
> configs/starfive_visionfive2_defconfig | 1 -
> 1 file changed, 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 1/1] cmd: sbi: add support for Debug Trigger Extension
On Wed, Jan 17, 2024 at 05:46:52PM +0100, Heinrich Schuchardt wrote: > Detect and show if the SBI implements the Debug Trigger Extension. > > Signed-off-by: Heinrich Schuchardt > --- > arch/riscv/include/asm/sbi.h | 1 + > cmd/riscv/sbi.c | 1 + > 2 files changed, 2 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH] board: sifive: spl: Initialized the PWM setting in the SPL stage
On Tue, Jan 16, 2024 at 02:35:57PM +0800, Nylon Chen wrote: > From: Vincent Chen > > LEDs and multiple fans can be controlled by SPL. This patch ensures > that all fans have been enabled in the SPL stage. In addition, the > LED's color will be set to yellow. > > Signed-off-by: Vincent Chen > Co-developed-by: Nylon Chen > Signed-off-by: Nylon Chen > Co-developed-by: Zong Li > Signed-off-by: Zong Li > --- > arch/riscv/include/asm/arch-fu740/eeprom.h | 15 +++ > board/sifive/unmatched/spl.c | 52 ++ > 2 files changed, 67 insertions(+) > create mode 100644 arch/riscv/include/asm/arch-fu740/eeprom.h Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH] riscv: qemu: enable booting on a second virtio device
On Wed, Jan 10, 2024 at 09:26:53PM +0100, Aurelien Jarno wrote: > QEMU RISC-V supports multiple virtio devices, but only tries to boot to > the first one. Enable support for a second virtio device, that is useful > for instance to boot on a disk image + an installer. Ideally that should > be made dynamic, but that's a first step. > > Signed-off-by: Aurelien Jarno > --- > include/configs/qemu-riscv.h | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH] board: starfive: handle compatible property in dynamic DT configuration
On Wed, Jan 10, 2024 at 09:17:44PM +0100, Aurelien Jarno wrote:
> The difference between the StarFive VisionFive 2 1.2A and 1.3B boards is
> handled dynamically by looking at the PCB version in the EEPROM in order
> to have a single u-boot version for both versions of the board. While
> the "model" property is correctly handled, the "compatible" one is
> always the the one of version 1.3b.
>
> This patch add support for dynamically configuring that property.
>
> Fixes: 9b7060bd15e7 ("riscv: dts: jh7110: Combine the board device tree files
> of 1.2A and 1.3B")
>
> Signed-off-by: Aurelien Jarno
> ---
> board/starfive/visionfive2/spl.c | 4
> 1 file changed, 4 insertions(+)
Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH V4 3/3] configs: andes: add the fdt blob copy address for SPL
On Fri, Dec 29, 2023 at 04:32:23PM +0800, Randolph wrote: > Add the address to which the FDT blob is to be moved. > > Signed-off-by: Randolph > --- > configs/ae350_rv32_falcon_defconfig | 1 + > configs/ae350_rv32_falcon_xip_defconfig | 1 + > configs/ae350_rv64_falcon_defconfig | 1 + > configs/ae350_rv64_falcon_xip_defconfig | 1 + > 4 files changed, 4 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH V4 2/3] spl: riscv: falcon: move fdt blob to specified address
On Fri, Dec 29, 2023 at 04:32:22PM +0800, Randolph wrote: > In Falcon Boot mode, the fdt blob should be move to the RAM from > kernel BSS section. To avoid being cleared by BSS initialisation. > SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies. > > Signed-off-by: Randolph > --- > board/AndesTech/ae350/ae350.c | 25 - > common/spl/Kconfig| 2 +- > common/spl/spl_opensbi.c | 15 +++ > 3 files changed, 16 insertions(+), 26 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH V4 1/3] doc: falcon: riscv: Falcon Mode boot on RISC-V
On Fri, Dec 29, 2023 at 04:32:21PM +0800, Randolph wrote: > Add documentation to introduce the Falcon Mode on RISC-V. > In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel. > > Signed-off-by: Randolph > --- > doc/develop/falcon.rst | 158 + > 1 file changed, 158 insertions(+) Reviewed-by: Leo Yu-Chi Liang
[GIT PULL] u-boot-riscv/next
Hi Tom, The following changes since commit 4b151562bb8e54160adedbc6a1c0c749c00a2f84: bootmeth: pass size to efi_binary_run() (2023-12-22 10:36:50 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git next for you to fetch changes up to 9924d44dbcd47bd3664fa9f1f9f24044d83eaebf: andes: ae350: Enable MISC_INIT_R for ae350 platform (2023-12-27 17:29:11 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19106 - Andes: Enable Andes CPU memboost and ECC feature by default - Sifive: Add private L2 cache driver Leo Yu-Chi Liang (6): andes: csr.h: Clean up CSR definition andes: ae350: Implement cache switch via Kconfig andes: cpu: Enable memboost feature andes: cpu: Enable cache and TLB ECC support andes: ae350: Save cpu name to env andes: ae350: Enable MISC_INIT_R for ae350 platform Michal Simek (1): riscv: Extend board compatible string with "qemu,mbv" Zong Li (2): cache: add sifive private L2 cache driver riscv: cache: support cache enable in SPL stage arch/riscv/cpu/andesv5/cpu.c| 33 ++--- arch/riscv/dts/xilinx-mbv32.dts | 2 +- arch/riscv/include/asm/arch-andes/csr.h | 29 +- arch/riscv/include/asm/csr.h| 1 + arch/riscv/lib/sifive_cache.c | 21 board/AndesTech/ae350/ae350.c | 26 ++- configs/ae350_rv32_defconfig| 5 ++-- configs/ae350_rv32_spl_defconfig| 5 ++-- configs/ae350_rv32_spl_xip_defconfig| 5 ++-- configs/ae350_rv32_xip_defconfig| 5 ++-- configs/ae350_rv64_defconfig| 5 ++-- configs/ae350_rv64_spl_defconfig| 5 ++-- configs/ae350_rv64_spl_xip_defconfig| 5 ++-- configs/ae350_rv64_xip_defconfig| 5 ++-- drivers/cache/Kconfig | 7 ++ drivers/cache/Makefile | 1 + drivers/cache/cache-sifive-pl2.c| 44 + 17 files changed, 165 insertions(+), 39 deletions(-) create mode 100644 drivers/cache/cache-sifive-pl2.c Best regards, Leo
Re: [PATCH] riscv: Extend board compatible string with "qemu,mbv"
On Wed, Dec 20, 2023 at 03:53:28PM +0100, Michal Simek wrote:
> Extend compatible string to match the latest change in dt binding.
>
> Fixes: 7576ab2facae ("riscv: Add support for AMD/Xilinx MicroBlaze V")
> Signed-off-by: Michal Simek
> ---
>
> dt binding patch is available here.
> https://lore.kernel.org/all/69670e5a46c98a2eb73d4f2e2d571a27c46b4640.1700722941.git.michal.si...@amd.com/
>
> ---
> arch/riscv/dts/xilinx-mbv32.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 2/2] riscv: cache: support cache enable in SPL stage
On Thu, Dec 14, 2023 at 02:09:37PM +, Zong Li wrote: > The power gating feature of pl2 should be enabled as early as possible, > it would be better to put it in SPL stage. > > Signed-off-by: Zong Li > --- > arch/riscv/lib/sifive_cache.c | 21 + > 1 file changed, 21 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 1/2] cache: add sifive private L2 cache driver
On Thu, Dec 14, 2023 at 02:09:36PM +, Zong Li wrote: > This driver is currently responsible for enabling the clock gating > feature of SiFive pre core's private L2 cache. > > Signed-off-by: Zong Li > --- > drivers/cache/Kconfig| 7 + > drivers/cache/Makefile | 1 + > drivers/cache/cache-sifive-pl2.c | 44 > 3 files changed, 52 insertions(+) > create mode 100644 drivers/cache/cache-sifive-pl2.c Reviewed-by: Leo Yu-Chi Liang
[GIT PULL] u-boot-riscv/next
Hi Tom, The following changes since commit fdefb4e194c65777fa11479119adaa71651f41d4: Merge tag 'efi-next-20231217' of https://source.denx.de/u-boot/custodians/u-boot-efi into next (2023-12-17 09:11:06 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git next for you to fetch changes up to 44a792c99498f5a9d3526019779d66585978c491: riscv: sifive: unmatched: migrate to text environment (2023-12-18 11:09:01 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18996 - VisionFive2: Enable CONFIG_SYSRESET - StarFive: Modify starfive timer driver - AMD/Xilinx: Add MicroBlaze V support - Unmatched: Migrate to text environment Jaehoon Chung (2): riscv: dts: jh7110: Add a gpio-restart node configs: visionfive2: Enable CONFIG_SYSRESET config Kuan Lim Lee (1): timer: starfive: Add Starfive timer support Michal Simek (1): riscv: Add support for AMD/Xilinx MicroBlaze V Yong-Xuan Wang (1): riscv: sifive: unmatched: migrate to text environment arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 2 + arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 5 ++ arch/riscv/dts/xilinx-mbv32.dts | 106 +++ board/sifive/unmatched/unmatched.env | 19 board/xilinx/Kconfig | 3 +- board/xilinx/common/board.c | 5 ++ board/xilinx/mbv/Kconfig | 28 ++ board/xilinx/mbv/MAINTAINERS | 7 ++ board/xilinx/mbv/Makefile| 5 ++ board/xilinx/mbv/board.c | 11 +++ configs/sifive_unmatched_defconfig | 2 +- configs/starfive_visionfive2_defconfig | 1 + configs/xilinx_mbv32_defconfig | 30 +++ configs/xilinx_mbv32_smode_defconfig | 32 +++ drivers/timer/starfive-timer.c | 16 ++-- include/configs/sifive-unmatched.h | 37 include/configs/xilinx_mbv.h | 6 ++ 18 files changed, 273 insertions(+), 46 deletions(-) create mode 100644 arch/riscv/dts/xilinx-mbv32.dts create mode 100644 board/sifive/unmatched/unmatched.env create mode 100644 board/xilinx/mbv/Kconfig create mode 100644 board/xilinx/mbv/MAINTAINERS create mode 100644 board/xilinx/mbv/Makefile create mode 100644 board/xilinx/mbv/board.c create mode 100644 configs/xilinx_mbv32_defconfig create mode 100644 configs/xilinx_mbv32_smode_defconfig create mode 100644 include/configs/xilinx_mbv.h Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
Hi Tom, On Thu, Dec 14, 2023 at 07:19:02AM -0500, Tom Rini wrote: > On Thu, Dec 14, 2023 at 10:38:07AM +0800, Leo Yu-Chi Liang(梁育齊) wrote: > > > Hi Tom, > > > > The following changes since commit 20d0464300c25db673cfb5e4539aa3767606d151: > > > > Merge tag 'u-boot-imx-20231212' of > > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2023-12-12 16:33:57 > > -0500) > > > > are available in the Git repository at: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to 8c785ddb7ae8d675faf558c81a29938cb0ec2b35: > > > > riscv: sifive: unmatched: migrate to text environment (2023-12-13 > > 16:19:43 +0800) > > > > CI result shows no issue: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18889 > > > > - VisionFive2: Enable CONFIG_SYSRESET > > - StarFive: Modify starfive timer driver > > - AMD/Xilinx: Add MicroBlaze V support > > - Unmatched: Migrate to text environment > > > > Are all of these really appropriate for a release less than a month away > or should I take this to -next? Thanks. Ah! You're right! I think merging to -next seems to be more appropriate! Thanks for the reminder! Best regards, Leo > -- > Tom
Re: [PATCH v2] timer: starfive: Add Starfive timer support
On Mon, Dec 11, 2023 at 10:22:10AM +0800, Jun Liang Tan wrote: > From: Kuan Lim Lee > > Add timer driver in Starfive SoC. It is an timer that outside > of CPU core and inside Starfive SoC. > > Signed-off-by: Kuan Lim Lee > Signed-off-by: Wei Liang Lim > > Changes for v2: > - correct driver name, comment, variable > --- > drivers/timer/starfive-timer.c | 16 +--- > 1 file changed, 9 insertions(+), 7 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 2/2] configs: starfive2: Enable CONFIG_SYSRET config
On Tue, Oct 31, 2023 at 05:24:39PM +0900, Jaehoon Chung wrote: > Enable CONFIG_SYSREST config to do reset. > > Signed-off-by: Jaehoon Chung > --- > configs/starfive_visionfive2_defconfig | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 1/2] riscv: dts: jh7110: Add a gpio-restart node
On Tue, Oct 31, 2023 at 05:24:38PM +0900, Jaehoon Chung wrote: > Add gpio-restart node to do reset. > > Before applied this patch, System Reset Extension doesn't appear with > sbi command. > > OpenSBI 1.3 > Machine: > Vendor ID 489 > Architecture ID 8007 > Implementation ID 4210427 > Extensions: > sbi_set_timer > sbi_console_putchar > ...[snip]... > IPI Extension > RFENCE Extension > Hart State Management Extension > Performance Monitoring Unit Extension > > After applied this patch, System Reset Extension is supported from SBI. > > OpenSBI 1.3 > Machine: > Vendor ID 489 > Architecture ID 8007 > Implementation ID 4210427 > Extensions: > sbi_set_timer > sbi_console_putchar > ...[snip]... > IPI Extension > RFENCE Extension > Hart State Management Extension > System Reset Extension > Performance Monitoring Unit Extension > > Signed-off-by: Jaehoon Chung > --- > arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 5 + > 1 file changed, 5 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH V2 2/2] configs: andes: add watchdog support fot andes ae350
On Thu, Nov 30, 2023 at 08:07:29PM +0800, Randolph wrote: > It adds the ATCWDT200 support for Andes AE350 platform. > It also enables wdt command support. > > Signed-off-by: CL Wang > Signed-off-by: Randolph > --- > configs/ae350_rv32_defconfig | 4 > configs/ae350_rv32_spl_defconfig | 4 > configs/ae350_rv32_spl_xip_defconfig | 4 > configs/ae350_rv32_xip_defconfig | 4 > configs/ae350_rv64_defconfig | 4 > configs/ae350_rv64_spl_defconfig | 4 > configs/ae350_rv64_spl_xip_defconfig | 4 > configs/ae350_rv64_xip_defconfig | 4 > 8 files changed, 32 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH V2 1/2] drivers: watchdog: add andes atcwdt200 support
On Thu, Nov 30, 2023 at 08:07:28PM +0800, Randolph wrote:
> This patch adds an implementation of the Andes watchdog ATCWDT200 driver.
>
> Signed-off-by: CL Wang
> Signed-off-by: Randolph
> ---
> drivers/watchdog/Kconfig | 6 +
> drivers/watchdog/Makefile| 1 +
> drivers/watchdog/atcwdt200_wdt.c | 220 +++
> 3 files changed, 227 insertions(+)
> create mode 100644 drivers/watchdog/atcwdt200_wdt.c
>
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index 07fc4940e9..6b0f77dd3f 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -130,6 +130,12 @@ config WDT_AT91
> Select this to enable Microchip watchdog timer, which can be found on
> some AT91 devices.
>
> +config WDT_ATCWDT200
> + bool "Andes watchdog timer support"
> + depends on WDT
> + help
> + Select this to enable Andes ATCWDT200 watchdog timer
> +
> config WDT_BCM6345
> bool "BCM6345 watchdog timer support"
> depends on WDT && (ARCH_BMIPS || BCM6856 || \
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index eef786f5e7..1750ebbb1f 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -22,6 +22,7 @@ obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o
> obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
> obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
> obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
> +obj-$(CONFIG_WDT_ATCWDT200) += atcwdt200_wdt.o
> obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o
> obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
> obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
> diff --git a/drivers/watchdog/atcwdt200_wdt.c
> b/drivers/watchdog/atcwdt200_wdt.c
> new file mode 100644
> index 00..2a456d7a46
> --- /dev/null
> +++ b/drivers/watchdog/atcwdt200_wdt.c
> @@ -0,0 +1,220 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2023 Andes Technology Corporation.
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define NODE_NOT_FOUND 0x
> +
> +#define WDT_WP_MAGIC 0x5aa5
> +#define WDT_RESTART_MAGIC 0xcafe
> +
> +/* Control Register */
> +#define REG_WDT_ID 0x00
> +#define REG_WDT_CFG0x10
> +#define REG_WDT_RS 0x14
> +#define REG_WDT_WE 0x18
> +#define REG_WDT_STA0x1C
> +
> +#define RST_TIME_OFF 8
> +#define RST_TIME_MSK (0x7 << RST_TIME_OFF)
> +#define RST_CLK_128(0 << RST_TIME_OFF)
> +#define RST_CLK_256(1 << RST_TIME_OFF)
> +#define RST_CLK_512(2 << RST_TIME_OFF)
> +#define RST_CLK_1024 (3 << RST_TIME_OFF)
> +#define INT_TIME_OFF 4
> +#define INT_TIME_MSK (0xf << INT_TIME_OFF)
> +#define INT_CLK_2_6(0 << INT_TIME_OFF) /* clk period*2^6 */
> +#define INT_CLK_2_8(1 << INT_TIME_OFF) /* clk period*2^8 */
> +#define INT_CLK_2_10 (2 << INT_TIME_OFF) /* clk period*2^10 */
> +#define INT_CLK_2_11 (3 << INT_TIME_OFF) /* clk period*2^11 */
> +#define INT_CLK_2_12 (4 << INT_TIME_OFF) /* clk period*2^12 */
> +#define INT_CLK_2_13 (5 << INT_TIME_OFF) /* clk period*2^13 */
> +#define INT_CLK_2_14 (6 << INT_TIME_OFF) /* clk period*2^14 */
> +#define INT_CLK_2_15 (7 << INT_TIME_OFF) /* clk period*2^15 */
> +#define INT_CLK_2_17 (8 << INT_TIME_OFF) /* clk period*2^17 */
> +#define INT_CLK_2_19 (9 << INT_TIME_OFF) /* clk period*2^19 */
> +#define INT_CLK_2_21 (10 << INT_TIME_OFF) /* clk period*2^21 */
> +#define INT_CLK_2_23 (11 << INT_TIME_OFF) /* clk period*2^23 */
> +#define INT_CLK_2_25 (12 << INT_TIME_OFF) /* clk period*2^25 */
> +#define INT_CLK_2_27 (13 << INT_TIME_OFF) /* clk period*2^27 */
> +#define INT_CLK_2_29 (14 << INT_TIME_OFF) /* clk period*2^29 */
> +#define INT_CLK_2_31 (15 << INT_TIME_OFF) /* clk period*2^31 */
> +#define INT_CLK_MIN0x0
> +#define INT_CLK_MAX_16B0x7
> +#define INT_CLK_MAX_32B0xF
> +#define RST_EN BIT(3)
> +#define INT_EN BIT(2)
> +#define CLK_PCLK BIT(1)
> +#define WDT_EN BIT(0)
> +#define INT_EXPIREDBIT(0)
> +
> +#define INT_TIME_ARRAY 16
> +#define RST_TIME_ARRAY 8
> +
> +struct wdt_priv {
> + void __iomem *base;
> + u32 wdt_clk_src;
> + u32 clk_freq;
> + u8 max_clk;
> +};
> +
> +static inline u8 atcwdt_get_2_power_of_n(u8 index, u8 type)
> +{
> + const u8 div_int[INT_TIME_ARRAY] = {6, 8, 10, 11, 12, 13, 14, 15,
> + 17, 19, 21, 23, 25, 27, 29, 31};
> + const u8 div_rst[RST_TIME_ARRAY] = {7, 8, 9, 10, 11, 12, 13, 14};
> + u8 *pdiv;
> +
> + if (type == RST_TIME_ARRAY)
> + pdiv = div_rst;
> + else
> + pdiv = div_int;
> +
> + if (index >= type)
> + index = type - 1;
> +
> + return pdiv[index];
> +}
> +
> +static u8 atwdt_search_msb(u64 freq_ms, u8 type)
^
Hi
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 2f0282922b2c458eea7f85c500a948a587437b63: Prepare v2024.01-rc4 (2023-12-04 13:46:56 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 94533cd9c15a60b74420e53a725fab54d38dd555: starfive: visionfive2: add device tree overlay support (2023-12-06 16:05:39 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18812 - StarFive: Add StarFive watchdog driver - VisionFive2: Support device tree overlay for VisionFive2 board - Andes: Fix PLIC-SW setting - RISC-V: Fix NVMe support by implying NVME_PCI for QEMU - RISC-V: Fix binman for 64 bit format load address Chanho Park (4): clk: starfive: jh7110: Add watchdog clocks watchdog: Add StarFive Watchdog driver riscv: dts: jh7110: Add watchdog device tree node configs: visionfive2: Enable watchdog driver Heinrich Schuchardt (1): risc-v: qemu: imply NVME_PCI John Clark (1): starfive: visionfive2: add device tree overlay support Randolph (1): riscv: binman: fix the load field format Yu Chien Peter Lin (1): riscv: andes: Fix enable register settings of PLICSW arch/riscv/dts/binman.dtsi | 14 +- arch/riscv/dts/jh7110.dtsi | 10 + arch/riscv/lib/andes_plicsw.c | 33 ++-- board/emulation/qemu-riscv/Kconfig | 2 +- configs/starfive_visionfive2_defconfig | 5 + drivers/clk/starfive/clk-jh7110.c | 9 + drivers/watchdog/Kconfig | 7 + drivers/watchdog/Makefile | 1 + drivers/watchdog/starfive_wdt.c| 329 + include/configs/starfive-visionfive2.h | 1 + 10 files changed, 382 insertions(+), 29 deletions(-) create mode 100644 drivers/watchdog/starfive_wdt.c Best regards, Leo
Re: [PATCH v2] timer: starfive: Add Starfive timer support
Hi Kuan Lim, On Tue, Nov 28, 2023 at 02:42:33PM +0800, Kuan Lim Lee wrote: > Add timer driver in Starfive SoC. It is an timer that outside > of CPU core and inside Starfive SoC. > > Signed-off-by: Kuan Lim Lee > Signed-off-by: Wei Liang Lim > > Changes for v2: > - correct driver name, comment, variable > --- > drivers/timer/Kconfig | 7 +++ > drivers/timer/Makefile | 1 + > drivers/timer/starfive-timer.c | 96 ++ > 3 files changed, 104 insertions(+) > create mode 100644 drivers/timer/starfive-timer.c I have already merged your v1 patch. So could you re-send a patch based on the current master with all the fixes you have in this patch ? Other than that, LGTM. Best regards, Leo
Re: [PATCH V3 3/3] configs: andes: add the fdt blob address for SPL copy to
On Thu, Nov 16, 2023 at 09:01:36PM +0800, Randolph wrote: > Add the address where the FDT blob should be moved. > > Signed-off-by: Randolph > --- > configs/ae350_rv32_falcon_defconfig | 1 + > configs/ae350_rv32_falcon_xip_defconfig | 1 + > configs/ae350_rv64_falcon_defconfig | 1 + > configs/ae350_rv64_falcon_xip_defconfig | 1 + > 4 files changed, 4 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH V3 2/3] spl: riscv: falcon: move fdt blob to specified address
On Thu, Nov 16, 2023 at 09:01:35PM +0800, Randolph wrote: > In Falcon Boot mode, the fdt blob should be move to the RAM from > kernel BSS section. To avoid being cleared by BSS initialisation. > SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies. > > Signed-off-by: Randolph > --- > board/AndesTech/ae350/ae350.c | 25 - > common/spl/Kconfig| 2 +- > common/spl/spl_opensbi.c | 16 > 3 files changed, 17 insertions(+), 26 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH V3 1/3] doc: falcon: riscv: Falcon Mode boot on RISC-V
On Thu, Nov 16, 2023 at 09:01:34PM +0800, Randolph wrote: > Add documentation to introduce the Falcon Mode on RISC-V. > In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel. > > Signed-off-by: Randolph > --- > doc/develop/falcon.rst | 171 + > 1 file changed, 171 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH] starfive: visionfive2: add device tree overlay support
On Mon, Nov 20, 2023 at 02:35:31AM +, John Clark wrote: > device tree overlay support requires fdtoverlay_addr_r to be set > > before > ~~ > Invalid fdtoverlay_addr_r for loading overlays > > after > ~ > Retrieving file: /boot/overlay/rtc-ds3231.dtbo > > Signed-off-by: John Clark > --- > > include/configs/starfive-visionfive2.h | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v2] riscv: Add support for AMD/Xilinx MicroBlaze V
On Mon, Nov 06, 2023 at 12:56:47PM +0100, Michal Simek wrote: > MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. > It is hardware compatible with classic MicroBlaze processor. > > The patch contains initial wiring and configuration for initial HW design > with memory, cpu, interrupt controller, timers and uartlite console > (interrupt controller is listed but U-Boot is not using it). > > Provided DT is just describing one configuration and should be taken only > as example. > > Signed-off-by: Michal Simek > --- > > Changes in v2: > - Extend commit message > - DT changes, add interrupt controller, check agains dt schema > - The patch for amd,mbv32 compatible string is here > https://lore.kernel.org/r/d442d916204d26f82c1c3a924a4cdfb117960e1b.1699270661.git.michal.si...@amd.com > - The patch for board compatibility is here > https://lore.kernel.org/r/50c277c92c41a582ef171fb75efc6a6a4f860be2.1699271616.git.michal.si...@amd.com > > xlnx,xps-intc-1.00.a driver exists in the Linux kernel but DT binding is > missing. That's something what we need to work on. > arch/arm64/boot/dts/xilinx/xilinx-mbv32.dtb: > /axi/interrupt-controller@4120: failed to match any schema with > compatible: ['xlnx,xps-intc-1.00.a'] > > Public annoucement is available here if someone is interested. > https://www.xilinx.com/products/design-tools/microblaze-v.html?utm_source=marketo_medium=email_campaign=EN-EM-2023-11-02-New-MicroBlaze-V-Processor_term=btn_tok=NDA5LVdZWC03MjQAAAGPMMJYuPPscCags7WdvOeUSWy-_mC9aOwrobFaZRf5ok_eHoQUvTLBzJdHrkcBId9tQ4a-odfnU91WjUkIxx-iSG4OKGofjK5iZcAiK_VN8_xK > > --- > arch/riscv/Kconfig | 4 + > arch/riscv/dts/Makefile | 2 + > arch/riscv/dts/xilinx-mbv32.dts | 106 +++ > board/xilinx/Kconfig | 3 +- > board/xilinx/common/board.c | 5 ++ > board/xilinx/mbv/Kconfig | 28 +++ > board/xilinx/mbv/MAINTAINERS | 7 ++ > board/xilinx/mbv/Makefile| 5 ++ > board/xilinx/mbv/board.c | 11 +++ > configs/xilinx_mbv32_defconfig | 30 > configs/xilinx_mbv32_smode_defconfig | 32 > include/configs/xilinx_mbv.h | 6 ++ > 12 files changed, 238 insertions(+), 1 deletion(-) > create mode 100644 arch/riscv/dts/xilinx-mbv32.dts > create mode 100644 board/xilinx/mbv/Kconfig > create mode 100644 board/xilinx/mbv/MAINTAINERS > create mode 100644 board/xilinx/mbv/Makefile > create mode 100644 board/xilinx/mbv/board.c > create mode 100644 configs/xilinx_mbv32_defconfig > create mode 100644 configs/xilinx_mbv32_smode_defconfig > create mode 100644 include/configs/xilinx_mbv.h Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 4/4] configs: visionfive2: Enable watchdog driver
On Mon, Nov 06, 2023 at 08:13:18AM +0900, Chanho Park wrote: > Enables StarFive Watchdog driver and WDT command. > > Signed-off-by: Chanho Park > --- > configs/starfive_visionfive2_defconfig | 5 + > 1 file changed, 5 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 3/4] riscv: dts: jh7110: Add watchdog device tree node
On Mon, Nov 06, 2023 at 08:13:17AM +0900, Chanho Park wrote: > Adds jh7110 watchdog device tree node. > > Signed-off-by: Chanho Park > --- > arch/riscv/dts/jh7110.dtsi | 10 ++ > 1 file changed, 10 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 2/4] watchdog: Add StarFive Watchdog driver
On Mon, Nov 06, 2023 at 08:13:16AM +0900, Chanho Park wrote: > Add to support StarFive watchdog driver. The driver is imported from > linux kernel's drivers/watchdog/starfive-wdt.c without jh7100 support > because there is no support of jh7100 SoC in u-boot yet. > Howver, this patch has been kept the variant coding style because JH7100 > can be added later and have a consistency with the linux driver. > > Signed-off-by: Chanho Park > --- > drivers/watchdog/Kconfig| 7 + > drivers/watchdog/Makefile | 1 + > drivers/watchdog/starfive_wdt.c | 329 > 3 files changed, 337 insertions(+) > create mode 100644 drivers/watchdog/starfive_wdt.c Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 1/4] clk: starfive: jh7110: Add watchdog clocks
On Mon, Nov 06, 2023 at 08:13:15AM +0900, Chanho Park wrote: > Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110 > watchdog device. > > Signed-off-by: Chanho Park > --- > drivers/clk/starfive/clk-jh7110.c | 9 + > 1 file changed, 9 insertions(+) Reviewed-by: Leo Yu-Chi Liang
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit a803f87202aa48974bdff4d8100464a8288931e4: Merge https://source.denx.de/u-boot/custodians/u-boot-mmc (2023-11-01 09:44:33 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 9d22d4a7cef7f2fdaf5c060b71574e6f82ea5ff0: configs: visionfive2: Enable JH7110 RNG driver (2023-11-02 17:45:53 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18407 + CI: Use OpenSBI 1.3.1 release for testing + riscv: Support resume after exception + rng: Support RNG provided by RISC-V Zkr ISA extension + board: starfive VF2: Support jtag + board: starfive VF2: Support TRNG driver + board: sifive unmatched: Move kernel load address Chanho Park (7): riscv: cpu: jh7110: Add gpio helper macros board: starfive: spl: Support jtag for VisionFive2 board riscv: import read/write_relaxed functions clk: starfive: jh7110: Add security clocks rng: Add StarFive JH7110 RNG driver riscv: dts: jh7110: Add rng device tree node configs: visionfive2: Enable JH7110 RNG driver Heinrich Schuchardt (3): CI: use OpenSBI 1.3.1 for testing riscv: allow resume after exception rng: Provide a RNG based on the RISC-V Zkr ISA extension Samuel Holland (3): riscv: Sort target configs alphabetically riscv: Align the trap handler to 64 bytes riscv: Weakly define invalidate_icache_range() Yong-Xuan Wang (1): board: sifive: unmatched: move kernel load address to 0x8020 .azure-pipelines.yml | 8 +- .gitlab-ci.yml| 8 +- arch/riscv/Kconfig| 18 +- arch/riscv/cpu/mtrap.S| 2 +- arch/riscv/dts/jh7110.dtsi| 10 ++ arch/riscv/include/asm/arch-jh7110/gpio.h | 85 + arch/riscv/include/asm/io.h | 45 + arch/riscv/lib/cache.c| 2 +- arch/riscv/lib/interrupts.c | 13 ++ board/starfive/visionfive2/spl.c | 23 +++ configs/starfive_visionfive2_defconfig| 2 + doc/api/index.rst | 1 + doc/api/interrupt.rst | 6 + drivers/clk/starfive/clk-jh7110.c | 10 ++ drivers/rng/Kconfig | 14 ++ drivers/rng/Makefile | 2 + drivers/rng/jh7110_rng.c | 274 ++ drivers/rng/riscv_zkr_rng.c | 116 + include/configs/sifive-unmatched.h| 2 +- include/interrupt.h | 45 + 20 files changed, 666 insertions(+), 20 deletions(-) create mode 100644 arch/riscv/include/asm/arch-jh7110/gpio.h create mode 100644 doc/api/interrupt.rst create mode 100644 drivers/rng/jh7110_rng.c create mode 100644 drivers/rng/riscv_zkr_rng.c create mode 100644 include/interrupt.h Best regards, Leo
Re: [PATCH v4 4/5] riscv: dts: jh7110: Add rng device tree node
On Wed, Nov 01, 2023 at 09:16:51PM +0900, Chanho Park wrote: > Adds jh7110 trng device tree node. > > Signed-off-by: Chanho Park > --- > arch/riscv/dts/jh7110.dtsi | 10 ++ > 1 file changed, 10 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v4 3/5] rng: Add StarFive JH7110 RNG driver
On Wed, Nov 01, 2023 at 09:16:50PM +0900, Chanho Park wrote: > Adds to support JH7110 TRNG driver which is based on linux kernel's > jh7110-trng.c. This can support to generate 256-bit random numbers and > 128-bit but this makes 256-bit default for convenience. > > Signed-off-by: Chanho Park > --- > drivers/rng/Kconfig | 6 + > drivers/rng/Makefile | 1 + > drivers/rng/jh7110_rng.c | 274 +++ > 3 files changed, 281 insertions(+) > create mode 100644 drivers/rng/jh7110_rng.c Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v4 2/5] clk: starfive: jh7110: Add security clocks
On Wed, Nov 01, 2023 at 09:16:49PM +0900, Chanho Park wrote: > Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG > device. > > Signed-off-by: Chanho Park > --- > drivers/clk/starfive/clk-jh7110.c | 10 ++ > 1 file changed, 10 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v4 1/5] riscv: import read/write_relaxed functions
On Wed, Nov 01, 2023 at 09:16:48PM +0900, Chanho Park wrote: > This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h > to use read/write[b|w|l|q]_relaxed functions. > > Signed-off-by: Chanho Park > --- > arch/riscv/include/asm/io.h | 45 + > 1 file changed, 45 insertions(+) Reviewed-by: Leo Yu-Chi Liang
