Re: [PATCH] ARM: stm32: Fix TAMP_SMCR BKP..PROT fields on STM32MP15xx
On 6/19/24 00:57, Marek Vasut wrote:
> Update the TAMP_SMCR BKP..PROT fields to put first 10 registers
> into protection zone 1 and next 5 into zone 2. This fixes use of
> boot counter which is often in zone 3 and has to be updated from
> Linux, which runs in NS.
>
> Fixes: 73f7fc944cf6 ("ARM: stm32: Initialize TAMP_SMCR BKP..PROT fields on
> STM32MP15xx")
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Tom Rini
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
> b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
> index f096fe538d8..ca202bec8ee 100644
> --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
> +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
> @@ -148,8 +148,8 @@ static void security_init(void)
>*/
> clrsetbits_le32(TAMP_SMCR,
> TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT,
> - FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x20) |
> - FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x20));
> + FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x0A) |
> + FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x0F));
>
> /* GPIOZ: deactivate the security */
> writel(BIT(0), RCC_MP_AHB5ENSETR);
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH] ARM: stm32: Ping IWDG on exit from PSCI suspend code
On 6/14/24 15:06, Marek Vasut wrote:
> On 6/14/24 2:00 PM, Patrice CHOTARD wrote:
>>
>>
>> On 4/20/24 00:03, Marek Vasut wrote:
>>> Make sure the OS would not get any spurious IWDG pretimeout IRQ
>>> right after the system wakes up. This may happen in case the SoC
>>> got woken up by another source than the IWDG pretimeout and the
>>> pretimeout IRQ arrived immediately afterward, but too late to be
>>> handled by the suspend main loop. In case either of the IWDG is
>>> enabled, ping it first and then return to the OS.
>>>
>>> Signed-off-by: Marek Vasut
>>> ---
>>> Cc: Igor Opaniuk
>>> Cc: Patrice Chotard
>>> Cc: Patrick Delaunay
>>> Cc: Simon Glass
>>> Cc: Tom Rini
>>> Cc: u-b...@dh-electronics.com
>>> Cc: uboot-st...@st-md-mailman.stormreply.com
>>> ---
>>> arch/arm/mach-stm32mp/stm32mp1/psci.c | 21 +
>>> 1 file changed, 21 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c
>>> b/arch/arm/mach-stm32mp/stm32mp1/psci.c
>>> index 4f2379df45f..e99103910d9 100644
>>> --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c
>>> +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c
>>> @@ -808,6 +808,27 @@ void __secure psci_system_suspend(u32 __always_unused
>>> function_id,
>>> writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
>>> clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
>>> + /*
>>> + * Make sure the OS would not get any spurious IWDG pretimeout IRQ
>>> + * right after the system wakes up. This may happen in case the SoC
>>> + * got woken up by another source than the IWDG pretimeout and the
>>> + * pretimeout IRQ arrived immediately afterward, but too late to be
>>> + * handled by the main loop above. In case either of the IWDG is
>>> + * enabled, ping it first and then return to the OS.
>>> + */
>>> +
>>> + /* Ping IWDG1 and ACK pretimer IRQ */
>>> + if (gic_enabled[4] & BIT(22)) {
>>> + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR);
>>> + writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR);
>>> + }
>>> +
>>> + /* Ping IWDG2 and ACK pretimer IRQ */
>>> + if (gic_enabled[4] & BIT(23)) {
>>> + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR);
>>> + writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR);
>>> + }
>>> +
>>> /*
>>> * The system has resumed successfully. Rewrite LR register stored
>>> * on stack with 'ep' value, so that on return from this PSCI call,
>> Applied to u-boot-stm32/next
>
> This is a fix, should go into /master .
Ah yes :-( , i will send another PR for fixes on monday
Thanks for pointing this
PAtrice
[PULL] Pull request for u-boot master / v2024.07 = u-boot-stm32-20240614
Hi Tom Please pull the STM32 related fixes for u-boot/master, v2024.07: u-boot-stm32-20240614 CI status: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/21116 The following changes since commit ca6a992e09441d6cca73439c63c3735f86b36ea4: cmd: sound: fix help text (2024-06-13 09:31:56 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-stm.git tags/u-boot-stm32-20240614 for you to fetch changes up to 55df13d930f4f191f458a6454f4b8e614e19c215: ARM: stm32: Fix livetree conversion on STM32MP15xx DHSOM (2024-06-14 13:25:06 +0200) STM32MP1: _ Fix spl compilation warning _ Fix optee_get_reserved_memory() _ Fix livetree conversion on STM32MP15xx DHSOM Marek Vasut (1): ARM: stm32: Fix livetree conversion on STM32MP15xx DHSOM Patrice Chotard (2): stm32mp1: spl: Fix compilation warnings stm32mp1: spl: Update optee_get_reserved_memory() return value arch/arm/mach-stm32mp/stm32mp1/spl.c| 4 ++-- board/dhelectronics/dh_stm32mp1/board.c | 15 +--
Re: [PATCH] ARM: dts: stm32: Auto-detect second MAC on STM32MP15xx DH electronics DHCOM
On 6/6/24 15:01, Marek Vasut wrote:
> Test whether this system is compatible with STM32MP15xx DHCOM SoM,
> if so, test whether R292 pull up is populated on pin PC3, which is
> an indication that the second MAC chip, KS8851-16MLL, is populated.
> Use this information to patch 'status' DT property into the second
> ethernet MAC DT node and enable/disable the MAC on systems where
> the chip is/isn't populated respectively.
>
> Use spl_perform_fixups() to patch the U-Boot proper DT from SPL and
> ft_board_setup() to patch Linux DT from U-Boot proper. This way both
> software components are configured the same way.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 1 +
> board/dhelectronics/dh_stm32mp1/board.c| 65 ++
> 2 files changed, 66 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> index 1b445619325..d7b78cdcfa9 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> @@ -26,6 +26,7 @@
> u-boot,error-led = "error";
> dh,som-coding-gpios = < 12 0>, < 13 0>, < 15
> 0>;
> dh,ddr3-coding-gpios = < 6 0>, < 7 0>;
> + dh,mac-coding-gpios = < 3 0>;
> };
> };
>
> diff --git a/board/dhelectronics/dh_stm32mp1/board.c
> b/board/dhelectronics/dh_stm32mp1/board.c
> index 20c9d70737e..ebd45f9053f 100644
> --- a/board/dhelectronics/dh_stm32mp1/board.c
> +++ b/board/dhelectronics/dh_stm32mp1/board.c
> @@ -37,6 +37,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -672,12 +673,69 @@ void board_quiesce_devices(void)
> #endif
> }
>
> +static void dh_stm32_ks8851_fixup(void *blob)
> +{
> + struct gpio_desc ks8851intrn;
> + bool compatible = false;
> + int ks8851intrn_value;
> + const char *prop;
> + ofnode node;
> + int idx = 0;
> + int offset;
> + int ret;
> +
> + /* Do nothing if not STM32MP15xx DHCOM SoM */
> + while ((prop = fdt_stringlist_get(blob, 0, "compatible", idx++, NULL)))
> {
> + if (!strstr(prop, "dhcom-som"))
> + continue;
> + compatible = true;
> + break;
> + }
> +
> + if (!compatible)
> + return;
> +
> + /*
> + * Read state of INTRN pull up resistor, if this pull up is populated,
> + * KS8851-16MLL is populated as well and should be enabled, otherwise
> + * it should be disabled.
> + */
> + node = ofnode_path("/config");
> + if (!ofnode_valid(node))
> + return;
> +
> + ret = gpio_request_by_name_nodev(node, "dh,mac-coding-gpios", 0,
> + , GPIOD_IS_IN);
> + if (ret)
> + return;
> +
> + ks8851intrn_value = dm_gpio_get_value();
> +
> + dm_gpio_free(NULL, );
> +
> + /* Set the 'status' property into KS8851-16MLL DT node. */
> + offset = fdt_path_offset(blob, "ethernet1");
> + ret = fdt_node_check_compatible(blob, offset, "micrel,ks8851-mll");
> + if (ret)/* Not compatible */
> + return;
> +
> + /* Add a bit of extra space for new 'status' property */
> + ret = fdt_shrink_to_minimum(blob, 4096);
> + if (!ret)
> + return;
> +
> + fdt_setprop_string(blob, offset, "status",
> +ks8851intrn_value ? "okay" : "disabled");
> +}
> +
> #if defined(CONFIG_OF_BOARD_SETUP)
> int ft_board_setup(void *blob, struct bd_info *bd)
> {
> const char *buck3path = "/soc/i2c@5c002000/stpmic@33/regulators/buck3";
> int buck3off, ret, uv;
>
> + dh_stm32_ks8851_fixup(blob);
> +
> ret = board_get_regulator_buck3_nvm_uv_av96();
> if (ret)/* Not Avenger96 board, do not patch Buck3 in DT. */
> return 0;
> @@ -698,6 +756,13 @@ int ft_board_setup(void *blob, struct bd_info *bd)
> }
> #endif
>
> +#if defined(CONFIG_SPL_BUILD)
> +void spl_perform_fixups(struct spl_image_info *spl_image)
> +{
> + dh_stm32_ks8851_fixup(spl_image_fdt_addr(spl_image));
> +}
> +#endif
> +
> static void board_copro_image_process(ulong fw_image, size_t fw_size)
> {
> int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
Applied to u-boot-stm32/next
Thanks
Patrice
Re: [PATCH] ARM: dts: stm32: Add generic SoM compatible to STM32MP15xx DH electronics DHSOM
On 5/17/24 01:47, Marek Vasut wrote:
> Add generic SoM compatible string into machine compatible string
> for all STM32MP15xx based DH electronics DHSOM. This way, common
> board code can match on this compatible. No functional change.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp15xx-dhcom-drc02.dts | 4 +++-
> arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts| 4 +++-
> arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts | 4 +++-
> arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 4 +++-
> arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts | 4 +++-
> arch/arm/dts/stm32mp15xx-dhcor-testbench.dts | 4 +++-
> 6 files changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
> b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
> index 1ef9ac29cea..90625bf6b60 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
> @@ -11,5 +11,7 @@
>
> / {
> model = "DH Electronics STM32MP15xx DHCOM DRC02";
> - compatible = "dh,stm32mp15xx-dhcom-drc02", "st,stm32mp1xx";
> + compatible = "dh,stm32mp15xx-dhcom-drc02",
> + "dh,stm32mp15xx-dhcom-som",
> + "st,stm32mp1xx";
> };
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
> b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
> index e2e01e2146c..b2e450aa13b 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
> @@ -11,5 +11,7 @@
>
> / {
> model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit
> (2)";
> - compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x";
> + compatible = "dh,stm32mp15xx-dhcom-pdk2",
> + "dh,stm32mp15xx-dhcom-som",
> + "st,stm32mp15x";
> };
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
> b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
> index 06770b47873..3e908102f61 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
> @@ -11,5 +11,7 @@
>
> / {
> model = "DH Electronics STM32MP15xx DHCOM PicoITX";
> - compatible = "dh,stm32mp15xx-dhcom-picoitx", "st,stm32mp1xx";
> + compatible = "dh,stm32mp15xx-dhcom-picoitx",
> + "dh,stm32mp15xx-dhcom-som",
> + "st,stm32mp1xx";
> };
> diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
> b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
> index 76ac5a873c1..dd8fcecbca5 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
> @@ -14,5 +14,7 @@
>
> / {
> model = "Arrow Electronics STM32MP15xx Avenger96 board";
> - compatible = "arrow,stm32mp15xx-avenger96", "st,stm32mp15x";
> + compatible = "arrow,stm32mp15xx-avenger96",
> + "dh,stm32mp15xx-dhcor-som",
> + "st,stm32mp15x";
> };
> diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
> b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
> index 77dd944ff53..c1f99c1685e 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
> @@ -12,5 +12,7 @@
>
> / {
> model = "DH electronics STM32MP15xx DHCOR DRC Compact";
> - compatible = "dh,stm32mp15xx-dhcor-drc-compact", "st,stm32mp1xx";
> + compatible = "dh,stm32mp15xx-dhcor-drc-compact",
> + "dh,stm32mp15xx-dhcor-som",
> + "st,stm32mp1xx";
> };
> diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
> b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
> index c9163e1c028..5fdd762ddbf 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
> @@ -9,7 +9,9 @@
>
> / {
> model = "DH electronics STM32MP15xx DHCOR Testbench";
> - compatible = "dh,stm32mp15xx-dhcor-testbench", "st,stm32mp1xx";
> + compatible = "dh,stm32mp15xx-dhcor-testbench",
> + "dh,stm32mp15xx-dhcor-som",
> + "st,stm32mp1xx";
>
> aliases {
> ethernet0 =
Applied to u-boot-stm32/next
Thanks
Patrice
Re: [PATCH 3/5] dts: stm32mp157c-odyssey: fix incorrect PHY address
On 4/28/24 16:24, Heesub Shin wrote:
> In Odyssey board, KSZ9031 is at the PHY address 0x7, not 0x0. This
> commit fixes it.
>
> Signed-off-by: Heesub Shin
> ---
> arch/arm/dts/stm32mp157c-odyssey.dts | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts
> b/arch/arm/dts/stm32mp157c-odyssey.dts
> index 53ba018197..b6210cf8b2 100644
> --- a/arch/arm/dts/stm32mp157c-odyssey.dts
> +++ b/arch/arm/dts/stm32mp157c-odyssey.dts
> @@ -81,8 +81,8 @@
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "snps,dwmac-mdio";
> - phy0: ethernet-phy@0 {
> - reg = <0>;
> + phy0: ethernet-phy@7 {
> + reg = <7>;
> };
> };
> };
Applied to u-boot-stm32/next
Thanks
Patrice
Re: [PATCH 3/5] dts: stm32mp157c-odyssey: fix incorrect PHY address
On 4/28/24 16:24, Heesub Shin wrote:
> In Odyssey board, KSZ9031 is at the PHY address 0x7, not 0x0. This
> commit fixes it.
>
> Signed-off-by: Heesub Shin
> ---
> arch/arm/dts/stm32mp157c-odyssey.dts | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts
> b/arch/arm/dts/stm32mp157c-odyssey.dts
> index 53ba018197..b6210cf8b2 100644
> --- a/arch/arm/dts/stm32mp157c-odyssey.dts
> +++ b/arch/arm/dts/stm32mp157c-odyssey.dts
> @@ -81,8 +81,8 @@
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "snps,dwmac-mdio";
> - phy0: ethernet-phy@0 {
> - reg = <0>;
> + phy0: ethernet-phy@7 {
> + reg = <7>;
> };
> };
> };
Applied to u-boot-stm32/next
Thanks
Patrice
Re: [PATCH 1/5] dts: stm32mp157c-odyssey: set PLL4_P to 125Mhz for ETH_CLK
On 4/28/24 16:24, Heesub Shin wrote:
> Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to
> 125, 62.5 and 62.5Mhz in respectively.
>
> Signed-off-by: Heesub Shin
> ---
> arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
> b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
> index b780dbd95e..d07fdcf4bc 100644
> --- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
> @@ -115,11 +115,11 @@
> bootph-all;
> };
>
> - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
> + /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */
> pll4: st,pll@3 {
> compatible = "st,stm32mp1-pll";
> reg = <3>;
> - cfg = < 3 98 5 7 7 PQR(1,1,1) >;
> + cfg = < 3 124 5 9 9 PQR(1,1,1) >;
> bootph-all;
> };
> };
Applied to u-boot-stm32/next
Thanks
Patrice
Re: [PATCH 5/5] dts: stm32mp157c-odyssey: add phy-reset-gpios property to ethernet node
On 4/28/24 16:24, Heesub Shin wrote:
> In Odyssey board, we should reset the PHY chipset, toggling G0 pin.
>
> Signed-off-by: Heesub Shin
> ---
> arch/arm/dts/stm32mp157c-odyssey.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts
> b/arch/arm/dts/stm32mp157c-odyssey.dts
> index b6210cf8b2..4cc5e07683 100644
> --- a/arch/arm/dts/stm32mp157c-odyssey.dts
> +++ b/arch/arm/dts/stm32mp157c-odyssey.dts
> @@ -75,6 +75,7 @@
> phy-mode = "rgmii-id";
> max-speed = <1000>;
> phy-handle = <>;
> + phy-reset-gpios = < 0 GPIO_ACTIVE_LOW>;
> st,ext-phyclk;
>
> mdio0 {
Applied to u-boot-stm32/next
Thanks
Patrice
Re: [PATCH 4/5] net: dwc_eth_qos: add support for phy-reset-gpios property
On 4/28/24 16:24, Heesub Shin wrote:
> This commit adds support for a property 'phy-reset-gpios' to reset PHY
> chipset.
>
> Signed-off-by: Heesub Shin
> ---
> drivers/net/dwc_eth_qos_stm32.c | 23 ++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c
> index fbc08bba1d..cffaa10b70 100644
> --- a/drivers/net/dwc_eth_qos_stm32.c
> +++ b/drivers/net/dwc_eth_qos_stm32.c
> @@ -266,6 +266,12 @@ static int eqos_probe_resources_stm32(struct udevice
> *dev)
> if (ret)
> dev_warn(dev, "No phy clock provided %d\n", ret);
>
> + /* Get reset gpio pin (optional) */
> + ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
> +>phy_reset_gpio, GPIOD_IS_OUT);
> + if (ret)
> + pr_warn("No phy reset gpio provided: %d\n", ret);
> +
> dev_dbg(dev, "%s: OK\n", __func__);
>
> return 0;
> @@ -277,6 +283,21 @@ err_probe:
> return ret;
> }
>
> +static int eqos_start_resets_stm32(struct udevice *dev)
> +{
> + struct eqos_priv *eqos = dev_get_priv(dev);
> +
> + debug("%s(dev=%p):\n", __func__, dev);
> +
> + if (dm_gpio_is_valid(>phy_reset_gpio)) {
> + dm_gpio_set_value(>phy_reset_gpio, 1);
> + udelay(2);
> + dm_gpio_set_value(>phy_reset_gpio, 0);
> + }
> +
> + return 0;
> +}
> +
> static int eqos_remove_resources_stm32(struct udevice *dev)
> {
> dev_dbg(dev, "%s:\n", __func__);
> @@ -292,7 +313,7 @@ static struct eqos_ops eqos_stm32_ops = {
> .eqos_probe_resources = eqos_probe_resources_stm32,
> .eqos_remove_resources = eqos_remove_resources_stm32,
> .eqos_stop_resets = eqos_null_ops,
> - .eqos_start_resets = eqos_null_ops,
> + .eqos_start_resets = eqos_start_resets_stm32,
> .eqos_stop_clks = eqos_stop_clks_stm32,
> .eqos_start_clks = eqos_start_clks_stm32,
> .eqos_calibrate_pads = eqos_null_ops,
Applied to u-boot-stm32/next
Thanks
Patrice
Re: [PATCH 2/5] dts: stm32mp157c-odyssey: use internal clock for Tx
On 6/6/24 16:37, Patrice CHOTARD wrote:
>
>
> On 4/28/24 16:24, Heesub Shin wrote:
>> In Odyssey board, we should use the internal clock from RCC as the
>> transmit clock, instead of the external clock from ETH_CLK125 pad. This
>> commit adds a property, st,eth-clk-sel, so that the ETH_CLK_SEL mux
>> selects ETH_CLK.
>>
>> Signed-off-by: Heesub Shin
>> ---
>> arch/arm/dts/stm32mp157c-odyssey.dts | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts
>> b/arch/arm/dts/stm32mp157c-odyssey.dts
>> index 17bcf56f74..53ba018197 100644
>> --- a/arch/arm/dts/stm32mp157c-odyssey.dts
>> +++ b/arch/arm/dts/stm32mp157c-odyssey.dts
>> @@ -75,6 +75,7 @@
>> phy-mode = "rgmii-id";
>> max-speed = <1000>;
>> phy-handle = <>;
>> +st,ext-phyclk;
>>
>> mdio0 {
>> #address-cells = <1>;
>
> Reviewed-by: Patrice Chotard
>
> Thanks
> Patrice
Applied to u-boot-stm32/next
Thanks
Patrice
Re: [PATCH v2 2/2] ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board
On 4/28/24 00:20, Marek Vasut wrote:
> This stm32mp135f-dhcor-dhsbc board is a stack of DHCOR SoM based on
> STM32MP135F SoC (900MHz / crypto capabilities) populated on DHSBC
> carrier board.
>
> The SoM contains the following peripherals:
> - STPMIC (power delivery)
> - 512MB DDR3L memory
> - eMMC and SDIO WiFi module
>
> The DHSBC carrier board contains the following peripherals:
> - Two RGMII Ethernet ports
> - USB-A Host port, USB-C peripheral port, USB-C power supply plug
> - Expansion connector
>
> Reviewed-by: Patrice Chotard
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> V2: Add RB from Patrice
> ---
> arch/arm/dts/Makefile | 1 +
> .../dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi | 25 ++
> arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts | 383 ++
> arch/arm/dts/stm32mp13xx-dhcor-som.dtsi | 308 ++
> arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi| 55 +++
> configs/stm32mp13_dhcor_defconfig | 148 +++
> 6 files changed, 920 insertions(+)
> create mode 100644 arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
> create mode 100644 arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
> create mode 100644 arch/arm/dts/stm32mp13xx-dhcor-som.dtsi
> create mode 100644 arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
> create mode 100644 configs/stm32mp13_dhcor_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 0c6f0221b77..6d4972827c8 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1285,6 +1285,7 @@ dtb-$(CONFIG_ASPEED_AST2600) += \
> dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
>
> dtb-$(CONFIG_STM32MP13X) += \
> + stm32mp135f-dhcor-dhsbc.dtb \
> stm32mp135f-dk.dtb
>
> dtb-$(CONFIG_STM32MP15X) += \
> diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
> b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
> new file mode 100644
> index 000..d718aae16ca
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2024 Marek Vasut
> + */
> +
> +#include "stm32mp13xx-dhcor-u-boot.dtsi"
> +
> + {
> + bootph-all;
> +};
> +
> +_pins_b {
> + bootph-all;
> +
> + pins1 {
> + bootph-all;
> + };
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> + {
> + bootph-all;
> +};
> diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
> b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
> new file mode 100644
> index 000..fc1c48ad56d
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
> @@ -0,0 +1,383 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2024 Marek Vasut
> + *
> + * DHCOR STM32MP13 variant:
> + * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
> + * DHCOR PCB number: 718-100 or newer
> + * DHSBC PCB number: 719-100 or newer
> + */
> +
> +/dts-v1/;
> +
> +#include
> +#include "stm32mp135.dtsi"
> +#include "stm32mp13xf.dtsi"
> +#include "stm32mp13xx-dhcor-som.dtsi"
> +
> +/ {
> + model = "DH electronics STM32MP135F DHCOR DHSBC";
> + compatible = "dh,stm32mp135f-dhcor-dhsbc",
> + "dh,stm32mp135f-dhcor-som",
> + "st,stm32mp135";
> +
> + aliases {
> + ethernet0 =
> + ethernet1 =
> + serial2 =
> + serial3 =
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +_1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins_a _usb_cc_pins_b>;
> + vdda-supply = <_adc>;
> + vref-supply = <_adc>;
> + status = "okay";
> +
> + adc1: adc@0 {
> + status = "okay";
> +
> + /*
> + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11.
> + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
> + * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
> + * Use arbitrary margin here (e.g. 5us).
> + *
> + * The pinmux pins must be set as ANALOG, use datasheet
> + * DS13483 Table 7. STM32MP135C/F ball definitions to
> + * find out which 'pin name' maps to which 'additional
> + * function
Re: [PATCH v2 1/2] ARM: dts: stm32: Add pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board
On 4/28/24 00:20, Marek Vasut wrote:
> Add new pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board.
> The following pinmux nodes are added:
> - ADC pins
> - ADC CC pins
> - ETH1 pins
> - ETH2 pins
> - I2C5 pins
> - MCAN1 pins
> - MCAN2 pins
> - PWM13 pins
> - PWM5 pins
> - QSPI pins
> - SAI1 pins
> - SDMMC2 D4..D7 pins
> - SPI2 pins
> - SPI3 pins
> - UART4 pins
> - UART7 pins
> - USART1 pins
> - USART2 pins
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> V2: Squash the pinmux patches into one megapatch
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 483
> 1 file changed, 483 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index 27e0c382678..c01d39f03ea 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -6,6 +6,12 @@
> #include
>
> {
> + adc1_pins_a: adc1-pins-0 {
> + pins {
> + pinmux = ; /* ADC1 in12 */
> + };
> + };
> +
> adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
> pins {
> pinmux = , /* ADC1 in6 */
> @@ -13,6 +19,104 @@
> };
> };
>
> + adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
> + pins {
> + pinmux = , /* ADC1_INP2 */
> + ; /* ADC1_INP11
> */
> + };
> + };
> +
> + eth1_rgmii_pins_a: eth1-rgmii-0 {
> + pins1 {
> + pinmux = , /*
> ETH_RGMII_TXD0 */
> + , /*
> ETH_RGMII_TXD1 */
> + , /*
> ETH_RGMII_TXD2 */
> + , /*
> ETH_RGMII_TXD3 */
> + , /*
> ETH_RGMII_TX_CTL */
> + , /*
> ETH_RGMII_GTX_CLK */
> + , /* ETH_MDIO */
> + ; /* ETH_MDC */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <2>;
> + };
> +
> + pins2 {
> + pinmux = , /*
> ETH_RGMII_RXD0 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RXD2 */
> + , /*
> ETH_RGMII_RXD3 */
> + , /*
> ETH_RGMII_RX_CTL */
> + ; /*
> ETH_RGMII_RX_CLK */
> + bias-disable;
> + };
> +
> + };
> +
> + eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
> + pins1 {
> + pinmux = , /*
> ETH_RGMII_TXD0 */
> + , /*
> ETH_RGMII_TXD1 */
> + , /*
> ETH_RGMII_TXD2 */
> + , /*
> ETH_RGMII_TXD3 */
> + , /*
> ETH_RGMII_TX_CTL */
> + , /*
> ETH_RGMII_GTX_CLK */
> + , /* ETH_MDIO */
> + , /* ETH_MDC */
> + , /*
> ETH_RGMII_RXD0 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RX_CTL */
> + ; /*
> ETH_RGMII_RX_CLK */
> + };
> + };
> +
> + eth2_rgmii_pins_a: eth2-rgmii-0 {
> + pins1 {
> + pinmux = , /*
> ETH_RGMII_TXD0 */
> + , /*
> ETH_RGMII_TXD1 */
> + , /*
> ETH_RGMII_TXD2 */
> + , /*
> ETH_RGMII_TXD3 */
> + , /*
> ETH_RGMII_TX_CTL */
> + , /*
> ETH_RGMII_GTX_CLK */
> + , /* ETH_MDIO */
> + ; /* ETH_MDC */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <2>;
> + };
> +
> + pins2 {
> + pinmux = , /*
> ETH_RGMII_RXD0 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RXD2 */
> +
Re: [PATCH] ARM: stm32: Ping IWDG on exit from PSCI suspend code
On 4/20/24 00:03, Marek Vasut wrote:
> Make sure the OS would not get any spurious IWDG pretimeout IRQ
> right after the system wakes up. This may happen in case the SoC
> got woken up by another source than the IWDG pretimeout and the
> pretimeout IRQ arrived immediately afterward, but too late to be
> handled by the suspend main loop. In case either of the IWDG is
> enabled, ping it first and then return to the OS.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Igor Opaniuk
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/mach-stm32mp/stm32mp1/psci.c | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c
> b/arch/arm/mach-stm32mp/stm32mp1/psci.c
> index 4f2379df45f..e99103910d9 100644
> --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c
> +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c
> @@ -808,6 +808,27 @@ void __secure psci_system_suspend(u32 __always_unused
> function_id,
> writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
> clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
>
> + /*
> + * Make sure the OS would not get any spurious IWDG pretimeout IRQ
> + * right after the system wakes up. This may happen in case the SoC
> + * got woken up by another source than the IWDG pretimeout and the
> + * pretimeout IRQ arrived immediately afterward, but too late to be
> + * handled by the main loop above. In case either of the IWDG is
> + * enabled, ping it first and then return to the OS.
> + */
> +
> + /* Ping IWDG1 and ACK pretimer IRQ */
> + if (gic_enabled[4] & BIT(22)) {
> + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR);
> + writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR);
> + }
> +
> + /* Ping IWDG2 and ACK pretimer IRQ */
> + if (gic_enabled[4] & BIT(23)) {
> + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR);
> + writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR);
> + }
> +
> /*
>* The system has resumed successfully. Rewrite LR register stored
>* on stack with 'ep' value, so that on return from this PSCI call,
Applied to u-boot-stm32/next
Thanks
Patrice
Re: [PATCH] ARM: stm32: Ping IWDG on exit from PSCI suspend code
On 6/10/24 10:36, Igor Opaniuk wrote:
> On Sat, Apr 20, 2024 at 12:03 AM Marek Vasut wrote:
>>
>> Make sure the OS would not get any spurious IWDG pretimeout IRQ
>> right after the system wakes up. This may happen in case the SoC
>> got woken up by another source than the IWDG pretimeout and the
>> pretimeout IRQ arrived immediately afterward, but too late to be
>> handled by the suspend main loop. In case either of the IWDG is
>> enabled, ping it first and then return to the OS.
>>
>> Signed-off-by: Marek Vasut
>> ---
>> Cc: Igor Opaniuk
>> Cc: Patrice Chotard
>> Cc: Patrick Delaunay
>> Cc: Simon Glass
>> Cc: Tom Rini
>> Cc: u-b...@dh-electronics.com
>> Cc: uboot-st...@st-md-mailman.stormreply.com
>> ---
>> arch/arm/mach-stm32mp/stm32mp1/psci.c | 21 +
>> 1 file changed, 21 insertions(+)
>>
>> diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c
>> b/arch/arm/mach-stm32mp/stm32mp1/psci.c
>> index 4f2379df45f..e99103910d9 100644
>> --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c
>> +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c
>> @@ -808,6 +808,27 @@ void __secure psci_system_suspend(u32 __always_unused
>> function_id,
>> writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
>> clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
>>
>> + /*
>> +* Make sure the OS would not get any spurious IWDG pretimeout IRQ
>> +* right after the system wakes up. This may happen in case the SoC
>> +* got woken up by another source than the IWDG pretimeout and the
>> +* pretimeout IRQ arrived immediately afterward, but too late to be
>> +* handled by the main loop above. In case either of the IWDG is
>> +* enabled, ping it first and then return to the OS.
>> +*/
>> +
>> + /* Ping IWDG1 and ACK pretimer IRQ */
>> + if (gic_enabled[4] & BIT(22)) {
>> + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR);
>> + writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR);
>> + }
>> +
>> + /* Ping IWDG2 and ACK pretimer IRQ */
>> + if (gic_enabled[4] & BIT(23)) {
>> + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR);
>> + writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR);
>> + }
>> +
>> /*
>> * The system has resumed successfully. Rewrite LR register stored
>> * on stack with 'ep' value, so that on return from this PSCI call,
>> --
>> 2.43.0
>>
>
> Reviewed-by: Igor Opaniuk
>
Applied to u-boot-stm32/next
Thanks
Patrice
Re: [PATCH 2/2] ARM: stm32: Make PWR regulator driver available on STM32MP13xx
On 3/19/24 03:45, Marek Vasut wrote: > This patch makes STM32 PWR regulators available on stm32mp13xx. > This requires TFA to clear RCC_SECCFGR, is disabled by default > on stm32mp13xx and can only be enabled on board config level. > > Signed-off-by: Marek Vasut > --- > Cc: Patrice Chotard > Cc: Patrick Delaunay > Cc: Tom Rini > Cc: u-b...@dh-electronics.com > Cc: u-boot@lists.denx.de > Cc: uboot-st...@st-md-mailman.stormreply.com > --- > arch/arm/mach-stm32mp/Kconfig | 17 + > arch/arm/mach-stm32mp/Kconfig.15x | 16 > 2 files changed, 17 insertions(+), 16 deletions(-) > > diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig > index b9af03d57e3..d5934a92771 100644 > --- a/arch/arm/mach-stm32mp/Kconfig > +++ b/arch/arm/mach-stm32mp/Kconfig > @@ -155,4 +155,21 @@ source "arch/arm/mach-stm32mp/Kconfig.13x" > source "arch/arm/mach-stm32mp/Kconfig.15x" > source "arch/arm/mach-stm32mp/Kconfig.25x" > source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" > + > +config STM32MP15_PWR > + bool "Enable driver for STM32MP15x PWR" > + depends on DM_REGULATOR && DM_PMIC && (STM32MP13X || STM32MP15X) > + default y if STM32MP15X > + help > + This config enables implementation of driver-model pmic and > + regulator uclass features for access to STM32MP15x PWR. > + > +config SPL_STM32MP15_PWR > + bool "Enable driver for STM32MP15x PWR in SPL" > + depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC && (STM32MP13X || > STM32MP15X) > + default y if STM32MP15X > + help > + This config enables implementation of driver-model pmic and > + regulator uclass features for access to STM32MP15x PWR in SPL. > + > endif > diff --git a/arch/arm/mach-stm32mp/Kconfig.15x > b/arch/arm/mach-stm32mp/Kconfig.15x > index 71c14eb4955..d99aa9fd694 100644 > --- a/arch/arm/mach-stm32mp/Kconfig.15x > +++ b/arch/arm/mach-stm32mp/Kconfig.15x > @@ -77,22 +77,6 @@ config TARGET_ICORE_STM32MP1 > > endchoice > > -config STM32MP15_PWR > - bool "Enable driver for STM32MP15x PWR" > - depends on DM_REGULATOR && DM_PMIC > - default y > - help > - This config enables implementation of driver-model pmic and > - regulator uclass features for access to STM32MP15x PWR. > - > -config SPL_STM32MP15_PWR > - bool "Enable driver for STM32MP15x PWR in SPL" > - depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC > - default y > - help > - This config enables implementation of driver-model pmic and > - regulator uclass features for access to STM32MP15x PWR in SPL. > - > config TEXT_BASE > default 0xC010 > Applied to u-boot-stm32/next Thanks Patrice
Re: [PATCH 1/2] ARM: dts: stm32: add PWR regulators support on stm32mp131
On 3/19/24 03:45, Marek Vasut wrote:
> This patch adds STM32 PWR regulators DT support on stm32mp131.
> This requires TFA to clear RCC_SECCFGR, is disabled by default
> and can only be enabled on board DT level.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp131.dtsi | 24
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
> index 81d99a7582b..ad331b73d18 100644
> --- a/arch/arm/dts/stm32mp131.dtsi
> +++ b/arch/arm/dts/stm32mp131.dtsi
> @@ -1092,6 +1092,30 @@
><_clk CK_SCMI_LSI>;
> };
>
> + pwr_regulators: pwr@50001000 {
> + compatible = "st,stm32mp1,pwr-reg";
> + reg = <0x50001000 0x10>;
> + status = "disabled";
> +
> + reg11: reg11 {
> + regulator-name = "reg11";
> + regulator-min-microvolt = <110>;
> + regulator-max-microvolt = <110>;
> + };
> +
> + reg18: reg18 {
> + regulator-name = "reg18";
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <180>;
> + };
> +
> + usb33: usb33 {
> + regulator-name = "usb33";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + };
> + };
> +
> exti: interrupt-controller@5000d000 {
> compatible = "st,stm32mp13-exti", "syscon";
> interrupt-controller;
Applied to u-boot-stm32/next
Thanks
Patrice
Re: [PATCH v2] stm32mp: Reserve OPTEE area in EFI memory map
On 6/14/24 10:43, Patrick DELAUNAY wrote:
> Hi,
>
> On 4/22/24 17:06, Patrice Chotard wrote:
>> Since commit 7b78d6438a2b3 ("efi_loader: Reserve unaccessible memory")
>> memory region above ram_top is tagged in EFI memory map as
>> EFI_BOOT_SERVICES_DATA.
>> In case of STM32MP1/STM32MP13 platforms, above ram_top, there is one
>> reserved-memory region tagged "no-map" dedicated to OP-TEE :
>> _ addr=de00 size=200 for stm32mp157x-dkx and stm32mp135f-dk
>> _ addr=fe00 size=200 for stm32mp157c-ev1
>>
>> Before booting kernel, EFI memory map is first built, the OPTEE region is
>> tagged as EFI_BOOT_SERVICES_DATA and when reserving LMB, the tag LMB_NONE
>> is used.
>>
>> Then after, the LMB are completed by boot_fdt_add_mem_rsv_regions()
>> which try to add again the same OPTEE region (addr=de00 size=200
>> in case of stm32mp157x-dkx / stm32mp135f-dk or addr=fe00 size=200
>> in case for stm2mp157c-ev1)
>> but now with LMB_NOMAP tag which produces the following error message :
>>
>> _ for stm32mp157x-dkx / stm32mp135f-dk :
>> "ERROR: reserving fdt memory region failed (addr=de00 size=200
>> flags=4)"
>>
>> _ for stm32mp157c-ev1 :
>> "ERROR: reserving fdt memory region failed (addr=fe00 size=200
>> flags=4)"
>>
>> To avoid this, OPTEE area shouldn't be used by EFI, so we need to mark
>> it as reserved.
>>
>> Signed-off-by: Patrice Chotard
>>
>> ---
>>
>> Changes in v2:
>> _ update commit message by adding information about memory area
>> dedicated for OPTEE for various STM32MP1/STM32MP13 boards.
>>
>> arch/arm/mach-stm32mp/dram_init.c | 12
>> 1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm/mach-stm32mp/dram_init.c
>> b/arch/arm/mach-stm32mp/dram_init.c
>> index fb1208fc5d5..f67f54f2ae0 100644
>> --- a/arch/arm/mach-stm32mp/dram_init.c
>> +++ b/arch/arm/mach-stm32mp/dram_init.c
>> @@ -7,6 +7,7 @@
>> #include
>> #include
>> +#include
>> #include
>> #include
>> #include
>> @@ -75,3 +76,14 @@ phys_addr_t board_get_usable_ram_top(phys_size_t
>> total_size)
>> return reg + size;
>> }
>> +
>> +void efi_add_known_memory(void)
>> +{
>> + if (IS_ENABLED(CONFIG_EFI_LOADER))
>> + /*
>> + * Memory over ram_top is reserved to OPTEE.
>> + * Declare to EFI only memory area below ram_top
>> + */
>> + efi_add_memory_map(gd->ram_base, gd->ram_top - gd->ram_base,
>> + EFI_CONVENTIONAL_MEMORY);
>> +}
>
> It seen like a temporary workaround after commit 7b78d6438a2b3
> ("efi_loader: Reserve unaccessible memory") to avoid warnings.
>
> And it is working because in the default memory mapping
> OP-TEE base address == RAM_TOP and the rest of memory is
> used by OP-TEE tagged "no map" (protected by firewall)
>
>
> Reviewed-by: Patrick Delaunay
>
> FYI: workaround because the memory above ram_top is
> "already occupied by firmware" =
> and it is OP-TEE for STM32MP2 platform.
>
> For me the LMB type used by EFI in not correct for OP-TEE usage region
> with "no-map" tag in device tree= see boot_fdt_add_mem_rsv_regions()
> for linux DT parsing
>
> and we have no way to indicated this LMB tag= LMB_NOMAP with EFI stack
> (with enum efi_memory_type ?)
>
>
> EFI_BOOT_SERVICES_DATA => doesn't means NOMAP flag for LMB
> so something is missing in EFI side like EFI_BOOT_NOMAP to be used in
> board
> implementation of efi_add_known_memory() ?
>
>
> Thanks
> Patrick
>
>
>
>
>
Applied to u-boot-stm32/next
Thanks
Patrice
Re: [PATCH] ARM: stm32: Fix livetree conversion on STM32MP15xx DHSOM
On 6/6/24 15:02, Marek Vasut wrote:
> Unlike fdt_node_check_compatible() which returns 0 if node is compatible,
> ofnode_device_is_compatible() return true which is non-zero if node is
> compatible. The intention of the code is to exit from the function in
> case the node is not compatible with "micrel,ks8851-mll". Add the missing
> invert into the conditional to reinstate original behavior.
>
> This exposes a follow up problem caused by conversion to DM based FMC2 EBI
> driver, where the FMC2 EBI is not configured when accessed by this code.
> Probe the KS8851 MAC, which also configures the FMC2 EBI as a dependency,
> so that the KS8851 MAC CCR register can be accessed over the FMC2 EBI bus
> and checked for EEPROM present bit.
>
> Fixes: 5a605b7c8615 ("board: dhelectronics: stm32mp1: convert to livetree")
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> board/dhelectronics/dh_stm32mp1/board.c | 15 +--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/board/dhelectronics/dh_stm32mp1/board.c
> b/board/dhelectronics/dh_stm32mp1/board.c
> index ebd45f9053f..4f4f537fee5 100644
> --- a/board/dhelectronics/dh_stm32mp1/board.c
> +++ b/board/dhelectronics/dh_stm32mp1/board.c
> @@ -76,14 +76,25 @@
>
> static bool dh_stm32_mac_is_in_ks8851(void)
> {
> - ofnode node;
> + struct udevice *udev;
> u32 reg, cider, ccr;
> + char path[256];
> + ofnode node;
> + int ret;
>
> node = ofnode_path("ethernet1");
> if (!ofnode_valid(node))
> return false;
>
> - if (ofnode_device_is_compatible(node, "micrel,ks8851-mll"))
> + ret = ofnode_get_path(node, path, sizeof(path));
> + if (ret)
> + return false;
> +
> + ret = uclass_get_device_by_of_path(UCLASS_ETH, path, );
> + if (ret)
> + return false;
> +
> + if (!ofnode_device_is_compatible(node, "micrel,ks8851-mll"))
> return false;
>
> /*
Applied to u-boot-stm32/master
Re: [PATCH] ARM: dts: stm32: Auto-detect second MAC on STM32MP15xx DH electronics DHCOM
On 6/6/24 15:01, Marek Vasut wrote:
> Test whether this system is compatible with STM32MP15xx DHCOM SoM,
> if so, test whether R292 pull up is populated on pin PC3, which is
> an indication that the second MAC chip, KS8851-16MLL, is populated.
> Use this information to patch 'status' DT property into the second
> ethernet MAC DT node and enable/disable the MAC on systems where
> the chip is/isn't populated respectively.
>
> Use spl_perform_fixups() to patch the U-Boot proper DT from SPL and
> ft_board_setup() to patch Linux DT from U-Boot proper. This way both
> software components are configured the same way.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 1 +
> board/dhelectronics/dh_stm32mp1/board.c| 65 ++
> 2 files changed, 66 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> index 1b445619325..d7b78cdcfa9 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> @@ -26,6 +26,7 @@
> u-boot,error-led = "error";
> dh,som-coding-gpios = < 12 0>, < 13 0>, < 15
> 0>;
> dh,ddr3-coding-gpios = < 6 0>, < 7 0>;
> + dh,mac-coding-gpios = < 3 0>;
> };
> };
>
> diff --git a/board/dhelectronics/dh_stm32mp1/board.c
> b/board/dhelectronics/dh_stm32mp1/board.c
> index 20c9d70737e..ebd45f9053f 100644
> --- a/board/dhelectronics/dh_stm32mp1/board.c
> +++ b/board/dhelectronics/dh_stm32mp1/board.c
> @@ -37,6 +37,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -672,12 +673,69 @@ void board_quiesce_devices(void)
> #endif
> }
>
> +static void dh_stm32_ks8851_fixup(void *blob)
> +{
> + struct gpio_desc ks8851intrn;
> + bool compatible = false;
> + int ks8851intrn_value;
> + const char *prop;
> + ofnode node;
> + int idx = 0;
> + int offset;
> + int ret;
> +
> + /* Do nothing if not STM32MP15xx DHCOM SoM */
> + while ((prop = fdt_stringlist_get(blob, 0, "compatible", idx++, NULL)))
> {
> + if (!strstr(prop, "dhcom-som"))
> + continue;
> + compatible = true;
> + break;
> + }
> +
> + if (!compatible)
> + return;
> +
> + /*
> + * Read state of INTRN pull up resistor, if this pull up is populated,
> + * KS8851-16MLL is populated as well and should be enabled, otherwise
> + * it should be disabled.
> + */
> + node = ofnode_path("/config");
> + if (!ofnode_valid(node))
> + return;
> +
> + ret = gpio_request_by_name_nodev(node, "dh,mac-coding-gpios", 0,
> + , GPIOD_IS_IN);
> + if (ret)
> + return;
> +
> + ks8851intrn_value = dm_gpio_get_value();
> +
> + dm_gpio_free(NULL, );
> +
> + /* Set the 'status' property into KS8851-16MLL DT node. */
> + offset = fdt_path_offset(blob, "ethernet1");
> + ret = fdt_node_check_compatible(blob, offset, "micrel,ks8851-mll");
> + if (ret)/* Not compatible */
> + return;
> +
> + /* Add a bit of extra space for new 'status' property */
> + ret = fdt_shrink_to_minimum(blob, 4096);
> + if (!ret)
> + return;
> +
> + fdt_setprop_string(blob, offset, "status",
> +ks8851intrn_value ? "okay" : "disabled");
> +}
> +
> #if defined(CONFIG_OF_BOARD_SETUP)
> int ft_board_setup(void *blob, struct bd_info *bd)
> {
> const char *buck3path = "/soc/i2c@5c002000/stpmic@33/regulators/buck3";
> int buck3off, ret, uv;
>
> + dh_stm32_ks8851_fixup(blob);
> +
> ret = board_get_regulator_buck3_nvm_uv_av96();
> if (ret)/* Not Avenger96 board, do not patch Buck3 in DT. */
> return 0;
> @@ -698,6 +756,13 @@ int ft_board_setup(void *blob, struct bd_info *bd)
> }
> #endif
>
> +#if defined(CONFIG_SPL_BUILD)
> +void spl_perform_fixups(struct spl_image_info *spl_image)
> +{
> + dh_stm32_ks8851_fixup(spl_image_fdt_addr(spl_image));
> +}
> +#endif
> +
> static void board_copro_image_process(ulong fw_image, size_t fw_size)
> {
> int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
Reviewed-by: Patrice Chotard
Thanks
PAtrice
Re: [PATCH] ARM: stm32: Fix livetree conversion on STM32MP15xx DHSOM
On 6/6/24 15:02, Marek Vasut wrote:
> Unlike fdt_node_check_compatible() which returns 0 if node is compatible,
> ofnode_device_is_compatible() return true which is non-zero if node is
> compatible. The intention of the code is to exit from the function in
> case the node is not compatible with "micrel,ks8851-mll". Add the missing
> invert into the conditional to reinstate original behavior.
>
> This exposes a follow up problem caused by conversion to DM based FMC2 EBI
> driver, where the FMC2 EBI is not configured when accessed by this code.
> Probe the KS8851 MAC, which also configures the FMC2 EBI as a dependency,
> so that the KS8851 MAC CCR register can be accessed over the FMC2 EBI bus
> and checked for EEPROM present bit.
>
> Fixes: 5a605b7c8615 ("board: dhelectronics: stm32mp1: convert to livetree")
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> board/dhelectronics/dh_stm32mp1/board.c | 15 +--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/board/dhelectronics/dh_stm32mp1/board.c
> b/board/dhelectronics/dh_stm32mp1/board.c
> index ebd45f9053f..4f4f537fee5 100644
> --- a/board/dhelectronics/dh_stm32mp1/board.c
> +++ b/board/dhelectronics/dh_stm32mp1/board.c
> @@ -76,14 +76,25 @@
>
> static bool dh_stm32_mac_is_in_ks8851(void)
> {
> - ofnode node;
> + struct udevice *udev;
> u32 reg, cider, ccr;
> + char path[256];
> + ofnode node;
> + int ret;
>
> node = ofnode_path("ethernet1");
> if (!ofnode_valid(node))
> return false;
>
> - if (ofnode_device_is_compatible(node, "micrel,ks8851-mll"))
> + ret = ofnode_get_path(node, path, sizeof(path));
> + if (ret)
> + return false;
> +
> + ret = uclass_get_device_by_of_path(UCLASS_ETH, path, );
> + if (ret)
> + return false;
> +
> + if (!ofnode_device_is_compatible(node, "micrel,ks8851-mll"))
> return false;
>
> /*
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 1/2] stm32mp1: spl: Fix compilation warnings
On 6/14/24 09:59, Patrick DELAUNAY wrote:
> Hi Patrice,
>
> On 6/11/24 11:52, Patrice Chotard wrote:
>> Fix the following compilation warnings :
>>
>> ../arch/arm/mach-stm32mp/stm32mp1/spl.c: In function
>> 'stm32_init_tzc_for_optee':
>> ../arch/arm/mach-stm32mp/stm32mp1/spl.c:148:37: warning: 'optee_size' may be
>> used uninitialized [-Wmaybe-uninitialized]
>> 148 | tee_shmem_base = optee_base + optee_size - CFG_SHMEM_SIZE;
>> | ~~~^~~~
>> ../arch/arm/mach-stm32mp/stm32mp1/spl.c:137:30: note: 'optee_size' was
>> declared here
>> 137 | uint32_t optee_base, optee_size, tee_shmem_base;
>> | ^~
>> ../arch/arm/mach-stm32mp/stm32mp1/spl.c:148:37: warning: 'optee_base' may be
>> used
>> uninitialized [-Wmaybe-uninitialized]
>> 148 | tee_shmem_base = optee_base + optee_size - CFG_SHMEM_SIZE;
>> | ~~~^~~~
>> ../arch/arm/mach-stm32mp/stm32mp1/spl.c:137:18: note: 'optee_base' was
>> declared here
>> 137 | uint32_t optee_base, optee_size, tee_shmem_base;
>> | ^~
>>
>> Fix also the following checkpatch "check" :
>>
>> CHECK: Prefer kernel type 'u32' over 'uint32_t'
>> 37: FILE: arch/arm/mach-stm32mp/stm32mp1/spl.c:137:
>> + uint32_t optee_base = 0, optee_size = 0, tee_shmem_base;
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> arch/arm/mach-stm32mp/stm32mp1/spl.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c
>> b/arch/arm/mach-stm32mp/stm32mp1/spl.c
>> index 6c79259b2c8..10abbed87f0 100644
>> --- a/arch/arm/mach-stm32mp/stm32mp1/spl.c
>> +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c
>> @@ -134,7 +134,7 @@ void stm32_init_tzc_for_optee(void)
>> {
>> const uint32_t dram_size = stm32mp_get_dram_size();
>> const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1);
>> - uint32_t optee_base, optee_size, tee_shmem_base;
>> + u32 optee_base = 0, optee_size = 0, tee_shmem_base;
>> const uintptr_t tzc = STM32_TZC_BASE;
>> int ret;
>>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
>
Applied to u-boot-stm32/master
Thanks
Patrice
Re: [PATCH 2/2] stm32mp1: spl: Update optee_get_reserved_memory() return value
On 6/14/24 09:59, Patrick DELAUNAY wrote:
> Hi Patrice
>
> On 6/11/24 11:52, Patrice Chotard wrote:
>> In case node "/reserved-memory/optee" is not found, return -ENOENT
>> instead of 0.
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> arch/arm/mach-stm32mp/stm32mp1/spl.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c
>> b/arch/arm/mach-stm32mp/stm32mp1/spl.c
>> index 10abbed87f0..beda69f3359 100644
>> --- a/arch/arm/mach-stm32mp/stm32mp1/spl.c
>> +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c
>> @@ -118,7 +118,7 @@ static int optee_get_reserved_memory(uint32_t *start,
>> uint32_t *size)
>> node = ofnode_path("/reserved-memory/optee");
>> if (!ofnode_valid(node))
>> - return 0;
>> + return -ENOENT;
>> fdt_start = ofnode_get_addr_size(node, "reg", _mem_size);
>> *start = fdt_start;
>
>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
>
>
Applied to u-boot-stm32/master
Thanks
Patrice
[PATCH 2/2] stm32mp1: spl: Update optee_get_reserved_memory() return value
In case node "/reserved-memory/optee" is not found, return -ENOENT
instead of 0.
Signed-off-by: Patrice Chotard
---
arch/arm/mach-stm32mp/stm32mp1/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c
b/arch/arm/mach-stm32mp/stm32mp1/spl.c
index 10abbed87f0..beda69f3359 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/spl.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c
@@ -118,7 +118,7 @@ static int optee_get_reserved_memory(uint32_t *start,
uint32_t *size)
node = ofnode_path("/reserved-memory/optee");
if (!ofnode_valid(node))
- return 0;
+ return -ENOENT;
fdt_start = ofnode_get_addr_size(node, "reg", _mem_size);
*start = fdt_start;
--
2.25.1
[PATCH 1/2] stm32mp1: spl: Fix compilation warnings
Fix the following compilation warnings :
../arch/arm/mach-stm32mp/stm32mp1/spl.c: In function 'stm32_init_tzc_for_optee':
../arch/arm/mach-stm32mp/stm32mp1/spl.c:148:37: warning: 'optee_size' may be
used uninitialized [-Wmaybe-uninitialized]
148 | tee_shmem_base = optee_base + optee_size - CFG_SHMEM_SIZE;
| ~~~^~~~
../arch/arm/mach-stm32mp/stm32mp1/spl.c:137:30: note: 'optee_size' was declared
here
137 | uint32_t optee_base, optee_size, tee_shmem_base;
| ^~
../arch/arm/mach-stm32mp/stm32mp1/spl.c:148:37: warning: 'optee_base' may be
used
uninitialized [-Wmaybe-uninitialized]
148 | tee_shmem_base = optee_base + optee_size - CFG_SHMEM_SIZE;
| ~~~^~~~
../arch/arm/mach-stm32mp/stm32mp1/spl.c:137:18: note: 'optee_base' was declared
here
137 | uint32_t optee_base, optee_size, tee_shmem_base;
| ^~
Fix also the following checkpatch "check" :
CHECK: Prefer kernel type 'u32' over 'uint32_t'
37: FILE: arch/arm/mach-stm32mp/stm32mp1/spl.c:137:
+ uint32_t optee_base = 0, optee_size = 0, tee_shmem_base;
Signed-off-by: Patrice Chotard
---
arch/arm/mach-stm32mp/stm32mp1/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c
b/arch/arm/mach-stm32mp/stm32mp1/spl.c
index 6c79259b2c8..10abbed87f0 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/spl.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c
@@ -134,7 +134,7 @@ void stm32_init_tzc_for_optee(void)
{
const uint32_t dram_size = stm32mp_get_dram_size();
const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1);
- uint32_t optee_base, optee_size, tee_shmem_base;
+ u32 optee_base = 0, optee_size = 0, tee_shmem_base;
const uintptr_t tzc = STM32_TZC_BASE;
int ret;
--
2.25.1
Re: [PATCH] ARM: stm32: Ping IWDG on exit from PSCI suspend code
On 4/20/24 00:03, Marek Vasut wrote:
> Make sure the OS would not get any spurious IWDG pretimeout IRQ
> right after the system wakes up. This may happen in case the SoC
> got woken up by another source than the IWDG pretimeout and the
> pretimeout IRQ arrived immediately afterward, but too late to be
> handled by the suspend main loop. In case either of the IWDG is
> enabled, ping it first and then return to the OS.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Igor Opaniuk
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/mach-stm32mp/stm32mp1/psci.c | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c
> b/arch/arm/mach-stm32mp/stm32mp1/psci.c
> index 4f2379df45f..e99103910d9 100644
> --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c
> +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c
> @@ -808,6 +808,27 @@ void __secure psci_system_suspend(u32 __always_unused
> function_id,
> writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
> clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
>
> + /*
> + * Make sure the OS would not get any spurious IWDG pretimeout IRQ
> + * right after the system wakes up. This may happen in case the SoC
> + * got woken up by another source than the IWDG pretimeout and the
> + * pretimeout IRQ arrived immediately afterward, but too late to be
> + * handled by the main loop above. In case either of the IWDG is
> + * enabled, ping it first and then return to the OS.
> + */
> +
> + /* Ping IWDG1 and ACK pretimer IRQ */
> + if (gic_enabled[4] & BIT(22)) {
> + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR);
> + writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR);
> + }
> +
> + /* Ping IWDG2 and ACK pretimer IRQ */
> + if (gic_enabled[4] & BIT(23)) {
> + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR);
> + writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR);
> + }
> +
> /*
> * The system has resumed successfully. Rewrite LR register stored
>* on stack with 'ep' value, so that on return from this PSCI call,
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 5/5] dts: stm32mp157c-odyssey: add phy-reset-gpios property to ethernet node
On 4/28/24 16:24, Heesub Shin wrote:
> In Odyssey board, we should reset the PHY chipset, toggling G0 pin.
>
> Signed-off-by: Heesub Shin
> ---
> arch/arm/dts/stm32mp157c-odyssey.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts
> b/arch/arm/dts/stm32mp157c-odyssey.dts
> index b6210cf8b2..4cc5e07683 100644
> --- a/arch/arm/dts/stm32mp157c-odyssey.dts
> +++ b/arch/arm/dts/stm32mp157c-odyssey.dts
> @@ -75,6 +75,7 @@
> phy-mode = "rgmii-id";
> max-speed = <1000>;
> phy-handle = <>;
> + phy-reset-gpios = < 0 GPIO_ACTIVE_LOW>;
> st,ext-phyclk;
>
> mdio0 {
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 4/5] net: dwc_eth_qos: add support for phy-reset-gpios property
On 4/28/24 16:24, Heesub Shin wrote:
> This commit adds support for a property 'phy-reset-gpios' to reset PHY
> chipset.
>
> Signed-off-by: Heesub Shin
> ---
> drivers/net/dwc_eth_qos_stm32.c | 23 ++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c
> index fbc08bba1d..cffaa10b70 100644
> --- a/drivers/net/dwc_eth_qos_stm32.c
> +++ b/drivers/net/dwc_eth_qos_stm32.c
> @@ -266,6 +266,12 @@ static int eqos_probe_resources_stm32(struct udevice
> *dev)
> if (ret)
> dev_warn(dev, "No phy clock provided %d\n", ret);
>
> + /* Get reset gpio pin (optional) */
> + ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
> +>phy_reset_gpio, GPIOD_IS_OUT);
> + if (ret)
> + pr_warn("No phy reset gpio provided: %d\n", ret);
> +
> dev_dbg(dev, "%s: OK\n", __func__);
>
> return 0;
> @@ -277,6 +283,21 @@ err_probe:
> return ret;
> }
>
> +static int eqos_start_resets_stm32(struct udevice *dev)
> +{
> + struct eqos_priv *eqos = dev_get_priv(dev);
> +
> + debug("%s(dev=%p):\n", __func__, dev);
> +
> + if (dm_gpio_is_valid(>phy_reset_gpio)) {
> + dm_gpio_set_value(>phy_reset_gpio, 1);
> + udelay(2);
> + dm_gpio_set_value(>phy_reset_gpio, 0);
> + }
> +
> + return 0;
> +}
> +
> static int eqos_remove_resources_stm32(struct udevice *dev)
> {
> dev_dbg(dev, "%s:\n", __func__);
> @@ -292,7 +313,7 @@ static struct eqos_ops eqos_stm32_ops = {
> .eqos_probe_resources = eqos_probe_resources_stm32,
> .eqos_remove_resources = eqos_remove_resources_stm32,
> .eqos_stop_resets = eqos_null_ops,
> - .eqos_start_resets = eqos_null_ops,
> + .eqos_start_resets = eqos_start_resets_stm32,
> .eqos_stop_clks = eqos_stop_clks_stm32,
> .eqos_start_clks = eqos_start_clks_stm32,
> .eqos_calibrate_pads = eqos_null_ops,
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 3/5] dts: stm32mp157c-odyssey: fix incorrect PHY address
On 4/28/24 16:24, Heesub Shin wrote:
> In Odyssey board, KSZ9031 is at the PHY address 0x7, not 0x0. This
> commit fixes it.
>
> Signed-off-by: Heesub Shin
> ---
> arch/arm/dts/stm32mp157c-odyssey.dts | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts
> b/arch/arm/dts/stm32mp157c-odyssey.dts
> index 53ba018197..b6210cf8b2 100644
> --- a/arch/arm/dts/stm32mp157c-odyssey.dts
> +++ b/arch/arm/dts/stm32mp157c-odyssey.dts
> @@ -81,8 +81,8 @@
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "snps,dwmac-mdio";
> - phy0: ethernet-phy@0 {
> - reg = <0>;
> + phy0: ethernet-phy@7 {
> + reg = <7>;
> };
> };
> };
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 2/5] dts: stm32mp157c-odyssey: use internal clock for Tx
On 4/28/24 16:24, Heesub Shin wrote:
> In Odyssey board, we should use the internal clock from RCC as the
> transmit clock, instead of the external clock from ETH_CLK125 pad. This
> commit adds a property, st,eth-clk-sel, so that the ETH_CLK_SEL mux
> selects ETH_CLK.
>
> Signed-off-by: Heesub Shin
> ---
> arch/arm/dts/stm32mp157c-odyssey.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts
> b/arch/arm/dts/stm32mp157c-odyssey.dts
> index 17bcf56f74..53ba018197 100644
> --- a/arch/arm/dts/stm32mp157c-odyssey.dts
> +++ b/arch/arm/dts/stm32mp157c-odyssey.dts
> @@ -75,6 +75,7 @@
> phy-mode = "rgmii-id";
> max-speed = <1000>;
> phy-handle = <>;
> + st,ext-phyclk;
>
> mdio0 {
> #address-cells = <1>;
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 1/5] dts: stm32mp157c-odyssey: set PLL4_P to 125Mhz for ETH_CLK
On 4/28/24 16:24, Heesub Shin wrote:
> Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to
> 125, 62.5 and 62.5Mhz in respectively.
>
> Signed-off-by: Heesub Shin
> ---
> arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
> b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
> index b780dbd95e..d07fdcf4bc 100644
> --- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
> @@ -115,11 +115,11 @@
> bootph-all;
> };
>
> - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
> + /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */
> pll4: st,pll@3 {
> compatible = "st,stm32mp1-pll";
> reg = <3>;
> - cfg = < 3 98 5 7 7 PQR(1,1,1) >;
> + cfg = < 3 124 5 9 9 PQR(1,1,1) >;
> bootph-all;
> };
> };
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH v2 1/2] ARM: dts: stm32: Add pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board
On 4/28/24 00:20, Marek Vasut wrote:
> Add new pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board.
> The following pinmux nodes are added:
> - ADC pins
> - ADC CC pins
> - ETH1 pins
> - ETH2 pins
> - I2C5 pins
> - MCAN1 pins
> - MCAN2 pins
> - PWM13 pins
> - PWM5 pins
> - QSPI pins
> - SAI1 pins
> - SDMMC2 D4..D7 pins
> - SPI2 pins
> - SPI3 pins
> - UART4 pins
> - UART7 pins
> - USART1 pins
> - USART2 pins
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> V2: Squash the pinmux patches into one megapatch
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 483
> 1 file changed, 483 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index 27e0c382678..c01d39f03ea 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -6,6 +6,12 @@
> #include
>
> {
> + adc1_pins_a: adc1-pins-0 {
> + pins {
> + pinmux = ; /* ADC1 in12 */
> + };
> + };
> +
> adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
> pins {
> pinmux = , /* ADC1 in6 */
> @@ -13,6 +19,104 @@
> };
> };
>
> + adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
> + pins {
> + pinmux = , /* ADC1_INP2 */
> + ; /* ADC1_INP11
> */
> + };
> + };
> +
> + eth1_rgmii_pins_a: eth1-rgmii-0 {
> + pins1 {
> + pinmux = , /*
> ETH_RGMII_TXD0 */
> + , /*
> ETH_RGMII_TXD1 */
> + , /*
> ETH_RGMII_TXD2 */
> + , /*
> ETH_RGMII_TXD3 */
> + , /*
> ETH_RGMII_TX_CTL */
> + , /*
> ETH_RGMII_GTX_CLK */
> + , /* ETH_MDIO */
> + ; /* ETH_MDC */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <2>;
> + };
> +
> + pins2 {
> + pinmux = , /*
> ETH_RGMII_RXD0 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RXD2 */
> + , /*
> ETH_RGMII_RXD3 */
> + , /*
> ETH_RGMII_RX_CTL */
> + ; /*
> ETH_RGMII_RX_CLK */
> + bias-disable;
> + };
> +
> + };
> +
> + eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
> + pins1 {
> + pinmux = , /*
> ETH_RGMII_TXD0 */
> + , /*
> ETH_RGMII_TXD1 */
> + , /*
> ETH_RGMII_TXD2 */
> + , /*
> ETH_RGMII_TXD3 */
> + , /*
> ETH_RGMII_TX_CTL */
> + , /*
> ETH_RGMII_GTX_CLK */
> + , /* ETH_MDIO */
> + , /* ETH_MDC */
> + , /*
> ETH_RGMII_RXD0 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RX_CTL */
> + ; /*
> ETH_RGMII_RX_CLK */
> + };
> + };
> +
> + eth2_rgmii_pins_a: eth2-rgmii-0 {
> + pins1 {
> + pinmux = , /*
> ETH_RGMII_TXD0 */
> + , /*
> ETH_RGMII_TXD1 */
> + , /*
> ETH_RGMII_TXD2 */
> + , /*
> ETH_RGMII_TXD3 */
> + , /*
> ETH_RGMII_TX_CTL */
> + , /*
> ETH_RGMII_GTX_CLK */
> + , /* ETH_MDIO */
> + ; /* ETH_MDC */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <2>;
> + };
> +
> + pins2 {
> + pinmux = , /*
> ETH_RGMII_RXD0 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RXD2 */
> +
Re: [PATCH 126/149] board: st: Remove and add needed includes
On 5/1/24 04:42, Tom Rini wrote: > Remove from this board vendor directory and when needed > add missing include files directly. > > Signed-off-by: Tom Rini > --- > Cc: Patrick Delaunay > Cc: Patrice Chotard > Cc: Kamil Lulko > Cc: Vikas Manocha > Cc: Dillon Min > --- > board/st/common/cmd_stboard.c| 1 - > board/st/common/stm32mp_dfu.c| 1 - > board/st/common/stm32mp_dfu_virt.c | 1 - > board/st/common/stpmic1.c| 1 - > board/st/common/stusb160x.c | 1 - > board/st/stih410-b2260/board.c | 1 - > board/st/stm32f429-discovery/led.c | 1 - > board/st/stm32f429-discovery/stm32f429-discovery.c | 1 - > board/st/stm32f429-evaluation/stm32f429-evaluation.c | 1 - > board/st/stm32f469-discovery/stm32f469-discovery.c | 1 - > board/st/stm32f746-disco/stm32f746-disco.c | 2 +- > board/st/stm32h743-disco/stm32h743-disco.c | 1 - > board/st/stm32h743-eval/stm32h743-eval.c | 1 - > board/st/stm32h750-art-pi/stm32h750-art-pi.c | 1 - > board/st/stm32mp1/spl.c | 1 - > board/st/stm32mp1/stm32mp1.c | 1 - > 16 files changed, 1 insertion(+), 16 deletions(-) > > diff --git a/board/st/common/cmd_stboard.c b/board/st/common/cmd_stboard.c > index c8c0bad5da16..50da063051b8 100644 > --- a/board/st/common/cmd_stboard.c > +++ b/board/st/common/cmd_stboard.c > @@ -30,7 +30,6 @@ > */ > > #ifndef CONFIG_SPL_BUILD > -#include > #include > #include > #include > diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c > index 77edb86e78c1..1db8e45480e1 100644 > --- a/board/st/common/stm32mp_dfu.c > +++ b/board/st/common/stm32mp_dfu.c > @@ -3,7 +3,6 @@ > * Copyright (C) 2020, STMicroelectronics - All Rights Reserved > */ > > -#include > #include > #include > #include > diff --git a/board/st/common/stm32mp_dfu_virt.c > b/board/st/common/stm32mp_dfu_virt.c > index f0f99605796a..4049d72bf9d5 100644 > --- a/board/st/common/stm32mp_dfu_virt.c > +++ b/board/st/common/stm32mp_dfu_virt.c > @@ -3,7 +3,6 @@ > * Copyright (C) 2023, STMicroelectronics - All Rights Reserved > */ > > -#include > #include > #include > #include > diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c > index 969ad484864d..45c2bb5bceac 100644 > --- a/board/st/common/stpmic1.c > +++ b/board/st/common/stpmic1.c > @@ -5,7 +5,6 @@ > > #define LOG_CATEGORY LOGC_BOARD > > -#include > #include > #include > #include > diff --git a/board/st/common/stusb160x.c b/board/st/common/stusb160x.c > index f0385e5e3830..e1ad8b00717a 100644 > --- a/board/st/common/stusb160x.c > +++ b/board/st/common/stusb160x.c > @@ -8,7 +8,6 @@ > > #define LOG_CATEGORY UCLASS_I2C_GENERIC > > -#include > #include > #include > > diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c > index 82817571ae3d..a912712c9dd9 100644 > --- a/board/st/stih410-b2260/board.c > +++ b/board/st/stih410-b2260/board.c > @@ -4,7 +4,6 @@ > * Author(s): Patrice Chotard, for > STMicroelectronics. > */ > > -#include > #include > #include > #include > diff --git a/board/st/stm32f429-discovery/led.c > b/board/st/stm32f429-discovery/led.c > index 8dda6a97bd1c..4b8038341b9e 100644 > --- a/board/st/stm32f429-discovery/led.c > +++ b/board/st/stm32f429-discovery/led.c > @@ -4,7 +4,6 @@ > * Kamil Lulko, > */ > > -#include > #include > #include > > diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c > b/board/st/stm32f429-discovery/stm32f429-discovery.c > index 55e464cc7cf1..22d751b44d3d 100644 > --- a/board/st/stm32f429-discovery/stm32f429-discovery.c > +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c > @@ -10,7 +10,6 @@ > * Kamil Lulko, > */ > > -#include > #include > #include > #include > diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c > b/board/st/stm32f429-evaluation/stm32f429-evaluation.c > index 25472f041fef..db59ebb838e7 100644 > --- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c > +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c > @@ -4,7 +4,6 @@ > * Author(s): Patrice Chotard, for > STMicroelectronics. > */ > > -#include > #include > #include > #include > diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c > b/board/st/stm32f469-discovery/stm32f469-discovery.c > index 9ed6c1e67680..134d207
Re: [PATCH] ARM: dts: stm32: Add generic SoM compatible to STM32MP15xx DH electronics DHSOM
On 5/17/24 01:47, Marek Vasut wrote:
> Add generic SoM compatible string into machine compatible string
> for all STM32MP15xx based DH electronics DHSOM. This way, common
> board code can match on this compatible. No functional change.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp15xx-dhcom-drc02.dts | 4 +++-
> arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts| 4 +++-
> arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts | 4 +++-
> arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 4 +++-
> arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts | 4 +++-
> arch/arm/dts/stm32mp15xx-dhcor-testbench.dts | 4 +++-
> 6 files changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
> b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
> index 1ef9ac29cea..90625bf6b60 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
> @@ -11,5 +11,7 @@
>
> / {
> model = "DH Electronics STM32MP15xx DHCOM DRC02";
> - compatible = "dh,stm32mp15xx-dhcom-drc02", "st,stm32mp1xx";
> + compatible = "dh,stm32mp15xx-dhcom-drc02",
> + "dh,stm32mp15xx-dhcom-som",
> + "st,stm32mp1xx";
> };
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
> b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
> index e2e01e2146c..b2e450aa13b 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
> @@ -11,5 +11,7 @@
>
> / {
> model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit
> (2)";
> - compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x";
> + compatible = "dh,stm32mp15xx-dhcom-pdk2",
> + "dh,stm32mp15xx-dhcom-som",
> + "st,stm32mp15x";
> };
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
> b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
> index 06770b47873..3e908102f61 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
> @@ -11,5 +11,7 @@
>
> / {
> model = "DH Electronics STM32MP15xx DHCOM PicoITX";
> - compatible = "dh,stm32mp15xx-dhcom-picoitx", "st,stm32mp1xx";
> + compatible = "dh,stm32mp15xx-dhcom-picoitx",
> + "dh,stm32mp15xx-dhcom-som",
> + "st,stm32mp1xx";
> };
> diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
> b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
> index 76ac5a873c1..dd8fcecbca5 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
> @@ -14,5 +14,7 @@
>
> / {
> model = "Arrow Electronics STM32MP15xx Avenger96 board";
> - compatible = "arrow,stm32mp15xx-avenger96", "st,stm32mp15x";
> + compatible = "arrow,stm32mp15xx-avenger96",
> + "dh,stm32mp15xx-dhcor-som",
> + "st,stm32mp15x";
> };
> diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
> b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
> index 77dd944ff53..c1f99c1685e 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
> @@ -12,5 +12,7 @@
>
> / {
> model = "DH electronics STM32MP15xx DHCOR DRC Compact";
> - compatible = "dh,stm32mp15xx-dhcor-drc-compact", "st,stm32mp1xx";
> + compatible = "dh,stm32mp15xx-dhcor-drc-compact",
> + "dh,stm32mp15xx-dhcor-som",
> + "st,stm32mp1xx";
> };
> diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
> b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
> index c9163e1c028..5fdd762ddbf 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
> @@ -9,7 +9,9 @@
>
> / {
> model = "DH electronics STM32MP15xx DHCOR Testbench";
> - compatible = "dh,stm32mp15xx-dhcor-testbench", "st,stm32mp1xx";
> + compatible = "dh,stm32mp15xx-dhcor-testbench",
> + "dh,stm32mp15xx-dhcor-som",
> + "st,stm32mp1xx";
>
> aliases {
> ethernet0 =
Reviewed-by: Patrice Chotard
Thanks
Re: [PATCH 19/19] ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board
On 4/22/24 01:17, Marek Vasut wrote:
> This stm32mp135f-dhcor-dhsbc board is a stack of DHCOR SoM based on
> STM32MP135F SoC (900MHz / crypto capabilities) populated on DHSBC
> carrier board.
>
> The SoM contains the following peripherals:
> - STPMIC (power delivery)
> - 512MB DDR3L memory
> - eMMC and SDIO WiFi module
>
> The DHSBC carrier board contains the following peripherals:
> - Two RGMII Ethernet ports
> - USB-A Host port, USB-C peripheral port, USB-C power supply plug
> - Expansion connector
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/Makefile | 1 +
> .../dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi | 25 ++
> arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts | 383 ++
> arch/arm/dts/stm32mp13xx-dhcor-som.dtsi | 308 ++
> arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi| 55 +++
> configs/stm32mp13_dhcor_defconfig | 148 +++
> 6 files changed, 920 insertions(+)
> create mode 100644 arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
> create mode 100644 arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
> create mode 100644 arch/arm/dts/stm32mp13xx-dhcor-som.dtsi
> create mode 100644 arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
> create mode 100644 configs/stm32mp13_dhcor_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index b1c9c6222e5..ca1e3bf3fc8 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1290,6 +1290,7 @@ dtb-$(CONFIG_ASPEED_AST2600) += \
> dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
>
> dtb-$(CONFIG_STM32MP13X) += \
> + stm32mp135f-dhcor-dhsbc.dtb \
> stm32mp135f-dk.dtb
>
> dtb-$(CONFIG_STM32MP15X) += \
> diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
> b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
> new file mode 100644
> index 000..d718aae16ca
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2024 Marek Vasut
> + */
> +
> +#include "stm32mp13xx-dhcor-u-boot.dtsi"
> +
> + {
> + bootph-all;
> +};
> +
> +_pins_b {
> + bootph-all;
> +
> + pins1 {
> + bootph-all;
> + };
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> + {
> + bootph-all;
> +};
> diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
> b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
> new file mode 100644
> index 000..fc1c48ad56d
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
> @@ -0,0 +1,383 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2024 Marek Vasut
> + *
> + * DHCOR STM32MP13 variant:
> + * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
> + * DHCOR PCB number: 718-100 or newer
> + * DHSBC PCB number: 719-100 or newer
> + */
> +
> +/dts-v1/;
> +
> +#include
> +#include "stm32mp135.dtsi"
> +#include "stm32mp13xf.dtsi"
> +#include "stm32mp13xx-dhcor-som.dtsi"
> +
> +/ {
> + model = "DH electronics STM32MP135F DHCOR DHSBC";
> + compatible = "dh,stm32mp135f-dhcor-dhsbc",
> + "dh,stm32mp135f-dhcor-som",
> + "st,stm32mp135";
> +
> + aliases {
> + ethernet0 =
> + ethernet1 =
> + serial2 =
> + serial3 =
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +_1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins_a _usb_cc_pins_b>;
> + vdda-supply = <_adc>;
> + vref-supply = <_adc>;
> + status = "okay";
> +
> + adc1: adc@0 {
> + status = "okay";
> +
> + /*
> + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11.
> + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
> + * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
> + * Use arbitrary margin here (e.g. 5us).
> + *
> + * The pinmux pins must be set as ANALOG, use datasheet
> + * DS13483 Table 7. STM32MP135C/F ball definitions to
> + * find out which 'pin name' maps to which 'additional
> + * functions', which lists the mapping between pin and
> + * ADC c
Re: [PATCH 18/19] ARM: dts: stm32: Add alternate pinmux for MP13 UART7 pins
On 4/22/24 01:17, Marek Vasut wrote:
> Add another mux option for UART7 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 41 +
> 1 file changed, 41 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index 7014c7a6d23..c01d39f03ea 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -647,6 +647,47 @@
> };
> };
>
> + uart7_pins_a: uart7-0 {
> + pins1 {
> + pinmux = , /* UART7_TX */
> + ; /* UART7_RTS */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <0>;
> + };
> + pins2 {
> + pinmux = , /* UART7_RX */
> + ; /* UART7_CTS_NSS
> */
> + bias-disable;
> + };
> + };
> +
> + uart7_idle_pins_a: uart7-idle-0 {
> + pins1 {
> + pinmux = , /* UART7_TX */
> + ; /*
> UART7_CTS_NSS */
> + };
> + pins2 {
> + pinmux = ; /* UART7_RTS */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <0>;
> + };
> + pins3 {
> + pinmux = ; /* UART7_RX */
> + bias-disable;
> + };
> + };
> +
> + uart7_sleep_pins_a: uart7-sleep-0 {
> + pins {
> + pinmux = , /* UART7_TX */
> + , /* UART7_RTS
> */
> + , /* UART7_RX */
> + ; /*
> UART7_CTS_NSS */
> + };
> + };
> +
> uart8_pins_a: uart8-0 {
> pins1 {
> pinmux = ; /* UART8_TX */
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 17/19] ARM: dts: stm32: Add alternate pinmux for MP13 UART4 pins
On 4/22/24 01:17, Marek Vasut wrote:
> Add another mux option for UART4 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 30 +
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index 65f91265a4d..7014c7a6d23 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -617,6 +617,36 @@
> };
> };
>
> + uart4_pins_b: uart4-1 {
> + pins1 {
> + pinmux = ; /* UART4_TX */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <0>;
> + };
> + pins2 {
> + pinmux = ; /* UART4_RX */
> + bias-pull-up;
> + };
> + };
> +
> + uart4_idle_pins_b: uart4-idle-1 {
> + pins1 {
> + pinmux = ; /* UART4_TX */
> + };
> + pins2 {
> + pinmux = ; /* UART4_RX */
> + bias-pull-up;
> + };
> + };
> +
> + uart4_sleep_pins_b: uart4-sleep-1 {
> + pins {
> + pinmux = , /* UART4_TX */
> + ; /* UART4_RX */
> + };
> + };
> +
> uart8_pins_a: uart8-0 {
> pins1 {
> pinmux = ; /* UART8_TX */
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 16/19] ARM: dts: stm32: Add alternate pinmux for MP13 USART2 pins
On 4/22/24 01:17, Marek Vasut wrote:
> Add another mux option for USART2 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 41 +
> 1 file changed, 41 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index dae015a0ddf..65f91265a4d 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -758,4 +758,45 @@
>; /*
> USART2_CTS_NSS */
> };
> };
> +
> + usart2_pins_b: usart2-0 {
> + pins1 {
> + pinmux = , /* USART2_TX */
> + ; /* USART2_RTS */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <0>;
> + };
> + pins2 {
> + pinmux = , /* USART2_RX */
> + ; /*
> USART2_CTS_NSS */
> + bias-disable;
> + };
> + };
> +
> + usart2_idle_pins_b: usart2-idle-0 {
> + pins1 {
> + pinmux = , /* USART2_TX
> */
> + ; /*
> USART2_CTS_NSS */
> + };
> + pins2 {
> + pinmux = ; /* USART2_RTS */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <0>;
> + };
> + pins3 {
> + pinmux = ; /* USART2_RX */
> + bias-disable;
> + };
> + };
> +
> + usart2_sleep_pins_b: usart2-sleep-0 {
> + pins {
> + pinmux = , /* USART2_TX
> */
> + , /* USART2_RTS
> */
> + , /* USART2_RX
> */
> + ; /*
> USART2_CTS_NSS */
> + };
> + };
> };
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 15/19] ARM: dts: stm32: Add alternate pinmux for MP13 USART1 pins
On 4/22/24 01:17, Marek Vasut wrote:
> Add another mux option for USART1 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 30 +
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index 7abd227e69f..dae015a0ddf 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -688,6 +688,36 @@
> };
> };
>
> + usart1_pins_b: usart1-1 {
> + pins1 {
> + pinmux = ; /* USART1_TX */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <0>;
> + };
> + pins2 {
> + pinmux = ; /* USART1_RX */
> + bias-pull-up;
> + };
> + };
> +
> + usart1_idle_pins_b: usart1-idle-1 {
> + pins1 {
> + pinmux = ; /* USART1_TX */
> + };
> + pins2 {
> + pinmux = ; /* USART1_RX */
> + bias-pull-up;
> + };
> + };
> +
> + usart1_sleep_pins_b: usart1-sleep-1 {
> + pins {
> + pinmux = , /* USART1_TX */
> + ; /* USART1_RX
> */
> + };
> + };
> +
> usart2_pins_a: usart2-0 {
> pins1 {
> pinmux = , /* USART2_TX */
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 14/19] ARM: dts: stm32: Add alternate pinmux for MP13 SPI3 pins
On 4/22/24 01:17, Marek Vasut wrote:
> Add another mux option for SPI3 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 23 +++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index 17acd2850d3..7abd227e69f 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -534,6 +534,29 @@
> };
> };
>
> + spi3_pins_a: spi3-0 {
> + pins1 {
> + pinmux = , /* SPI3_SCK */
> + ; /* SPI3_MOSI */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <1>;
> + };
> +
> + pins2 {
> + pinmux = ; /* SPI3_MISO */
> + bias-disable;
> + };
> + };
> +
> + spi3_sleep_pins_a: spi3-sleep-0 {
> + pins {
> + pinmux = , /* SPI3_SCK */
> + , /* SPI3_MISO */
> + ; /* SPI3_MOSI */
> + };
> + };
> +
> spi5_pins_a: spi5-0 {
> pins1 {
> pinmux = , /* SPI5_SCK */
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 13/19] ARM: dts: stm32: Add alternate pinmux for MP13 SPI2 pins
On 4/22/24 01:16, Marek Vasut wrote:
> Add another mux option for SPI2 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 23 +++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index c6967e82b5d..17acd2850d3 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -511,6 +511,29 @@
> };
> };
>
> + spi2_pins_a: spi2-0 {
> + pins1 {
> + pinmux = , /* SPI2_SCK */
> + ; /* SPI2_MOSI */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <1>;
> + };
> +
> + pins2 {
> + pinmux = ; /* SPI2_MISO */
> + bias-disable;
> + };
> + };
> +
> + spi2_sleep_pins_a: spi2-sleep-0 {
> + pins {
> + pinmux = , /* SPI2_SCK */
> + , /* SPI2_MISO */
> + ; /* SPI2_MOSI
> */
> + };
> + };
> +
> spi5_pins_a: spi5-0 {
> pins1 {
> pinmux = , /* SPI5_SCK */
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 12/19] ARM: dts: stm32: Add alternate pinmux for MP13 SDMMC2 D4..D7 pins
On 4/22/24 01:16, Marek Vasut wrote:
> Add another mux option for SDMMC2 D4..D7 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index f2b41104a58..c6967e82b5d 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -490,6 +490,27 @@
> };
> };
>
> + sdmmc2_d47_pins_a: sdmmc2-d47-0 {
> + pins {
> + pinmux = , /* SDMMC2_D4 */
> + , /* SDMMC2_D5 */
> + , /* SDMMC2_D6 */
> + ; /* SDMMC2_D7 */
> + slew-rate = <1>;
> + drive-push-pull;
> + bias-pull-up;
> + };
> + };
> +
> + sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
> + pins {
> + pinmux = , /* SDMMC2_D4 */
> + , /* SDMMC2_D5 */
> + , /* SDMMC2_D6 */
> + ; /* SDMMC2_D7 */
> + };
> + };
> +
> spi5_pins_a: spi5-0 {
> pins1 {
> pinmux = , /* SPI5_SCK */
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 11/19] ARM: dts: stm32: Add alternate pinmux for MP13 SAI1 pins
On 4/22/24 01:16, Marek Vasut wrote:
> Add another mux option for SAI1 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 32 +
> 1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index 77a222903de..f2b41104a58 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -356,6 +356,38 @@
> };
> };
>
> + sai1a_pins_a: sai1a-0 {
> + pins {
> + pinmux = , /* SAI1_SCK_A */
> + , /* SAI1_SD_A */
> + ; /* SAI1_FS_A */
> + slew-rate = <0>;
> + drive-push-pull;
> + bias-disable;
> + };
> + };
> +
> + sai1a_sleep_pins_a: sai1a-sleep-0 {
> + pins {
> + pinmux = , /* SAI1_SCK_A
> */
> + , /* SAI1_SD_A */
> + ; /* SAI1_FS_A
> */
> + };
> + };
> +
> + sai1b_pins_a: sai1b-0 {
> + pins {
> + pinmux = ; /* SAI1_SD_B */
> + bias-disable;
> + };
> + };
> +
> + sai1b_sleep_pins_a: sai1b-sleep-0 {
> + pins {
> + pinmux = ; /* SAI1_SD_B */
> + };
> + };
> +
> sdmmc1_b4_pins_a: sdmmc1-b4-0 {
> pins {
> pinmux = , /* SDMMC1_D0 */
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 10/19] ARM: dts: stm32: Add alternate pinmux for MP13 QSPI pins
On 4/22/24 01:16, Marek Vasut wrote:
> Add another mux option for QSPI pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 51 +
> 1 file changed, 51 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index cf070fbd7f7..77a222903de 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -305,6 +305,57 @@
> };
> };
>
> + qspi_clk_pins_a: qspi-clk-0 {
> + pins {
> + pinmux = ; /* QSPI_CLK */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <3>;
> + };
> + };
> +
> + qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
> + pins {
> + pinmux = ; /* QSPI_CLK */
> + };
> + };
> +
> + qspi_bk1_pins_a: qspi-bk1-0 {
> + pins {
> + pinmux = , /* QSPI_BK1_IO0
> */
> + , /* QSPI_BK1_IO1
> */
> + , /* QSPI_BK1_IO2
> */
> + ; /* QSPI_BK1_IO3
> */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <1>;
> + };
> + };
> +
> + qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
> + pins {
> + pinmux = , /*
> QSPI_BK1_IO0 */
> + , /*
> QSPI_BK1_IO1 */
> + , /*
> QSPI_BK1_IO2 */
> + ; /*
> QSPI_BK1_IO3 */
> + };
> + };
> +
> + qspi_cs1_pins_a: qspi-cs1-0 {
> + pins {
> + pinmux = ; /* QSPI_BK1_NCS */
> + bias-pull-up;
> + drive-push-pull;
> + slew-rate = <1>;
> + };
> + };
> +
> + qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
> + pins {
> + pinmux = ; /*
> QSPI_BK1_NCS */
> + };
> + };
> +
> sdmmc1_b4_pins_a: sdmmc1-b4-0 {
> pins {
> pinmux = , /* SDMMC1_D0 */
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 09/19] ARM: dts: stm32: Add alternate pinmux for MP13 PWM13 pins
On 4/22/24 01:16, Marek Vasut wrote:
> Add another mux option for PWM13 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index d19408f19f9..cf070fbd7f7 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -275,6 +275,21 @@
> };
> };
>
> + pwm13_pins_a: pwm13-0 {
> + pins {
> + pinmux = ; /* TIM13_CH1 */
> + bias-pull-down;
> + drive-push-pull;
> + slew-rate = <0>;
> + };
> + };
> +
> + pwm13_sleep_pins_a: pwm13-sleep-0 {
> + pins {
> + pinmux = ; /* TIM13_CH1 */
> + };
> + };
> +
> pwm14_pins_a: pwm14-0 {
> pins {
> pinmux = ; /* TIM14_CH1 */
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 08/19] ARM: dts: stm32: Add alternate pinmux for MP13 PWM5 pins
On 4/22/24 01:16, Marek Vasut wrote:
> Add another mux option for PWM5 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index b58bf6c0024..d19408f19f9 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -245,6 +245,21 @@
> };
> };
>
> + pwm5_pins_a: pwm5-0 {
> + pins {
> + pinmux = ; /* TIM5_CH3 */
> + bias-pull-down;
> + drive-push-pull;
> + slew-rate = <0>;
> + };
> + };
> +
> + pwm5_sleep_pins_a: pwm5-sleep-0 {
> + pins {
> + pinmux = ; /* TIM5_CH3 */
> + };
> + };
> +
> pwm8_pins_a: pwm8-0 {
> pins {
> pinmux = ; /* TIM8_CH3 */
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 07/19] ARM: dts: stm32: Add alternate pinmux for MP13 MCAN2 pins
On 4/22/24 01:16, Marek Vasut wrote:
> Add another mux option for MCAN2 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 20
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index b38174504ff..b58bf6c0024 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -188,6 +188,26 @@
> };
> };
>
> + m_can2_pins_a: m-can2-0 {
> + pins1 {
> + pinmux = ; /* CAN2_TX */
> + slew-rate = <1>;
> + drive-push-pull;
> + bias-disable;
> + };
> + pins2 {
> + pinmux = ; /* CAN2_RX */
> + bias-disable;
> + };
> + };
> +
> + m_can2_sleep_pins_a: m_can2-sleep-0 {
> + pins {
> + pinmux = , /* CAN2_TX */
> + ; /* CAN2_RX */
> + };
> + };
> +
> mcp23017_pins_a: mcp23017-0 {
> pins {
> pinmux = ;
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 06/19] ARM: dts: stm32: Add alternate pinmux for MP13 MCAN1 pins
On 4/22/24 01:16, Marek Vasut wrote:
> Add another mux option for MCAN1 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 20
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index cfbae71efc7..b38174504ff 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -168,6 +168,26 @@
> };
> };
>
> + m_can1_pins_a: m-can1-0 {
> + pins1 {
> + pinmux = ; /* CAN1_TX */
> + slew-rate = <1>;
> + drive-push-pull;
> + bias-disable;
> + };
> + pins2 {
> + pinmux = ; /* CAN1_RX */
> + bias-disable;
> + };
> + };
> +
> + m_can1_sleep_pins_a: m_can1-sleep-0 {
> + pins {
> + pinmux = , /* CAN1_TX */
> + ; /* CAN1_RX */
> + };
> + };
> +
> mcp23017_pins_a: mcp23017-0 {
> pins {
> pinmux = ;
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 05/19] ARM: dts: stm32: Add alternate pinmux for MP13 I2C5 pins
On 4/22/24 01:16, Marek Vasut wrote:
> Add another mux option for I2C5 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index 899f0f98e1a..cfbae71efc7 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -151,6 +151,23 @@
> };
> };
>
> + i2c5_pins_b: i2c5-1 {
> + pins {
> + pinmux = , /* I2C5_SCL */
> + ; /* I2C5_SDA */
> + bias-disable;
> + drive-open-drain;
> + slew-rate = <0>;
> + };
> + };
> +
> + i2c5_sleep_pins_b: i2c5-sleep-1 {
> + pins {
> + pinmux = , /* I2C5_SCL */
> + ; /* I2C5_SDA */
> + };
> + };
> +
> mcp23017_pins_a: mcp23017-0 {
> pins {
> pinmux = ;
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 04/19] ARM: dts: stm32: Add alternate pinmux for MP13 ETH2 pins
On 4/22/24 01:16, Marek Vasut wrote:
> Add another mux option for ETH2 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 45 +
> 1 file changed, 45 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index c709d64edcc..899f0f98e1a 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -72,6 +72,51 @@
> };
> };
>
> + eth2_rgmii_pins_a: eth2-rgmii-0 {
> + pins1 {
> + pinmux = , /*
> ETH_RGMII_TXD0 */
> + , /*
> ETH_RGMII_TXD1 */
> + , /*
> ETH_RGMII_TXD2 */
> + , /*
> ETH_RGMII_TXD3 */
> + , /*
> ETH_RGMII_TX_CTL */
> + , /*
> ETH_RGMII_GTX_CLK */
> + , /* ETH_MDIO */
> + ; /* ETH_MDC */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <2>;
> + };
> +
> + pins2 {
> + pinmux = , /*
> ETH_RGMII_RXD0 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RXD2 */
> + , /*
> ETH_RGMII_RXD3 */
> + , /*
> ETH_RGMII_RX_CTL */
> + ; /*
> ETH_RGMII_RX_CLK */
> + bias-disable;
> + };
> + };
> +
> + eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
> + pins1 {
> + pinmux = , /*
> ETH_RGMII_TXD0 */
> + , /*
> ETH_RGMII_TXD1 */
> + , /*
> ETH_RGMII_TXD2 */
> + , /*
> ETH_RGMII_TXD3 */
> + , /*
> ETH_RGMII_TX_CTL */
> + , /*
> ETH_RGMII_GTX_CLK */
> + , /* ETH_MDIO */
> + , /* ETH_MDC */
> + , /*
> ETH_RGMII_RXD0 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RXD2 */
> + , /*
> ETH_RGMII_RXD3 */
> + , /*
> ETH_RGMII_RX_CTL */
> + ; /*
> ETH_RGMII_RX_CLK */
> + };
> + };
> +
> i2c1_pins_a: i2c1-0 {
> pins {
> pinmux = , /* I2C1_SCL */
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 03/19] ARM: dts: stm32: Add alternate pinmux for MP13 ETH1 pins
On 4/22/24 01:16, Marek Vasut wrote:
> Add another mux option for ETH1 pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 46 +
> 1 file changed, 46 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index 396fb6eee84..c709d64edcc 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -26,6 +26,52 @@
> };
> };
>
> + eth1_rgmii_pins_a: eth1-rgmii-0 {
> + pins1 {
> + pinmux = , /*
> ETH_RGMII_TXD0 */
> + , /*
> ETH_RGMII_TXD1 */
> + , /*
> ETH_RGMII_TXD2 */
> + , /*
> ETH_RGMII_TXD3 */
> + , /*
> ETH_RGMII_TX_CTL */
> + , /*
> ETH_RGMII_GTX_CLK */
> + , /* ETH_MDIO */
> + ; /* ETH_MDC */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <2>;
> + };
> +
> + pins2 {
> + pinmux = , /*
> ETH_RGMII_RXD0 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RXD2 */
> + , /*
> ETH_RGMII_RXD3 */
> + , /*
> ETH_RGMII_RX_CTL */
> + ; /*
> ETH_RGMII_RX_CLK */
> + bias-disable;
> + };
> +
> + };
> +
> + eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
> + pins1 {
> + pinmux = , /*
> ETH_RGMII_TXD0 */
> + , /*
> ETH_RGMII_TXD1 */
> + , /*
> ETH_RGMII_TXD2 */
> + , /*
> ETH_RGMII_TXD3 */
> + , /*
> ETH_RGMII_TX_CTL */
> + , /*
> ETH_RGMII_GTX_CLK */
> + , /* ETH_MDIO */
> + , /* ETH_MDC */
> + , /*
> ETH_RGMII_RXD0 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RXD1 */
> + , /*
> ETH_RGMII_RX_CTL */
> + ; /*
> ETH_RGMII_RX_CLK */
> + };
> + };
> +
> i2c1_pins_a: i2c1-0 {
> pins {
> pinmux = , /* I2C1_SCL */
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 02/19] ARM: dts: stm32: Add alternate pinmux for MP13 ADC CC pins
On 4/22/24 01:16, Marek Vasut wrote:
> Add another mux option for ADC CC pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index 03ded415390..396fb6eee84 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -19,6 +19,13 @@
> };
> };
>
> + adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
> + pins {
> + pinmux = , /* ADC1_INP2 */
> + ; /* ADC1_INP11
> */
> + };
> + };
> +
> i2c1_pins_a: i2c1-0 {
> pins {
> pinmux = , /* I2C1_SCL */
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 01/19] ARM: dts: stm32: Add alternate pinmux for MP13 ADC pins
On 4/22/24 01:16, Marek Vasut wrote:
> Add another mux option for ADC pins, this is used on
> DH electronics STM32MP13xx DHCOR DHSBC board.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp13-pinctrl.dtsi | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> index 27e0c382678..03ded415390 100644
> --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
> @@ -6,6 +6,12 @@
> #include
>
> {
> + adc1_pins_a: adc1-pins-0 {
> + pins {
> + pinmux = ; /* ADC1 in12 */
> + };
> + };
> +
> adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
> pins {
> pinmux = , /* ADC1 in6 */
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH] ARM: dts: stm32: add eth1 and eth2 support on stm32mp13
On 4/22/24 01:09, Marek Vasut wrote:
> From: Christophe Roullier
>
> Add both ethernet MACs based on GMAC SNPS IP on stm32mp13.
>
> Signed-off-by: Christophe Roullier
> ---
> Cc: Christophe Roullier
> Cc: Joe Hershberger
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Ramon Fried
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp131.dtsi | 37
> arch/arm/dts/stm32mp133.dtsi | 30 +
> 2 files changed, 67 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
> index 159ba8f8c9c..ad331b73d18 100644
> --- a/arch/arm/dts/stm32mp131.dtsi
> +++ b/arch/arm/dts/stm32mp131.dtsi
> @@ -1328,6 +1328,37 @@
> status = "disabled";
> };
>
> + eth1: eth1@5800a000 {
> + compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
> + reg = <0x5800a000 0x2000>;
> + reg-names = "stmmaceth";
> + interrupts-extended = < GIC_SPI 62
> IRQ_TYPE_LEVEL_HIGH>,
> + < 68 1>;
> + interrupt-names = "macirq", "eth_wake_irq";
> + clock-names = "stmmaceth",
> + "mac-clk-tx",
> + "mac-clk-rx",
> + "ethstp",
> + "eth-ck";
> + clocks = < ETH1MAC>,
> + < ETH1TX>,
> + < ETH1RX>,
> + < ETH1STP>,
> + < ETH1CK_K>;
> + st,syscon = < 0x4 0xff>;
> + snps,mixed-burst;
> + snps,pbl = <2>;
> + snps,axi-config = <_axi_config_1>;
> + snps,tso;
> + status = "disabled";
> +
> + stmmac_axi_config_1: stmmac-axi-config {
> + snps,wr_osr_lmt = <0x7>;
> + snps,rd_osr_lmt = <0x7>;
> + snps,blen = <0 0 0 0 16 8 4>;
> + };
> + };
> +
> usbh_ohci: usb@5800c000 {
> compatible = "generic-ohci";
> reg = <0x5800c000 0x1000>;
> @@ -1404,6 +1435,12 @@
> ts_cal2: calib@5e {
> reg = <0x5e 0x2>;
> };
> + ethernet_mac1_address: mac1@e4 {
> + reg = <0xe4 0x6>;
> + };
> + ethernet_mac2_address: mac2@ea {
> + reg = <0xea 0x6>;
> + };
> };
>
> /*
> diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi
> index df451c3c2a2..5cd5bde9535 100644
> --- a/arch/arm/dts/stm32mp133.dtsi
> +++ b/arch/arm/dts/stm32mp133.dtsi
> @@ -64,5 +64,35 @@
> };
> };
> };
> +
> + eth2: eth2@5800e000 {
> + compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
> + reg = <0x5800e000 0x2000>;
> + reg-names = "stmmaceth";
> + interrupts-extended = < GIC_SPI 97
> IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + clock-names = "stmmaceth",
> + "mac-clk-tx",
> + "mac-clk-rx",
> + "ethstp",
> + "eth-ck";
> + clocks = < ETH2MAC>,
> + < ETH2TX>,
> + < ETH2RX>,
> + < ETH2STP>,
> + < ETH2CK_K>;
> + st,syscon = < 0x4 0xff00>;
> + snps,mixed-burst;
> + snps,pbl = <2>;
> + snps,axi-config = <_axi_config_2>;
> + snps,tso;
> + status = "disabled";
> +
> + stmmac_axi_config_2: stmmac-axi-config {
> + snps,wr_osr_lmt = <0x7>;
> + snps,rd_osr_lmt = <0x7>;
> + snps,blen = <0 0 0 0 16 8 4>;
> + };
> + };
> };
> };
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 2/2] ARM: stm32: Make PWR regulator driver available on STM32MP13xx
On 3/19/24 03:45, Marek Vasut wrote: > This patch makes STM32 PWR regulators available on stm32mp13xx. > This requires TFA to clear RCC_SECCFGR, is disabled by default > on stm32mp13xx and can only be enabled on board config level. > > Signed-off-by: Marek Vasut > --- > Cc: Patrice Chotard > Cc: Patrick Delaunay > Cc: Tom Rini > Cc: u-b...@dh-electronics.com > Cc: u-boot@lists.denx.de > Cc: uboot-st...@st-md-mailman.stormreply.com > --- > arch/arm/mach-stm32mp/Kconfig | 17 + > arch/arm/mach-stm32mp/Kconfig.15x | 16 > 2 files changed, 17 insertions(+), 16 deletions(-) > > diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig > index b9af03d57e3..d5934a92771 100644 > --- a/arch/arm/mach-stm32mp/Kconfig > +++ b/arch/arm/mach-stm32mp/Kconfig > @@ -155,4 +155,21 @@ source "arch/arm/mach-stm32mp/Kconfig.13x" > source "arch/arm/mach-stm32mp/Kconfig.15x" > source "arch/arm/mach-stm32mp/Kconfig.25x" > source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" > + > +config STM32MP15_PWR > + bool "Enable driver for STM32MP15x PWR" > + depends on DM_REGULATOR && DM_PMIC && (STM32MP13X || STM32MP15X) > + default y if STM32MP15X > + help > + This config enables implementation of driver-model pmic and > + regulator uclass features for access to STM32MP15x PWR. > + > +config SPL_STM32MP15_PWR > + bool "Enable driver for STM32MP15x PWR in SPL" > + depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC && (STM32MP13X || > STM32MP15X) > + default y if STM32MP15X > + help > + This config enables implementation of driver-model pmic and > + regulator uclass features for access to STM32MP15x PWR in SPL. > + > endif > diff --git a/arch/arm/mach-stm32mp/Kconfig.15x > b/arch/arm/mach-stm32mp/Kconfig.15x > index 71c14eb4955..d99aa9fd694 100644 > --- a/arch/arm/mach-stm32mp/Kconfig.15x > +++ b/arch/arm/mach-stm32mp/Kconfig.15x > @@ -77,22 +77,6 @@ config TARGET_ICORE_STM32MP1 > > endchoice > > -config STM32MP15_PWR > - bool "Enable driver for STM32MP15x PWR" > - depends on DM_REGULATOR && DM_PMIC > - default y > - help > - This config enables implementation of driver-model pmic and > - regulator uclass features for access to STM32MP15x PWR. > - > -config SPL_STM32MP15_PWR > - bool "Enable driver for STM32MP15x PWR in SPL" > - depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC > - default y > - help > - This config enables implementation of driver-model pmic and > - regulator uclass features for access to STM32MP15x PWR in SPL. > - > config TEXT_BASE > default 0xC010 > Reviewed-by: Patrice Chotard Thanks Patrice
Re: [PATCH 1/2] ARM: dts: stm32: add PWR regulators support on stm32mp131
On 3/19/24 03:45, Marek Vasut wrote:
> This patch adds STM32 PWR regulators DT support on stm32mp131.
> This requires TFA to clear RCC_SECCFGR, is disabled by default
> and can only be enabled on board DT level.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/dts/stm32mp131.dtsi | 24
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
> index 81d99a7582b..ad331b73d18 100644
> --- a/arch/arm/dts/stm32mp131.dtsi
> +++ b/arch/arm/dts/stm32mp131.dtsi
> @@ -1092,6 +1092,30 @@
><_clk CK_SCMI_LSI>;
> };
>
> + pwr_regulators: pwr@50001000 {
> + compatible = "st,stm32mp1,pwr-reg";
> + reg = <0x50001000 0x10>;
> + status = "disabled";
> +
> + reg11: reg11 {
> + regulator-name = "reg11";
> + regulator-min-microvolt = <110>;
> + regulator-max-microvolt = <110>;
> + };
> +
> + reg18: reg18 {
> + regulator-name = "reg18";
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <180>;
> + };
> +
> + usb33: usb33 {
> + regulator-name = "usb33";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + };
> + };
> +
> exti: interrupt-controller@5000d000 {
> compatible = "st,stm32mp13-exti", "syscon";
> interrupt-controller;
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 1/2] ARM: dts: stm32: add PWR regulators support on stm32mp131
On 4/21/24 22:27, Marek Vasut wrote: > On 3/19/24 3:45 AM, Marek Vasut wrote: >> This patch adds STM32 PWR regulators DT support on stm32mp131. >> This requires TFA to clear RCC_SECCFGR, is disabled by default >> and can only be enabled on board DT level. >> >> Signed-off-by: Marek Vasut > > It seems these patches have been missed from the recent PR ? > > Is there any feedback on those patches ? Hi Marek Yes, these patches was voluntary suspended on our side due to internal discussion. On my side these patches are ok. They will be part on next STM32 pull request. Thanks Patrice
[PATCH v2] stm32mp: Reserve OPTEE area in EFI memory map
Since commit 7b78d6438a2b3 ("efi_loader: Reserve unaccessible memory")
memory region above ram_top is tagged in EFI memory map as
EFI_BOOT_SERVICES_DATA.
In case of STM32MP1/STM32MP13 platforms, above ram_top, there is one
reserved-memory region tagged "no-map" dedicated to OP-TEE :
_ addr=de00 size=200 for stm32mp157x-dkx and stm32mp135f-dk
_ addr=fe00 size=200 for stm32mp157c-ev1
Before booting kernel, EFI memory map is first built, the OPTEE region is
tagged as EFI_BOOT_SERVICES_DATA and when reserving LMB, the tag LMB_NONE
is used.
Then after, the LMB are completed by boot_fdt_add_mem_rsv_regions()
which try to add again the same OPTEE region (addr=de00 size=200
in case of stm32mp157x-dkx / stm32mp135f-dk or addr=fe00 size=200
in case for stm2mp157c-ev1)
but now with LMB_NOMAP tag which produces the following error message :
_ for stm32mp157x-dkx / stm32mp135f-dk :
"ERROR: reserving fdt memory region failed (addr=de00 size=200
flags=4)"
_ for stm32mp157c-ev1 :
"ERROR: reserving fdt memory region failed (addr=fe00 size=200
flags=4)"
To avoid this, OPTEE area shouldn't be used by EFI, so we need to mark
it as reserved.
Signed-off-by: Patrice Chotard
---
Changes in v2:
_ update commit message by adding information about memory area
dedicated for OPTEE for various STM32MP1/STM32MP13 boards.
arch/arm/mach-stm32mp/dram_init.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-stm32mp/dram_init.c
b/arch/arm/mach-stm32mp/dram_init.c
index fb1208fc5d5..f67f54f2ae0 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -7,6 +7,7 @@
#include
#include
+#include
#include
#include
#include
@@ -75,3 +76,14 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
return reg + size;
}
+
+void efi_add_known_memory(void)
+{
+ if (IS_ENABLED(CONFIG_EFI_LOADER))
+ /*
+* Memory over ram_top is reserved to OPTEE.
+* Declare to EFI only memory area below ram_top
+*/
+ efi_add_memory_map(gd->ram_base, gd->ram_top - gd->ram_base,
+ EFI_CONVENTIONAL_MEMORY);
+}
--
2.25.1
Re: [Uboot-stm32] [PATCH] stm32mp: Reserve OPTEE area in EFI memory map
On 4/19/24 09:44, Patrice CHOTARD wrote:
>
>
> On 4/17/24 09:45, Heinrich Schuchardt wrote:
>> On 17.04.24 09:25, Patrick DELAUNAY wrote:
>>> Hi,
>>>
>>> On 3/8/24 11:12, Patrice Chotard wrote:
>>>> Since commit 7b78d6438a2b3 ("efi_loader: Reserve unaccessible memory")
>>>> memory region above ram_top is tagged in EFI memory map as
>>>> EFI_BOOT_SERVICES_DATA.
>>>> In case of STM32MP1 platform, above ram_top, there is one reserved-memory
>>>> region tagged "no-map" dedicated to OP-TEE (addr=de00 size=200).
>>>>
>>>> Before booting kernel, EFI memory map is first built, the OPTEE region is
>>>> tagged as EFI_BOOT_SERVICES_DATA and when reserving LMB, the tag LMB_NONE
>>>> is used.
>>>>
>>>> Then after, the LMB are completed by boot_fdt_add_mem_rsv_regions()
>>>> which try to add again the same OPTEE region (addr=de00 size=200)
>>>> but now with LMB_NOMAP tag which produces the following error message :
>>>>
>>>> "ERROR: reserving fdt memory region failed (addr=de00 size=200
>>>> flags=4)"
>>>>
>>>> To avoid this, OPTEE area shouldn't be used by EFI, so we need to mark
>>>> it as reserved.
>>>>
>>>> Signed-off-by: Patrice Chotard
>>>> ---
>>>>
>>>> arch/arm/mach-stm32mp/dram_init.c | 12
>>>> 1 file changed, 12 insertions(+)
>>>>
>>>> diff --git a/arch/arm/mach-stm32mp/dram_init.c
>>>> b/arch/arm/mach-stm32mp/dram_init.c
>>>> index fb1208fc5d5..f67f54f2ae0 100644
>>>> --- a/arch/arm/mach-stm32mp/dram_init.c
>>>> +++ b/arch/arm/mach-stm32mp/dram_init.c
>>>> @@ -7,6 +7,7 @@
>>>> #include
>>>> #include
>>>> +#include
>>>> #include
>>>> #include
>>>> #include
>>>> @@ -75,3 +76,14 @@ phys_addr_t board_get_usable_ram_top(phys_size_t
>>>> total_size)
>>>> return reg + size;
>>>> }
>>>> +
>>>> +void efi_add_known_memory(void)
>>>> +{
>>>> + if (IS_ENABLED(CONFIG_EFI_LOADER))
>>>> + /*
>>>> + * Memory over ram_top is reserved to OPTEE.
>>>> + * Declare to EFI only memory area below ram_top
>>>> + */
>>>> + efi_add_memory_map(gd->ram_base, gd->ram_top - gd->ram_base,
>>>> + EFI_CONVENTIONAL_MEMORY);
>>
>> With this change the EFI memory map passed to the operating system will
>> not contain any memory above gd->ram_top. Is this really your intent?
>> Don't you have any memory above 0xe000?
>
> Hi Heinrich
>
> On stm32mp157x-dk and stm32mp135x-dk boards, there is no memory above
> 0xe000.
> But, on stm32mp157x-ed1 or stm32mp157x-ev1, you are right, we got memory
> above 0xe000.
>
> I will rework this patch to take into account memory that could be present
> above OPTEE area.
After double checking, this patch is correct but i need to update the commit
message.
In fact for stm32mp157x-dk and stm32mp135x-dk boards, there is 512MB of memory
(0xc000 0x2000),
OPTEE is located at the end of memory : 0xde00 0x0200
But for stm32mp157c-ev1, there is 1GB of memory (0xC000 0x4000), and
identically,
OPTEE is located at the end of memory : 0xfe00 0x200
So in both cases, above OPTEE reserved-memory area, there is no more free
memory.
Thanks
Patrice
>
> Thanks for pointing this
> Patrice
>
>>
>> Best regards
>>
>> Heinrich
>>
>>>> +}
>>>
>>>
>>>
>>> Reviewed-by: Patrick Delaunay
>>>
>>> Thanks
>>> Patrick
>>>
>>
> ___
> Uboot-stm32 mailing list
> uboot-st...@st-md-mailman.stormreply.com
> https://st-md-mailman.stormreply.com/mailman/listinfo/uboot-stm32
Re: [PATCH 3/3] ARM: dts: stm32: Fix partition node name for stm32mp15xx-dhcom-u-boot
On 4/17/24 11:00, Patrick DELAUNAY wrote:
> Hi,
>
> On 3/8/24 14:50, Patrice Chotard wrote:
>> Fix flash@0 partition node name with correct offset.
>>
>> Fixes: 90f992e6a58c ("arm: dts: stm32: Add partitions in flash0 and nand
>> node for stm32mp15xx-dhcom/dhcor")
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
>> b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
>> index 2f70b0690d2..1b445619325 100644
>> --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
>> +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
>> @@ -106,15 +106,15 @@
>> label = "fsbl2";
>> reg = <0x0004 0x0004>;
>> };
>> - partition@50 {
>> + partition@8 {
>> label = "uboot";
>> reg = <0x0008 0x0016>;
>> };
>> - partition@90 {
>> + partition@1e {
>> label = "env1";
>> reg = <0x001E 0x0001>;
>> };
>> - partition@98 {
>> + partition@1f {
>> label = "env2";
>> reg = <0x001F 0x0001>;
>> };
>
>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
Applied on u-boot-stm32/master
Re: [PATCH 1/3] ARM: dts: stm32: Fix partition node name for stm32mp157c-ev1-u-boot
On 4/17/24 10:59, Patrick DELAUNAY wrote:
> Hi,
>
> On 3/8/24 14:50, Patrice Chotard wrote:
>> Fix flash@0 and nand@0 partition node name with correct offset.
>>
>> Fixes: e91d3c61767b ("arm: dts: stm32: Add partitions in flash0 and nand
>> node for stm32mp15xx-ev1")
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 8
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
>> b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
>> index 139940bd5d4..3515347e91d 100644
>> --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
>> +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
>> @@ -33,11 +33,11 @@
>> label = "fsbl1";
>> reg = <0x 0x0004>;
>> };
>> - partition@8 {
>> + partition@4 {
>> label = "fsbl2";
>> reg = <0x0004 0x0004>;
>> };
>> - partition@10 {
>> + partition@8 {
>> label = "ssbl";
>> reg = <0x0008 0x0020>;
>> };
>> @@ -58,7 +58,7 @@
>> label = "fsbl2";
>> reg = <0x0004 0x0004>;
>> };
>> - partition@10 {
>> + partition@8 {
>> label = "fip";
>> reg = <0x0008 0x0040>;
>> };
>> @@ -112,7 +112,7 @@
>> label = "fip2";
>> reg = <0x0060 0x0040>;
>> };
>> - partition@120 {
>> + partition@a0 {
>> label = "UBI";
>> reg = <0x00a0 0x3f60>;
>> };
>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
>
Applied on u-boot-stm32/master
Re: [PATCH 2/3] ARM: dts: stm32: Fix partition node name for stm32mp15xx-dhcor-u-boot
On 4/17/24 11:00, Patrick DELAUNAY wrote:
> Hi
>
> On 3/8/24 14:50, Patrice Chotard wrote:
>> Fix flash@0 partition node name with correct offset.
>>
>> Fixes: 90f992e6a58c ("arm: dts: stm32: Add partitions in flash0 and nand
>> node for
>> stm32mp15xx-dhcom/dhcor")
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
>> b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
>> index 552b35db3c7..ba84db679e1 100644
>> --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
>> +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
>> @@ -42,15 +42,15 @@
>> label = "fsbl2";
>> reg = <0x0004 0x0004>;
>> };
>> - partition@50 {
>> + partition@8 {
>> label = "uboot";
>> reg = <0x0008 0x0016>;
>> };
>> - partition@90 {
>> + partition@1e {
>> label = "env1";
>> reg = <0x001E 0x0001>;
>> };
>> - partition@98 {
>> + partition@1f {
>> label = "env2";
>> reg = <0x001F 0x0001>;
>> };
>
>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
Applied on u-boot-stm32/master
Re: [PATCH 1/2] mmc: stm32_sdmmc2: Add "st,stm32mp25-sdmmc2" compatible
On 4/17/24 13:10, Jaehoon Chung wrote:
> Hi
>
>> -Original Message-
>> From: Patrick DELAUNAY
>> Sent: Wednesday, April 17, 2024 6:02 PM
>> To: Patrice Chotard ; u-boot@lists.denx.de
>> Cc: U-Boot STM32 ; Jaehoon Chung
>> ;
>> Peng Fan ; Sean Anderson ; Simon Glass
>> ; Tom
>> Rini
>> Subject: Re: [PATCH 1/2] mmc: stm32_sdmmc2: Add "st,stm32mp25-sdmmc2"
>> compatible
>>
>> Hi,
>>
>> On 3/8/24 15:26, Patrice Chotard wrote:
>>> From: Patrick Delaunay
>>>
>>> Add compatible used for STM32MP25 family.
>>>
>>> Signed-off-by: Patrick Delaunay
>>> Signed-off-by: Patrice Chotard
>>> ---
>>>
>>> drivers/mmc/stm32_sdmmc2.c | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
>>> index a2b111a8435..d4982a14281 100644
>>> --- a/drivers/mmc/stm32_sdmmc2.c
>>> +++ b/drivers/mmc/stm32_sdmmc2.c
>>> @@ -789,6 +789,7 @@ static int stm32_sdmmc2_bind(struct udevice *dev)
>>>
>>> static const struct udevice_id stm32_sdmmc2_ids[] = {
>>> { .compatible = "st,stm32-sdmmc2" },
>>> + { .compatible = "st,stm32mp25-sdmmc2" },
>>> { }
>>> };
>>>
>>
>>
>> Reviewed-by: Patrick Delaunay
>
> Reviewed-by: Jaehoon Chung
>
> Best Regards,
> Jaehoon Chung
>
>>
>> Thanks
>> Patrick
>>
>
>
Applied on u-boot-stm32/master
Re: [PATCH 2/2] mmc: stm32_sdmmc2: Fix AARCH64 compilation warnings
On 4/17/24 13:11, Jaehoon Chung wrote:
>
>
>> -Original Message-
>> From: Patrick DELAUNAY
>> Sent: Wednesday, April 17, 2024 6:02 PM
>> To: Patrice Chotard ; u-boot@lists.denx.de
>> Cc: U-Boot STM32 ; Jaehoon Chung
>> ;
>> Peng Fan ; Sean Anderson ; Simon Glass
>> ; Tom
>> Rini
>> Subject: Re: [PATCH 2/2] mmc: stm32_sdmmc2: Fix AARCH64 compilation warnings
>>
>> Hi,
>>
>> On 3/8/24 15:26, Patrice Chotard wrote:
>>> When building with AARCH64 defconfig, we got warnings, fix them.
>>>
>>> Signed-off-by: Patrice Chotard
>>> ---
>>>
>>> drivers/mmc/stm32_sdmmc2.c | 8
>>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
>>> index d4982a14281..39ae79ba129 100644
>>> --- a/drivers/mmc/stm32_sdmmc2.c
>>> +++ b/drivers/mmc/stm32_sdmmc2.c
>>> @@ -220,9 +220,9 @@ static void stm32_sdmmc2_start_data(struct udevice *dev,
>>>
>>> if (data->flags & MMC_DATA_READ) {
>>> data_ctrl |= SDMMC_DCTRL_DTDIR;
>>> - idmabase0 = (u32)data->dest;
>>> + idmabase0 = (u32)(long)data->dest;
>>> } else {
>>> - idmabase0 = (u32)data->src;
>>> + idmabase0 = (u32)(long)data->src;
>>> }
>>>
>>> /* Set the SDMMC DataLength value */
>>> @@ -463,8 +463,8 @@ retry_cmd:
>>>
>>> stm32_sdmmc2_start_cmd(dev, cmd, cmdat, );
>>>
>>> - dev_dbg(dev, "send cmd %d data: 0x%x @ 0x%x\n",
>>> - cmd->cmdidx, data ? ctx.data_length : 0, (unsigned int)data);
>>> + dev_dbg(dev, "send cmd %d data: 0x%x @ 0x%p\n",
>>> + cmd->cmdidx, data ? ctx.data_length : 0, data);
>>>
>>> ret = stm32_sdmmc2_end_cmd(dev, cmd, );
>>>
>>
>>
>>
>> Reviewed-by: Patrick Delaunay
>
> Reviewed-by: Jaehoon Chung
>
> Best Regards,
> Jaehoon Chung
>
>>
>> Thanks
>> Patrick
>
>
Applied on u-boot-stm32/master
Re: [PATCH v1 25/25] ARM: dts: stm32: Add led-blue for stm32mp157c-ed1-scmi-u-boot
On 4/17/24 11:28, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:02, Patrice Chotard wrote: >> The blue led is used to indicate U-Boot entering / exit indication >> then Linux heartbeat. >> >> Signed-off-by: Patrice Chotard >> --- >> >> arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi | 6 +- >> 1 file changed, 5 insertions(+), 1 deletion(-) >> > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 24/25] ARM: dts: stm32: Update red led node for stm32mp157c-ed1-scmi-u-boot
On 4/17/24 11:13, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:02, Patrice Chotard wrote: >> As indicated in kernel led dt-bindings, label is a deprecated >> property, so remove it and use led node's name instead for >> u-boot,error-led property. >> Rename red led node's name to led-red. >> Remove status property which is useless. >> Add compatible = "gpio-leds"; which is not present in kernel DT. >> >> Signed-off-by: Patrice Chotard >> --- >> >> arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi | 8 >> 1 file changed, 4 insertions(+), 4 deletions(-) >> > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 23/25] ARM: dts: stm32: Don't probe red led at boot for stm32mp157c-ed1-scmi-u-boot
On 4/17/24 11:13, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:02, Patrice Chotard wrote: >> red led and button dedicated to fastboot share the same gpio GPIOA13. >> Led driver is probed early so the corresponding gpio is taken and >> configured in output which forbid fastboot and stm32prog button usage. >> >> To avoid this, remove the "default-state" property from red led node. >> >> This will avoid to trigger the led driver probe() to configure the led >> default state during startup. >> >> Signed-off-by: Patrice Chotard >> --- >> >> arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi | 1 - >> 1 file changed, 1 deletion(-) >> > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 23/25] ARM: dts: stm32: Don't probe red led at boot for stm32mp157c-ed1-scmi-u-boot
On 4/9/24 17:02, Patrice Chotard wrote:
> red led and button dedicated to fastboot share the same gpio GPIOA13.
> Led driver is probed early so the corresponding gpio is taken and
> configured in output which forbid fastboot and stm32prog button usage.
>
> To avoid this, remove the "default-state" property from red led node.
>
> This will avoid to trigger the led driver probe() to configure the led
> default state during startup.
>
> Signed-off-by: Patrice Chotard
> ---
>
> arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
> b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
> index 84920f53496..2abd512e297 100644
> --- a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
> @@ -37,7 +37,6 @@
> red {
> label = "error";
> gpios = < 13 GPIO_ACTIVE_LOW>;
> - default-state = "off";
> status = "okay";
> };
> };
Applied on u-boot-stm32/master
Re: [PATCH v1 22/25] ARM: dts: stm32: Add gpio-keys for stm32mp157c-ed1-scmi-u-boot
On 4/17/24 11:12, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:02, Patrice Chotard wrote: >> Add 2 gpio-keys : >> _ button-user-1 for stm32prog mode activation. >> _ button-user-2 for fastboot mode activation. >> >> Remove proprietary st,fastboot-gpios and st,stm32prog-gpios. >> >> Signed-off-by: Patrice Chotard >> --- >> >> arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi | 19 +-- >> 1 file changed, 17 insertions(+), 2 deletions(-) >> > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 21/25] ARM: dts: stm32: Add led-blue for stm32mp157c-ed1-u-boot
On 4/17/24 11:11, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:02, Patrice Chotard wrote: >> The blue led is used to indicate U-Boot entering / exit indication >> then Linux heartbeat. >> >> Signed-off-by: Patrice Chotard >> --- >> >> arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 6 +- >> 1 file changed, 5 insertions(+), 1 deletion(-) >> > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 20/25] ARM: dts: stm32: Update red led node for stm32mp157c-ed1-u-boot
On 4/17/24 11:11, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:02, Patrice Chotard wrote: >> As indicated in kernel led dt-bindings, label is a deprecated >> property, so remove it and use led node's name instead for >> u-boot,error-led property. >> Rename red led node's name to led-red. >> Remove status property which is useless. >> Add compatible = "gpio-leds" which is not present in kernel DT. >> >> Signed-off-by: Patrice Chotard >> --- >> >> arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 8 >> 1 file changed, 4 insertions(+), 4 deletions(-) >> > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 19/25] ARM: dts: stm32: Don't probe red led at boot for stm32mp157c-ed1-u-boot
On 4/17/24 11:11, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:02, Patrice Chotard wrote: >> red led and button dedicated to fastboot share the same gpio GPIOA13. >> Led driver is probed early so the corresponding gpio is taken and >> configured in output which forbid fastboot and stm32prog button usage. >> >> To avoid this, remove the "default-state" property from red led node. >> >> This will avoid to trigger the led driver probe() to configure the led >> default state during startup. >> >> Signed-off-by: Patrice Chotard >> --- >> >> arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 1 - >> 1 file changed, 1 deletion(-) >> > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 18/25] ARM: dts: stm32: Add gpio-keys for stm32mp157c-ed1-u-boot
On 4/17/24 11:11, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:02, Patrice Chotard wrote: >> Add 2 gpio-keys : >> _ button-user-1 for stm32prog mode activation. >> _ button-user-2 for fastboot mode activation. >> >> Remove proprietary st,fastboot-gpios and st,stm32prog-gpios. >> >> Signed-off-by: Patrice Chotard >> --- >> >> arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 19 +-- >> 1 file changed, 17 insertions(+), 2 deletions(-) >> > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 17/25] ARM: dts: stm32: Update u-boot,boot-led for stm32mp157a-dk1-u-boot
On 4/17/24 11:10, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:02, Patrice Chotard wrote: >> As indicated in kernel led dt-bindings, label is a deprecated >> property, so remove it and use blue led node's name instead >> for u-boot,boot-led property. >> >> Signed-off-by: Patrice Chotard >> --- >> >> arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 6 +- >> 1 file changed, 5 insertions(+), 1 deletion(-) >> > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 16/25] ARM: dts: stm32: Update red led node for stm32mp157a-dk1-u-boot
On 4/17/24 11:10, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:02, Patrice Chotard wrote: >> As indicated in kernel led dt-bindings, label is a deprecated >> property, so remove it and use red led node's name instead >> for u-boot,error-led property. >> Rename red led node's name to led-red. >> Remove status property which is useless. >> >> Signed-off-by: Patrice Chotard >> --- >> >> arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 6 ++ >> 1 file changed, 2 insertions(+), 4 deletions(-) > > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 15/25] ARM: dts: stm32: Don't probe red led at boot for stm32mp157a-dk1-u-boot
On 4/17/24 11:09, Patrick DELAUNAY wrote:
> Hi,
>
> On 4/9/24 17:02, Patrice Chotard wrote:
>> red led and button dedicated to fastboot share the same gpio GPIOA13.
>> Led driver is probed early so the corresponding gpio is taken and
>> configured in output which forbid fastboot and stm32prog button usage.
>>
>> To avoid this, remove the "default-state" property from red led node.
>>
>> This will avoid to trigger the led driver probe() to configure the led
>> default state during startup.
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 1 -
>> 1 file changed, 1 deletion(-)
>>
>> diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
>> b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
>> index 6bf6136c5fd..ee9b51d42b7 100644
>> --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
>> +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
>> @@ -67,7 +67,6 @@
>> red {
>> label = "error";
>> gpios = < 13 GPIO_ACTIVE_LOW>;
>> - default-state = "off";
>> status = "okay";
>> };
>> };
>
>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
Applied on u-boot-stm32/master
Re: [PATCH v1 14/25] ARM: dts: stm32: Add gpio-keys for stm32mp157a-dk1-u-boot
On 4/17/24 11:09, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:02, Patrice Chotard wrote: >> Instead of using "st,fastboot-gpios" and "st,stm32prog-gpios", declare >> 2 gpio-keys. >> >> Signed-off-by: Patrice Chotard >> --- >> >> arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 19 +-- >> 1 file changed, 17 insertions(+), 2 deletions(-) >> > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 13/25] ARM: dts: stm32: Add led-blue for stm32mp157a-dk1-scmi-u-boot
On 4/17/24 11:09, Patrick DELAUNAY wrote:
> Hi,
>
> On 4/9/24 17:02, Patrice Chotard wrote:
>> As indicated in kernel led dt-bindings, label is a deprecated
>> property, so remove it and use blue led node's name instead
>> for u-boot,boot-led property.
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi | 6 +-
>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> index e61814fd66e..a5158fec7ef 100644
>> --- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> +++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> @@ -13,7 +13,7 @@
>> };
>> config {
>> - u-boot,boot-led = "heartbeat";
>> + u-boot,boot-led = "led-blue";
>> u-boot,error-led = "led-red";
>> u-boot,mmc-env-partition = "u-boot-env";
>> st,adc_usb_pd = < 18>, < 19>;
>> @@ -36,6 +36,10 @@
>> };
>> led {
>> + led-blue {
>> + /delete-property/label;
>> + };
>> +
>> led-red {
>> gpios = < 13 GPIO_ACTIVE_LOW>;
>> };
>
>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
Applied on u-boot-stm32/master
Re: [PATCH v1 12/25] ARM: dts: stm32: Update red led node for stm32mp157a-dk1-scmi-u-boot
On 4/17/24 11:08, Patrick DELAUNAY wrote:
> Hi,
>
> On 4/9/24 17:02, Patrice Chotard wrote:
>> As indicated in kernel led dt-bindings, label is a deprecated
>> property, so remove it and use red led node's name instead
>> for u-boot,error-led property.
>> Rename "red" led node's name to "led-red".
>> Remove status property which is useless.
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi | 6 ++
>> 1 file changed, 2 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> index 8760d6c7d93..e61814fd66e 100644
>> --- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> +++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> @@ -14,7 +14,7 @@
>> config {
>> u-boot,boot-led = "heartbeat";
>> - u-boot,error-led = "error";
>> + u-boot,error-led = "led-red";
>> u-boot,mmc-env-partition = "u-boot-env";
>> st,adc_usb_pd = < 18>, < 19>;
>> };
>> @@ -36,10 +36,8 @@
>> };
>> led {
>> - red {
>> - label = "error";
>> + led-red {
>> gpios = < 13 GPIO_ACTIVE_LOW>;
>> - status = "okay";
>> };
>> };
>> };
>
>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
Applied on u-boot-stm32/master
Re: [PATCH v1 11/25] ARM: dts: stm32: Don't probe red led at boot for stm32mp157a-dk1-scmi-u-boot
On 4/17/24 11:07, Patrick DELAUNAY wrote:
> Hi,
>
> On 4/9/24 17:02, Patrice Chotard wrote:
>> red led and button dedicated to fastboot share the same gpio GPIOA13.
>> Led driver is probed early so the corresponding gpio is taken and
>> configured in output which forbid fastboot and stm32prog button usage.
>>
>> To avoid this, remove the "default-state" property from red led node.
>>
>> This will avoid to trigger the led driver probe() to configure the led
>> default state during startup.
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi | 1 -
>> 1 file changed, 1 deletion(-)
>>
>> diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> index 5d49b09c35d..8760d6c7d93 100644
>> --- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> +++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> @@ -39,7 +39,6 @@
>> red {
>> label = "error";
>> gpios = < 13 GPIO_ACTIVE_LOW>;
>> - default-state = "off";
>> status = "okay";
>> };
>> };
>
>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
Applied on u-boot-stm32/master
Re: [PATCH v1 10/25] ARM: dts: stm32: Add gpio-keys for stm32mp157a-dk1-scmi-u-boot
On 4/17/24 11:07, Patrick DELAUNAY wrote:
> Hi,
>
> On 4/9/24 17:02, Patrice Chotard wrote:
>> Instead of using "st,fastboot-gpios" and "st,stm32prog-gpios", declare
>> 2 gpio-keys.
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi | 19 +--
>> 1 file changed, 17 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> index 20728f27ee1..5d49b09c35d 100644
>> --- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> +++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
>> @@ -3,6 +3,7 @@
>> * Copyright : STMicroelectronics 2022
>> */
>> +#include
>> #include "stm32mp15-scmi-u-boot.dtsi"
>> / {
>> @@ -16,8 +17,22 @@
>> u-boot,error-led = "error";
>> u-boot,mmc-env-partition = "u-boot-env";
>> st,adc_usb_pd = < 18>, < 19>;
>> - st,fastboot-gpios = < 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
>> - st,stm32prog-gpios = < 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
>> + };
>> +
>> + gpio-keys {
>> + compatible = "gpio-keys";
>> +
>> + button-user-1 {
>> + label = "User-1";
>> + linux,code = ;
>> + gpios = < 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
>> + };
>> +
>> + button-user-2 {
>> + label = "User-2";
>> + linux,code = ;
>> + gpios = < 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
>> + };
>> };
>> led {
>
>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
Applied on u-boot-stm32/master
Re: [PATCH v1 09/25] ARM: dts: stm32: Clean led-red node for stm32mp135f-dk-u-boot
On 4/17/24 11:07, Patrick DELAUNAY wrote:
> Hi,
>
> On 4/9/24 17:01, Patrice Chotard wrote:
>> Remove "color" property from led-red node which is not supported
>> by U-Boot.
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> arch/arm/dts/stm32mp135f-dk-u-boot.dtsi | 1 -
>> 1 file changed, 1 deletion(-)
>>
>> diff --git a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
>> b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
>> index 8f42735609a..f004e9840a2 100644
>> --- a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
>> +++ b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
>> @@ -35,7 +35,6 @@
>> };
>> led-red {
>> - color = ;
>> gpios = < 13 GPIO_ACTIVE_LOW>;
>> };
>> };
>
>
>
> Reviewed-by: Patrick Delaunay
>
> Thanks
> Patrick
>
Applied on u-boot-stm32/master
Re: [PATCH v1 08/25] ARM: dts: stm32: Don't probe led-red/led-blue at boot for stm32mp135f-dk-u-boot
On 4/17/24 11:06, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:01, Patrice Chotard wrote: >> led-red and button dedicated to fastboot share the same gpio GPIOA13. >> led-blue and button dedicated to stm32prog share the same gpio GPIOA14. >> Led driver is probed early so the corresponding gpio is taken and >> configured in output which forbid fastboot and stm32prog button usage. >> >> To avoid this, remove the "default-state" property from led-red and >> led-blue led's node. >> >> This will avoid to trigger the led driver probe() to configure the led >> default state during startup. >> >> Signed-off-by: Patrice Chotard >> --- >> >> arch/arm/dts/stm32mp135f-dk-u-boot.dtsi | 5 - >> 1 file changed, 4 insertions(+), 1 deletion(-) >> > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 06/25] board: st: stmp32mp1: Use BUTTON UCLASS in board_key_check()
On 4/17/24 11:05, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:01, Patrice Chotard wrote: >> Instead of using gpio directly to detect key pressed on button >> dedicated for fastboot and stm32mprog, make usage of BUTTON UCLASS. >> >> Signed-off-by: Patrice Chotard >> --- >> >> board/st/stm32mp1/stm32mp1.c | 68 +--- >> 1 file changed, 40 insertions(+), 28 deletions(-) >> > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 07/25] ARM: dts: stm32: Add gpio-keys for stm32mp135f-dk-u-boot
On 4/17/24 11:06, Patrick DELAUNAY wrote: > Hi > > On 4/9/24 17:01, Patrice Chotard wrote: >> Add 2 gpio-keys : >> _ button-user-1 for stm32prog mode activation. >> _ update button-user's label (defined in kernel DT) to match label >> requested in board_key_check() for fastboot mode activation. >> >> Signed-off-by: Patrice Chotard >> --- >> >> arch/arm/dts/stm32mp135f-dk-u-boot.dtsi | 13 + >> 1 file changed, 13 insertions(+) >> > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 05/25] configs: stm32mp1: Enable BUTTON_GPIO flag for stm32mp13_defconfig
On 4/18/24 13:48, Igor Opaniuk wrote: > On Tue, Apr 9, 2024 at 5:05 PM Patrice Chotard > wrote: >> >> Enable BUTTON_GPIO flag for STM32MP15. >> >> Signed-off-by: Patrice Chotard >> --- >> >> configs/stm32mp13_defconfig | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig >> index db09e63100e..caaabf39ef3 100644 >> --- a/configs/stm32mp13_defconfig >> +++ b/configs/stm32mp13_defconfig >> @@ -52,6 +52,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y >> CONFIG_SYS_RELOC_GD_ENV_ADDR=y >> CONFIG_SYS_MMC_ENV_DEV=-1 >> CONFIG_ENV_MMC_USE_DT=y >> +CONFIG_BUTTON=y >> +CONFIG_BUTTON_GPIO=y >> CONFIG_CLK_SCMI=y >> CONFIG_SET_DFU_ALT_INFO=y >> CONFIG_USB_FUNCTION_FASTBOOT=y >> -- >> 2.25.1 >> > > Reviewed-by: Igor Opaniuk Applied on u-boot-stm32/master
Re: [PATCH v1 03/25] configs: stm32mp1: Enable BUTTON_GPIO flag for stm32mp15_basic_defconfig
On 4/17/24 11:04, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:01, Patrice Chotard wrote: >> Enable BUTTON_GPIO flag for STM32MP15. >> >> Signed-off-by: Patrice Chotard >> --- >> >> configs/stm32mp15_basic_defconfig | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/configs/stm32mp15_basic_defconfig >> b/configs/stm32mp15_basic_defconfig >> index 005f1d55f80..2e22bf86000 100644 >> --- a/configs/stm32mp15_basic_defconfig >> +++ b/configs/stm32mp15_basic_defconfig >> @@ -97,6 +97,8 @@ CONFIG_TFTP_TSIZE=y >> CONFIG_USE_SERVERIP=y >> CONFIG_SERVERIP="192.168.1.1" >> CONFIG_STM32_ADC=y >> +CONFIG_BUTTON=y >> +CONFIG_BUTTON_GPIO=y >> CONFIG_SET_DFU_ALT_INFO=y >> CONFIG_USB_FUNCTION_FASTBOOT=y >> CONFIG_FASTBOOT_BUF_ADDR=0xC000 > > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 04/25] configs: stm32mp1: Enable BUTTON_GPIO flag for stm32mp15_trusted_defconfig
On 4/17/24 11:04, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:01, Patrice Chotard wrote: >> Enable BUTTON_GPIO flag for STM32MP15. >> >> Signed-off-by: Patrice Chotard >> --- >> >> configs/stm32mp15_trusted_defconfig | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/configs/stm32mp15_trusted_defconfig >> b/configs/stm32mp15_trusted_defconfig >> index 84b0854b557..74deaaba2e4 100644 >> --- a/configs/stm32mp15_trusted_defconfig >> +++ b/configs/stm32mp15_trusted_defconfig >> @@ -70,6 +70,8 @@ CONFIG_TFTP_TSIZE=y >> CONFIG_USE_SERVERIP=y >> CONFIG_SERVERIP="192.168.1.1" >> CONFIG_STM32_ADC=y >> +CONFIG_BUTTON=y >> +CONFIG_BUTTON_GPIO=y >> CONFIG_CLK_SCMI=y >> CONFIG_SET_DFU_ALT_INFO=y >> CONFIG_USB_FUNCTION_FASTBOOT=y > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 02/25] configs: stm32mp1: Enable BUTTON_GPIO flag for stm32mp15_defconfig
On 4/17/24 11:03, Patrick DELAUNAY wrote: > Hi, > > On 4/9/24 17:01, Patrice Chotard wrote: >> Enable BUTTON_GPIO flag for STM32MP15. >> >> Signed-off-by: Patrice Chotard >> --- >> >> configs/stm32mp15_defconfig | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig >> index 3302b306996..ffe7512650e 100644 >> --- a/configs/stm32mp15_defconfig >> +++ b/configs/stm32mp15_defconfig >> @@ -69,6 +69,8 @@ CONFIG_TFTP_TSIZE=y >> CONFIG_USE_SERVERIP=y >> CONFIG_SERVERIP="192.168.1.1" >> CONFIG_STM32_ADC=y >> +CONFIG_BUTTON=y >> +CONFIG_BUTTON_GPIO=y >> CONFIG_CLK_SCMI=y >> CONFIG_SET_DFU_ALT_INFO=y >> CONFIG_USB_FUNCTION_FASTBOOT=y > > > > Reviewed-by: Patrick Delaunay > > Thanks > Patrick > Applied on u-boot-stm32/master
Re: [PATCH v1 01/25] configs: stm32mp13: Enable FASTBOOT
On 4/18/24 13:48, Igor Opaniuk wrote: > On Tue, Apr 9, 2024 at 5:19 PM Patrice Chotard > wrote: >> >> Enable FASTBOOT relative flags for stm32mp13_defconfig. >> >> Signed-off-by: Patrice Chotard >> >> --- >> >> configs/stm32mp13_defconfig | 9 - >> 1 file changed, 8 insertions(+), 1 deletion(-) >> >> diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig >> index c893e272db9..db09e63100e 100644 >> --- a/configs/stm32mp13_defconfig >> +++ b/configs/stm32mp13_defconfig >> @@ -15,6 +15,7 @@ CONFIG_CMD_STM32PROG=y >> CONFIG_SYS_LOAD_ADDR=0xc200 >> CONFIG_SYS_MEMTEST_START=0xc000 >> CONFIG_SYS_MEMTEST_END=0xc400 >> +# CONFIG_ANDROID_BOOT_IMAGE is not set >> CONFIG_FIT=y >> CONFIG_SYS_BOOTM_LEN=0x200 >> CONFIG_DISTRO_DEFAULTS=y >> @@ -53,6 +54,13 @@ CONFIG_SYS_MMC_ENV_DEV=-1 >> CONFIG_ENV_MMC_USE_DT=y >> CONFIG_CLK_SCMI=y >> CONFIG_SET_DFU_ALT_INFO=y >> +CONFIG_USB_FUNCTION_FASTBOOT=y >> +CONFIG_FASTBOOT_BUF_ADDR=0xc000 >> +CONFIG_FASTBOOT_BUF_SIZE=0x0200 >> +CONFIG_FASTBOOT_FLASH=y >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 >> +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y >> +CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y >> CONFIG_GPIO_HOG=y >> CONFIG_DM_I2C=y >> CONFIG_SYS_I2C_STM32F7=y >> @@ -92,7 +100,6 @@ CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" >> CONFIG_USB_GADGET_VENDOR_NUM=0x0483 >> CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 >> CONFIG_USB_GADGET_DWC2_OTG=y >> -CONFIG_USB_GADGET_DOWNLOAD=y >> CONFIG_ERRNO_STR=y >> # CONFIG_LMB_USE_MAX_REGIONS is not set >> CONFIG_LMB_MEMORY_REGIONS=2 >> -- >> 2.25.1 >> > Reviewed-by: Igor Opaniuk > Applied on u-boot-stm32/master
Re: [PATCH] stm32mp: cmd_stm32prog: add dependencies with USB_GADGET_DOWNLOAD
On 2/7/24 16:59, Igor Opaniuk wrote: > On Wed, Feb 7, 2024 at 2:12 PM Patrick Delaunay > wrote: >> >> This patch avoids compilation issue when CONFIG_USB_GADGET is deactivated >> in defconfig, with undefined reference to run_usb_dnl_gadget and to >> g_dnl_set_product. >> >> Signed-off-by: Patrick Delaunay >> --- >> >> arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig >> b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig >> index 8f91db4b46b9..589276282e44 100644 >> --- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig >> +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig >> @@ -17,6 +17,7 @@ config CMD_STM32PROG >> config CMD_STM32PROG_USB >> bool "support stm32prog over USB" >> depends on CMD_STM32PROG >> + depends on USB_GADGET_DOWNLOAD >> default y >> help >> activate the command "stm32prog usb" for STM32MP soc family >> -- >> 2.25.1 >> > > Reviewed-by: Igor Opaniuk Applied on u-boot-stm32/master
Re: [PATCH] arm: stm32: Enable OHCI HCD support on STM32MP15xx DHSOM
On 3/4/24 19:25, Marek Vasut wrote: > The OHCI HCD is mandatory for USB 1.1 FS/LS device support, enable it. > This used to be enabled implicitly before, now that implicit dependency > disappeared and this got disabled. Enable it manually. > > Signed-off-by: Marek Vasut > --- > Cc: Patrice Chotard > Cc: Patrick Delaunay > Cc: u-b...@dh-electronics.com > Cc: uboot-st...@st-md-mailman.stormreply.com > --- > configs/stm32mp15_dhcom_basic_defconfig | 2 ++ > configs/stm32mp15_dhcor_basic_defconfig | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/configs/stm32mp15_dhcom_basic_defconfig > b/configs/stm32mp15_dhcom_basic_defconfig > index 1d241529be7..0bfd3b76d6a 100644 > --- a/configs/stm32mp15_dhcom_basic_defconfig > +++ b/configs/stm32mp15_dhcom_basic_defconfig > @@ -164,6 +164,8 @@ CONFIG_DM_USB_GADGET=y > CONFIG_SPL_DM_USB_GADGET=y > CONFIG_USB_EHCI_HCD=y > CONFIG_USB_EHCI_GENERIC=y > +CONFIG_USB_OHCI_HCD=y > +CONFIG_USB_OHCI_GENERIC=y > CONFIG_USB_DWC2=y > CONFIG_USB_HOST_ETHER=y > CONFIG_USB_ETHER_ASIX=y > diff --git a/configs/stm32mp15_dhcor_basic_defconfig > b/configs/stm32mp15_dhcor_basic_defconfig > index 6e0c4a8cf9f..1c1fbc5c7db 100644 > --- a/configs/stm32mp15_dhcor_basic_defconfig > +++ b/configs/stm32mp15_dhcor_basic_defconfig > @@ -164,6 +164,8 @@ CONFIG_DM_USB_GADGET=y > CONFIG_SPL_DM_USB_GADGET=y > CONFIG_USB_EHCI_HCD=y > CONFIG_USB_EHCI_GENERIC=y > +CONFIG_USB_OHCI_HCD=y > +CONFIG_USB_OHCI_GENERIC=y > CONFIG_USB_DWC2=y > CONFIG_USB_HOST_ETHER=y > CONFIG_USB_ETHER_ASIX=y Applied on u-boot-stm32/master
Re: [PATCH] mtd: rawnand: stm32_fmc2: add MP25 support
On 3/6/24 10:54, Christophe Kerello wrote:
> FMC2 IP supports up to 4 chip select. On MP1 SoC, only 2 of them are
> available when on MP25 SoC, the 4 chip select are available.
>
> Let's use a platform data structure for parameters that will differ.
>
> Signed-off-by: Christophe Kerello
> ---
>
> drivers/mtd/nand/raw/stm32_fmc2_nand.c | 47 ++
> 1 file changed, 40 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
> b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
> index 3528824575b..d284b8cbb12 100644
> --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
> +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
> @@ -34,7 +34,7 @@
> #define FMC2_RB_DELAY_US 30
>
> /* Max chip enable */
> -#define FMC2_MAX_CE 2
> +#define FMC2_MAX_CE 4
>
> /* Timings */
> #define FMC2_THIZ1
> @@ -160,6 +160,11 @@ static inline struct stm32_fmc2_nand
> *to_fmc2_nand(struct nand_chip *chip)
> return container_of(chip, struct stm32_fmc2_nand, chip);
> }
>
> +struct stm32_fmc2_nfc_data {
> + int max_ncs;
> + struct udevice *(*get_cdev)(struct udevice *dev);
> +};
> +
> struct stm32_fmc2_nfc {
> struct nand_hw_control base;
> struct stm32_fmc2_nand nand;
> @@ -169,6 +174,7 @@ struct stm32_fmc2_nfc {
> fdt_addr_t cmd_base[FMC2_MAX_CE];
> fdt_addr_t addr_base[FMC2_MAX_CE];
> struct clk clk;
> + const struct stm32_fmc2_nfc_data *data;
>
> u8 cs_assigned;
> int cs_sel;
> @@ -815,7 +821,7 @@ static int stm32_fmc2_nfc_parse_child(struct
> stm32_fmc2_nfc *nfc, ofnode node)
> }
>
> for (i = 0; i < nand->ncs; i++) {
> - if (cs[i] >= FMC2_MAX_CE) {
> + if (cs[i] >= nfc->data->max_ncs) {
> log_err("Invalid reg value: %d\n", nand->cs_used[i]);
> return -EINVAL;
> }
> @@ -906,10 +912,18 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev)
> spin_lock_init(>controller.lock);
> init_waitqueue_head(>controller.wq);
>
> - cdev = stm32_fmc2_nfc_get_cdev(dev);
> - if (!cdev)
> + nfc->data = (void *)dev_get_driver_data(dev);
> + if (!nfc->data)
> return -EINVAL;
>
> + if (nfc->data->get_cdev) {
> + cdev = nfc->data->get_cdev(dev);
> + if (!cdev)
> + return -EINVAL;
> + } else {
> + cdev = dev->parent;
> + }
> +
> ret = stm32_fmc2_nfc_parse_dt(dev, nfc);
> if (ret)
> return ret;
> @@ -921,7 +935,7 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev)
> if (dev == cdev)
> start_region = 1;
>
> - for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE;
> + for (chip_cs = 0, mem_region = start_region; chip_cs <
> nfc->data->max_ncs;
>chip_cs++, mem_region += 3) {
> if (!(nfc->cs_assigned & BIT(chip_cs)))
> continue;
> @@ -1033,9 +1047,28 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev)
> return nand_register(0, mtd);
> }
>
> +static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp1_data = {
> + .max_ncs = 2,
> + .get_cdev = stm32_fmc2_nfc_get_cdev,
> +};
> +
> +static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp25_data = {
> + .max_ncs = 4,
> +};
> +
> static const struct udevice_id stm32_fmc2_nfc_match[] = {
> - { .compatible = "st,stm32mp15-fmc2" },
> - { .compatible = "st,stm32mp1-fmc2-nfc" },
> + {
> + .compatible = "st,stm32mp15-fmc2",
> + .data = (ulong)_fmc2_nfc_mp1_data,
> + },
> + {
> + .compatible = "st,stm32mp1-fmc2-nfc",
> + .data = (ulong)_fmc2_nfc_mp1_data,
> + },
> + {
> + .compatible = "st,stm32mp25-fmc2-nfc",
> + .data = (ulong)_fmc2_nfc_mp25_data,
> + },
> { /* Sentinel */ }
> };
>
Applied on u-boot-stm32/master
Re: [PATCH v1 2/2] memory: stm32-fmc2-ebi: add MP25 RIF support
On 3/6/24 10:50, Christophe Kerello wrote:
> The FMC2 revision 2 supports security and isolation compliant with
> the Resource Isolation Framework (RIF). From RIF point of view,
> the FMC2 is composed of several independent resources, listed below,
> which can be assigned to different security and compartment domains:
> - 0: Common FMC_CFGR register.
> - 1: EBI controller for Chip Select 1.
> - 2: EBI controller for Chip Select 2.
> - 3: EBI controller for Chip Select 3.
> - 4: EBI controller for Chip Select 4.
> - 5: NAND controller.
>
> Signed-off-by: Christophe Kerello
> ---
>
> drivers/memory/stm32-fmc2-ebi.c | 140 +++-
> 1 file changed, 138 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c
> index c7db16463e8..1ce96077858 100644
> --- a/drivers/memory/stm32-fmc2-ebi.c
> +++ b/drivers/memory/stm32-fmc2-ebi.c
> @@ -23,8 +23,14 @@
> #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1)
> #define FMC2_PCSCNTR 0x20
> #define FMC2_CFGR0x20
> +#define FMC2_SR 0x84
> #define FMC2_BWTR1 0x104
> #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1)
> +#define FMC2_SECCFGR 0x300
> +#define FMC2_CIDCFGR00x30c
> +#define FMC2_CIDCFGR(x) ((x) * 0x8 + FMC2_CIDCFGR0)
> +#define FMC2_SEMCR0 0x310
> +#define FMC2_SEMCR(x)((x) * 0x8 + FMC2_SEMCR0)
>
> /* Register: FMC2_BCR1 */
> #define FMC2_BCR1_CCLKEN BIT(20)
> @@ -67,8 +73,23 @@
> #define FMC2_CFGR_CCLKEN BIT(20)
> #define FMC2_CFGR_FMC2EN BIT(31)
>
> +/* Register: FMC2_SR */
> +#define FMC2_SR_ISOSTGENMASK(1, 0)
> +
> +/* Register: FMC2_CIDCFGR */
> +#define FMC2_CIDCFGR_CFENBIT(0)
> +#define FMC2_CIDCFGR_SEMEN BIT(1)
> +#define FMC2_CIDCFGR_SCIDGENMASK(6, 4)
> +#define FMC2_CIDCFGR_SEMWLC1 BIT(17)
> +
> +/* Register: FMC2_SEMCR */
> +#define FMC2_SEMCR_SEM_MUTEX BIT(0)
> +#define FMC2_SEMCR_SEMCIDGENMASK(6, 4)
> +
> #define FMC2_MAX_EBI_CE 4
> #define FMC2_MAX_BANKS 5
> +#define FMC2_MAX_RESOURCES 6
> +#define FMC2_CID11
>
> #define FMC2_BCR_CPSIZE_00x0
> #define FMC2_BCR_CPSIZE_128 0x1
> @@ -163,6 +184,7 @@ struct stm32_fmc2_ebi_data {
> u32 fmc2_enable_reg;
> u32 fmc2_enable_bit;
> int (*nwait_used_by_ctrls)(struct stm32_fmc2_ebi *ebi);
> + int (*check_rif)(struct stm32_fmc2_ebi *ebi, u32 resource);
> };
>
> struct stm32_fmc2_ebi {
> @@ -170,6 +192,7 @@ struct stm32_fmc2_ebi {
> fdt_addr_t io_base;
> const struct stm32_fmc2_ebi_data *data;
> u8 bank_assigned;
> + bool access_granted;
> };
>
> /*
> @@ -241,6 +264,28 @@ static int stm32_fmc2_ebi_check_sync_trans(struct
> stm32_fmc2_ebi *ebi,
> return -EINVAL;
> }
>
> +static int stm32_fmc2_ebi_mp25_check_cclk(struct stm32_fmc2_ebi *ebi,
> + const struct stm32_fmc2_prop *prop,
> + int cs)
> +{
> + if (!ebi->access_granted)
> + return -EACCES;
> +
> + return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs);
> +}
> +
> +static int stm32_fmc2_ebi_mp25_check_clk_period(struct stm32_fmc2_ebi *ebi,
> + const struct stm32_fmc2_prop
> *prop,
> + int cs)
> +{
> + u32 cfgr = readl(ebi->io_base + FMC2_CFGR);
> +
> + if (cfgr & FMC2_CFGR_CCLKEN && !ebi->access_granted)
> + return -EACCES;
> +
> + return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs);
> +}
> +
> static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi,
> const struct stm32_fmc2_prop *prop,
> int cs)
> @@ -960,7 +1005,7 @@ static const struct stm32_fmc2_prop
> stm32_fmc2_mp25_child_props[] = {
> .bprop = true,
> .reg_type = FMC2_REG_CFGR,
> .reg_mask = FMC2_CFGR_CCLKEN,
> - .check = stm32_fmc2_ebi_check_sync_trans,
> + .check = stm32_fmc2_ebi_mp25_check_cclk,
> .set = stm32_fmc2_ebi_set_bit_field,
> },
> {
> @@ -1058,7 +1103,7 @@ static const struct stm32_fmc2_prop
> stm32_fmc2_mp25_child_props[] = {
> {
> .name = "st,fmc2-ebi-cs-clk-period-ns",
> .reset_val = FMC2_CFGR_CLKDIV_MAX + 1,
> - .check = stm32_fmc2_ebi_check_sync_trans,
> + .check = stm32_fmc2_ebi_mp25_check_clk_period,
> .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
> .set = stm32_fmc2_ebi_mp25_set_clk_period,
> },
> @@
Re: [PATCH v1 1/2] memory: stm32-fmc2-ebi: add MP25 support
On 3/6/24 10:50, Christophe Kerello wrote:
> Add the support of the revision 2 of FMC2 IP.
> - PCSCNTR register has been removed,
> - CFGR register has been added,
> - the bit used to enable the IP has moved from BCR1 to CFGR,
> - the timeout for CEx deassertion has moved from PCSCNTR to BCRx,
> - the continuous clock enable has moved from BCR1 to CFGR,
> - the clk divide ratio has moved from BCR1 to CFGR.
>
> The MP1 SoCs have only one signal to manage all the controllers (NWAIT).
> The MP25 SOC has one RNB signal for the NAND controller and one NWAIT
> signal for the memory controller.
>
> Let's use a platform data structure for parameters that will differ
> between MP1 and MP25.
>
> Signed-off-by: Christophe Kerello
>
> ---
>
> drivers/memory/stm32-fmc2-ebi.c | 313 ++--
> 1 file changed, 301 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c
> index a722a3836f7..c7db16463e8 100644
> --- a/drivers/memory/stm32-fmc2-ebi.c
> +++ b/drivers/memory/stm32-fmc2-ebi.c
> @@ -22,6 +22,7 @@
> #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1)
> #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1)
> #define FMC2_PCSCNTR 0x20
> +#define FMC2_CFGR0x20
> #define FMC2_BWTR1 0x104
> #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1)
>
> @@ -44,6 +45,7 @@
> #define FMC2_BCR_ASYNCWAIT BIT(15)
> #define FMC2_BCR_CPSIZE GENMASK(18, 16)
> #define FMC2_BCR_CBURSTRWBIT(19)
> +#define FMC2_BCR_CSCOUNT GENMASK(21, 20)
> #define FMC2_BCR_NBLSET GENMASK(23, 22)
>
> /* Register: FMC2_BTRx/FMC2_BWTRx */
> @@ -60,6 +62,11 @@
> #define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0)
> #define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16)
>
> +/* Register: FMC2_CFGR */
> +#define FMC2_CFGR_CLKDIV GENMASK(19, 16)
> +#define FMC2_CFGR_CCLKEN BIT(20)
> +#define FMC2_CFGR_FMC2EN BIT(31)
> +
> #define FMC2_MAX_EBI_CE 4
> #define FMC2_MAX_BANKS 5
>
> @@ -76,6 +83,11 @@
> #define FMC2_BCR_MTYP_PSRAM 0x1
> #define FMC2_BCR_MTYP_NOR0x2
>
> +#define FMC2_BCR_CSCOUNT_0 0x0
> +#define FMC2_BCR_CSCOUNT_1 0x1
> +#define FMC2_BCR_CSCOUNT_64 0x2
> +#define FMC2_BCR_CSCOUNT_256 0x3
> +
> #define FMC2_BXTR_EXTMOD_A 0x0
> #define FMC2_BXTR_EXTMOD_B 0x1
> #define FMC2_BXTR_EXTMOD_C 0x2
> @@ -90,6 +102,7 @@
> #define FMC2_BTR_CLKDIV_MAX 0xf
> #define FMC2_BTR_DATLAT_MAX 0xf
> #define FMC2_PCSCNTR_CSCOUNT_MAX 0xff
> +#define FMC2_CFGR_CLKDIV_MAX 0xf
>
> enum stm32_fmc2_ebi_bank {
> FMC2_EBI1 = 0,
> @@ -103,7 +116,8 @@ enum stm32_fmc2_ebi_register_type {
> FMC2_REG_BCR = 1,
> FMC2_REG_BTR,
> FMC2_REG_BWTR,
> - FMC2_REG_PCSCNTR
> + FMC2_REG_PCSCNTR,
> + FMC2_REG_CFGR
> };
>
> enum stm32_fmc2_ebi_transaction_type {
> @@ -134,9 +148,27 @@ enum stm32_fmc2_ebi_cpsize {
> FMC2_CPSIZE_1024 = 1024
> };
>
> +enum stm32_fmc2_ebi_cscount {
> + FMC2_CSCOUNT_0 = 0,
> + FMC2_CSCOUNT_1 = 1,
> + FMC2_CSCOUNT_64 = 64,
> + FMC2_CSCOUNT_256 = 256
> +};
> +
> +struct stm32_fmc2_ebi;
> +
> +struct stm32_fmc2_ebi_data {
> + const struct stm32_fmc2_prop *child_props;
> + unsigned int nb_child_props;
> + u32 fmc2_enable_reg;
> + u32 fmc2_enable_bit;
> + int (*nwait_used_by_ctrls)(struct stm32_fmc2_ebi *ebi);
> +};
> +
> struct stm32_fmc2_ebi {
> struct clk clk;
> fdt_addr_t io_base;
> + const struct stm32_fmc2_ebi_data *data;
> u8 bank_assigned;
> };
>
> @@ -296,6 +328,24 @@ static u32 stm32_fmc2_ebi_ns_to_clk_period(struct
> stm32_fmc2_ebi *ebi,
> return DIV_ROUND_UP(nb_clk_cycles, clk_period);
> }
>
> +static u32 stm32_fmc2_ebi_mp25_ns_to_clk_period(struct stm32_fmc2_ebi *ebi,
> + int cs, u32 setup)
> +{
> + u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup);
> + u32 cfgr = readl(ebi->io_base + FMC2_CFGR);
> + u32 clk_period;
> +
> + if (cfgr & FMC2_CFGR_CCLKEN) {
> + clk_period = FIELD_GET(FMC2_CFGR_CLKDIV, cfgr) + 1;
> + } else {
> + u32 btr = readl(ebi->io_base + FMC2_BTR(cs));
> +
> + clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1;
> + }
> +
> + return DIV_ROUND_UP(nb_clk_cycles, clk_period);
> +}
> +
> static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg)
> {
> switch (reg_type) {
> @@ -311,6 +361,9 @@ static int stm32_fmc2_ebi_get_reg(int reg_type, int cs,
> u32 *reg)
> case FMC2_REG_PCSCNTR:
> *reg = FMC2_PCSCNTR;
> break;
> + case FMC2_REG_CFGR:
> +
Re: [PATCH v2] ARM: stm32: Jump to ep on successful resume in PSCI suspend code
On 4/7/24 22:21, Marek Vasut wrote:
> In case the system has resumed successfully, the PSCI suspend resume
> code has to jump to the 'ep' successful resume entry point code path,
> otherwise the code has to jump to content of the LR register, which
> points to failed resume code path.
>
> To implement this distinction, rewrite LR register stored on stack
> with 'ep' value in case of a successful resume, which is really in
> every case unless some catastrophic failure occurred during suspend.
>
> Without this change, Linux counts every resume as failed in
> /sys/power/suspend_stats/fail
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: u-b...@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> V2: Rebase on u-boot/master
> ---
> arch/arm/mach-stm32mp/stm32mp1/psci.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c
> b/arch/arm/mach-stm32mp/stm32mp1/psci.c
> index 8cdeb0ab3f2..4f2379df45f 100644
> --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c
> +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c
> @@ -703,6 +703,8 @@ void __secure psci_system_suspend(u32 __always_unused
> function_id,
> {
> u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr;
> u32 gicd_addr = stm32mp_get_gicd_base_address();
> + u32 cpu = psci_get_cpu_id();
> + u32 sp = (u32)__secure_stack_end - (cpu << ARM_PSCI_STACK_SHIFT);
> bool iwdg1_wake = false;
> bool iwdg2_wake = false;
> bool other_wake = false;
> @@ -805,4 +807,16 @@ void __secure psci_system_suspend(u32 __always_unused
> function_id,
>
> writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
> clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
> +
> + /*
> + * The system has resumed successfully. Rewrite LR register stored
> + * on stack with 'ep' value, so that on return from this PSCI call,
> + * the code would jump to that 'ep' resume entry point code path
> + * instead of the previous 'lr' register content which (e.g. with
> + * Linux) points to resume failure code path.
> + *
> + * See arch/arm/cpu/armv7/psci.S _smc_psci: for the stack layout
> + * used here, SP-4 is PC, SP-8 is LR, SP-12 is R7, and so on.
> + */
> + writel(ep, sp - 8);
> }
Applied on u-boot-stm32/master
Re: [PATCH] ARM: stm32: Drop superfluous Makefile entry for ecdsa_romapi.o
On 4/14/24 20:38, Marek Vasut wrote: > The source file is in arch/arm/mach-stm32mp/ecdsa_romapi.c and not > in arch/arm/mach-stm32mp/stm32mp1/ecdsa_romapi.c . There are two > Makefile entries in each subdirectory. Drop the bogus one and keep > only the correct one, the one in arch/arm/mach-stm32mp/Makefile . > > Signed-off-by: Marek Vasut > --- > Cc: Igor Opaniuk > Cc: Patrice Chotard > Cc: Patrick Delaunay > Cc: Simon Glass Cc: Simon Glass > Cc: Tom Rini > Cc: u-b...@dh-electronics.com > Cc: uboot-st...@st-md-mailman.stormreply.com > --- > arch/arm/mach-stm32mp/stm32mp1/Makefile | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile > b/arch/arm/mach-stm32mp/stm32mp1/Makefile > index 857148747ef..ebae50f66c9 100644 > --- a/arch/arm/mach-stm32mp/stm32mp1/Makefile > +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile > @@ -8,7 +8,6 @@ obj-y += cpu.o > obj-$(CONFIG_STM32MP13X) += stm32mp13x.o > obj-$(CONFIG_STM32MP15X) += stm32mp15x.o > > -obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o > ifdef CONFIG_SPL_BUILD > obj-y += spl.o > obj-y += tzc400.o Applied on u-boot-stm32/master
Re: [PATCH] ARM: stm32: Report OTP-CLOSED instead of rev.? on closed STM32MP15xx
On 4/14/24 20:39, Marek Vasut wrote:
> SoC revision is only accessible via DBUMCU IDC register,
> which requires BSEC.DENABLE DBGSWENABLE bit to be set to
> make the register accessible, otherwise an access to the
> register triggers bus fault. As BSEC.DBGSWENABLE is zero
> in case of an OTP-CLOSED system, do NOT set DBGSWENABLE
> bit as this might open a brief window for timing attacks.
> Instead, report that this system is OTP-CLOSED and do not
> report any SoC revision to avoid confusing users. Use an
> SEC/C abbreviation to avoid growing SOC_NAME_SIZE .
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Igor Opaniuk
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass Cc: Simon Glass
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 19 +--
> 1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
> b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
> index afc56b02eea..dd99150fbc2 100644
> --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
> +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
> @@ -322,8 +322,23 @@ void get_soc_name(char name[SOC_NAME_SIZE])
>
> get_cpu_string_offsets(, , );
>
> - snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
> - soc_type[type], soc_pkg[pkg], soc_rev[rev]);
> + if (bsec_dbgswenable()) {
> + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
> + soc_type[type], soc_pkg[pkg], soc_rev[rev]);
> + } else {
> + /*
> + * SoC revision is only accessible via DBUMCU IDC register,
> + * which requires BSEC.DENABLE DBGSWENABLE bit to be set to
> + * make the register accessible, otherwise an access to the
> + * register triggers bus fault. As BSEC.DBGSWENABLE is zero
> + * in case of an OTP-CLOSED system, do NOT set DBGSWENABLE
> + * bit as this might open a brief window for timing attacks.
> + * Instead, report that this system is OTP-CLOSED and do not
> + * report any SoC revision to avoid confusing users.
> + */
> + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s SEC/C",
> + soc_type[type], soc_pkg[pkg]);
> + }
> }
>
> static void setup_soc_type_pkg_rev(void)
Applied on u-boot-stm32/master
Re: [PATCH v2 11/11] net: dwc_eth_qos: Add support for st, ext-phyclk property
On 4/8/24 17:52, Christophe ROULLIER wrote: >> -Original Message- >> From: Marek Vasut >> Sent: Tuesday, March 26, 2024 1:08 PM >> To:u-boot@lists.denx.de >> Cc: Marek Vasut; Christophe >> ROULLIER; Joe >> Hershberger; Patrice CHOTARD - >> foss; Patrick DELAUNAY - >> foss; Ramon >> Fried;u-b...@dh-electronics.com;uboot-st...@st-md-mailman.stormreply.com >> Subject: [PATCH v2 11/11] net: dwc_eth_qos: Add support for st,ext-phyclk >> property >> >> The "st,ext-phyclk" property is a unification of "st,eth-clk-sel" >> and "st,eth-ref-clk-sel" properties. All three properties define ETH CK >> clock direction, however: >> - "st,eth-clk-sel" selects clock direction for GMII/RGMII mode >> - "st,eth-ref-clk-sel" selects clock direction for RMII mode >> - "st,ext-phyclk" selects clock direction for all RMII/GMII/RGMII modes The >> "st,ext-phyclk" is the preferrable property to use. >> >> Signed-off-by: Marek Vasut >> --- >> Cc: Christophe Roullier >> Cc: Joe Hershberger >> Cc: Patrice Chotard >> Cc: Patrick Delaunay >> Cc: Ramon Fried >> Cc:u-b...@dh-electronics.com >> Cc:uboot-st...@st-md-mailman.stormreply.com >> --- >> V2: New patch >> --- >> drivers/net/dwc_eth_qos_stm32.c | 30 +++--- >> 1 file changed, 27 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/net/dwc_eth_qos_stm32.c >> b/drivers/net/dwc_eth_qos_stm32.c index 435473f99a6..9ee82b54c62 100644 >> --- a/drivers/net/dwc_eth_qos_stm32.c >> +++ b/drivers/net/dwc_eth_qos_stm32.c >> @@ -140,6 +140,8 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev, >> const bool is_mp13 = device_is_compatible(dev, >> "st,stm32mp13-dwmac"); >> /* Gigabit Ethernet 125MHz clock selection. */ >> const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel"); >> + /* Ethernet clock source is RCC. */ >> + const bool ext_phyclk = dev_read_bool(dev, "st,ext-phyclk"); >> struct regmap *regmap; >> u32 regmap_mask; >> u32 value; >> @@ -156,6 +158,12 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev, >> dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n"); >> value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> SYSCFG_PMCSETR_ETH_SEL_GMII_MII); >> + /* >> + * STM32MP15xx supports both MII and GMII, STM32MP13xx MII >> only. >> + * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx >> and >> + * acts as a selector between 0:GMII and 1:MII. As >> STM32MP13xx >> + * supports only MII, ETH_SELMII is not present. >> + */ >> if (!is_mp13) /* Select MII mode on STM32MP15xx */ >> value |= SYSCFG_PMCSETR_ETH_SELMII; >> break; >> @@ -163,14 +171,25 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev, >> dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n"); >> value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> SYSCFG_PMCSETR_ETH_SEL_GMII_MII); >> - if (eth_clk_sel) >> + /* >> + * If eth_clk_sel is set, use internal ETH_CLKx clock from >> RCC, >> + * otherwise use external clock from IO pin (requires >> matching >> + * GPIO block AF setting of that pin). >> + */ >> + if (eth_clk_sel || ext_phyclk) >> value |= SYSCFG_PMCSETR_ETH_CLK_SEL; >> break; >> case PHY_INTERFACE_MODE_RMII: >> dev_dbg(dev, "PHY_INTERFACE_MODE_RMII\n"); >> value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> SYSCFG_PMCSETR_ETH_SEL_RMII); >> - if (eth_ref_clk_sel) >> + /* >> + * If eth_ref_clk_sel is set, use internal clock from RCC, >> + * otherwise use external clock from ETHn_RX_CLK/ETHn_REF_CLK >> + * IO pin (requires matching GPIO block AF setting of that >> + * pin). >> + */ >> + if (eth_ref_clk_sel || ext_phyclk) >> value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >>
Re: [PATCH v2 09/11] net: dwc_eth_qos: Add DT parsing for STM32MP13xx platform
On 4/8/24 17:50, Christophe ROULLIER wrote:
>> -Original Message-
>> From: Marek Vasut
>> Sent: Tuesday, March 26, 2024 1:08 PM
>> To:u-boot@lists.denx.de
>> Cc: Christophe ROULLIER; Marek
>> Vasut; Joe Hershberger; Patrice
>> CHOTARD - foss; Patrick DELAUNAY -
>> foss; Ramon
>> Fried;u-b...@dh-electronics.com;uboot-st...@st-md-mailman.stormreply.com
>> Subject: [PATCH v2 09/11] net: dwc_eth_qos: Add DT parsing for STM32MP13xx
>> platform
>>
>> From: Christophe Roullier
>>
>> Manage 2 ethernet instances, select which instance to configure with mask If
>> mask is not present in DT, it is stm32mp15 platform.
>>
>> Signed-off-by: Christophe Roullier
>> Signed-off-by: Marek Vasut # Rework the code
>> ---
>> Cc: Christophe Roullier
>> Cc: Joe Hershberger
>> Cc: Patrice Chotard
>> Cc: Patrick Delaunay
>> Cc: Ramon Fried
>> Cc:u-b...@dh-electronics.com
>> Cc:uboot-st...@st-md-mailman.stormreply.com
>> ---
>> V2: - Drop unrelated clock frequency validation
>> - Move "st,ext-phyclk" property support into separate patch
>> - This leaves only the regmap parts here
>> ---
>> drivers/net/dwc_eth_qos_stm32.c | 41 ++---
>> 1 file changed, 28 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/net/dwc_eth_qos_stm32.c
>> b/drivers/net/dwc_eth_qos_stm32.c index 0b13d01346b..5a20fe5bea2 100644
>> --- a/drivers/net/dwc_eth_qos_stm32.c
>> +++ b/drivers/net/dwc_eth_qos_stm32.c
>> @@ -23,6 +23,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>> #include
>> @@ -33,11 +34,16 @@
>>
>> /* SYSCFG registers */
>> #define SYSCFG_PMCSETR 0x04
>> -#define SYSCFG_PMCCLRR 0x44
>> +#define SYSCFG_PMCCLRR_MP13 0x08
>> +#define SYSCFG_PMCCLRR_MP15 0x44
>> +
>> +#define SYSCFG_PMCSETR_ETH1_MASK GENMASK(23, 16)
>> +#define SYSCFG_PMCSETR_ETH2_MASK GENMASK(31, 24)
>>
>> #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
>> #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
>>
>> +/* STM32MP15xx specific bit */
>> #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
>>
>> #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
>> @@ -130,23 +136,30 @@ static int eqos_probe_syscfg_stm32(struct udevice
>> *dev, {
>> /* Ethernet 50MHz RMII clock selection. */
>> const bool eth_ref_clk_sel = dev_read_bool(dev,
>> "st,eth-ref-clk-sel");
>> + /* SoC is STM32MP13xx with two ethernet MACs */
>> + const bool is_mp13 = device_is_compatible(dev, "st,stm32mp13-dwmac");
>> /* Gigabit Ethernet 125MHz clock selection. */
>> const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel");
>> - u8 *syscfg;
>> + struct regmap *regmap;
>> + u32 regmap_mask;
>> u32 value;
>>
>> - syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
>> - if (!syscfg)
>> - return -ENODEV;
>> + regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscon");
>> + if (IS_ERR(regmap))
>> + return PTR_ERR(regmap);
>> +
>> + regmap_mask = dev_read_u32_index_default(dev, "st,syscon", 2,
>> + SYSCFG_PMCSETR_ETH1_MASK);
>>
>> switch (interface_type) {
>> case PHY_INTERFACE_MODE_MII:
>> dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n");
>> value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
>> SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
>> - value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
>> + if (!is_mp13) /* Select MII mode on STM32MP15xx */
>> + value |= SYSCFG_PMCSETR_ETH_SELMII;
>> break;
>> - case PHY_INTERFACE_MODE_GMII:
>> + case PHY_INTERFACE_MODE_GMII: /* STM32MP15xx only */
>> dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n");
>> value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
>> SYSCFG_PMCSETR_ETH_SEL_GMII_MII); @@
>> -177,13 +190,15 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,
>> return -EINVAL;
>> }
>>
>> - /* clear and set ETH configuration bits */
>> - writel
