[U-Boot] [PATCH][v2] net: fman: fix 2.5G SGMII settings

[Shaohui Xie]

The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
---
changes in v2:
1. code style changes for readability.
2. uses leading 0's in values set to PHY registers.

 drivers/net/fm/eth.c   | 33 +++--
 drivers/net/fm/memac.c |  1 +
 include/fsl_memac.h|  1 +
 3 files changed, 25 insertions(+), 10 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index eb8e936..bf5f89b 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -45,9 +45,12 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
 
 qsgmii_loop:
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
-   value = PHY_SGMII_IF_MODE_SGMII;
-   if (!sgmii_2500)
-   value |= PHY_SGMII_IF_MODE_AN;
+   if (sgmii_2500)
+   value = PHY_SGMII_CR_PHY_RESET |
+   PHY_SGMII_IF_SPEED_GIGABIT |
+   PHY_SGMII_IF_MODE_SGMII;
+   else
+   value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
 
memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x14, value);
 
@@ -55,15 +58,24 @@ qsgmii_loop:
value = PHY_SGMII_DEV_ABILITY_SGMII;
memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x4, value);
 
-   /* Adjust link timer for SGMII  -
-   1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
-   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x13, 0x3);
-   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
+   if (sgmii_2500) {
+   /* Adjust link timer for 2.5G SGMII,
+* 1.6 ms in units of 3.2 ns:
+* 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
+*/
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
+   } else {
+   /* Adjust link timer for SGMII,
+* 1.6 ms in units of 8 ns:
+* 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
+*/
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
+   }
 
/* Restart AN */
-   value = PHY_SGMII_CR_DEF_VAL;
-   if (!sgmii_2500)
-   value |= PHY_SGMII_CR_RESET_AN;
+   value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
memac_mdio_write(, i, MDIO_DEVAD_NONE, 0, value);
 
if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
@@ -391,6 +403,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth)
 
/* For some reason we need to set SPEED_100 */
if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
+(fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
  mac->set_if_mode)
mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 81a64bf..1b5779c 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -90,6 +90,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
if_mode |= (IF_MODE_GMII | IF_MODE_RM);
break;
case PHY_INTERFACE_MODE_SGMII:
+   case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_QSGMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= (IF_MODE_GMII);
diff --git a/include/fsl_memac.h b/include/fsl_memac.h
index bed2a40..431c2a0 100644
--- a/include/fsl_memac.h
+++ b/include/fsl_memac.h
@@ -226,6 +226,7 @@ struct memac {
 #define PHY_SGMII_CR_PHY_RESET  0x8000
 #define PHY_SGMII_CR_RESET_AN   0x0200
 #define PHY_SGMII_CR_DEF_VAL0x1140
+#define PHY_SGMII_IF_SPEED_GIGABIT  0x0008
 #define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
 #define PHY_SGMII_IF_MODE_AN0x0002
 #define PHY_SGMII_IF_MODE_SGMII 0x0001
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] [resend] net: fman: fix 2.5G SGMII settings

[Shaohui Xie]

The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
---
not sure what was wrong, the patch did not show in patchwork, so resend it.
Sorry for the bothering.

 drivers/net/fm/eth.c   | 32 ++--
 drivers/net/fm/memac.c |  1 +
 include/fsl_memac.h|  1 +
 3 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index eb8e936..543aaa8 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -45,9 +45,11 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
 
 qsgmii_loop:
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
-   value = PHY_SGMII_IF_MODE_SGMII;
-   if (!sgmii_2500)
-   value |= PHY_SGMII_IF_MODE_AN;
+   value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
+   if (sgmii_2500)
+   value = PHY_SGMII_CR_PHY_RESET |
+   PHY_SGMII_IF_SPEED_GIGABIT |
+   PHY_SGMII_IF_MODE_SGMII;
 
memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x14, value);
 
@@ -55,15 +57,24 @@ qsgmii_loop:
value = PHY_SGMII_DEV_ABILITY_SGMII;
memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x4, value);
 
-   /* Adjust link timer for SGMII  -
-   1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
-   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x13, 0x3);
-   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
+   if (sgmii_2500) {
+   /* Adjust link timer for 2.5G SGMII,
+* 1.6 ms in units of 3.2 ns:
+* 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
+*/
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
+   } else {
+   /* Adjust link timer for SGMII,
+* 1.6 ms in units of 8 ns:
+* 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
+*/
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x13, 0x3);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
+   }
 
/* Restart AN */
-   value = PHY_SGMII_CR_DEF_VAL;
-   if (!sgmii_2500)
-   value |= PHY_SGMII_CR_RESET_AN;
+   value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
memac_mdio_write(, i, MDIO_DEVAD_NONE, 0, value);
 
if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
@@ -391,6 +402,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth)
 
/* For some reason we need to set SPEED_100 */
if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
+(fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
  mac->set_if_mode)
mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 81a64bf..1b5779c 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -90,6 +90,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
if_mode |= (IF_MODE_GMII | IF_MODE_RM);
break;
case PHY_INTERFACE_MODE_SGMII:
+   case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_QSGMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= (IF_MODE_GMII);
diff --git a/include/fsl_memac.h b/include/fsl_memac.h
index bed2a40..431c2a0 100644
--- a/include/fsl_memac.h
+++ b/include/fsl_memac.h
@@ -226,6 +226,7 @@ struct memac {
 #define PHY_SGMII_CR_PHY_RESET  0x8000
 #define PHY_SGMII_CR_RESET_AN   0x0200
 #define PHY_SGMII_CR_DEF_VAL0x1140
+#define PHY_SGMII_IF_SPEED_GIGABIT  0x0008
 #define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
 #define PHY_SGMII_IF_MODE_AN0x0002
 #define PHY_SGMII_IF_MODE_SGMII 0x0001
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH 5/8] armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone app

[Shaohui Xie]

> On 08/26/2016 04:40 AM, Gong Qianyu wrote:
> > From: Shaohui Xie <shaohui@nxp.com>
> >
> > The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
> >
> > Signed-off-by: Shaohui Xie <shaohui@nxp.com>
> > Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
> > ---
> >  arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > index b0ad4b4..c7e374c 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > @@ -9,6 +9,8 @@
> >
> >  #include 
> >
> > +#define CONFIG_STANDALONE_LOAD_ADDR0x8030
> > +
> 
> Do you really need this? It is default to 0x8030 in arch/arm/config.mk.
[S.H] It's needed, in the arch/arm/config.mk, it's defined as:

ifndef CONFIG_STANDALONE_LOAD_ADDR
ifneq ($(CONFIG_OMAP_COMMON),)
CONFIG_STANDALONE_LOAD_ADDR = 0x8030
else
CONFIG_STANDALONE_LOAD_ADDR = 0xc10
endif
endif

we need the CONFIG_STANDALONE_LOAD_ADDR defined as a valid address for ARM.
The proposed patch is to clearly define the CONFIG_STANDALONE_LOAD_ADDR for our 
SOCs.

Thanks,
Shaohui



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Re: [U-Boot] [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR

[Shaohui Xie]

> -Original Message-
> From: york sun
> Sent: Saturday, August 27, 2016 12:08 AM
> To: Qianyu Gong <qianyu.g...@nxp.com>; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>; Mingkai Hu
> <mingkai...@nxp.com>; Shaohui Xie <shaohui@nxp.com>; Zhiqiang Hou
> <zhiqiang@nxp.com>; Wenbin Song <wenbin.s...@nxp.com>
> Subject: Re: [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR
> 
> On 08/26/2016 04:40 AM, Gong Qianyu wrote:
> > From: Shaohui Xie <shaohui@nxp.com>
> >
> > So to fix SATA CRC error.
> 
> Does ECC cause the CRC error? Please explain more what you are doing in this
> patch.
[S.H] We only know disable ECC can fix CRC error which provided by validation 
team
As a workaround, the root cause is not clear.

Maybe we can drop it for now, there might be a better solution for this issue 
in future, 
or the solution is still the same, but we know exactly what is going on.

Thanks,
Shaohui

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Re: [U-Boot] [PATCH 2/2] board/t4240rdb: some ethernet ports shouldn't be detected

[Shaohui Xie]

Hi Ying,

The commit message should be more clear about what is wrong.
Like when using protocols to support 10G on MAC9 and MAC10, these
MACs should not be identified as 1G interface, otherwise, one MAC will be
Listed as two Ethernet ports, for ex. MAC9 will be listed as FM1@TGEC1
And FM1@DTSEC9.

Thanks,
Shaohui

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Shengzhou Liu
> Sent: Friday, April 15, 2016 3:58 PM
> To: ying.zh...@freescale.com; u-boot@lists.denx.de
> Cc: york...@freescale.com; Ying Zhang 
> Subject: Re: [U-Boot] [PATCH 2/2] board/t4240rdb: some ethernet ports 
> shouldn't
> be detected
> 
> 
> 
> > -Original Message-
> > From: Shengzhou Liu
> > Sent: Friday, April 15, 2016 3:45 PM
> > To: 'ying.zh...@freescale.com' ; u-
> > b...@lists.denx.de
> > Cc: york...@freescale.com; Ying Zhang 
> > Subject: RE: [U-Boot] [PATCH 2/2] board/t4240rdb: some ethernet ports
> > shouldn't be detected
> >
> >
> > > -Original Message-
> > > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of
> > > ying.zh...@freescale.com
> > > Sent: Friday, April 15, 2016 2:19 PM
> > > To: u-boot@lists.denx.de
> > > Cc: york...@freescale.com; Ying Zhang 
> > > Subject: [U-Boot] [PATCH 2/2] board/t4240rdb: some ethernet ports
> > > shouldn't be detected
> > >
> > > From: Ying Zhang 
> > >
> > > FM1_DTSEC9 & FM1_DTSEC10 should not be detected.
> > >
> > > Signed-off-by: Ying Zhang 
> > > ---
> > >  drivers/net/fm/t4240.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c index
> > > ae5aca4..70887fa 100644
> > > --- a/drivers/net/fm/t4240.c
> > > +++ b/drivers/net/fm/t4240.c
> > > @@ -74,7 +74,7 @@ phy_interface_t fman_port_enet_if(enum fm_port
> > port)
> > >   if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) &&
> > >   ((is_serdes_configured(XFI_FM1_MAC9)) ||
> > >(is_serdes_configured(XFI_FM1_MAC10
> > > - return PHY_INTERFACE_MODE_XGMII;
> > > + return PHY_INTERFACE_MODE_NONE;
> >
> > This patch is making things wrongly, FM1_DTSEC9 & FM1_DTSEC10 should
> > be configured when RCW uses the these MACs.
> > -Shengzhou
> Sorry, I missed the condition, the change is right.
> Shengzhou
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Re: [U-Boot] [PATCH 1/2] net: phy: introduce a quirk PHY_BROKEN_RESET

[Shaohui Xie]

> -Original Message-
> From: Joe Hershberger [mailto:joe.hershber...@gmail.com]
> Sent: Wednesday, January 27, 2016 11:37 PM
> To: shaohui 谢 <shh@gmail.com>
> Cc: u-boot <u-boot@lists.denx.de>; Joe Hershberger <joe.hershber...@ni.com>;
> Shaohui Xie <shaohui@nxp.com>; York Sun <york...@freescale.com>
> Subject: Re: [U-Boot] [PATCH 1/2] net: phy: introduce a quirk PHY_BROKEN_RESET
> 
> On Tue, Jan 12, 2016 at 3:55 AM,  <shh@gmail.com> wrote:
> > From: Shaohui Xie <shaohui@nxp.com>
> >
> > Current driver always performs a phy soft reset when connecting the
> > phy device, but soft reset is not always supported by a phy device, so
> > introduce a quirk PHY_BROKEN_RESET to let such a phy device to skip
> > soft reset. This commit uses 'flags' of phy device structure to store
> > the quirk.
> >
> > Signed-off-by: Shaohui Xie <shaohui@nxp.com>
> > ---
> >  drivers/net/phy/phy.c | 3 +++
> >  include/phy.h | 1 +
> >  2 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index
> > 51b5746..2a36ae7 100644
> > --- a/drivers/net/phy/phy.c
> > +++ b/drivers/net/phy/phy.c
> > @@ -707,6 +707,9 @@ int phy_reset(struct phy_device *phydev)
> > int timeout = 500;
> > int devad = MDIO_DEVAD_NONE;
> >
> > +   if (phydev->flags == PHY_BROKEN_RESET)
> 
> Please mask off this bit so this test still work if someone adds a different 
> flag.
> 
> E.g.: if (phydev->flags & PHY_BROKEN_RESET)
[S.H] OK. Will fix it.

> 
> > +   return 0;
> > +
> >  #ifdef CONFIG_PHYLIB_10G
> > /* If it's 10G, we need to issue reset through one of the MMDs */
> > if (is_10g_interface(phydev->interface)) { diff --git
> > a/include/phy.h b/include/phy.h index 66cf61b..5f604a1 100644
> > --- a/include/phy.h
> > +++ b/include/phy.h
> > @@ -16,6 +16,7 @@
> >  #include 
> >
> >  #define PHY_MAX_ADDR 32
> > +#define PHY_BROKEN_RESET   (1 << 0) /* soft reset not supported */
> 
> Please name this something like PHY_FLAG_BROKEN_RESET.
[S.H] OK. Will do.

Thank you!
Shaohui
> 
> >
> >  #define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
> >  SUPPORTED_10baseT_Full | \
> > --
> > 2.1.0.27.g96db324
> >
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Re: [U-Boot] [PATCH 1/3] armv8/ls1043aqds: add DSPI support

[Shaohui Xie]

> -Original Message-
> From: Gong Qianyu [mailto:qianyu.g...@nxp.com]
> Sent: Thursday, December 24, 2015 4:40 PM
> To: u-boot@lists.denx.de
> Cc: Mingkai Hu; r58...@freescale.com; b48...@freescale.com;
> shaohui@freescale.com; wenbin.s...@freescale.com;
> b07...@freescale.com; Gong Qianyu; Qianyu Gong
> Subject: [PATCH 1/3] armv8/ls1043aqds: add DSPI support
> 
> From: Gong Qianyu 
> 
> Enable three DSPI flash memories on board.
> 
> Commands:
> => sf probe 1:0
> SF: Detected N25Q128A with page size 256 Bytes,
>   erase size 64 KiB, total 16 MiB
> => sf probe 1:1
> SF: Detected SST25WF040B with page size 256 Bytes,
>   erase size 4 KiB, total 512 KiB
> => sf probe 1:2
> SF: Detected EN25S64 with page size 256 Bytes,
>   erase size 64 KiB, total 8 MiB
> 
> Signed-off-by: Gong Qianyu 
> Signed-off-by: Gong Qianyu 
[S.H] keep one email address.

> ---
>  arch/arm/dts/fsl-ls1043a-qds.dts| 30
> ++
>  configs/ls1043aqds_defconfig|  3 +++
>  configs/ls1043aqds_nand_defconfig   |  5 +
>  configs/ls1043aqds_sdcard_ifc_defconfig |  5 +
>  include/configs/ls1043a_common.h| 13 +
>  include/configs/ls1043ardb.h| 10 --
>  6 files changed, 56 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts b/arch/arm/dts/fsl-ls1043a-
> qds.dts
> index 7435222..0fe9c54 100644
> --- a/arch/arm/dts/fsl-ls1043a-qds.dts
> +++ b/arch/arm/dts/fsl-ls1043a-qds.dts
> @@ -15,6 +15,36 @@
> 
>  / {
>   model = "LS1043A QDS Board";
> + aliases {
> + spi1 = 
> + };
> +};
> +
> + {
> + bus-num = <0>;
> + status = "okay";
> +
> + dflash0: n25q128a {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "spi-flash";
> + reg = <0>;
> + spi-max-frequency = <100>; /* input clock */
> + };
[S.H] empty line.

> + dflash1: sst25wf040b {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "spi-flash";
> + spi-max-frequency = <350>;
> + reg = <1>;
> + };
[S.H] ditto.

> + dflash2: en25s64 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "spi-flash";
> + spi-max-frequency = <350>;
> + reg = <2>;
> + };
>  };
> 
>   {
> diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
> index 60fb0ad..5b12632 100644
> --- a/configs/ls1043aqds_defconfig
> +++ b/configs/ls1043aqds_defconfig
> @@ -4,3 +4,6 @@ CONFIG_TARGET_LS1043AQDS=y  CONFIG_SYS_NS16550=y
> CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
>  CONFIG_OF_CONTROL=y
> +CONFIG_DM=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_DM_SPI=y
> diff --git a/configs/ls1043aqds_nand_defconfig
> b/configs/ls1043aqds_nand_defconfig
> index e9d5afd..d4f758c 100644
> --- a/configs/ls1043aqds_nand_defconfig
> +++ b/configs/ls1043aqds_nand_defconfig
> @@ -3,3 +3,8 @@
> CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
>  CONFIG_ARM=y
>  CONFIG_TARGET_LS1043AQDS=y
>  CONFIG_SYS_NS16550=y
> +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
> +CONFIG_OF_CONTROL=y
> +CONFIG_DM=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_DM_SPI=y
> diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig
> b/configs/ls1043aqds_sdcard_ifc_defconfig
> index 6765d3d..25ae9cc 100644
> --- a/configs/ls1043aqds_sdcard_ifc_defconfig
> +++ b/configs/ls1043aqds_sdcard_ifc_defconfig
> @@ -3,3 +3,8 @@
> CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
>  CONFIG_ARM=y
>  CONFIG_TARGET_LS1043AQDS=y
>  CONFIG_SYS_NS16550=y
> +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
> +CONFIG_OF_CONTROL=y
> +CONFIG_DM=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_DM_SPI=y
> diff --git a/include/configs/ls1043a_common.h
> b/include/configs/ls1043a_common.h
> index 677d281..139d1d4 100644
> --- a/include/configs/ls1043a_common.h
> +++ b/include/configs/ls1043a_common.h
> @@ -197,6 +197,19 @@
>  #define CONFIG_DOS_PARTITION
>  #endif
> 
> +/*  DSPI  */
> +#define CONFIG_FSL_DSPI
> +#ifdef CONFIG_FSL_DSPI
> +#define CONFIG_CMD_SF
> +#define CONFIG_DM_SPI_FLASH
> +#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
> +#define CONFIG_SPI_FLASH_SST /* cs1 */
> +#define CONFIG_SPI_FLASH_EON /* cs2 */
> +#define CONFIG_SF_DEFAULT_BUS1
> +#define CONFIG_SF_DEFAULT_CS 0
> +#endif
> +
> +
[S.H] remove one empty line.

>  /* FMan ucode */
>  #define CONFIG_SYS_DPAA_FMAN
>  #ifdef CONFIG_SYS_DPAA_FMAN
> diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
> index 585114f..f768348 100644
> --- a/include/configs/ls1043ardb.h
> +++ b/include/configs/ls1043ardb.h
> @@ -222,16 +222,6 @@
>  #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS3
>  

Re: [U-Boot] [PATCH] eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

[Shaohui Xie]

Hi,

As mentioned, the value 0x4001 is the desired one in AN3869 for SGMII setting,
quoted as below:
" Program TBI ANA = 0x4001 (SGMII) or 0x01A0 (1000BASE-X). "

I think the AN3869 should be followed, change SGMII setting just because it 
worked on P2041rdb is not a good reason.

To distinguish SGMII from other connections should be the way to program TBI 
ANA,
This is also follow the AN3869.

Best Regards, 
Shaohui Xie


> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Monday, December 14, 2015 11:55 AM
> To: 李远正; Xie Shaohui-B21989
> Cc: Ciubotariu Codrin Constantin-B43658; u-boot@lists.denx.de; Liu Dave-
> R63238
> Subject: Re: [PATCH] eth: dtsec: fix TBI ANA setting bug in
> dtsec_configure_serdes()
> 
> Shaohui,
> 
> Please comment/confirm.
> 
> York
> 
> On 12/09/2015 10:25 PM, 李远正 wrote:
> > The value TBIANA_SETTINGS is also work on the p2041rdb board, so it
> > can work on the both phy and phyless connections.
> >
> >
> >
> > At 2015-11-26 12:17:42, "Shaohui Xie" <shaohui@freescale.com> wrote:
> >>> -Original Message-
> >>> From: York Sun [mailto:york...@freescale.com]
> >>> Sent: Thursday, November 26, 2015 1:03 AM
> >>> To: Xie Shaohui-B21989; Ciubotariu Codrin Constantin-B43658
> >>> Cc: Yuanzheng Li; u-boot@lists.denx.de; Liu Dave-R63238
> >>> Subject: Re: [PATCH] eth: dtsec: fix TBI ANA setting bug in
> >>> dtsec_configure_serdes()
> >>>
> >>> + Experts
> >>>
> >>> On 11/24/2015 11:04 PM, Yuanzheng Li wrote:
> >>> > The TBI_ANA register is configurated with the wrong value 0x4001,
> >>> > refer to QorIQ Data Path Acceleration Architecture (DPAA)
> >>> > Reference
> >>> Manual.
> >>> > It set the reserved areas, bit 1 and bit 11 to bit 15 in big
> >>> > endian, which should be cleared. But the normal functions of the
> >>> > auto-negotiation, e.g. Pause and Full Duplex, do not be set.
> >>[S.H] The value 0x4001 is so special, as mentioned, it does not match
> >>the DPAA RM, So I dig some docs and found AN3869, in which the 0x4001
> >>is the desired one to write to TBI_ANA for SGMII.
> >>
> >>> >
> >>> > There is no problem in the p2041rdb board, because the ppc is
> >>> > connected directly with the phy chip which support
> >>> > auto-negotiation by default in SGMII interface. But the link
> >>> > problem will occur when it is connected with a switch chip like
> >>> > BCM5389, the switch chip disable auto-negotiation by default, and
> >>> > the ppc also disable auto-negotiation, then there is no link
> between them.
> >>[S.H] This seems a phyless connection. If BCM5389 disables AN, then
> >>PPC should Also disable AN by setting TBI_CR.
> >>
> >>> >
> >>> > So use the vlue TBIANA_SETTINGS to enable the ppc's auto-
> negotiation.
> >>[S.H] The TBI_ANA is " AN Advertisement Register ", it does not
> enable/disable AN.
> >>A proper way should be to distinguish the phy and phyless connections
> >>and configure The TBI registers accordingly.
> >>
> >>Thanks,
> >>Shaohui
> >>
> >>> >
> >>> > Signed-off-by: Yuanzheng Li <liyuanzhen...@163.com>
> >>> > Cc: York Sun <york...@freescale.com>
> >>> > ---
> >>> >  drivers/net/fm/eth.c |2 +-
> >>> >  1 files changed, 1 insertions(+), 1 deletions(-)
> >>> >
> >>> > diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index
> >>> > eb8e936..78c0988 100644
> >>> > --- a/drivers/net/fm/eth.c
> >>> > +++ b/drivers/net/fm/eth.c
> >>> > @@ -81,7 +81,7 @@ qsgmii_loop:
> >>> > tsec_local_mdio_write(phyregs, in_be32(>tbipa), 0,
> TBI_TBICON,
> >>> > TBICON_CLK_SELECT);
> >>> > tsec_local_mdio_write(phyregs, in_be32(>tbipa), 0,
> TBI_ANA,
> >>> > -   TBIANA_SGMII_ACK);
> >>> > +   TBIANA_SETTINGS);
> >>> > tsec_local_mdio_write(phyregs, in_be32(>tbipa), 0,
> >>> > TBI_CR, TBICR_SETTINGS);
> >>> >  #endif
> >>> >
> >>>
> >>> Yuanzheng,
> >>>
> >>> After your change, TBIANA_SGMII_ACK is not used and should be removed.
> >>>
> >>> Shaohui and Codrin,
> >>>
> >>> Please comment.
> >>>
> >>> York
> >
> >
> >
> >
> >
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Re: [U-Boot] [PATCH] eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()

[Shaohui Xie]

> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Thursday, November 26, 2015 1:03 AM
> To: Xie Shaohui-B21989; Ciubotariu Codrin Constantin-B43658
> Cc: Yuanzheng Li; u-boot@lists.denx.de; Liu Dave-R63238
> Subject: Re: [PATCH] eth: dtsec: fix TBI ANA setting bug in
> dtsec_configure_serdes()
> 
> + Experts
> 
> On 11/24/2015 11:04 PM, Yuanzheng Li wrote:
> > The TBI_ANA register is configurated with the wrong value 0x4001,
> > refer to QorIQ Data Path Acceleration Architecture (DPAA) Reference
> Manual.
> > It set the reserved areas, bit 1 and bit 11 to bit 15 in big endian,
> > which should be cleared. But the normal functions of the
> > auto-negotiation, e.g. Pause and Full Duplex, do not be set.
[S.H] The value 0x4001 is so special, as mentioned, it does not match the 
DPAA RM, So I dig some docs and found AN3869, in which the 0x4001 is the
desired one to write to TBI_ANA for SGMII.
 
> >
> > There is no problem in the p2041rdb board, because the ppc is
> > connected directly with the phy chip which support auto-negotiation by
> > default in SGMII interface. But the link problem will occur when it is
> > connected with a switch chip like BCM5389, the switch chip disable
> > auto-negotiation by default, and the ppc also disable
> > auto-negotiation, then there is no link between them.
[S.H] This seems a phyless connection. If BCM5389 disables AN, then PPC should
Also disable AN by setting TBI_CR.

> >
> > So use the vlue TBIANA_SETTINGS to enable the ppc's auto-negotiation.
[S.H] The TBI_ANA is " AN Advertisement Register ", it does not enable/disable 
AN.
A proper way should be to distinguish the phy and phyless connections and 
configure
The TBI registers accordingly.

Thanks,
Shaohui

> >
> > Signed-off-by: Yuanzheng Li 
> > Cc: York Sun 
> > ---
> >  drivers/net/fm/eth.c |2 +-
> >  1 files changed, 1 insertions(+), 1 deletions(-)
> >
> > diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index
> > eb8e936..78c0988 100644
> > --- a/drivers/net/fm/eth.c
> > +++ b/drivers/net/fm/eth.c
> > @@ -81,7 +81,7 @@ qsgmii_loop:
> > tsec_local_mdio_write(phyregs, in_be32(>tbipa), 0, TBI_TBICON,
> > TBICON_CLK_SELECT);
> > tsec_local_mdio_write(phyregs, in_be32(>tbipa), 0, TBI_ANA,
> > -   TBIANA_SGMII_ACK);
> > +   TBIANA_SETTINGS);
> > tsec_local_mdio_write(phyregs, in_be32(>tbipa), 0,
> > TBI_CR, TBICR_SETTINGS);
> >  #endif
> >
> 
> Yuanzheng,
> 
> After your change, TBIANA_SGMII_ACK is not used and should be removed.
> 
> Shaohui and Codrin,
> 
> Please comment.
> 
> York
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Re: [U-Boot] [PATCH] armv8: fsl-layerscape: added XFI protocol support for fsl_lsch3

[Shaohui Xie]

Please ignore this patch, I just saw some Freescale internal changes, the patch 
is obsolete.

Best Regards, 
Shaohui Xie

> -Original Message-
> From: shh@gmail.com [mailto:shh@gmail.com]
> Sent: Tuesday, November 10, 2015 7:12 PM
> To: u-boot@lists.denx.de; Sun York-R58495
> Cc: Xie Shaohui-B21989
> Subject: [PATCH] armv8: fsl-layerscape: added XFI protocol support for
> fsl_lsch3
> 
> From: Shaohui Xie <shaohui@freescale.com>
> 
> This needed to init dpmac.
> 
> Signed-off-by: Shaohui Xie <shaohui@freescale.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> index 2ab8da6..67c3a45 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> @@ -120,6 +120,10 @@ void serdes_init(u32 sd, u32 sd_addr, u32
> sd_prctl_mask, u32 sd_prctl_shift,
>  lane_prtcl <= SGMII16)
>   wriop_init_dpmac(sd, lane + 1,
>(int)lane_prtcl);
> +  if (lane_prtcl >= XFI1 &&
> +  lane_prtcl <= XFI8)
> + wriop_init_dpmac(sd, lane + 1,
> +  (int)lane_prtcl);
>   break;
>   }
>  #endif
> --
> 2.1.0.27.g96db324

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Re: [U-Boot] [PATCH] powerpc/t4240qds: add support of reading Core voltage

[Shaohui Xie]

> On 08/25/2015 01:30 AM, shh@gmail.com wrote:
> > From: Shaohui Xie <shaohui@freescale.com>
> >
> > A U-boot CMD vdd_read is implemented to read Core voltage.
> 
> Can you explain why you need this command? You already get the voltage if
> you run bdinfo. If you override vdd, you also get a print.
> 
[S.H] there was a request that the commands override_vdd and vdd_read should be
Supported pair wise on T4240QDS, like what T2080RDB does... 

So if the request is not really necessary, we can drop it.

Thanks!
Shaohui

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Re: [U-Boot] [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2

[Shaohui Xie]

> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, September 18, 2015 2:05 AM
> To: Gong Qianyu-B52263
> Cc: u-boot@lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou
> Zhiqiang-B48286; Song Wenbin-B53747; Xie Shaohui-B21989; Wood Scott-
> B07421
> Subject: Re: [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2
> 
> On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> > From: Shaohui Xie <shaohui@freescale.com>
> >
> > MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
> > plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are
> > two FMANs, so we should only define MDIO controller base on FMAN2 when
> > there is FMAN2.
> >
> > Signed-off-by: Shaohui Xie <shaohui@freescale.com>
> > Signed-off-by: Mingkai Hu <mingkai...@freescale.com>
> > Signed-off-by: Gong Qianyu <qianyu.g...@freescale.com>
> > ---
> >  include/fm_eth.h | 17 +
> >  1 file changed, 17 insertions(+)
> >
> > diff --git a/include/fm_eth.h b/include/fm_eth.h index
> > 3e1b9f4..d43f801 100644
> > --- a/include/fm_eth.h
> > +++ b/include/fm_eth.h
> > @@ -45,8 +45,10 @@ enum fm_eth_type {
> >  #ifdef CONFIG_SYS_FMAN_V3
> >  #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR   (CONFIG_SYS_FSL_FM1_ADDR
> + 0xfc000)
> >  #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR(CONFIG_SYS_FSL_FM1_ADDR
> + 0xfd000)
> > +#if (CONFIG_SYS_NUM_FMAN == 2)
> >  #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR   (CONFIG_SYS_FSL_FM2_ADDR
> + 0xfc000)
> >  #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR(CONFIG_SYS_FSL_FM2_ADDR
> + 0xfd000)
> > +#endif
> >  #else
> >  #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR  (CONFIG_SYS_FSL_FM1_ADDR
> + 0xe1120)
> >  #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR(CONFIG_SYS_FSL_FM1_ADDR
> + 0xf1000)
> > @@ -89,6 +91,7 @@ enum fm_eth_type {
> >offsetof(struct ccsr_fman,
> > memac[n-1]),\  }  #else
> > +#if (CONFIG_SYS_NUM_FMAN == 2)
> > #define FM_TGEC_INFO_INITIALIZER(idx, n) \
> >  {\
> >   FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
> > @@ -101,6 +104,20 @@ enum fm_eth_type {
> >   .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
> >   offsetof(struct ccsr_fman,
> > memac[n-1+8]),\  }
> > +#else
> > +#define FM_TGEC_INFO_INITIALIZER(idx, n) \
> > +{\
> > + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
> > + .index  = idx,  \
> > + .num= n - 1,\
> > + .type   = FM_ETH_10G_E, \
> > + .port   = FM##idx##_10GEC##n,   \
> > + .rx_port_id = RX_PORT_10G_BASE + n - 1, \
> > + .tx_port_id = TX_PORT_10G_BASE + n - 1, \
> > + .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
> > + offsetof(struct ccsr_fman,
> > +memac[n-1+8]),\ } #endif
> >  #endif
> 
> doc/README.fsl-dpaa says that CONFIG_FSL_FM_10GEC_REGULAR_NOTATION is for
> newer SoCs.  Presumably this patch is for ls1043a -- is that not
> considered a newer SoC?  Or does the README need to be fixed?
[S.H] Yes, this is for LS1043A. LS1043A has one FMAN same as T2080. 
A new SoC but has an old DPAA.

The issue this patch intends to fix is there is only one FMAN on LS1043A,
So CONFIG_SYS_FSL_FM2_ADDR is not defined on LS1043A, the define of MDIO 
controller base
On FMAN2 uses CONFIG_SYS_FSL_FM2_ADDR caused error on LS1043A.

Thanks!
Shaohui


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Re: [U-Boot] [PATCH] t4240qds: apply some updates

[Shaohui Xie]

 On 04/27/2015 12:28 AM, shh@gmail.com wrote:
  From: Shaohui Xie shaohui@freescale.com
 
  1. board/freescale/t4qds/t4_rcw.cfg
  1.8GHz support is requested as default frequency, so update the rcw.
 
  2. remove un-used configs
  configs/T4160QDS_SPIFLASH_defconfig
  configs/T4240QDS_SPIFLASH_defconfig
  SPI boot is not available on T4QDS, so the configs should be removed.
 
  3. board/freescale/t4qds/MAINTAINERS
  Updated MAINTAINERS accordingly.
 
  Signed-off-by: Shaohui Xie shaohui@freescale.com
  ---
 
 I will rewrite the subject to powerpc/t4240qds: Update RCW, defconfig
 and maintainer. No action for you.
Thank you!

Best Regards, 
Shaohui Xie


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Re: [U-Boot] [PATCH] powerpc/mpc85xx: Use GOT when loading IVORs post-relocation

[Shaohui Xie]

 -Original Message-
 From: Wood Scott-B07421
 Sent: Friday, April 24, 2015 9:02 AM
 To: u-boot@lists.denx.de; Sun York-R58495
 Cc: Wood Scott-B07421; Alexander Graf; Xie Shaohui-B21989
 Subject: [PATCH] powerpc/mpc85xx: Use GOT when loading IVORs post-
 relocation
 
 Commit 96d2bb952bb (powerpc/mpc85xx: Don't relocate exception vectors)
 simplified IVOR initialization a bit too much, failing to use the post-
 relocation offset.  This doesn't cause a problem with normal NOR boot, in
 which both the pre-relocation and post-relocation addresses are 64 KiB
 aligned.  However, if TEXT_BASE is only 4 KiB aligned, such as for
 NAND/SD/etc. boot on some targets, as well as the QEMU target, the post-
 relocation address will not be the same in the lower 16 bits, as
 reserve_uboot() ensures that the relocation address is always 64 KiB
 aligned even if the pre-relocation address was not.
 
 Use the GOT to get the proper post-relocation offsets.
 
 Fixes: 96d2bb952bb (powerpc/mpc85xx: Don't relocate exception vectors)
 Signed-off-by: Scott Wood scottw...@freescale.com
 Cc: Alexander Graf ag...@suse.de
 Cc: Shaohui Xie shaohui@freescale.com
 ---
  arch/powerpc/cpu/mpc85xx/start.S | 35 --
 -
  1 file changed, 20 insertions(+), 15 deletions(-)
 

Tested-by: Shaohui Xie shaohui@freescale.com
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Re: [U-Boot] [PATCH] powerpc/mpc85xx: Use GOT when loading IVORs post-relocation

[Shaohui Xie]

Tested on T4240QDS_NAND and T4240QDS_SDCARD, the hang issue fixed.
Thanks!

Best Regards, 
Shaohui Xie

 -Original Message-
 From: Wood Scott-B07421
 Sent: Friday, April 24, 2015 9:02 AM
 To: u-boot@lists.denx.de; Sun York-R58495
 Cc: Wood Scott-B07421; Alexander Graf; Xie Shaohui-B21989
 Subject: [PATCH] powerpc/mpc85xx: Use GOT when loading IVORs post-
 relocation
 
 Commit 96d2bb952bb (powerpc/mpc85xx: Don't relocate exception vectors)
 simplified IVOR initialization a bit too much, failing to use the post-
 relocation offset.  This doesn't cause a problem with normal NOR boot, in
 which both the pre-relocation and post-relocation addresses are 64 KiB
 aligned.  However, if TEXT_BASE is only 4 KiB aligned, such as for
 NAND/SD/etc. boot on some targets, as well as the QEMU target, the post-
 relocation address will not be the same in the lower 16 bits, as
 reserve_uboot() ensures that the relocation address is always 64 KiB
 aligned even if the pre-relocation address was not.
 
 Use the GOT to get the proper post-relocation offsets.
 
 Fixes: 96d2bb952bb (powerpc/mpc85xx: Don't relocate exception vectors)
 Signed-off-by: Scott Wood scottw...@freescale.com
 Cc: Alexander Graf ag...@suse.de
 Cc: Shaohui Xie shaohui@freescale.com
 ---
  arch/powerpc/cpu/mpc85xx/start.S | 35 --
 -
  1 file changed, 20 insertions(+), 15 deletions(-)
 
 diff --git a/arch/powerpc/cpu/mpc85xx/start.S
 b/arch/powerpc/cpu/mpc85xx/start.S
 index 28f04ee..e61d8e0 100644
 --- a/arch/powerpc/cpu/mpc85xx/start.S
 +++ b/arch/powerpc/cpu/mpc85xx/start.S
 @@ -1664,41 +1664,46 @@ clear_bss:
*/
   .globl  trap_init
  trap_init:
 + mflrr11
 + bl  _GLOBAL_OFFSET_TABLE_-4
 + mflrr12
 +
   /* Update IVORs as per relocation */
   mtspr   IVPR,r3
 
 - li  r4,CriticalInput@l
 + lwz r4,CriticalInput@got(r12)
   mtspr   IVOR0,r4/* 0: Critical input */
 - li  r4,MachineCheck@l
 + lwz r4,MachineCheck@got(r12)
   mtspr   IVOR1,r4/* 1: Machine check */
 - li  r4,DataStorage@l
 + lwz r4,DataStorage@got(r12)
   mtspr   IVOR2,r4/* 2: Data storage */
 - li  r4,InstStorage@l
 + lwz r4,InstStorage@got(r12)
   mtspr   IVOR3,r4/* 3: Instruction storage */
 - li  r4,ExtInterrupt@l
 + lwz r4,ExtInterrupt@got(r12)
   mtspr   IVOR4,r4/* 4: External interrupt */
 - li  r4,Alignment@l
 + lwz r4,Alignment@got(r12)
   mtspr   IVOR5,r4/* 5: Alignment */
 - li  r4,ProgramCheck@l
 + lwz r4,ProgramCheck@got(r12)
   mtspr   IVOR6,r4/* 6: Program check */
 - li  r4,FPUnavailable@l
 + lwz r4,FPUnavailable@got(r12)
   mtspr   IVOR7,r4/* 7: floating point unavailable */
 - li  r4,SystemCall@l
 + lwz r4,SystemCall@got(r12)
   mtspr   IVOR8,r4/* 8: System call */
   /* 9: Auxiliary processor unavailable(unsupported) */
 - li  r4,Decrementer@l
 + lwz r4,Decrementer@got(r12)
   mtspr   IVOR10,r4   /* 10: Decrementer */
 - li  r4,IntervalTimer@l
 + lwz r4,IntervalTimer@got(r12)
   mtspr   IVOR11,r4   /* 11: Interval timer */
 - li  r4,WatchdogTimer@l
 + lwz r4,WatchdogTimer@got(r12)
   mtspr   IVOR12,r4   /* 12: Watchdog timer */
 - li  r4,DataTLBError@l
 + lwz r4,DataTLBError@got(r12)
   mtspr   IVOR13,r4   /* 13: Data TLB error */
 - li  r4,InstructionTLBError@l
 + lwz r4,InstructionTLBError@got(r12)
   mtspr   IVOR14,r4   /* 14: Instruction TLB error */
 - li  r4,DebugBreakpoint@l
 + lwz r4,DebugBreakpoint@got(r12)
   mtspr   IVOR15,r4   /* 15: Debug */
 
 + mtlrr11
   blr
 
  .globl unlock_ram_in_cache
 --
 2.1.0

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Re: [U-Boot] [PATCH 15/28] net/memac_phy: reuse driver for little endian SoCs

[Shaohui Xie]

   /* IFC */
   #define CONFIG_SYS_FSL_IFC_LE
  +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN

 It seems tedious to have to define this. Can't you just use the functions 
 available?

 [S.H] To use a define is based on a concern that we cannot assume the I/O 
 access of an IP share same endianness as the Soc(s), we cannot assume on 
 little endian Soc the I/O access is little endian, on big endian Soc the I/O 
 access is big endian, the I/O access could be little endian on big endian Soc 
 and vice versa.

You're saying that the IP is expected to be in different endianness? If that is 
practically the case, then I'm fine with this patch. I just want to ensure that 
it is not just speculative generality.
[S.H] Yes. The IP is in different endianness, i.e. little endian on LS2, big 
endian on PowerPc Soc(s).
Thank you!
Shaohui
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Re: [U-Boot] [PATCH 15/28] net/memac_phy: reuse driver for little endian SoCs

[Shaohui Xie]

Hello Joe,

Thank you for reviewing this patch!
Please see inline.

Best Regards,
Shaohui Xie

From: Joe Hershberger [mailto:joe.hershber...@gmail.com]
Sent: Friday, March 20, 2015 2:04 AM
To: Sun York-R58495
Cc: u-boot; Joe Hershberger; Xie Shaohui-B21989
Subject: Re: [U-Boot] [PATCH 15/28] net/memac_phy: reuse driver for little 
endian SoCs

Hi Shaohui Xie,

On Thu, Mar 19, 2015 at 11:45 AM, York Sun 
york...@freescale.commailto:york...@freescale.com wrote:

 From: Shaohui Xie 
 shaohui@freescale.commailto:shaohui@freescale.com

 The memac for PHY management on little endian SoCs is similar on big
 endian SoCs, so we modify the driver by using I/O accessor function to
 handle the endianness, so the driver can be reused on little endian
 SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian
 SoCs, if the CONFIG_SYS_MEMAC_LITTLE_ENDIAN is defined, the I/O access
 is little endian, if not, the I/O access is big endian. Move fsl_memac.h
 out of powerpc include.

 Signed-off-by: Shaohui Xie 
 shaohui@freescale.commailto:shaohui@freescale.com
 CC: Joe Hershberger joe.hershber...@ni.commailto:joe.hershber...@ni.com
 ---
  arch/arm/include/asm/arch-fsl-lsch3/config.h  |1 +
  drivers/net/Makefile  |1 +
  drivers/net/fm/eth.c  |2 +-
  drivers/net/fm/memac.c|2 +-
  drivers/net/fm/memac_phy.c|   62 
 ++---
  drivers/net/vsc9953.c |2 +-
  {arch/powerpc/include/asm = include}/fsl_memac.h |0
  7 files changed, 46 insertions(+), 24 deletions(-)
  rename {arch/powerpc/include/asm = include}/fsl_memac.h (100%)

 diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h 
 b/arch/arm/include/asm/arch-fsl-lsch3/config.h
 index 98db1ef..684c70f 100644
 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
 +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
 @@ -109,6 +109,7 @@

  /* IFC */
  #define CONFIG_SYS_FSL_IFC_LE
 +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN

It seems tedious to have to define this. Can't you just use the functions 
available?
[S.H] To use a define is based on a concern that we cannot assume the I/O 
access of an IP share same endianness as the Soc(s), we cannot assume on little 
endian Soc the I/O access is little endian, on big endian Soc the I/O access is 
big endian, the I/O access could be little endian on big endian Soc and vice 
versa.


  /* PCIe */
  #define CONFIG_SYS_PCIE1_ADDR  (CONFIG_SYS_IMMR + 0x240)
 diff --git a/drivers/net/Makefile b/drivers/net/Makefile
 index 5497934..d871093 100644
 --- a/drivers/net/Makefile
 +++ b/drivers/net/Makefile
 @@ -66,4 +66,5 @@ obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o 
 xilinx_ll_temac_mdio.o \
  obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
  obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
  obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
 +obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
  obj-$(CONFIG_VSC9953) += vsc9953.o
 diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
 index 1d1089d..a7a5c69 100644
 --- a/drivers/net/fm/eth.c
 +++ b/drivers/net/fm/eth.c
 @@ -15,7 +15,7 @@
  #include phy.h
  #include asm/fsl_dtsec.h
  #include asm/fsl_tgec.h
 -#include asm/fsl_memac.h
 +#include fsl_memac.h

  #include fm.h

 diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
 index 60e898c..81a64bf 100644
 --- a/drivers/net/fm/memac.c
 +++ b/drivers/net/fm/memac.c
 @@ -12,7 +12,7 @@
  #include phy.h
  #include asm/types.h
  #include asm/io.h
 -#include asm/fsl_memac.h
 +#include fsl_memac.h

  #include fm.h

 diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
 index a155d89..4ab78e6 100644
 --- a/drivers/net/fm/memac_phy.c
 +++ b/drivers/net/fm/memac_phy.c
 @@ -10,9 +10,28 @@
  #include miiphy.h
  #include phy.h
  #include asm/io.h
 -#include asm/fsl_memac.h
 +#include fsl_memac.h
  #include fm_eth.h

 +#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
This can already be detected, right?

#if __BYTE_ORDER == __LITTLE_ENDIAN
[S.H] The issue is the IP’s I/O access order on LS2 is different from big 
endian Soc(s).
 +#define memac_out_32(a, v) out_le32(a, v)
 +#define memac_clrbits_32(a, v) clrbits_le32(a, v)
 +#define memac_setbits_32(a, v) setbits_le32(a, v)
 +#else
 +#define memac_out_32(a, v) out_be32(a, v)
 +#define memac_clrbits_32(a, v) clrbits_be32(a, v)
 +#define memac_setbits_32(a, v) setbits_be32(a, v)
 +#endif
 +
 +static u32 memac_in_32(u32 *reg)
 +{
 +#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
 +   return in_le32(reg);
 +#else
 +   return in_be32(reg);
 +#endif
 +}
Another option you have is to take the approach that you don't care the 
endianness. Something like using the this type of pattern:

value = ntohl(in_be32(reg));
out_be32(reg, htonl(value));
[S.H] same concern as above.

 +
  /*
   * Write value to the PHY for this device to the register at regnum, waiting
   * until the write is done before it returns.  All PHY

Re: [U-Boot] [PATCH 1/5] powerpc/b4860qds: add xfi support

[Shaohui Xie]

This patch series are based on patch:
http://patchwork.ozlabs.org/patch/409932/


Best Regards, 
Shaohui Xie
 -Original Message-
 From: shh@gmail.com [mailto:shh@gmail.com]
 Sent: Thursday, November 13, 2014 11:26 AM
 To: u-boot@lists.denx.de; Sun York-R58495
 Cc: Xie Shaohui-B21989
 Subject: [PATCH 1/5] powerpc/b4860qds: add xfi support
 
 From: Shaohui Xie shaohui@freescale.com
 
 We need following changes to make xfi work on B4:
 1. set cross-point switch VSC3308 to use sfp config when running xfi; 2. add 
 10G
 interface check for xfi; 3. set phy address for xfi so the 10G ports can be
 registered by mdio;
 
 Signed-off-by: Shaohui Xie shaohui@freescale.com
 ---
  board/freescale/b4860qds/b4860qds.c | 40 
 +++--
  board/freescale/b4860qds/eth_b4860qds.c |  6 +
  drivers/net/fm/b4860.c  |  4 +++-
  3 files changed, 42 insertions(+), 8 deletions(-)

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[U-Boot] [PATCH 1/2][v2] powerpc/t2080qds: fixup dtb for 10g-kr

[Shaohui Xie]

XFI ports on t2080qds can work with fiber cable and direct attach
cable(copper). We use hwconfig to define cable type for XFI, and fixup
dtb based on the cable type.

For copper cable, set below env in hwconfig:

fsl_10gkr_copper:10g_mac_name

the 10g_mac_name can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4.
fm1_10g1 stands for FM1-MAC9, fm1_10g2 stands for FM1-MAC10, fm1_10g3
stands for FM1-MAC1, fm1_10g4 stands for FM1-MAC2. The four
10g_mac_names do not have to be coexist in hwconfig. For XFI ports, if
a given 10G port will use the copper cable for 10GBASE-KR, set the
10g_mac_name of the port in hwconfig, otherwise, fiber cable will be
assumed to be used for the port.

For ex. if four XFI ports will both use copper cable, the hwconfig
should contain:

fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for V2:
add XFI description in t208xqds README.
 board/freescale/t208xqds/README | 23 -
 board/freescale/t208xqds/eth_t208xqds.c | 86 +
 2 files changed, 98 insertions(+), 11 deletions(-)

diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README
index e05a10f..e3eb5ba 100755
--- a/board/freescale/t208xqds/README
+++ b/board/freescale/t208xqds/README
@@ -85,10 +85,29 @@ System Logic:
  - QIXIS-II FPGA system controll
 Debug Features:
  - Support Legacy, COP/JTAG, Aurora, Event and EVT
-
+XFI:
+ - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
+ a on-board SFP+ cages, which to house optical module (fiber cable) or
+ direct attach cable(copper), the copper cable is used to emulate
+ 10GBASE-KR scenario.
+ So, for XFI usage, there are two scenarios, one will use fiber cable,
+ another will use copper cable. An hwconfig env fsl_10gkr_copper is
+ introduced to indicate a XFI port will use copper cable, and U-boot
+ will fixup the dtb accordingly.
+ It's used as: fsl_10gkr_copper:10g_mac_name
+ The 10g_mac_name can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
+ do not have to be coexist in hwconfig. If a MAC is listed in the env
+ fsl_10gkr_copper, it will use copper cable, otherwise, fiber cable
+ will be used by default.
+ for ex. set fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4 in
+ hwconfig, then both four XFI ports will use copper cable.
+ set fsl_10gkr_copper:fm1_10g1,fm1_10g2 in hwconfig, then first two
+ XFI ports will use copper cable, the other two XFI ports will use fiber
+ cable.
 
 System Memory map
--
+
+
 Start Address  End Address  DescriptionSize
 0xF_FFDF_  0xF_FFDF_0FFFIFC - CPLD 4KB
 0xF_FF80_  0xF_FF80_IFC - NAND Flash   64KB
diff --git a/board/freescale/t208xqds/eth_t208xqds.c 
b/board/freescale/t208xqds/eth_t208xqds.c
index 5879198..8675dbb 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -23,6 +23,7 @@
 #include phy.h
 #include asm/fsl_dtsec.h
 #include asm/fsl_serdes.h
+#include hwconfig.h
 #include ../common/qixis.h
 #include ../common/fman.h
 #include t208xqds_qixis.h
@@ -187,7 +188,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
 {
int phy;
char alias[20];
+   char lane_mode[2][20] = {1000BASE-KX, 10GBASE-KR};
+   char buf[32] = serdes-1,;
struct fixed_link f_link;
+   int media_type = 0;
+   int off;
+
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1 = in_be32(gur-rcwsr[4]) 
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -265,15 +271,77 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
case 0x6c:
case 0x6d:
case 0x71:
-   f_link.phy_id = port;
-   f_link.duplex = 1;
-   f_link.link_speed = 1;
-   f_link.pause = 0;
-   f_link.asym_pause = 0;
-   /* no PHY for XFI */
-   fdt_delprop(fdt, offset, phy-handle);
-   fdt_setprop(fdt, offset, fixed-link, f_link,
-   sizeof(f_link));
+   /*
+   * if the 10G is XFI, check hwconfig to see what is the
+   * media type, there are two types, fiber or copper,
+   * fix the dtb accordingly.
+   */
+   switch (port) {
+   case FM1_10GEC1:
+   if (hwconfig_sub(fsl_10gkr_copper, fm1_10g1)) {
+   /* it's MAC9 */
+   media_type = 1;
+   fdt_set_phy_handle(fdt, compat, addr,
+   phy_xfi9);
+   fdt_status_okay_by_alias(fdt

Re: [U-Boot] [PATCH v3 04/18] net: mdio: Add private MDIO read/write function

[Shaohui Xie]

 -Original Message-
 From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
 On Behalf Of Alison Wang
 Sent: Thursday, August 14, 2014 10:45 AM
 To: Sun York-R58495; u-boot@lists.denx.de
 Subject: [U-Boot] [PATCH v3 04/18] net: mdio: Add private MDIO read/write
 function
 
 As extra FPGA settings is needed for MDIO read/write on LS1021AQDS,
 private MDIO read/write functions are created.
[S.H] There are examples of how to handle MDIO bus read/write with FPGA 
settings, check
board/freescale/corenet_ds/eth_hydra.c
board/freescale/corenet_ds/eth_p4080.c

not necessary to add private stuff here.

Best Regards, 
Shaohui Xie

 

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Re: [U-Boot] [PATCH] powerpc/T4240QDS/eth: some fix for XFI

[Shaohui Xie]

 -Original Message-
 From: Sun York-R58495
 Sent: Wednesday, August 13, 2014 2:56 AM
 To: shh@gmail.com; u-boot@lists.denx.de
 Cc: Xie Shaohui-B21989
 Subject: Re: [PATCH] powerpc/T4240QDS/eth: some fix for XFI
 
 Shaohui,
 
 Do you mind to put this information into a README file?
[S.H] OK. I'll put these information include 'hwconfig' settings into README 
files of
T4QDS  T2QDS respectively.
Thanks!

Best Regards, 
Shaohui Xie

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Re: [U-Boot] [PATCH] powerpc/T4240QDS/eth: fix for XFI

[Shaohui Xie]

Please ignore this patch, it has some info only meaningful for Freescale.

Best Regards, 
Shaohui Xie


 -Original Message-
 From: shh@gmail.com [mailto:shh@gmail.com]
 Sent: Friday, July 25, 2014 4:55 PM
 To: u-boot@lists.denx.de
 Cc: Xie Shaohui-B21989
 Subject: [PATCH] powerpc/T4240QDS/eth: fix for XFI
 
 From: Shaohui Xie shaohui@freescale.com
 

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Re: [U-Boot] [RFC PATCH] Fix bug in T4240QDS code. Don't access nonexistent registers

[Shaohui Xie]

Hi, York,

There is already a patch sent upstream to fix this bug, the state is under 
review.
http://patchwork.ozlabs.org/patch/364807/


Best Regards, 
Shaohui Xie

 -Original Message-
 From: Sun York-R58495
 Sent: Wednesday, July 23, 2014 5:16 AM
 To: Xie Shaohui-B21989
 Cc: Vasili Galka; u-boot@lists.denx.de; Zang Roy-R61911
 Subject: Re: [RFC PATCH] Fix bug in T4240QDS code. Don't access
 nonexistent registers
 
 This patch points out a bug in T4240QDS code. But the fix is not correct.
 
 Shaohui, please take a closer look and submit a patch to fix it. I
 believe the code should check each Bank of each SerDes (totally 8 clocks).
 
 Thanks Vasili for pointing out.
 
 York
 
 
 On 06/16/2014 07:41 AM, Vasili Galka wrote:
  The code in misc_init_r() verifies actual SERDES clocks versus
  expected. It supposes that the number of clocks is MAX_SERDES.
  However, the number of pllcr0 registers is only SRDS_MAX_BANK. This
  clearly results in access to wrong memory. I don't have the datasheet
  to design a correct solution, but at least let's change it to access
  only the existing registers.
 
  Signed-off-by: Vasili Galka vvv...@gmail.com
  Cc: York Sun york...@freescale.com
  ---
   board/freescale/t4qds/t4240qds.c |2 +-
   1 files changed, 1 insertions(+), 1 deletions(-)
 
  diff --git a/board/freescale/t4qds/t4240qds.c
  b/board/freescale/t4qds/t4240qds.c
  index fe1bc7f..6646042 100644
  --- a/board/freescale/t4qds/t4240qds.c
  +++ b/board/freescale/t4qds/t4240qds.c
  @@ -662,7 +662,7 @@ int misc_init_r(void)
  }
  }
 
  -   for (i = 0; i  MAX_SERDES; i++) {
  +   for (i = 0; i  SRDS_MAX_BANK; i++) {
  u32 pllcr0 = srds_regs-bank[i].pllcr0;
  u32 expected = pllcr0  SRDS_PLLCR0_RFCK_SEL_MASK;
  if (expected != actual[i]) {
 

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Re: [U-Boot] [PATCH] powerpc/t4240: updated RCW and PBI for rev2.0

[Shaohui Xie]

Please ignore this patch. Will send a new version.

Best Regards, 
Shaohui Xie

 -Original Message-
 From: shh@gmail.com [mailto:shh@gmail.com]
 Sent: Saturday, March 22, 2014 4:08 PM
 To: u-boot@lists.denx.de
 Cc: Xie Shaohui-B21989
 Subject: [PATCH] powerpc/t4240: updated RCW and PBI for rev2.0
 
 From: Shaohui Xie shaohui@freescale.com
 
 Also, remove workaround of rev1.0.
 
 Signed-off-by: Shaohui Xie shaohui@freescale.com
 ---
  board/freescale/t4qds/t4_pbi.cfg | 17 +++--
 board/freescale/t4qds/t4_rcw.cfg |  6 +++---
  2 files changed, 6 insertions(+), 17 deletions(-)
 
 diff --git a/board/freescale/t4qds/t4_pbi.cfg
 b/board/freescale/t4qds/t4_pbi.cfg
 index c598fb5..e592c45 100644
 --- a/board/freescale/t4qds/t4_pbi.cfg
 +++ b/board/freescale/t4qds/t4_pbi.cfg
 @@ -13,20 +13,9 @@
  09000d00 
  09000d04 fff8
  09000d08 8112
 -#workaround for IFC bus speed
 -091241c0 f03f3f3f
 -091241c4 ff003f3f
 -09124010 0101
 -09124130 000c
 -#workaround for SERDES A-006031
 -090ea000 064740e6
 -090ea020 064740e6
 -090eb000 064740e6
 -090eb020 064740e6
 -090ec000 064740e6
 -090ec020 064740e6
 -090ed000 064740e6
 -090ed020 064740e6
 +#MDIO workaround for rev2.0
 +095fc030 8148
 +095fd030 00808148
  #Configure alternate space
  0910 
  0914 ff00
 diff --git a/board/freescale/t4qds/t4_rcw.cfg
 b/board/freescale/t4qds/t4_rcw.cfg
 index 74df01a..0732b9a 100644
 --- a/board/freescale/t4qds/t4_rcw.cfg
 +++ b/board/freescale/t4qds/t4_rcw.cfg
 @@ -1,7 +1,7 @@
  #PBL preamble and RCW header
  aa55aa55 010e0100
  #serdes protocol  1_28_6_12
 -120c0019 0c101915  
 -04383063 30548c00 6c02 1d00
 +16070019 18101916  
 +04383063 30548c00 ec108000 1d00
   eeee  000307fc
 -   0020
 +   0028
 --
 1.8.0
 

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Re: [U-Boot] [PATCH] phy: introduce structure fixed-link

[Shaohui Xie]

 -Original Message-
 From: York Sun [mailto:york...@freescale.com]
 Sent: Friday, November 22, 2013 2:03 AM
 To: shh@gmail.com; u-boot@lists.denx.de
 Cc: Xie Shaohui-B21989
 Subject: Re: [PATCH] phy: introduce structure fixed-link
 
 On 11/14/2013 03:00 AM, shh@gmail.com wrote:
  From: Shaohui Xie shaohui@freescale.com
 
  fixed-link is used in kernel for PHY-less MAC, so introduce this
  structure that U-boot can use it to fixup dtb dynamically.
 
  Signed-off-by: Shaohui Xie shaohui@freescale.com
  ---
   include/phy.h | 8 
   1 file changed, 8 insertions(+)
 
  diff --git a/include/phy.h b/include/phy.h index f0f522a..f86ffb9
  100644
  --- a/include/phy.h
  +++ b/include/phy.h
  @@ -160,6 +160,14 @@ struct phy_device {
  u32 flags;
   };
 
  +struct fixed_link {
  +   int phy_id;
  +   int duplex;
  +   int link_speed;
  +   int pause;
  +   int asym_pause;
  +};
  +
 
 How is this code used? Do you have other patches following?
 

[S.H] Shengzhou has posted patches, link: 
http://patchwork.ozlabs.org/patch/291206/

It uses as below (quoted some codes):

+   switch (srds_s1) {
+   case 0x66: /* XFI interface */
+   case 0x6b:
+   case 0x6c:
+   case 0x6d:
+   case 0x71:
+   f_link.phy_id = port;
+   f_link.duplex = 1;
+   f_link.link_speed = 1;
+   f_link.pause = 0;
+   f_link.asym_pause = 0;
+   /* no PHY for XFI */
+   fdt_delprop(fdt, offset, phy-handle);
+   fdt_setprop(fdt, offset, fixed-link, f_link,
+   sizeof(f_link));
+   break;
+   default:
+   break;
+   }


Best Regards, 
Shaohui Xie

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Re: [U-Boot] [u-boot-release] [PATCH] net/phy: Add Vitesse VSC8514 PHY support

[Shaohui Xie]

I do not see your patch in upstream, and I was not aware of your patch also.
For 8514 it can use the same setting as 8574. 
But one interesting thing is the PHY ID in your patch is 0x70570, but the PHY 
ID I read from the card is 0x70670.

Roy,
Please confirm if the card installed on board is 8514.

Best Regards, 
Shaohui Xie


 -Original Message-
 From: Sharma Bhupesh-B45370
 Sent: Wednesday, November 20, 2013 4:31 PM
 To: 'shh@gmail.com'; 'u-boot@lists.denx.de'; sun york-R58495
 Cc: Xie Shaohui-B21989; Goel Arpit-B44344
 Subject: RE: [u-boot-release] [PATCH] net/phy: Add Vitesse VSC8514 PHY
 support
 
 There is a patch for VSC8514 support already circulated by Arpit and me :
 http://lists.denx.de/pipermail/u-boot/2013-August/161393.html
 
 regards,
 Bhupesh
 
  -Original Message-
  From: u-boot-release-boun...@linux.freescale.net
  [mailto:u-boot-release- boun...@linux.freescale.net] On Behalf Of
  shh@gmail.com
  Sent: Wednesday, November 20, 2013 1:07 PM
  To: u-boot@lists.denx.de; sun york-R58495
  Cc: Xie Shaohui-B21989
  Subject: [u-boot-release] [PATCH] net/phy: Add Vitesse VSC8514 PHY
  support
 
  From: Shaohui Xie shaohui@freescale.com
 
  The VSC8514 works in QSGMII interface. Its register set and features
  are similar to VSC8574 which in QSGMII mode.
 
  Signed-off-by: Shaohui Xie shaohui@freescale.com
  ---
   drivers/net/phy/vitesse.c | 11 +++
   1 file changed, 11 insertions(+)
 
  diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
  index 61f863e..9af4efe 100644
  --- a/drivers/net/phy/vitesse.c
  +++ b/drivers/net/phy/vitesse.c
  @@ -241,6 +241,16 @@ static struct phy_driver VSC8234_driver = {
  .shutdown = genphy_shutdown,
   };
 
  +static struct phy_driver VSC8514_driver = {
  +   .name = Vitesse VSC8514,
  +   .uid = 0x70670,
  +   .mask = 0x0,
  +   .features = PHY_GBIT_FEATURES,
  +   .config = vsc8574_config,
  +   .startup = vitesse_startup,
  +   .shutdown = genphy_shutdown,
  +};
  +
   static struct phy_driver VSC8574_driver = {
  .name = Vitesse VSC8574,
  .uid = 0x704a0,
  @@ -310,6 +320,7 @@ int phy_vitesse_init(void)
  phy_register(VSC8244_driver);
  phy_register(VSC8211_driver);
  phy_register(VSC8221_driver);
  +   phy_register(VSC8514_driver);
  phy_register(VSC8574_driver);
  phy_register(VSC8662_driver);
  phy_register(cis8201_driver);
  --
  1.8.0
 
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[U-Boot] [PATCH] powerpc/p2041: fix I2C controller's offset

[Shaohui Xie]

Without this patch, SPD access will fail which leads to DDR init fail.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 include/configs/P2041RDB.h |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 905bacf..862614b 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -354,10 +354,10 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED   40
 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET  0x3000
+#define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 #define CONFIG_SYS_FSL_I2C2_SPEED  40
 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 
 /*
  * RapidIO
-- 
1.7.0.4


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[U-Boot] [PATCH 1/3][v3] powerpc/common/vsc3316: remove const from vsc3316_config parameter define

[Shaohui Xie]

Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this. Also remove const from
arrays define used by vsc3316_config.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for V3:
1. rebased on top of master branch.

changes for V2:
1. changed subject;
2. fix broken on B4xxx boards;

 board/freescale/b4860qds/b4860qds_crossbar_con.h |   12 ++--
 board/freescale/common/vsc3316_3308.c|2 +-
 board/freescale/common/vsc3316_3308.h|2 +-
 board/freescale/t4qds/t4240qds.c |8 
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h 
b/board/freescale/b4860qds/b4860qds_crossbar_con.h
index 6e64745..db0cf28 100644
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -13,10 +13,10 @@
 static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
{5, 11}, {4, 5}, {2, 6}, {12, 9} };
 
-static const int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
+static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
-static const int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
+static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
{7, 8}, {9, 0}, {2, 14}, {12, 15},
{-1, -1}, {-1, -1} };
 
@@ -25,7 +25,7 @@ static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, 
{0, 1},
{-1, -1}, {-1, -1} };
 
 #ifdef CONFIG_PPC_B4420
-static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
+static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 #endif
 
@@ -35,10 +35,10 @@ static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 
12}, {-1, -1},
 static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
{11, 11}, {5, 10}, {6, 3}, {9, 12} };
 
-static const int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
+static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
-static const int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
+static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
{7, 8}, {1, 9}, {14, 3}, {15, 12},
{-1, -1}, {-1, -1} };
 
@@ -47,7 +47,7 @@ static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, 
{0, 1},
{-1, -1}, {-1, -1} };
 
 #ifdef CONFIG_PPC_B4420
-static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
+static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 #endif
 
diff --git a/board/freescale/common/vsc3316_3308.c 
b/board/freescale/common/vsc3316_3308.c
index 8a3dc33..97a25e8 100644
--- a/board/freescale/common/vsc3316_3308.c
+++ b/board/freescale/common/vsc3316_3308.c
@@ -31,7 +31,7 @@ int vsc_if_enable(unsigned int vsc_addr)
return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, data, 1);
 }
 
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con)
 {
unsigned int i;
diff --git a/board/freescale/common/vsc3316_3308.h 
b/board/freescale/common/vsc3316_3308.h
index 4003fcd..2a49187 100644
--- a/board/freescale/common/vsc3316_3308.h
+++ b/board/freescale/common/vsc3316_3308.h
@@ -12,7 +12,7 @@
 #include errno.h
 
 int vsc_if_enable(unsigned int vsc_addr);
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con);
 int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con);
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 7ee0f54..c3f6247 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -26,16 +26,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
{8, 8}, {9, 9}, {14, 14}, {15, 15} };
 
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
{10, 10}, {11, 11}, {12, 12}, {13, 13} };
 
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4

[U-Boot] [PATCH 1/3][v3] powerpc/common/vsc3316: remove const from vsc3316_config parameter define

[Shaohui Xie]

From: Shaohui Xie shaohui@freescale.com

Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this. Also remove const from
arrays define used by vsc3316_config.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for V3:
1. rebased on top of master branch.

changes for V2:
1. changed subject;
2. fix broken on B4xxx boards;

 board/freescale/b4860qds/b4860qds_crossbar_con.h |   12 ++--
 board/freescale/common/vsc3316_3308.c|2 +-
 board/freescale/common/vsc3316_3308.h|2 +-
 board/freescale/t4qds/t4240qds.c |8 
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h 
b/board/freescale/b4860qds/b4860qds_crossbar_con.h
index 6e64745..db0cf28 100644
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -13,10 +13,10 @@
 static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
{5, 11}, {4, 5}, {2, 6}, {12, 9} };
 
-static const int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
+static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
-static const int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
+static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
{7, 8}, {9, 0}, {2, 14}, {12, 15},
{-1, -1}, {-1, -1} };
 
@@ -25,7 +25,7 @@ static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, 
{0, 1},
{-1, -1}, {-1, -1} };
 
 #ifdef CONFIG_PPC_B4420
-static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
+static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 #endif
 
@@ -35,10 +35,10 @@ static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 
12}, {-1, -1},
 static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
{11, 11}, {5, 10}, {6, 3}, {9, 12} };
 
-static const int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
+static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
-static const int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
+static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
{7, 8}, {1, 9}, {14, 3}, {15, 12},
{-1, -1}, {-1, -1} };
 
@@ -47,7 +47,7 @@ static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, 
{0, 1},
{-1, -1}, {-1, -1} };
 
 #ifdef CONFIG_PPC_B4420
-static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
+static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 #endif
 
diff --git a/board/freescale/common/vsc3316_3308.c 
b/board/freescale/common/vsc3316_3308.c
index 8a3dc33..97a25e8 100644
--- a/board/freescale/common/vsc3316_3308.c
+++ b/board/freescale/common/vsc3316_3308.c
@@ -31,7 +31,7 @@ int vsc_if_enable(unsigned int vsc_addr)
return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, data, 1);
 }
 
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con)
 {
unsigned int i;
diff --git a/board/freescale/common/vsc3316_3308.h 
b/board/freescale/common/vsc3316_3308.h
index 4003fcd..2a49187 100644
--- a/board/freescale/common/vsc3316_3308.h
+++ b/board/freescale/common/vsc3316_3308.h
@@ -12,7 +12,7 @@
 #include errno.h
 
 int vsc_if_enable(unsigned int vsc_addr);
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con);
 int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con);
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 7ee0f54..c3f6247 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -26,16 +26,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
{8, 8}, {9, 9}, {14, 14}, {15, 15} };
 
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
{10, 10}, {11, 11}, {12, 12}, {13, 13} };
 
-static const int8_t vsc3316_fsm1_rx

[U-Boot] [PATCH 2/3] powerpc/t4240: fix lanes routing for QSGMII protocols

[Shaohui Xie]

From: Shaohui Xie shaohui@freescale.com

When using QSGMII protocols, the first lane and third lane on each slot
need to be swapped.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
resend for patchwork to catch.

 board/freescale/t4qds/t4240qds.c |   39 -
 1 files changed, 37 insertions(+), 2 deletions(-)

diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index c3f6247..0c1a4fb 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -353,25 +353,60 @@ int config_frontside_crossbar_vsc3316(void)
srds_prtcl_s1 = in_be32(gur-rcwsr[4]) 
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 = FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-   if (srds_prtcl_s1) {
+   switch (srds_prtcl_s1) {
+   case 38:
+   /* swap first lane and third lane on slot1 */
+   vsc3316_fsm1_tx[0][1] = 14;
+   vsc3316_fsm1_tx[6][1] = 0;
+   vsc3316_fsm1_rx[1][1] = 2;
+   vsc3316_fsm1_rx[6][1] = 13;
+   case 40:
+   case 46:
+   case 48:
+   /* swap first lane and third lane on slot2 */
+   vsc3316_fsm1_tx[2][1] = 8;
+   vsc3316_fsm1_tx[4][1] = 6;
+   vsc3316_fsm1_rx[2][1] = 10;
+   vsc3316_fsm1_rx[5][1] = 5;
+   default:
ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
if (ret)
return ret;
ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
if (ret)
return ret;
+   break;
}
 
srds_prtcl_s2 = in_be32(gur-rcwsr[4]) 
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 = FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-   if (srds_prtcl_s2) {
+   switch (srds_prtcl_s2) {
+   case 38:
+   /* swap first lane and third lane on slot3 */
+   vsc3316_fsm2_tx[2][1] = 11;
+   vsc3316_fsm2_tx[5][1] = 4;
+   vsc3316_fsm2_rx[2][1] = 9;
+   vsc3316_fsm2_rx[4][1] = 7;
+   case 40:
+   case 46:
+   case 48:
+   case 50:
+   case 52:
+   case 54:
+   /* swap first lane and third lane on slot4 */
+   vsc3316_fsm2_tx[6][1] = 3;
+   vsc3316_fsm2_tx[1][1] = 12;
+   vsc3316_fsm2_rx[0][1] = 1;
+   vsc3316_fsm2_rx[6][1] = 15;
+   default:
ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
if (ret)
return ret;
ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
if (ret)
return ret;
+   break;
}
 
return 0;
-- 
1.7.0.4


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[U-Boot] [PATCH 3/3] powerpc/t4240: add QSGMII interface support

[Shaohui Xie]

From: Shaohui Xie shaohui@freescale.com

Also some fix for QSGMII.
1. fix QSGMII configure of Serdes2.
2. fix PHY address of QSGMII MAC9  MAC10 for each FMAN.
3. fix dtb for QSGMII interface.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
resend for patchwork to catch.

 arch/powerpc/cpu/mpc85xx/t4240_serdes.c |   14 +++---
 board/freescale/t4qds/eth.c |   80 ++
 drivers/net/fm/eth.c|4 +-
 drivers/net/fm/memac.c  |1 +
 drivers/net/fm/t4240.c  |   40 +++-
 5 files changed, 108 insertions(+), 31 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c 
b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index ed88602..ff55e3c 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -106,25 +106,25 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
{38, {NONE, NONE, QSGMII_FM2_B, NONE,
-   NONE, NONE, QSGMII_FM1_A, NONE}},
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-   NONE, NONE, QSGMII_FM1_A, NONE}},
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-   NONE, NONE, QSGMII_FM1_A, NONE}},
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-   NONE, NONE, QSGMII_FM1_A, NONE}},
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-   NONE, NONE, QSGMII_FM1_A, NONE}},
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-   NONE, NONE, QSGMII_FM1_A, NONE}},
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-   NONE, NONE, QSGMII_FM1_A, NONE}},
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
XFI_FM2_MAC10, XFI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index c771e17..b5f488b 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -172,7 +172,10 @@ static int t4240qds_mdio_init(char *realbusname, u8 muxval)
 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
 {
-   if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+   int interface = fm_info_get_enet_if(port);
+
+   if (interface == PHY_INTERFACE_MODE_SGMII ||
+   interface == PHY_INTERFACE_MODE_QSGMII) {
switch (port) {
case FM1_DTSEC1:
if (qsgmiiphy_fix[port])
@@ -272,6 +275,7 @@ void fdt_fixup_board_enet(void *fdt)
for (i = FM1_DTSEC1; i  NUM_FM_PORTS; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
+   case PHY_INTERFACE_MODE_QSGMII:
switch (mdio_mux[i]) {
case EMI1_SLOT1:
fdt_status_okay_by_alias(fdt, emi1_slot1);
@@ -393,7 +397,7 @@ static void initialize_qsgmiiphy_fix(void)
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FMAN_ENET)
-   int i, idx, lane, slot;
+   int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -470,9 +474,9 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56)  (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC9,
-   slot_qsgmii_phyaddr[1][3]);
-   fm_info_set_phy_address(FM1_DTSEC10,
slot_qsgmii_phyaddr[1][2]);
+   fm_info_set_phy_address(FM1_DTSEC10,
+   slot_qsgmii_phyaddr[1][3]);
}
break;
case 40:
@@ -482,9 +486,9 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56)  (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC10

[U-Boot] [PATCH 2/3] powerpc/t4qds: fix lanes routing for QSGMII protocols

[Shaohui Xie]

When using QSGMII protocols, the first lane and third lane on each slot
need to be swapped.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/t4qds/t4qds.c | 39 +--
 1 file changed, 37 insertions(+), 2 deletions(-)

diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index 2dade85..a082950 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -367,25 +367,60 @@ int config_frontside_crossbar_vsc3316(void)
srds_prtcl_s1 = in_be32(gur-rcwsr[4]) 
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 = FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-   if (srds_prtcl_s1) {
+   switch (srds_prtcl_s1) {
+   case 38:
+   /* swap first lane and third lane on slot1 */
+   vsc3316_fsm1_tx[0][1] = 14;
+   vsc3316_fsm1_tx[6][1] = 0;
+   vsc3316_fsm1_rx[1][1] = 2;
+   vsc3316_fsm1_rx[6][1] = 13;
+   case 40:
+   case 46:
+   case 48:
+   /* swap first lane and third lane on slot2 */
+   vsc3316_fsm1_tx[2][1] = 8;
+   vsc3316_fsm1_tx[4][1] = 6;
+   vsc3316_fsm1_rx[2][1] = 10;
+   vsc3316_fsm1_rx[5][1] = 5;
+   default:
ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
if (ret)
return ret;
ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
if (ret)
return ret;
+   break;
}
 
srds_prtcl_s2 = in_be32(gur-rcwsr[4]) 
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 = FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-   if (srds_prtcl_s2) {
+   switch (srds_prtcl_s2) {
+   case 38:
+   /* swap first lane and third lane on slot3 */
+   vsc3316_fsm2_tx[2][1] = 11;
+   vsc3316_fsm2_tx[5][1] = 4;
+   vsc3316_fsm2_rx[2][1] = 9;
+   vsc3316_fsm2_rx[4][1] = 7;
+   case 40:
+   case 46:
+   case 48:
+   case 50:
+   case 52:
+   case 54:
+   /* swap first lane and third lane on slot4 */
+   vsc3316_fsm2_tx[6][1] = 3;
+   vsc3316_fsm2_tx[1][1] = 12;
+   vsc3316_fsm2_rx[0][1] = 1;
+   vsc3316_fsm2_rx[6][1] = 15;
+   default:
ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
if (ret)
return ret;
ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
if (ret)
return ret;
+   break;
}
 
return 0;
-- 
1.8.0


___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH 3/3] powerpc/t4240: add QSGMII interface support

[Shaohui Xie]

Also some fix for QSGMII.
1. fix QSGMII configure of Serdes2.
2. fix PHY address of QSGMII MAC9  MAC10 for each FMAN.
3. fix dtb for QSGMII interface.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 arch/powerpc/cpu/mpc85xx/t4240_serdes.c |   14 +++---
 board/freescale/t4qds/eth.c |   80 ++
 drivers/net/fm/eth.c|4 +-
 drivers/net/fm/memac.c  |1 +
 drivers/net/fm/t4240.c  |   40 +++-
 5 files changed, 108 insertions(+), 31 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c 
b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index c001780..d0782f1 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -122,25 +122,25 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
{38, {NONE, NONE, QSGMII_FM2_B, NONE,
-   NONE, NONE, QSGMII_FM1_A, NONE}},
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-   NONE, NONE, QSGMII_FM1_A, NONE}},
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-   NONE, NONE, QSGMII_FM1_A, NONE}},
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-   NONE, NONE, QSGMII_FM1_A, NONE}},
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-   NONE, NONE, QSGMII_FM1_A, NONE}},
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-   NONE, NONE, QSGMII_FM1_A, NONE}},
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-   NONE, NONE, QSGMII_FM1_A, NONE}},
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
XFI_FM2_MAC10, XFI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 7103a0d..6575bfe 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -188,7 +188,10 @@ static int t4240qds_mdio_init(char *realbusname, u8 muxval)
 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
 {
-   if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+   int interface = fm_info_get_enet_if(port);
+
+   if (interface == PHY_INTERFACE_MODE_SGMII ||
+   interface == PHY_INTERFACE_MODE_QSGMII) {
switch (port) {
case FM1_DTSEC1:
if (qsgmiiphy_fix[port])
@@ -288,6 +291,7 @@ void fdt_fixup_board_enet(void *fdt)
for (i = FM1_DTSEC1; i  NUM_FM_PORTS; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
+   case PHY_INTERFACE_MODE_QSGMII:
switch (mdio_mux[i]) {
case EMI1_SLOT1:
fdt_status_okay_by_alias(fdt, emi1_slot1);
@@ -409,7 +413,7 @@ static void initialize_qsgmiiphy_fix(void)
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FMAN_ENET)
-   int i, idx, lane, slot;
+   int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -486,9 +490,9 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56)  (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC9,
-   slot_qsgmii_phyaddr[1][3]);
-   fm_info_set_phy_address(FM1_DTSEC10,
slot_qsgmii_phyaddr[1][2]);
+   fm_info_set_phy_address(FM1_DTSEC10,
+   slot_qsgmii_phyaddr[1][3]);
}
break;
case 40:
@@ -498,9 +502,9 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56)  (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC10,
-   slot_qsgmii_phyaddr[1][3

[U-Boot] [PATCH][v2] powerpc/common/vsc3316: remove const from vsc3316_config parameter define

[Shaohui Xie]

Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this. Also remove const from
arrays define used by vsc3316_config.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for V2:
1. changed subject;
2. fix broken on B4xxx boards;

 board/freescale/b4860qds/b4860qds_crossbar_con.h | 12 ++--
 board/freescale/common/vsc3316_3308.c|  2 +-
 board/freescale/common/vsc3316_3308.h|  2 +-
 board/freescale/t4qds/t4qds.c|  8 
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h 
b/board/freescale/b4860qds/b4860qds_crossbar_con.h
index 6e64745..db0cf28 100644
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -13,10 +13,10 @@
 static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
{5, 11}, {4, 5}, {2, 6}, {12, 9} };
 
-static const int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
+static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
-static const int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
+static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
{7, 8}, {9, 0}, {2, 14}, {12, 15},
{-1, -1}, {-1, -1} };
 
@@ -25,7 +25,7 @@ static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, 
{0, 1},
{-1, -1}, {-1, -1} };
 
 #ifdef CONFIG_PPC_B4420
-static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
+static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 #endif
 
@@ -35,10 +35,10 @@ static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 
12}, {-1, -1},
 static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
{11, 11}, {5, 10}, {6, 3}, {9, 12} };
 
-static const int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
+static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
-static const int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
+static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
{7, 8}, {1, 9}, {14, 3}, {15, 12},
{-1, -1}, {-1, -1} };
 
@@ -47,7 +47,7 @@ static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, 
{0, 1},
{-1, -1}, {-1, -1} };
 
 #ifdef CONFIG_PPC_B4420
-static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
+static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 #endif
 
diff --git a/board/freescale/common/vsc3316_3308.c 
b/board/freescale/common/vsc3316_3308.c
index 8a3dc33..97a25e8 100644
--- a/board/freescale/common/vsc3316_3308.c
+++ b/board/freescale/common/vsc3316_3308.c
@@ -31,7 +31,7 @@ int vsc_if_enable(unsigned int vsc_addr)
return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, data, 1);
 }
 
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con)
 {
unsigned int i;
diff --git a/board/freescale/common/vsc3316_3308.h 
b/board/freescale/common/vsc3316_3308.h
index 4003fcd..2a49187 100644
--- a/board/freescale/common/vsc3316_3308.h
+++ b/board/freescale/common/vsc3316_3308.h
@@ -12,7 +12,7 @@
 #include errno.h
 
 int vsc_if_enable(unsigned int vsc_addr);
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con);
 int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con);
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index aa6a217..2dade85 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -26,16 +26,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
{8, 8}, {9, 9}, {14, 14}, {15, 15} };
 
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
{10, 10}, {11, 11}, {12, 12}, {13, 13} };
 
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4

[U-Boot] [PATCH 1/3] powerpc/t4qds: remove const from vsc3316 parameter define

[Shaohui Xie]

Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/common/vsc3316_3308.c | 2 +-
 board/freescale/common/vsc3316_3308.h | 2 +-
 board/freescale/t4qds/t4qds.c | 8 
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/board/freescale/common/vsc3316_3308.c 
b/board/freescale/common/vsc3316_3308.c
index 8a3dc33..97a25e8 100644
--- a/board/freescale/common/vsc3316_3308.c
+++ b/board/freescale/common/vsc3316_3308.c
@@ -31,7 +31,7 @@ int vsc_if_enable(unsigned int vsc_addr)
return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, data, 1);
 }
 
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con)
 {
unsigned int i;
diff --git a/board/freescale/common/vsc3316_3308.h 
b/board/freescale/common/vsc3316_3308.h
index 4003fcd..2a49187 100644
--- a/board/freescale/common/vsc3316_3308.h
+++ b/board/freescale/common/vsc3316_3308.h
@@ -12,7 +12,7 @@
 #include errno.h
 
 int vsc_if_enable(unsigned int vsc_addr);
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con);
 int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con);
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index aa6a217..2dade85 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -26,16 +26,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
{8, 8}, {9, 9}, {14, 14}, {15, 15} };
 
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
{10, 10}, {11, 11}, {12, 12}, {13, 13} };
 
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
{10, 11}, {11, 10}, {12, 2}, {13, 3} };
 
-static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
{8, 9}, {9, 8}, {14, 1}, {15, 0} };
 
 int checkboard(void)
-- 
1.8.0


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[U-Boot] [PATCH 1/3] powerpc/t4qds: remove const from vsc3316 parameter define

[Shaohui Xie]

Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/common/vsc3316_3308.c | 2 +-
 board/freescale/common/vsc3316_3308.h | 2 +-
 board/freescale/t4qds/t4qds.c | 8 
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/board/freescale/common/vsc3316_3308.c 
b/board/freescale/common/vsc3316_3308.c
index 8a3dc33..97a25e8 100644
--- a/board/freescale/common/vsc3316_3308.c
+++ b/board/freescale/common/vsc3316_3308.c
@@ -31,7 +31,7 @@ int vsc_if_enable(unsigned int vsc_addr)
return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, data, 1);
 }
 
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con)
 {
unsigned int i;
diff --git a/board/freescale/common/vsc3316_3308.h 
b/board/freescale/common/vsc3316_3308.h
index 4003fcd..2a49187 100644
--- a/board/freescale/common/vsc3316_3308.h
+++ b/board/freescale/common/vsc3316_3308.h
@@ -12,7 +12,7 @@
 #include errno.h
 
 int vsc_if_enable(unsigned int vsc_addr);
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con);
 int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con);
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index aa6a217..2dade85 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -26,16 +26,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
{8, 8}, {9, 9}, {14, 14}, {15, 15} };
 
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
{10, 10}, {11, 11}, {12, 12}, {13, 13} };
 
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
{10, 11}, {11, 10}, {12, 2}, {13, 3} };
 
-static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
{8, 9}, {9, 8}, {14, 1}, {15, 0} };
 
 int checkboard(void)
-- 
1.8.0


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[U-Boot] [PATCH 1/3] powerpc/t4qds: remove const from vsc3316 parameter define

[Shaohui Xie]

Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/common/vsc3316_3308.c | 2 +-
 board/freescale/common/vsc3316_3308.h | 2 +-
 board/freescale/t4qds/t4qds.c | 8 
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/board/freescale/common/vsc3316_3308.c 
b/board/freescale/common/vsc3316_3308.c
index 8a3dc33..97a25e8 100644
--- a/board/freescale/common/vsc3316_3308.c
+++ b/board/freescale/common/vsc3316_3308.c
@@ -31,7 +31,7 @@ int vsc_if_enable(unsigned int vsc_addr)
return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, data, 1);
 }
 
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con)
 {
unsigned int i;
diff --git a/board/freescale/common/vsc3316_3308.h 
b/board/freescale/common/vsc3316_3308.h
index 4003fcd..2a49187 100644
--- a/board/freescale/common/vsc3316_3308.h
+++ b/board/freescale/common/vsc3316_3308.h
@@ -12,7 +12,7 @@
 #include errno.h
 
 int vsc_if_enable(unsigned int vsc_addr);
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con);
 int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con);
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index aa6a217..2dade85 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -26,16 +26,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
{8, 8}, {9, 9}, {14, 14}, {15, 15} };
 
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
{10, 10}, {11, 11}, {12, 12}, {13, 13} };
 
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
{10, 11}, {11, 10}, {12, 2}, {13, 3} };
 
-static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
{8, 9}, {9, 8}, {14, 1}, {15, 0} };
 
 int checkboard(void)
-- 
1.8.0


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[U-Boot] [PATCH] powerpc/B4860: enable PBL tool for B4860

[Shaohui Xie]

Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which
uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a
pbl boot image.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/b4860qds/b4_pbi.cfg | 27 +++
 board/freescale/b4860qds/b4_rcw.cfg |  7 +++
 include/configs/B4860QDS.h  |  2 ++
 3 files changed, 36 insertions(+)
 create mode 100644 board/freescale/b4860qds/b4_pbi.cfg
 create mode 100644 board/freescale/b4860qds/b4_rcw.cfg

diff --git a/board/freescale/b4860qds/b4_pbi.cfg 
b/board/freescale/b4860qds/b4_pbi.cfg
new file mode 100644
index 000..57b726e
--- /dev/null
+++ b/board/freescale/b4860qds/b4_pbi.cfg
@@ -0,0 +1,27 @@
+#PBI commands
+#Initialize CPC1
+0901 00200400
+09138000 
+091380c0 0100
+#Configure CPC1 as 512KB SRAM
+09010100 
+09010104 fff80009
+09010f00 0800
+0901 8000
+#Configure LAW for CPC1
+09000d00 
+09000d04 fff8
+09000d08 8112
+#Configure alternate space
+0910 
+0914 ff00
+0918 8100
+#Configure SPI controller
+0911 8403
+09110020 2d170008
+09110024 0018
+09110028 0018
+0911002c 0018
+#Flush PBL data
+09138000 
+091380c0 
diff --git a/board/freescale/b4860qds/b4_rcw.cfg 
b/board/freescale/b4860qds/b4_rcw.cfg
new file mode 100644
index 000..7bf0066
--- /dev/null
+++ b/board/freescale/b4860qds/b4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x2A_0x98
+140e0018 0f001218  
+5498 9000a000 e8904000 a900
+0100   0001f1f8
+ 1420  0011
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 1c9d08e..f8ab478 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -32,6 +32,8 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE   CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS0xfffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
 #endif
 
 /* High Level Configuration Options */
-- 
1.8.0


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[U-Boot] [PATCH] powerpc/p2041rdb: fix SerDes clock display for RevC RevD boards

[Shaohui Xie]

For now there are three boards supported:

Early -PB board used schematic RevC(x) and it's PCBA rev4.0.
Now -PB board used schematic RevD(x) and it's PCBA rev5.0.
Now -PC board used schematic RevD(x) and it's PCBA rev5.0.

All RevD(x) boards have same clock setting on bank1 and bank2,
RevC(x) board has different clock setting on two banks, PCBA can
be used to distinguish the boards, PCBA could be increased on
RevD(x) board in future, but RevC(x) board will never has PCBA  4.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/p2041rdb/p2041rdb.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/board/freescale/p2041rdb/p2041rdb.c 
b/board/freescale/p2041rdb/p2041rdb.c
index a706a6d..8549639 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -84,7 +84,10 @@ int checkboard(void)
};
unsigned int clock = (sw  (2 * i))  3;
 
-   printf(Bank%u=%sMhz , i+1, freq[i][clock]);
+   if ((i == 1)  (CPLD_READ(pcba_ver) = 5))
+   printf(Bank%u=%sMhz , i+1, freq[i-1][clock]);
+   else
+   printf(Bank%u=%sMhz , i+1, freq[i][clock]);
}
puts(\n);
 
@@ -227,6 +230,16 @@ int misc_init_r(void)
'00' is unsupported\n);
else
actual[i] = freq[i][clock];
+
+   /*
+* RevD(x) board has a different clock setting with RevC(x)
+* board, CPLD on RevD(x) board has pcba_ver = 5. RevC(x)
+* board has pcba_ver = 4, it can be used to distinguish
+* the two boards.
+*/
+   if ((i == 1)  (CPLD_READ(pcba_ver) = 5))
+   /* RevD(x) board bank2 frequency */
+   actual[i] = freq[i-1][clock];
}
 
for (i = 0; i  NUM_SRDS_BANKS; i++) {
-- 
1.8.0


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[U-Boot] [PATCH] powerpc/p2041rdb: fix SerDes clock display for RevC RevD boards

[Shaohui Xie]

For now there are three boards supported:

Early -PB board used schematic RevC(x) and it's PCBA rev4.0.
Now -PB board used schematic RevD(x) and it's PCBA rev5.0.
Now -PC board used schematic RevD(x) and it's PCBA rev5.0.

All RevD(x) boards have same clock setting on bank1 and bank2,
RevC(x) board has different clock setting on two banks, PCBA can
be used to distinguish the boards, PCBA could be increased on
RevD(x) board in future, but RevC(x) board will never has PCBA  4.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/p2041rdb/p2041rdb.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/board/freescale/p2041rdb/p2041rdb.c 
b/board/freescale/p2041rdb/p2041rdb.c
index a706a6d..8549639 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -84,7 +84,10 @@ int checkboard(void)
};
unsigned int clock = (sw  (2 * i))  3;
 
-   printf(Bank%u=%sMhz , i+1, freq[i][clock]);
+   if ((i == 1)  (CPLD_READ(pcba_ver) = 5))
+   printf(Bank%u=%sMhz , i+1, freq[i-1][clock]);
+   else
+   printf(Bank%u=%sMhz , i+1, freq[i][clock]);
}
puts(\n);
 
@@ -227,6 +230,16 @@ int misc_init_r(void)
'00' is unsupported\n);
else
actual[i] = freq[i][clock];
+
+   /*
+* RevD(x) board has a different clock setting with RevC(x)
+* board, CPLD on RevD(x) board has pcba_ver = 5. RevC(x)
+* board has pcba_ver = 4, it can be used to distinguish
+* the two boards.
+*/
+   if ((i == 1)  (CPLD_READ(pcba_ver) = 5))
+   /* RevD(x) board bank2 frequency */
+   actual[i] = freq[i-1][clock];
}
 
for (i = 0; i  NUM_SRDS_BANKS; i++) {
-- 
1.8.0


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[U-Boot] [PATCH] powerpc/tools/pblimage: use SYS_TEXT_BASE instead of hardcoded value

[Shaohui Xie]

That the pblimage can be built according to the SYS_TEXT_BASE, then building a
different size of pblimage is available.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 tools/pblimage.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/tools/pblimage.c b/tools/pblimage.c
index 508a747..60277a4 100644
--- a/tools/pblimage.c
+++ b/tools/pblimage.c
@@ -29,10 +29,9 @@
  * The PBL can load up to 64 bytes at a time, so we split the U-Boot
  * image into 64 byte chunks. PBL needs a command for each piece, of
  * the form 81xx, where xx is the offset. SYS_TEXT_BASE
- * is 0xFFF8 for PBL boot, and PBL only cares about low 24-bit,
- * so it starts from 0x81F8.
+ * is the start offset and PBL only cares about low 24-bit.
  */
-static uint32_t next_pbl_cmd = 0x81F8;
+static uint32_t next_pbl_cmd = 0x8100 | (CONFIG_SYS_TEXT_BASE  0xFF);
 /*
  * need to store all bytes in memory for calculating crc32, then write the
  * bytes to image file for PBL boot.
-- 
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[U-Boot] [PATCH] powerpc/corenet: Add workaround for ELBC multi-bit ECC error

[Shaohui Xie]

NAND operations in condition like below will result ELBC internal multi-bit
ECC error, DCFG will send this error to MPIC to report it as an error
interrupt (Interrupt 0), which causes call trace in kernel, so software
should disable the DCFG not to send the ELBC ECC error by setting bit 15
in the register at DCSRBASE + 0x0002_0520. This won't inhibit the reporting
of LTESR[PAR]. This workaround is enabled on P2041/P3041/P50x0.

steps to reproduce the issue:
1. power cycle the board
2. use following command to do NAND test:
flashcp -v file-jffs2 /dev/mtdx

The 'mtdx' should be a NAND partition, the file 'file-jffs2' should be
page aligned.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
resent due to patch work did not capture the patch.

 arch/powerpc/cpu/mpc85xx/cmd_errata.c |  3 +++
 arch/powerpc/cpu/mpc85xx/cpu_init.c   | 10 ++
 arch/powerpc/include/asm/config_mpc85xx.h |  4 
 3 files changed, 17 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 5d72f4c..671c205 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -227,6 +227,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
puts(Work-around for Erratum NMG_LBC103 enabled\n);
 #endif
+#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+   puts(Work-around for Erratum ELBC MULTIBIT ECC enabled\n);
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
puts(Work-around for Erratum NMG ETSEC129 enabled\n);
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index de9d916..c43be5e 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -592,6 +592,16 @@ skip_l2:
}
}
 #endif
+#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+   /*
+* On P2041/P3041/P50x0, NAND operations will result internal multi-bit
+* ECC error, which causes call trace in kernel, so software should
+* disable the ECC error reported from eLBC by setting bit 15 in
+* the register at DCSRBASE + 0x0002_0520.
+*/
+#define DCFG_ECC   (CONFIG_SYS_DCSRBAR + 0x20520)
+   setbits_be32((void *)DCFG_ECC, 1  (31 - 15));
+#endif
 
 #ifdef CONFIG_SYS_LBC_LCRR
/*
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index d57c178..926316d 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -345,6 +345,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -377,6 +378,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -451,6 +453,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P5040)
 #define CONFIG_SYS_PPC64
@@ -480,6 +483,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS1
-- 
1.8.0


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[U-Boot] [PATCH] powerpc/corenet: Add workaround for ELBC multi-bit ECC error

[Shaohui Xie]

NAND operations in condition like below will result ELBC internal multi-bit
ECC error, DCFG will send this error to MPIC to report it as an error
interrupt (Interrupt 0), which causes call trace in kernel, so software
should disable the DCFG not to send the ELBC ECC error by setting bit 15
in the register at DCSRBASE + 0x0002_0520. This won't inhibit the reporting
of LTESR[PAR]. This workaround is enabled on P2041/P3041/P50x0.

steps to reproduce the issue:
1. power cycle the board
2. use following command to do NAND test:
flashcp -v file-jffs2 /dev/mtdx

The 'mtdx' should be a NAND partition, the file 'file-jffs2' should be
page aligned.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Sorry! 
I have to resent since I still cannot find the patch in patch work.

 arch/powerpc/cpu/mpc85xx/cmd_errata.c |  3 +++
 arch/powerpc/cpu/mpc85xx/cpu_init.c   | 10 ++
 arch/powerpc/include/asm/config_mpc85xx.h |  4 
 3 files changed, 17 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 5d72f4c..671c205 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -227,6 +227,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
puts(Work-around for Erratum NMG_LBC103 enabled\n);
 #endif
+#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+   puts(Work-around for Erratum ELBC MULTIBIT ECC enabled\n);
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
puts(Work-around for Erratum NMG ETSEC129 enabled\n);
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index de9d916..c43be5e 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -592,6 +592,16 @@ skip_l2:
}
}
 #endif
+#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+   /*
+* On P2041/P3041/P50x0, NAND operations will result internal multi-bit
+* ECC error, which causes call trace in kernel, so software should
+* disable the ECC error reported from eLBC by setting bit 15 in
+* the register at DCSRBASE + 0x0002_0520.
+*/
+#define DCFG_ECC   (CONFIG_SYS_DCSRBAR + 0x20520)
+   setbits_be32((void *)DCFG_ECC, 1  (31 - 15));
+#endif
 
 #ifdef CONFIG_SYS_LBC_LCRR
/*
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index d57c178..926316d 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -345,6 +345,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -377,6 +378,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -451,6 +453,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P5040)
 #define CONFIG_SYS_PPC64
@@ -480,6 +483,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS1
-- 
1.8.0


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[U-Boot] [PATCH 1/2] powerpc/t4240qds: Fix SPI flash type

[Shaohui Xie]

T4240QDS uses a SST instead of SPANSION SPI flash.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 include/configs/t4qds.h |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index d58c24c..b3eaf5d 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -504,7 +504,7 @@ unsigned long get_board_ddr_clk(void);
  */
 #define CONFIG_FSL_ESPI
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_SST
 #define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED 1000
 #define CONFIG_SF_DEFAULT_MODE  0
-- 
1.6.4


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[U-Boot] [PATCH 2/2] powerpc/t4240qds: fix XAUI card PHY address

[Shaohui Xie]

Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
 include/configs/t4qds.h |8 
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index b3eaf5d..5f0286d 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -646,10 +646,10 @@ unsigned long get_board_ddr_clk(void);
 #define XFI_CARD_PORT3_PHY_ADDR0x3
 #define XFI_CARD_PORT4_PHY_ADDR0x4
 #define QSGMII_CARD_PHY_ADDR   0x5
-#define FM1_10GEC1_PHY_ADDR0x6
-#define FM1_10GEC2_PHY_ADDR0x7
-#define FM2_10GEC1_PHY_ADDR0x8
-#define FM2_10GEC2_PHY_ADDR0x9
+#define FM1_10GEC1_PHY_ADDR0x0
+#define FM1_10GEC2_PHY_ADDR0x1
+#define FM2_10GEC1_PHY_ADDR0x2
+#define FM2_10GEC2_PHY_ADDR0x3
 #endif
 
 #ifdef CONFIG_PCI
-- 
1.6.4


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[U-Boot] [PATCH] powerpc/Fman/mEMAC: mEMAC fix for 10G MAC and PHY

[Shaohui Xie]

1. use Payload length check disable when enable MAC;
2. add XGMII support for setting MAC interface mode;
3. only enable auto negotiation for Non-XGMII mode;
4. return 0x if clause 22 is used to read 10G phy_id;

Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
 arch/powerpc/include/asm/fsl_memac.h |1 +
 drivers/net/fm/memac.c   |   12 +---
 drivers/net/fm/memac_phy.c   |2 ++
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_memac.h 
b/arch/powerpc/include/asm/fsl_memac.h
index d6b60e6..7359f8b 100644
--- a/arch/powerpc/include/asm/fsl_memac.h
+++ b/arch/powerpc/include/asm/fsl_memac.h
@@ -172,6 +172,7 @@ struct memac {
 #define MEMAC_CMD_CFG_RX_EN0x0002 /* MAC Rx path enable */
 #define MEMAC_CMD_CFG_TX_EN0x0001 /* MAC Tx path enable */
 #define MEMAC_CMD_CFG_RXTX_EN  (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN)
+#define MEMAC_CMD_CFG_NO_LEN_CHK 0x2 /* Payload length check disable */
 
 /* HASHTABLE_CTRL - Hashtable control register */
 #define HASHTABLE_CTRL_MCAST_EN0x0200 /* enable mulitcast Rx hash 
*/
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 32c7054..8eec7b3 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -51,7 +51,8 @@ static void memac_enable_mac(struct fsl_enet_mac *mac)
 {
struct memac *regs = mac-base;
 
-   setbits_be32(regs-command_config, MEMAC_CMD_CFG_RXTX_EN);
+   setbits_be32(regs-command_config, MEMAC_CMD_CFG_RXTX_EN
+   | MEMAC_CMD_CFG_NO_LEN_CHK);
 }
 
 static void memac_disable_mac(struct fsl_enet_mac *mac)
@@ -106,11 +107,16 @@ static void memac_set_interface_mode(struct fsl_enet_mac 
*mac,
if_mode = ~IF_MODE_MASK;
if_mode |= (IF_MODE_GMII);
break;
+   case PHY_INTERFACE_MODE_XGMII:
+   if_mode = ~IF_MODE_MASK;
+   if_mode |= IF_MODE_XGMII;
+   break;
default:
break;
}
-   /* Enable automatic speed selection */
-   if_mode |= IF_MODE_EN_AUTO;
+   /* Enable automatic speed selection for Non-XGMII */
+   if (type != PHY_INTERFACE_MODE_XGMII)
+   if_mode |= IF_MODE_EN_AUTO;
 
debug( %s, if_mode = %x\n, __func__,  if_mode);
debug( %s, if_status = %x\n, __func__,  if_status);
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index ea6118b..18dc2aa 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -86,6 +86,8 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int 
dev_addr,
u32 c45 = 1;
 
if (dev_addr == MDIO_DEVAD_NONE) {
+   if (!strcmp(bus-name, DEFAULT_FM_TGEC_MDIO_NAME))
+   return 0x;
c45 = 0; /* clause 22 */
dev_addr = regnum  0x1f;
clrbits_be32(regs-mdio_stat, MDIO_STAT_ENC);
-- 
1.6.4


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[U-Boot] [PATCH] powerpc/corenet: Add workaround for ELBC multi-bit ECC error

[Shaohui Xie]

NAND operations in condition like below will result ELBC internal multi-bit
ECC error, DCFG will send this error to MPIC to report it as an error
interrupt (Interrupt 0), which causes call trace in kernel, so software
should disable the DCFG not to send the ELBC ECC error by setting bit 15
in the register at DCSRBASE + 0x0002_0520. This won't inhibit the reporting
of LTESR[PAR]. This workaround is enabled on P2041/P3041/P50x0.

steps to reproduce the issue:
1. power cycle the board
2. use following command to do NAND test:
flashcp -v file-jffs2 /dev/mtdx

The 'mtdx' should be a NAND partition, the file 'file-jffs2' should be
page aligned.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +++
 arch/powerpc/cpu/mpc85xx/cpu_init.c   |   10 ++
 arch/powerpc/include/asm/config_mpc85xx.h |4 
 3 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index e5ecf5d..f26d608 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -227,6 +227,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
puts(Work-around for Erratum NMG_LBC103 enabled\n);
 #endif
+#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+   puts(Work-around for Erratum ELBC MULTIBIT ECC enabled\n);
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
puts(Work-around for Erratum NMG ETSEC129 enabled\n);
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index d1155e8..5d6f996 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -564,6 +564,16 @@ skip_l2:
}
}
 #endif
+#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+   /*
+* On P2041/P3041/P50x0, NAND operations will result internal multi-bit
+* ECC error, which causes call trace in kernel, so software should
+* disable the ECC error reported from eLBC by setting bit 15 in
+* the register at DCSRBASE + 0x0002_0520.
+*/
+#define DCFG_ECC   (CONFIG_SYS_DCSRBAR + 0x20520)
+   setbits_be32((void *)DCFG_ECC, 1  (31 - 15));
+#endif
 
 #ifdef CONFIG_SYS_LBC_LCRR
/*
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 0b9638b..8f8aea7 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -345,6 +345,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -377,6 +378,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -451,6 +453,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P5040)
 #define CONFIG_SYS_PPC64
@@ -480,6 +483,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS1
-- 
1.6.4


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[U-Boot] [PATCH] powerpc/p5040: fix mdio mux for 10G port

[Shaohui Xie]

Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in
eth port enum structure, it will assign mdio mux depend on this assumption.
This is not true with Fman V3, which added more 1G ports after port DTSEC5
in eth port enum structure, then 10G ports on p5040 will have wrong mdio mux.
So we use dynamic index for 10G ports instead of hardcoded enum value
when doing mdio mux for 10G ports.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/corenet_ds/eth_superhydra.c |8 
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/freescale/corenet_ds/eth_superhydra.c 
b/board/freescale/corenet_ds/eth_superhydra.c
index ef9de25..ae07073 100644
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -605,8 +605,8 @@ int board_eth_init(bd_t *bis)
lane = serdes_get_first_lane(XAUI_FM1);
if (lane = 0) {
debug(FM1@TGEC1 expects XAUI in slot %u\n, 
lane_to_slot[lane]);
-   mdio_mux[FM1_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK;
-   mdio_mux[FM1_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT2;
+   mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
+   mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2;
super_hydra_mdio_set_mux(SUPER_HYDRA_FM1_TGEC_MDIO,
mdio_mux[i].mask, mdio_mux[i].val);
}
@@ -704,8 +704,8 @@ int board_eth_init(bd_t *bis)
lane = serdes_get_first_lane(XAUI_FM2);
if (lane = 0) {
debug(FM2@TGEC1 expects XAUI in slot %u\n, 
lane_to_slot[lane]);
-   mdio_mux[FM2_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK;
-   mdio_mux[FM2_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT1;
+   mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
+   mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1;
super_hydra_mdio_set_mux(SUPER_HYDRA_FM2_TGEC_MDIO,
mdio_mux[i].mask, mdio_mux[i].val);
}
-- 
1.6.4


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[U-Boot] [PATCH] powerpc/corenet: set USB2 default mode to 'device' for (super)hydra boards

[Shaohui Xie]

The Hydra and Superhydra (P3041DS, P5020DS, and P5040DS) boards have a
second USB port that can be configured in either host, peripheral (aka
device), or OTG (on-the-go) mode.  When configured in host mode, if
the port is connected to another USB host, damage to the board can
occur.

To avoid this, we change the default setting to peripheral mode.  Ideally,
we'd set it to OTG mode, but currently there is no OTG support for
these boards.

Setting the hwconfig variable will also update the device tree, and so
Linux will configure the port for peripheral mode as well.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 include/configs/corenet_ds.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 47f7b7e..1489b34 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -713,6 +713,7 @@
 #defineCONFIG_EXTRA_ENV_SETTINGS   \
hwconfig=fsl_ddr:ctlr_intlv=cacheline,\
bank_intlv=cs0_cs1;   \
+   usb2:dr_mode=peripheral,phy_type= __stringify(__USB_PHY_TYPE) ;\
usb1:dr_mode=host,phy_type= __stringify(__USB_PHY_TYPE) \0\
netdev=eth0\0 \
uboot= __stringify(CONFIG_UBOOTPATH) \0 \
-- 
1.6.4


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[U-Boot] [PATCH][v2] powerpc/p2041: fix serdes reference clock frequency display for PC board

[Shaohui Xie]

PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for v2:
fix logical error and use braces around multi-line if bodies.

 board/freescale/p2041rdb/p2041rdb.c |   11 +++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/board/freescale/p2041rdb/p2041rdb.c 
b/board/freescale/p2041rdb/p2041rdb.c
index 4e4d18f..6476c8b 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -227,6 +227,17 @@ int misc_init_r(void)
'00' is unsupported\n);
else
actual[i] = freq[i][clock];
+
+   /*
+* PC board uses a different CPLD with PB board, this CPLD
+* has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
+* board has cpld_ver_sub = 0, and pcba_ver = 4.
+*/
+   if ((i == 1)  (CPLD_READ(cpld_ver_sub) == 1)
+(CPLD_READ(pcba_ver) == 5)) {
+   /* PC board bank2 frequency */
+   actual[i] = freq[i-1][clock];
+   }
}
 
for (i = 0; i  NUM_SRDS_BANKS; i++) {
-- 
1.6.4


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[U-Boot] [PATCH] powerpc/p2041: fix serdes reference clock frequency for PC board

[Shaohui Xie]

PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/p2041rdb/p2041rdb.c |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/board/freescale/p2041rdb/p2041rdb.c 
b/board/freescale/p2041rdb/p2041rdb.c
index 4e4d18f..f6de0d3 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -227,6 +227,11 @@ int misc_init_r(void)
'00' is unsupported\n);
else
actual[i] = freq[i][clock];
+
+   if ((i == 1)  (CPLD_READ(cpld_ver_sub) == 1)
+(CPLD_READ(pcba_ver) == 5))
+   /* PC board frequency */
+   actual[i] = freq[i-1][clock];
}
 
for (i = 0; i  NUM_SRDS_BANKS; i++) {
-- 
1.6.4


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[U-Boot] [PATCH] powerpc/85xx: add missing QMAN frequency calculation

[Shaohui Xie]

When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not
be initialized, and QMAN will have a wrong frequency display.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 arch/powerpc/cpu/mpc85xx/speed.c |4 
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 801ee07..882fc5f 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -285,6 +285,10 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif
 #endif
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+   sysInfo-freqQMAN = sysInfo-freqSystemBus / 2;
+#endif
+
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
 #else /* CONFIG_FSL_CORENET */
-- 
1.6.4


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[U-Boot] [PATCH][v2] powerpc/p5040: enable NAND/SD/SPI boot support

[Shaohui Xie]

Also update README.pblimage for p5040.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for v2:
1. merge NAND/SD/SPI to one patch;
2. update README.pblimage for p5040;

 boards.cfg  |3 +++
 doc/README.pblimage |6 +++---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index e4b0d44..710942f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -855,6 +855,9 @@ P5020DS_SECURE_BOOT  powerpc mpc85xx 
corenet_ds  freesca
 P5020DS_SPIFLASHpowerpc mpc85xx corenet_ds  
freescale  -   P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
 P5020DS_SRIO_PCIE_BOOT  powerpc mpc85xx corenet_ds  
freescale  -   P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF8
 P5040DS  powerpc mpc85xx corenet_ds  
freescale
+P5040DS_NANDpowerpc mpc85xx corenet_ds  
freescale  -   P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
+P5040DS_SDCARD  powerpc mpc85xx corenet_ds  
freescale  -   P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
+P5040DS_SPIFLASHpowerpc mpc85xx corenet_ds  
freescale  -   P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
 BSC9131RDB_SPIFLASH  powerpc mpc85xx bsc9131rdb  
freescale  -   BSC9131RDB:BSC9131RDB,SPIFLASH
 stxgp3   powerpc mpc85xx stxgp3  stx
 stxssa   powerpc mpc85xx stxssa  stx   
 -   stxssa
diff --git a/doc/README.pblimage b/doc/README.pblimage
index 2b9bb5c..bbf7658 100644
--- a/doc/README.pblimage
+++ b/doc/README.pblimage
@@ -14,17 +14,17 @@ Building PBL Boot Image and boot steps
 1. Building PBL Boot Image.
The default Image is u-boot.pbl.
 
-   For eSPI boot(available on P3041/P4080/P5020):
+   For eSPI boot(available on P3041/P4080/P5020/P5040):
To build the eSPI boot image:
make board_name_SPIFLASH_config
make u-boot.pbl
 
-   For SD boot(available on P3041/P4080/P5020):
+   For SD boot(available on P3041/P4080/P5020/P5040):
To build the SD boot image:
make board_name_SDCARD_config
make u-boot.pbl
 
-   For Nand boot(available on P3041/P5020):
+   For Nand boot(available on P3041/P5020/P5040):
To build the NAND boot image:
make board_name_NAND_config
make u-boot.pbl
-- 
1.6.4


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[U-Boot] [PATCH] powerpc/p5040: enable PBL tool support

[Shaohui Xie]

Provided a default RCW for P5040, then it can use PBL to build
ramboot image.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/corenet_ds/rcw_p5040ds.cfg |   11 +++
 include/configs/corenet_ds.h   |2 ++
 2 files changed, 13 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/corenet_ds/rcw_p5040ds.cfg

diff --git a/board/freescale/corenet_ds/rcw_p5040ds.cfg 
b/board/freescale/corenet_ds/rcw_p5040ds.cfg
new file mode 100644
index 000..82fa741
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p5040ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P5040DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+0c58  22121200 
+089c4400 00283000 5800 6100
+   1007
+   
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 3f42cd9..06281c6 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -38,6 +38,8 @@
 #define CONFIG_PBLRCW_CONFIG 
$(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
 #elif defined(CONFIG_P5020DS)
 #define CONFIG_PBLRCW_CONFIG 
$(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
+#elif defined(CONFIG_P5040DS)
+#define CONFIG_PBLRCW_CONFIG 
$(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
 #endif
 #endif
 
-- 
1.6.4


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[U-Boot] [PATCH 2/3] powerpc/p5040: enable SD boot support

[Shaohui Xie]

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 boards.cfg |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index 8cf4936..314afa2 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -856,6 +856,7 @@ P5020DS_SPIFLASH powerpc mpc85xx corenet_ds 
 freescale
 P5020DS_SRIO_PCIE_BOOT  powerpc mpc85xx corenet_ds  
freescale  -   P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF8
 P5040DS  powerpc mpc85xx corenet_ds  
freescale
 P5040DS_NANDpowerpc mpc85xx corenet_ds  
freescale  -   P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
+P5040DS_SDCARD  powerpc mpc85xx corenet_ds  
freescale  -   P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
 BSC9131RDB_SPIFLASH  powerpc mpc85xx bsc9131rdb  
freescale  -   BSC9131RDB:BSC9131RDB,SPIFLASH
 stxgp3   powerpc mpc85xx stxgp3  stx
 stxssa   powerpc mpc85xx stxssa  stx   
 -   stxssa
-- 
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[U-Boot] [PATCH 1/3] powerpc/p5040: enable NAND boot support

[Shaohui Xie]

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 boards.cfg |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index e4b0d44..8cf4936 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -855,6 +855,7 @@ P5020DS_SECURE_BOOT  powerpc mpc85xx 
corenet_ds  freesca
 P5020DS_SPIFLASHpowerpc mpc85xx corenet_ds  
freescale  -   P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
 P5020DS_SRIO_PCIE_BOOT  powerpc mpc85xx corenet_ds  
freescale  -   P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF8
 P5040DS  powerpc mpc85xx corenet_ds  
freescale
+P5040DS_NANDpowerpc mpc85xx corenet_ds  
freescale  -   P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
 BSC9131RDB_SPIFLASH  powerpc mpc85xx bsc9131rdb  
freescale  -   BSC9131RDB:BSC9131RDB,SPIFLASH
 stxgp3   powerpc mpc85xx stxgp3  stx
 stxssa   powerpc mpc85xx stxssa  stx   
 -   stxssa
-- 
1.6.4


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[U-Boot] [PATCH 3/3] powerpc/p5040: enable SPI boot support

[Shaohui Xie]

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 boards.cfg |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index 314afa2..710942f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -857,6 +857,7 @@ P5020DS_SRIO_PCIE_BOOT  powerpc mpc85xx 
corenet_ds  free
 P5040DS  powerpc mpc85xx corenet_ds  
freescale
 P5040DS_NANDpowerpc mpc85xx corenet_ds  
freescale  -   P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
 P5040DS_SDCARD  powerpc mpc85xx corenet_ds  
freescale  -   P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
+P5040DS_SPIFLASHpowerpc mpc85xx corenet_ds  
freescale  -   P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
 BSC9131RDB_SPIFLASH  powerpc mpc85xx bsc9131rdb  
freescale  -   BSC9131RDB:BSC9131RDB,SPIFLASH
 stxgp3   powerpc mpc85xx stxgp3  stx
 stxssa   powerpc mpc85xx stxssa  stx   
 -   stxssa
-- 
1.6.4


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[U-Boot] [PATCH] net/phy: fix select line for TN80xx

[Shaohui Xie]

TN80xx has same PHY ID as TN2020, but it needs different setting to register
30.93 which used to select line, so we read register 30.32 which has
bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2,
for TN80xx we will get 5 or 4.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 drivers/net/phy/teranetics.c |   15 +--
 1 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c
index 78447b7..c0f13b8 100644
--- a/drivers/net/phy/teranetics.c
+++ b/drivers/net/phy/teranetics.c
@@ -34,9 +34,20 @@ int tn2020_config(struct phy_device *phydev)
unsigned short restart_an = (MDIO_AN_CTRL1_RESTART |
MDIO_AN_CTRL1_ENABLE |
MDIO_AN_CTRL1_XNP);
+   u8 phy_hwversion;
 
-   phy_write(phydev, 30, 93, 2);
-   phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an);
+   /*
+* bit 15:12 of register 30.32 indicates PHY hardware
+* version. It can be used to distinguish TN80xx from
+* TN2020. TN2020 needs write 0x2 to 30.93, but TN80xx
+* needs 0x1.
+*/
+   phy_hwversion = (phy_read(phydev, 30, 32)  12)  0xf;
+   if (phy_hwversion = 3) {
+   phy_write(phydev, 30, 93, 2);
+   phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an);
+   } else
+   phy_write(phydev, 30, 93, 1);
}
 
return 0;
-- 
1.6.4


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[U-Boot] [PATCH] powerpc/p2041: move Lanes mux to board early init

[Shaohui Xie]

Lanes mux currently is configured in eth.c when initializing FMAN ethernet
ports, but SRIO and PCIe also need lanes mux, so we move the lanes mux to
p2041rdb.c which implements a board-specific initialization and will be
called at early stage.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/p2041rdb/eth.c  |   39 ---
 board/freescale/p2041rdb/p2041rdb.c |   44 +++
 2 files changed, 44 insertions(+), 39 deletions(-)

diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index fec9777..4b0d577 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -136,11 +136,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
 }
 #endif /* #ifdef CONFIG_FMAN_ENET */
 
-#define CPLD_LANE_A_SEL0x1
-#define CPLD_LANE_G_SEL0x2
-#define CPLD_LANE_C_SEL0x4
-#define CPLD_LANE_D_SEL0x8
-
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FMAN_ENET
@@ -148,10 +143,6 @@ int board_eth_init(bd_t *bis)
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
int lane;
-   ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-   int srds_prtcl = (in_be32(gur-rcwsr[4]) 
-   FSL_CORENET_RCWSR4_SRDS_PRTCL)  26;
-   u8 mux = CPLD_READ(serdes_mux);
 
printf(Initializing Fman\n);
 
@@ -181,36 +172,6 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
 
-   mux = ~(CPLD_LANE_A_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL);
-   switch (srds_prtcl) {
-   case 0x2:
-   case 0xf:
-   mux = ~CPLD_LANE_G_SEL;
-   break;
-   case 0x5:
-   case 0x9:
-   case 0xa:
-   case 0x17:
-   mux |= CPLD_LANE_G_SEL;
-   break;
-   case 0x14:
-   mux = (mux  (~CPLD_LANE_G_SEL)) | CPLD_LANE_A_SEL;
-   break;
-   case 0x8:
-   case 0x16:
-   case 0x19:
-   case 0x1a:
-   mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
-   break;
-   case 0x1c:
-   mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
-   break;
-   default:
-   printf(Fman:Unsupported SerDes Protocol 0x%02x\n, srds_prtcl);
-   break;
-   }
-   CPLD_WRITE(serdes_mux, mux);
-
for (i = FM1_DTSEC1; i  FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
 
diff --git a/board/freescale/p2041rdb/p2041rdb.c 
b/board/freescale/p2041rdb/p2041rdb.c
index 51c4310..3bda09c 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -105,6 +105,49 @@ int board_early_init_f(void)
return 0;
 }
 
+#define CPLD_LANE_A_SEL0x1
+#define CPLD_LANE_G_SEL0x2
+#define CPLD_LANE_C_SEL0x4
+#define CPLD_LANE_D_SEL0x8
+
+void board_config_lanes_mux(void)
+{
+   ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+   int srds_prtcl = (in_be32(gur-rcwsr[4]) 
+   FSL_CORENET_RCWSR4_SRDS_PRTCL)  26;
+
+   u8 mux = 0;
+   switch (srds_prtcl) {
+   case 0x2:
+   case 0x5:
+   case 0x9:
+   case 0xa:
+   case 0xf:
+   break;
+   case 0x8:
+   mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+   break;
+   case 0x14:
+   mux |= CPLD_LANE_A_SEL;
+   break;
+   case 0x17:
+   mux |= CPLD_LANE_G_SEL;
+   break;
+   case 0x16:
+   case 0x19:
+   case 0x1a:
+   mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+   break;
+   case 0x1c:
+   mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
+   break;
+   default:
+   printf(Fman:Unsupported SerDes Protocol 0x%02x\n, srds_prtcl);
+   break;
+   }
+   CPLD_WRITE(serdes_mux, mux);
+}
+
 int board_early_init_r(void)
 {
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
@@ -128,6 +171,7 @@ int board_early_init_r(void)
 
set_liodns();
setup_portals();
+   board_config_lanes_mux();
 
return 0;
 }
-- 
1.6.4


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[U-Boot] [PATCH] powerpc/fm: fix TBI PHY address settings

[Shaohui Xie]

From: shaohui xie shaohui@freescale.com

TBI PHY address (TBIPA) register is set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c, and
it is supposed to set TBIPA on FM1@DTSEC1 in case of FM1@DTSEC1
isn't used directly, which provides MDIO for other ports. So
following code is wrong in case of FM2, which has a different
mac base.

struct dtsec *regs = (struct dtsec *)fm_eth-mac-base;
/* Assign a Physical address to the TBI */
out_be32(regs-tbipa, CONFIG_SYS_TBIPA_VALUE);

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 drivers/net/fm/eth.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 2b616ad..c8dc1d0 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -65,7 +65,7 @@ void dtsec_configure_serdes(struct fm_eth *priv)
 static void dtsec_init_phy(struct eth_device *dev)
 {
struct fm_eth *fm_eth = dev-priv;
-   struct dtsec *regs = (struct dtsec *)fm_eth-mac-base;
+   struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
 
/* Assign a Physical address to the TBI */
out_be32(regs-tbipa, CONFIG_SYS_TBIPA_VALUE);
-- 
1.6.4


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[U-Boot] [PATCH] powerpc/espi: remove write command length check

[Shaohui Xie]

Current espi controller driver assumes the command length of write command is
not equal to '1', it was made based on SPANSION SPI flash, but some SPI flash
driver such as SST does use write command length as '1', so write command on
SST SPI flash will not work. And the length check for write command is not
necessary for SPANSION, though it's harmless for SPANSION, it will stop write
operation on flashes like SST, so we remove the check.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 drivers/spi/fsl_espi.c |6 ++
 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index a1ebd33..eb99e90 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -216,10 +216,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 
const void *data_out,
return 1;
}
memcpy(buffer, cmd_buf, cmd_len);
-   if (cmd_len != 1) {
-   if (data_in == NULL)
-   memcpy(buffer + cmd_len, data_out, data_len);
-   }
+   if (data_in == NULL)
+   memcpy(buffer + cmd_len, data_out, data_len);
break;
case SPI_XFER_BEGIN | SPI_XFER_END:
len = data_len;
-- 
1.7.0.4


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[U-Boot] [PATCH][v4] powerpc/CoreNet: add tool to support pbl image build.

[Shaohui Xie]

Provides a tool to build boot Image for PBL(Pre boot loader) which is
used on Freescale CoreNet SoCs, PBL can be used to load some instructions
and/or data for pre-initialization. The default output image is u-boot.pbl,
for more details please refer to doc/README.pblimage.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for v4:
1. provid default RCW config file for p3041, p4080, p5020.

changes for v3:
1. dump config.mk, aligned to comment of Wolfgang Denk;
2. split one configuration file to two, one is for RCW,
one is for PBI commands, add second entry in mkimage
for second configuration file, aligned to
comment of Wood Scott;
3. refined the README.pblimage;

 Makefile   |6 +
 board/freescale/corenet_ds/pbi.cfg |   51 +
 board/freescale/corenet_ds/rcw_p3041ds.cfg |   11 +
 board/freescale/corenet_ds/rcw_p4080ds.cfg |   11 +
 board/freescale/corenet_ds/rcw_p5020ds.cfg |   11 +
 common/image.c |1 +
 doc/README.pblimage|  114 ++
 include/configs/corenet_ds.h   |8 +
 include/image.h|1 +
 tools/Makefile |2 +
 tools/mkimage.c|   15 ++
 tools/mkimage.h|3 +
 tools/pblimage.c   |  331 
 tools/pblimage.h   |   36 +++
 14 files changed, 601 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/corenet_ds/pbi.cfg
 create mode 100644 board/freescale/corenet_ds/rcw_p3041ds.cfg
 create mode 100644 board/freescale/corenet_ds/rcw_p4080ds.cfg
 create mode 100644 board/freescale/corenet_ds/rcw_p5020ds.cfg
 create mode 100644 doc/README.pblimage
 create mode 100644 tools/pblimage.c
 create mode 100644 tools/pblimage.h

diff --git a/Makefile b/Makefile
index 73c8e39..d518588 100644
--- a/Makefile
+++ b/Makefile
@@ -427,6 +427,11 @@ $(obj)u-boot.kwb:   $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $ $@
 
+$(obj)u-boot.pbl:  $(obj)u-boot.bin
+   $(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \
+   -R $(CONFIG_PBLPBI_CONFIG) -T pblimage \
+   -d $ $@
+
 $(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)tools/ubsha1 $(obj)u-boot.bin
 
@@ -787,6 +792,7 @@ clobber:tidy
$(obj)cscope.* $(obj)*.*~
@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y)
@rm -f $(obj)u-boot.kwb
+   @rm -f $(obj)u-boot.pbl
@rm -f $(obj)u-boot.imx
@rm -f $(obj)u-boot.ubl
@rm -f $(obj)u-boot.ais
diff --git a/board/freescale/corenet_ds/pbi.cfg 
b/board/freescale/corenet_ds/pbi.cfg
new file mode 100644
index 000..50806ca
--- /dev/null
+++ b/board/freescale/corenet_ds/pbi.cfg
@@ -0,0 +1,51 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1 as 1MB SRAM
+0901 00200400
+09138000 
+091380c0 0100
+09010100 
+09010104 fffb
+09010f00 0800
+0901 8000
+#Configure LAW for CPC1
+09000d00 
+09000d04 fff0
+09000d08 8113
+0910 
+0914 ff00
+0918 8100
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+0911 8403
+09110020 2d170008
+09110024 0018
+09110028 0018
+0911002c 0018
+#Flush PBL data
+09138000 
+091380c0 
diff --git a/board/freescale/corenet_ds/rcw_p3041ds.cfg 
b/board/freescale/corenet_ds/rcw_p3041ds.cfg
new file mode 100644
index 000..8813156
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p3041ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P3041DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+1260  241C 
+D8984A01 03002000 5800 4100
+   1007

[U-Boot] [PATCH] powerpc/p2041: configure the CPLD lane_mux according to RCW

[Shaohui Xie]

Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg
is 0xc, CPLD supports SATA by default, we should re-configure the lane
muxing according to RCW, which indicates what SerDes protocol it is running.

Default lane muxing map is as below:
Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg;
Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg;
Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2
and bit 3 respectively.

Default value of these bits for lane muxing is '1', we should set or clear
these bits accoring to RCW.

Signed-off-by: Shaohui Xie shaohui@freescale.com
Acked-by: Timur Tabi ti...@freescale.com
---
 board/freescale/p2041rdb/eth.c |   39 +++
 1 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 4b0d577..fec9777 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -136,6 +136,11 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
 }
 #endif /* #ifdef CONFIG_FMAN_ENET */
 
+#define CPLD_LANE_A_SEL0x1
+#define CPLD_LANE_G_SEL0x2
+#define CPLD_LANE_C_SEL0x4
+#define CPLD_LANE_D_SEL0x8
+
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FMAN_ENET
@@ -143,6 +148,10 @@ int board_eth_init(bd_t *bis)
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
int lane;
+   ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+   int srds_prtcl = (in_be32(gur-rcwsr[4]) 
+   FSL_CORENET_RCWSR4_SRDS_PRTCL)  26;
+   u8 mux = CPLD_READ(serdes_mux);
 
printf(Initializing Fman\n);
 
@@ -172,6 +181,36 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
 
+   mux = ~(CPLD_LANE_A_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL);
+   switch (srds_prtcl) {
+   case 0x2:
+   case 0xf:
+   mux = ~CPLD_LANE_G_SEL;
+   break;
+   case 0x5:
+   case 0x9:
+   case 0xa:
+   case 0x17:
+   mux |= CPLD_LANE_G_SEL;
+   break;
+   case 0x14:
+   mux = (mux  (~CPLD_LANE_G_SEL)) | CPLD_LANE_A_SEL;
+   break;
+   case 0x8:
+   case 0x16:
+   case 0x19:
+   case 0x1a:
+   mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+   break;
+   case 0x1c:
+   mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
+   break;
+   default:
+   printf(Fman:Unsupported SerDes Protocol 0x%02x\n, srds_prtcl);
+   break;
+   }
+   CPLD_WRITE(serdes_mux, mux);
+
for (i = FM1_DTSEC1; i  FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
 
-- 
1.6.4


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[U-Boot] [PATCH][v3] powerpc/CoreNet: add tool to support pbl image build.

[Shaohui Xie]

Provides a tool to build boot Image for PBL(Pre boot loader) which is
used on Freescale CoreNet SoCs, PBL can be used to load some instructions
and/or data for pre-initialization. The default output image is u-boot.pbl,
for more details please refer to doc/README.pblimage.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for v3:
1. dump config.mk, aligned to comment of Wolfgang Denk;
2. split one configuration file to two, one is for RCW, one is for PBI
commands, add second entry in mkimage for second configuration file,
aligned to comment of Wood Scott;
3. refined the README.pblimage;

 Makefile   |6 +
 board/freescale/corenet_ds/pbi.cfg |   51 ++
 board/freescale/corenet_ds/rcw.cfg |   32 
 common/image.c |1 +
 doc/README.pblimage|  114 +
 include/configs/corenet_ds.h   |2 +
 include/image.h|1 +
 tools/Makefile |2 +
 tools/mkimage.c|   15 ++
 tools/mkimage.h|3 +
 tools/pblimage.c   |  328 
 tools/pblimage.h   |   36 
 12 files changed, 591 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/corenet_ds/pbi.cfg
 create mode 100644 board/freescale/corenet_ds/rcw.cfg
 create mode 100644 doc/README.pblimage
 create mode 100644 tools/pblimage.c
 create mode 100644 tools/pblimage.h

diff --git a/Makefile b/Makefile
index 57ad45b..98421b9 100644
--- a/Makefile
+++ b/Makefile
@@ -416,6 +416,11 @@ $(obj)u-boot.kwb:   $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $ $@
 
+$(obj)u-boot.pbl:  $(obj)u-boot.bin
+   $(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \
+   -R $(CONFIG_PBLPBI_CONFIG) -T pblimage \
+   -d $ $@
+
 $(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)tools/ubsha1 $(obj)u-boot.bin
 
@@ -773,6 +778,7 @@ clobber:tidy
$(obj)cscope.* $(obj)*.*~
@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y)
@rm -f $(obj)u-boot.kwb
+   @rm -f $(obj)u-boot.pbl
@rm -f $(obj)u-boot.imx
@rm -f $(obj)u-boot.ubl
@rm -f $(obj)u-boot.ais
diff --git a/board/freescale/corenet_ds/pbi.cfg 
b/board/freescale/corenet_ds/pbi.cfg
new file mode 100644
index 000..50806ca
--- /dev/null
+++ b/board/freescale/corenet_ds/pbi.cfg
@@ -0,0 +1,51 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1 as 1MB SRAM
+0901 00200400
+09138000 
+091380c0 0100
+09010100 
+09010104 fffb
+09010f00 0800
+0901 8000
+#Configure LAW for CPC1
+09000d00 
+09000d04 fff0
+09000d08 8113
+0910 
+0914 ff00
+0918 8100
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+0911 8403
+09110020 2d170008
+09110024 0018
+09110028 0018
+0911002c 0018
+#Flush PBL data
+09138000 
+091380c0 
diff --git a/board/freescale/corenet_ds/rcw.cfg 
b/board/freescale/corenet_ds/rcw.cfg
new file mode 100644
index 000..424c7c4
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw.cfg
@@ -0,0 +1,32 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details

[U-Boot] [PATCH][v2] powerpc/CoreNet: add tool to support pbl image build.

[Shaohui Xie]

Provides a tool to build boot Image for PBL(Pre boot loader) which is
used on Freescale CoreNet SoCs, PBL can be used to load some instructions
and/or data for pre-initialization. The default output image is u-boot.pbl,
for more details please refer to doc/README.pblimage.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 Makefile|5 +
 board/freescale/corenet_ds/config.mk|   26 +++
 board/freescale/corenet_ds/pblimage.cfg |   60 ++
 common/image.c  |1 +
 doc/README.pblimage |  138 +
 include/image.h |1 +
 tools/Makefile  |2 +
 tools/mkimage.c |5 +
 tools/mkimage.h |2 +
 tools/pblimage.c|  325 +++
 tools/pblimage.h|   36 
 11 files changed, 601 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/corenet_ds/config.mk
 create mode 100644 board/freescale/corenet_ds/pblimage.cfg
 create mode 100644 doc/README.pblimage
 create mode 100644 tools/pblimage.c
 create mode 100644 tools/pblimage.h

diff --git a/Makefile b/Makefile
index 57ad45b..06f079f 100644
--- a/Makefile
+++ b/Makefile
@@ -416,6 +416,10 @@ $(obj)u-boot.kwb:   $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $ $@
 
+$(obj)u-boot.pbl:  $(obj)u-boot.bin
+   $(obj)tools/mkimage -n $(CONFIG_PBL_CONFIG) -T pblimage \
+   -d $ $@
+
 $(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)tools/ubsha1 $(obj)u-boot.bin
 
@@ -773,6 +777,7 @@ clobber:tidy
$(obj)cscope.* $(obj)*.*~
@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y)
@rm -f $(obj)u-boot.kwb
+   @rm -f $(obj)u-boot.pbl
@rm -f $(obj)u-boot.imx
@rm -f $(obj)u-boot.ubl
@rm -f $(obj)u-boot.ais
diff --git a/board/freescale/corenet_ds/config.mk 
b/board/freescale/corenet_ds/config.mk
new file mode 100644
index 000..2a0ab9d
--- /dev/null
+++ b/board/freescale/corenet_ds/config.mk
@@ -0,0 +1,26 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+ifeq ($(CONFIG_RAMBOOT_PBL), y)
+CONFIG_PBL_CONFIG = $(SRCTREE)/$(CONFIG_BOARDDIR)/pblimage.cfg
+ALL-y += $(obj)u-boot.pbl
+endif
diff --git a/board/freescale/corenet_ds/pblimage.cfg 
b/board/freescale/corenet_ds/pblimage.cfg
new file mode 100644
index 000..01003ce
--- /dev/null
+++ b/board/freescale/corenet_ds/pblimage.cfg
@@ -0,0 +1,60 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+# Written-by: Shaohui Xieshaohui@freescale.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data for P4080, replace it when building image
+#for P3041DS or P5020DS.
+4c58  18185218 
+40464000 3c3c2000 5800 6100
+   008b6000
+   
+
+#PBI commands
+#Initialize CPC1
+0901 00200400
+09138000 
+091380c0 0100
+09010100 
+09010104 fffb
+09010f00 0800
+0901 8000
+#Configure LAW for CPC1
+09000d00 

[U-Boot] [PATCH] powerpc/CoreNet: add tool to support pbl image build.

[Shaohui Xie]

From: Shaohui Xie b21...@freescale.com

Provides a tool to build boot Image for PBL(Pre boot loader) which is
used on Freescale CoreNet SoCs, PBL can be used to load some instructions
and/or data for pre-initialization. The default output image is u-boot.pbl,
for more details please refer to doc/README.pblimage.

Signed-off-by: Shaohui Xie b21...@freescale.com
---
rebased to lasted tree.

 Makefile|5 +
 board/freescale/corenet_ds/config.mk|   26 +++
 board/freescale/corenet_ds/pblimage.cfg |   60 ++
 common/image.c  |1 +
 doc/README.pblimage |  140 +
 include/image.h |1 +
 tools/Makefile  |2 +
 tools/mkimage.c |5 +
 tools/mkimage.h |2 +
 tools/pblimage.c|  329 +++
 tools/pblimage.h|   36 
 11 files changed, 607 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/corenet_ds/config.mk
 create mode 100644 board/freescale/corenet_ds/pblimage.cfg
 create mode 100644 doc/README.pblimage
 create mode 100644 tools/pblimage.c
 create mode 100644 tools/pblimage.h

diff --git a/Makefile b/Makefile
index 57ad45b..99f993a 100644
--- a/Makefile
+++ b/Makefile
@@ -416,6 +416,10 @@ $(obj)u-boot.kwb:   $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $ $@
 
+$(obj)u-boot.pbl:   $(obj)u-boot.bin
+   $(obj)tools/mkimage -n $(CONFIG_PBL_CONFIG) -T pblimage \
+   -d $ $@
+
 $(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)tools/ubsha1 $(obj)u-boot.bin
 
@@ -773,6 +777,7 @@ clobber:tidy
$(obj)cscope.* $(obj)*.*~
@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y)
@rm -f $(obj)u-boot.kwb
+   @rm -f $(obj)u-boot.pbl
@rm -f $(obj)u-boot.imx
@rm -f $(obj)u-boot.ubl
@rm -f $(obj)u-boot.ais
diff --git a/board/freescale/corenet_ds/config.mk 
b/board/freescale/corenet_ds/config.mk
new file mode 100644
index 000..72464dc
--- /dev/null
+++ b/board/freescale/corenet_ds/config.mk
@@ -0,0 +1,26 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+ifeq ($(CONFIG_RAMBOOT_PBL), y)
+CONFIG_PBL_CONFIG = $(SRCTREE)/$(CONFIG_BOARDDIR)/pblimage.cfg
+ALL-y += $(obj)u-boot.pbl
+endif
diff --git a/board/freescale/corenet_ds/pblimage.cfg 
b/board/freescale/corenet_ds/pblimage.cfg
new file mode 100644
index 000..898fe6d
--- /dev/null
+++ b/board/freescale/corenet_ds/pblimage.cfg
@@ -0,0 +1,60 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+# Written-by: Shaohui Xieb21...@freescale.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data for P4080, replace it when building image
+#for P3041DS or P5020DS.
+4c58  18185218 
+40464000 3c3c2000 5800 6100
+   008b6000
+   
+
+#PBI commands
+#Initialize CPC1
+0901 00200400
+09138000 
+091380c0 0100
+09010100 
+09010104 fffb
+09010f00 0800
+0901

[U-Boot] [PATCH 2/2] powerpc/p2041rdb: add env in NAND support

[Shaohui Xie]

Add env in NAND support when boot from NAND.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 include/configs/P2041RDB.h |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 501726c..fe39d4e 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -96,6 +96,11 @@
#define CONFIG_SYS_MMC_ENV_DEV  0
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET   (512 * 1097)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZECONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET  (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
-- 
1.6.4


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[U-Boot] [PATCH 1/2] powerpc/p2041rdb: add NAND and NAND boot support

[Shaohui Xie]

New P2041RDB board will add a NAND chip, so add support for NAND and
NAND boot.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 boards.cfg |1 +
 include/configs/P2041RDB.h |   54 +--
 2 files changed, 52 insertions(+), 3 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index 05ce1ae..4e4e9a5 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -748,6 +748,7 @@ P2020RDB-PC_SPIFLASH powerpc mpc85xx 
p1_p2_rdb_pcfreesca
 P2020RDB_SDCARD  powerpc mpc85xx p1_p2_rdb   
freescale  -   P1_P2_RDB:P2020RDB,SDCARD
 P2020RDB_SPIFLASHpowerpc mpc85xx p1_p2_rdb   
freescale  -   P1_P2_RDB:P2020RDB,SPIFLASH
 P2041RDB powerpc mpc85xx p2041rdb
freescale
+P2041RDB_NAND   powerpc mpc85xx p2041rdb
freescale  -   P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
 P2041RDB_SDCARD  powerpc mpc85xx p2041rdb
freescale  -   P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
 P2041RDB_SECURE_BOOT powerpc mpc85xx p2041rdb
freescale  -   P2041RDB:SECURE_BOOT
 P2041RDB_SPIFLASHpowerpc mpc85xx p2041rdb
freescale  -   
P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index da98f8f..501726c 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -186,10 +186,11 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_SYS_BR0_PRELIM \
+#define CONFIG_SYS_FLASH_BR_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7  ~OR_GPCM_SCY  ~OR_GPCM_EHTR) \
-   | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
+#define CONFIG_SYS_FLASH_OR_PRELIM \
+   ((0xf8000ff7  ~OR_GPCM_SCY  ~OR_GPCM_EHTR) \
+| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 
 #define CONFIG_FSL_CPLD
 #define CPLD_BASE  0xffdf  /* CPLD registers */
@@ -221,6 +222,53 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_RAMBOOT
 #endif
 
+#define CONFIG_NAND_FSL_ELBC
+/* Nand Flash */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE   0xffa0
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS  0xfffa0ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS  CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE(128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+  | (2BR_DECC_SHIFT)/* Use HW ECC */ \
+  | BR_PS_8   /* Port Size = 8 bit */ \
+  | BR_MS_FCM /* MSEL = FCM */ \
+  | BR_V) /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC   /* length 256K */ \
+  | OR_FCM_PGS/* Large Page*/ \
+  | OR_FCM_CSCT \
+  | OR_FCM_CST \
+  | OR_FCM_CHT \
+  | OR_FCM_SCY_1 \
+  | OR_FCM_TRLX \
+  | OR_FCM_EHTR)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address 
*/
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address 
*/
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address 
*/
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address 
*/
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address 
*/
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#endif /* CONFIG_NAND_FSL_ELBC */
+
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 #define CONFIG_SYS_FLASH_BANKS_LIST{CONFIG_SYS_FLASH_BASE_PHYS}
-- 
1.6.4


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[U-Boot] [PATCH] p2041rdb: fix serdes clock map

[Shaohui Xie]

Description of SerDes clock Bank2 setting in p2041 hardware specification
is wrong, the clock map which based on it is wrong either, so fix the
serdes clock map.

wrong setting of SERDES Reference Clocks Bank2:
SW2[5:6] = ON OFF   =100MHz for PCI mode
SW2[5:6] = OFF ON   =125MHz for SGMII mode

right setting of SERDES Reference Clocks Bank2:
SW2[5:6] = OFF OFF  =100MHz for PCI mode
SW2[5:6] = OFF ON   =125MHz for SGMII mode
SW2[5:6] = ON OFF   =156.25MHZ

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/p2041rdb/p2041rdb.c |   25 +++--
 1 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/board/freescale/p2041rdb/p2041rdb.c 
b/board/freescale/p2041rdb/p2041rdb.c
index 6461bd7..1f6a34b 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -83,10 +83,12 @@ int checkboard(void)
puts(SERDES Reference Clocks: );
sw = in_8(CPLD_SW(2))  2;
for (i = 0; i  2; i++) {
-   static const char * const freq[] = {0, 100, 125};
+   static const char * const freq[][3] = {{0, 100, 125},
+   {100, 156.25, 125}
+   };
unsigned int clock = (sw  (2 * i))  3;
 
-   printf(Bank%u=%sMhz , i+1, freq[clock]);
+   printf(Bank%u=%sMhz , i+1, freq[i][clock]);
}
puts(\n);
 
@@ -166,22 +168,25 @@ int misc_init_r(void)
u32 actual[NUM_SRDS_BANKS];
unsigned int i;
u8 sw;
+   static const int freq[][3] = {
+   {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
+   {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
+   SRDS_PLLCR0_RFCK_SEL_125}
+   };
 
sw = in_8(CPLD_SW(2))  2;
for (i = 0; i  NUM_SRDS_BANKS; i++) {
unsigned int clock = (sw  (2 * i))  3;
-   switch (clock) {
-   case 1:
-   actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
-   break;
-   case 2:
-   actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
-   break;
-   default:
+   if (clock == 0x3) {
printf(Warning: SDREFCLK%u switch setting of '11' is 
   unsupported\n, i + 1);
break;
}
+   if (i == 0  clock == 0)
+   puts(Warning: SDREFCLK1 switch setting of
+   '00' is unsupported\n);
+   else
+   actual[i] = freq[i][clock];
}
 
for (i = 0; i  NUM_SRDS_BANKS; i++) {
-- 
1.6.4


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[U-Boot] [PATCH] powerpc/usb: fix usb mode and phy_type

[Shaohui Xie]

Currently, to make usb work as different modes, we need to set its' dr_mode
string in 'hwconfig', and it will be handled by fdt_fixup_usb_mode_phy_type().
This API has a hardcoded compat which is fsl-usb2-dr, so it should not
be called when handle the 'hwconfig' for 'usb1', 'usb1' has a compat of
fsl-usb2-mph in dts, otherwise, dr_mode of 'usb2' will be set when handling
'usb1', and this will cause error when handling 'usb2'.

Also, sometimes phy_type may need to be set for both USB controllers,
hardcoded compat is limited to handle this, so add compat fsl-usb2-mph
handle in the API.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 arch/powerpc/cpu/mpc8xxx/fdt.c |   40 +++-
 1 files changed, 19 insertions(+), 21 deletions(-)

diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 112c603..a2b56ae 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -88,9 +88,9 @@ void ft_fixup_num_cores(void *blob) {
 
 #ifdef CONFIG_HAS_FSL_DR_USB
 static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
-   const char *phy_type)
+   const char *phy_type, int port)
 {
-   const char *compat = fsl-usb2-dr;
+   const char *compat[] = {fsl-usb2-mph, fsl-usb2-dr};
const char *prop_mode = dr_mode;
const char *prop_type = phy_type;
static int start_offset = -1;
@@ -98,27 +98,27 @@ static void fdt_fixup_usb_mode_phy_type(void *blob, const 
char *mode,
int err;
 
node_offset = fdt_node_offset_by_compatible(blob,
-   start_offset, compat);
+   start_offset, compat[port]);
if (node_offset  0) {
printf(WARNING: could not find compatible node %s: %s.\n,
-   compat, fdt_strerror(node_offset));
+   compat[port], fdt_strerror(node_offset));
return;
}
 
-   if (mode) {
+   if (strlen(mode)) {
err = fdt_setprop(blob, node_offset, prop_mode, mode,
  strlen(mode) + 1);
if (err  0)
printf(WARNING: could not set %s for %s: %s.\n,
-  prop_mode, compat, fdt_strerror(err));
+  prop_mode, compat[port], fdt_strerror(err));
}
 
-   if (phy_type) {
+   if (strlen(phy_type)) {
err = fdt_setprop(blob, node_offset, prop_type, phy_type,
  strlen(phy_type) + 1);
if (err  0)
printf(WARNING: could not set %s for %s: %s.\n,
-  prop_type, compat, fdt_strerror(err));
+  prop_type, compat[port], fdt_strerror(err));
}
 
start_offset = node_offset;
@@ -126,8 +126,8 @@ static void fdt_fixup_usb_mode_phy_type(void *blob, const 
char *mode,
 
 void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 {
-   const char *modes[] = { host, peripheral, otg };
-   const char *phys[] = { ulpi, umti };
+   const char *modes[] = { , host, peripheral, otg };
+   const char *phys[] = { , ulpi, umti };
const char *mode = NULL;
const char *phy_type = NULL;
char usb1_defined = 0;
@@ -135,7 +135,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
int i, j;
 
for (i = 1; i = FSL_MAX_NUM_USB_CTRLS; i++) {
-   int mode_idx = -1, phy_idx = -1;
+   int mode_idx = 0, phy_idx = 0;
sprintf(str, %s%d, usb, i);
if (hwconfig(str)) {
for (j = 0; j  sizeof(modes); j++) {
@@ -152,16 +152,14 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
break;
}
}
-   if (mode_idx = 0)
-   fdt_fixup_usb_mode_phy_type(blob,
-   modes[mode_idx], NULL);
-   if (phy_idx = 0)
-   fdt_fixup_usb_mode_phy_type(blob,
-   NULL, phys[phy_idx]);
-   if (!strcmp(str, usb1))
-   usb1_defined = 1;
-   if (mode_idx  0  phy_idx  0)
+   if (!mode_idx  !phy_idx) {
printf(WARNING: invalid phy or mode\n);
+   } else {
+   fdt_fixup_usb_mode_phy_type(blob,
+   modes[mode_idx], phys[phy_idx], i - 1);
+   if (!strcmp(str, usb1))
+   usb1_defined = 1;
+   }
}
}
if (!usb1_defined) {
@@ -169,7 +167,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
phy_type = getenv

[U-Boot] [PATCH] spi/eon: add support for new EON spi flash EN25Q32B

[Shaohui Xie]

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 drivers/mtd/spi/eon.c |8 
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/spi/eon.c b/drivers/mtd/spi/eon.c
index 806b44e..4c64494 100644
--- a/drivers/mtd/spi/eon.c
+++ b/drivers/mtd/spi/eon.c
@@ -41,6 +41,14 @@ static const struct eon_spi_flash_params 
eon_spi_flash_table[] = {
.nr_sectors = 4096,
.name = EN25Q128,
},
+   {
+   .idcode1 = 0x16,
+   .page_size = 256,
+   .pages_per_sector = 16,
+   .sectors_per_block = 16,
+   .nr_sectors = 1024,
+   .name = EN25Q32B,
+   },
 };
 
 static int eon_erase(struct spi_flash *flash, u32 offset, size_t len)
-- 
1.6.4


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[U-Boot] [PATCH] powerpc/p2041rdb: add more ddr frequencies support

[Shaohui Xie]

This table covers DDR frequencies from 666 to 1666. Frequencies 666, 833, 1000,
1066 and 1333 were verified on this board with SO-DIMM (UG51U6400N8SU-ACF).

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/p2041rdb/ddr.c |5 -
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c
index e9c699c..3637093 100644
--- a/board/freescale/p2041rdb/ddr.c
+++ b/board/freescale/p2041rdb/ddr.c
@@ -37,7 +37,10 @@ const board_specific_parameters_t 
board_specific_parameters[] = {
 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
 * mhz| mhz|ranks|adjst| start | delay|
 */
-   {  1017, 1116,2,4, 6,   0xff,2,  0},
+   {0,  750,2,3, 5,   0xff,2,  0},
+   {  751, 1250,2,4, 6,   0xff,2,  0},
+   { 1251, 1350,2,5, 7,   0xff,2,  0},
+   { 1351, 1666,2,5, 8,   0xff,2,  0},
 };
 
 void fsl_ddr_board_options(memctl_options_t *popts,
-- 
1.6.4


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[U-Boot] [PATCH 1/2] powerpc/p2041: update cpld reset command according to CPLD 2.0

[Shaohui Xie]

CPLD 2.0 provides a new register which bit[0] is set to '1' will reset board
with initializing the CPLD registers to default values. And add bit[6] of
register at offset 0x5 to use to enable flash bank selection .

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/p2041rdb/cpld.c |   16 +---
 board/freescale/p2041rdb/cpld.h |2 ++
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c
index 8e1f46e..37b0ed5 100644
--- a/board/freescale/p2041rdb/cpld.c
+++ b/board/freescale/p2041rdb/cpld.c
@@ -53,7 +53,11 @@ void cpld_reset(void) __attribute__((weak, 
alias(__cpld_reset)));
  */
 void __cpld_set_altbank(void)
 {
+   u8 reg5 = CPLD_READ(sw_ctl_on);
+
+   CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE);
CPLD_WRITE(fbank_sel, 1);
+   CPLD_WRITE(system_rst, 1);
 }
 void cpld_set_altbank(void)
__attribute__((weak, alias(__cpld_set_altbank)));
@@ -61,12 +65,12 @@ void cpld_set_altbank(void)
 /**
  * Set the boot bank to the default bank
  */
-void __cpld_clear_altbank(void)
+void __cpld_set_defbank(void)
 {
-   CPLD_WRITE(fbank_sel, 0);
+   CPLD_WRITE(system_rst_default, 1);
 }
-void cpld_clear_altbank(void)
-   __attribute__((weak, alias(__cpld_clear_altbank)));
+void cpld_set_defbank(void)
+   __attribute__((weak, alias(__cpld_set_defbank)));
 
 #ifdef DEBUG
 static void cpld_dump_regs(void)
@@ -101,9 +105,7 @@ int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
if (strcmp(argv[2], altbank) == 0)
cpld_set_altbank();
else
-   cpld_clear_altbank();
-
-   cpld_reset();
+   cpld_set_defbank();
} else if (strcmp(argv[1], watchdog) == 0) {
static char *period[8] = {1ms, 10ms, 30ms, disable,
100ms, 1s, 10s, 60s};
diff --git a/board/freescale/p2041rdb/cpld.h b/board/freescale/p2041rdb/cpld.h
index 3b24cb0..dcdb410 100644
--- a/board/freescale/p2041rdb/cpld.h
+++ b/board/freescale/p2041rdb/cpld.h
@@ -29,6 +29,7 @@ typedef struct cpld_data {
u8 fbank_sel;   /* 0xb - Flash bank selection */
u8 serdes_mux;  /* 0xc - Multiplexed pin Select Register */
u8 sw[1];   /* 0xd - SW2 Status */
+   u8 system_rst_default;  /* 0xe - system reset to default register */
 } __attribute__ ((packed)) cpld_data_t;
 
 #define SERDES_MUX_LANE_6_MASK 0x2
@@ -39,6 +40,7 @@ typedef struct cpld_data {
 #define SERDES_MUX_LANE_C_SHIFT2
 #define SERDES_MUX_LANE_D_MASK 0x8
 #define SERDES_MUX_LANE_D_SHIFT3
+#define CPLD_SWITCH_BANK_ENABLE0x40
 
 /* Pointer to the CPLD register set */
 #define cpld ((cpld_data_t *)CPLD_BASE)
-- 
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[U-Boot] [PATCH 2/2] powerpc/p2041: set sysclk according to status of physical switch SW1

[Shaohui Xie]

P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8], software
need to read the SW1 status to decide what the sysclk needs.

SW1[8~6] : frequency
0 0 1 : 83.3MHz
0 1 0 : 100MHz
others: 66.667MHz

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/p2041rdb/cpld.h |3 +++
 board/freescale/p2041rdb/p2041rdb.c |   14 ++
 include/configs/P2041RDB.h  |5 -
 3 files changed, 21 insertions(+), 1 deletions(-)

diff --git a/board/freescale/p2041rdb/cpld.h b/board/freescale/p2041rdb/cpld.h
index dcdb410..bece5dd 100644
--- a/board/freescale/p2041rdb/cpld.h
+++ b/board/freescale/p2041rdb/cpld.h
@@ -30,6 +30,7 @@ typedef struct cpld_data {
u8 serdes_mux;  /* 0xc - Multiplexed pin Select Register */
u8 sw[1];   /* 0xd - SW2 Status */
u8 system_rst_default;  /* 0xe - system reset to default register */
+   u8 sysclk_sw1;  /* 0xf - sysclk configuration register */
 } __attribute__ ((packed)) cpld_data_t;
 
 #define SERDES_MUX_LANE_6_MASK 0x2
@@ -41,6 +42,8 @@ typedef struct cpld_data {
 #define SERDES_MUX_LANE_D_MASK 0x8
 #define SERDES_MUX_LANE_D_SHIFT3
 #define CPLD_SWITCH_BANK_ENABLE0x40
+#define CPLD_SYSCLK_83 0x1 /* system clock 83.3MHz */
+#define CPLD_SYSCLK_1000x2 /* system clock 100MHz */
 
 /* Pointer to the CPLD register set */
 #define cpld ((cpld_data_t *)CPLD_BASE)
diff --git a/board/freescale/p2041rdb/p2041rdb.c 
b/board/freescale/p2041rdb/p2041rdb.c
index 52269d3..8685a29 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -129,6 +129,20 @@ int board_early_init_r(void)
return 0;
 }
 
+unsigned long get_board_sys_clk(unsigned long dummy)
+{
+   u8 sysclk_conf = CPLD_READ(sysclk_sw1);
+
+   switch (sysclk_conf  0x7) {
+   case CPLD_SYSCLK_83:
+   return 8333;
+   case CPLD_SYSCLK_100:
+   return 1;
+   default:
+   return ;
+   }
+}
+
 static const char *serdes_clock_to_string(u32 clock)
 {
switch (clock) {
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 638dbe7..382f1fc 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -102,7 +102,10 @@
#define CONFIG_ENV_SECT_SIZE0x2 /* 128K (one sector) */
 #endif
 
-#define CONFIG_SYS_CLK_FREQ
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQget_board_sys_clk(0)
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
-- 
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[U-Boot] [PATCH] Powerpc/85xx: set liodn for srio in device tree

[Shaohui Xie]

Previous, U-boot did not set fsl,liodn for rapidio in device tree, which is
needed by HV(hypervisor), and HV needs fsl,liodn of rapidio have more values,
for ex for P4080, fsl,liodn = 198 199 200; while P2040/P3041/P5020 has 4
LIODNs respectivelly.

This patch using a generic mechanism which allow a device have mutilple liodns.

Reported-and-tested-by: Diana CRACIUN diana.crac...@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 arch/powerpc/cpu/mpc85xx/liodn.c |   20 +---
 arch/powerpc/cpu/mpc85xx/p2041_ids.c |8 
 arch/powerpc/cpu/mpc85xx/p3041_ids.c |8 
 arch/powerpc/cpu/mpc85xx/p4080_ids.c |6 +++---
 arch/powerpc/cpu/mpc85xx/p5020_ids.c |8 
 5 files changed, 32 insertions(+), 18 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index bd19094..5ccaaf5 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -149,7 +149,11 @@ void set_liodns(void)
 
 static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
 {
-   int i;
+   int i, j;
+   int fdt_liodn[8];
+   int *p = fdt_liodn;
+   char *p_compat = NULL;
+   phys_addr_t cmp_offset = 0;
 
for (i = 0; i  sz; i++) {
int off;
@@ -160,9 +164,19 @@ static void fdt_fixup_liodn_tbl(void *blob, struct 
liodn_id_table *tbl, int sz)
off = fdt_node_offset_by_compat_reg(blob,
tbl[i].compat, tbl[i].compat_offset);
if (off = 0) {
+   if (p_compat != NULL) {
+   if (strcmp(tbl[i].compat, p_compat))
+   p = fdt_liodn;
+   else if (cmp_offset != tbl[i].compat_offset)
+   p = fdt_liodn;
+   }
+   for (j = 0; j  tbl[i].num_ids; j++)
+   *p++ = tbl[i].id[j];
off = fdt_setprop(blob, off, fsl,liodn,
-   tbl[i].id[0],
-   sizeof(u32) * tbl[i].num_ids);
+   fdt_liodn,
+   sizeof(u32) * (p - fdt_liodn));
+   p_compat = (char *)tbl[i].compat;
+   cmp_offset = tbl[i].compat_offset;
if (off  0)
printf(WARNING unable to set fsl,liodn for 
%s: %s\n,
diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c 
b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
index 112ea56..f3b2e7f 100644
--- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
@@ -63,10 +63,10 @@ struct liodn_id_table liodn_tbl[] = {
SET_DMA_LIODN(1, 197),
SET_DMA_LIODN(2, 198),
 
-   SET_GUTS_LIODN(fsl,rapidio-delta, 199, rio1liodnr, 0),
-   SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
-   SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
-   SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+   SET_GUTS_LIODN(fsl,rapidio-delta, 199, rio1liodnr, 0xc),
+   SET_GUTS_LIODN(fsl,rapidio-delta, 200, rio2liodnr, 0xc),
+   SET_GUTS_LIODN(fsl,rapidio-delta, 201, rio1maintliodnr, 0xc),
+   SET_GUTS_LIODN(fsl,rapidio-delta, 202, rio2maintliodnr, 0xc),
 };
 int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
 
diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c 
b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
index 9836588..b1fbd74 100644
--- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
@@ -64,10 +64,10 @@ struct liodn_id_table liodn_tbl[] = {
SET_DMA_LIODN(1, 197),
SET_DMA_LIODN(2, 198),
 
-   SET_GUTS_LIODN(fsl,rapidio-delta, 199, rio1liodnr, 0),
-   SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
-   SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
-   SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+   SET_GUTS_LIODN(fsl,rapidio-delta, 199, rio1liodnr, 0xc),
+   SET_GUTS_LIODN(fsl,rapidio-delta, 200, rio2liodnr, 0xc),
+   SET_GUTS_LIODN(fsl,rapidio-delta, 201, rio1maintliodnr, 0xc),
+   SET_GUTS_LIODN(fsl,rapidio-delta, 202, rio2maintliodnr, 0xc),
 };
 int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
 
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c 
b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
index 560c02a..04164ba 100644
--- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
@@ -53,9 +53,9 @@ struct liodn_id_table liodn_tbl[] = {
SET_DMA_LIODN(1, 196),
SET_DMA_LIODN(2, 197),
 
-   SET_GUTS_LIODN(fsl,rapidio-delta, 198, rio1liodnr, 0),
-   SET_GUTS_LIODN(NULL, 199, rio2liodnr, 0),
-   SET_GUTS_LIODN(NULL, 200, rmuliodnr, 0),
+   SET_GUTS_LIODN(fsl,rapidio-delta, 198, rio1liodnr, 0xc),
+   SET_GUTS_LIODN(fsl,rapidio-delta, 199, rio2liodnr, 0xc

[U-Boot] [PATCH][v3] powerpc/85xx: enable USB2 gadget mode for corenet ds board

[Shaohui Xie]

to make USB2 worked in gadget mode, we need to set it's 'dr_mode' to
'peripheral' in hwconfig, but driver starts scan from 'usb1', it'll break
out if it cannot find 'usb1', so drop the 'else' clause to make driver scan
all the 'usbx'.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for v3:
1. drop 'else'.
2. drop #define CONFIG_SYS_USB_DEVICE.

changes for v2:
1. fixed a typo in title.
2. Added some details in commit.

 arch/powerpc/cpu/mpc8xxx/fdt.c  |2 --
 board/freescale/corenet_ds/corenet_ds.c |1 +
 include/configs/corenet_ds.h|1 +
 3 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index d9e3e7e..6c757f8 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -163,8 +163,6 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
usb1_defined = 1;
if (mode_idx  0  phy_idx  0)
printf(WARNING: invalid phy or mode\n);
-   } else {
-   break;
}
}
if (!usb1_defined) {
diff --git a/board/freescale/corenet_ds/corenet_ds.c 
b/board/freescale/corenet_ds/corenet_ds.c
index cf9b7b8..b1e7823 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -236,6 +236,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 #endif
 
fdt_fixup_liodn(blob);
+   fdt_fixup_dr_usb(blob, bd);
 }
 
 int board_eth_init(bd_t *bis)
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index c9cc22a..1d62146 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -580,6 +580,7 @@
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
 
 #define CONFIG_MMC
 
-- 
1.6.4


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[U-Boot] [PATCH][v2] powerpc/85xx: enable USB2 gadget mode for corenet ds board

[Shaohui Xie]

to make USB2 worked in gadget mode, we need to set it's 'dr_mode' to
'peripheral' in hwconfig, but driver starts scan from 'usb1', it'll break
if it cannot find 'usb1', so we need to tell driver do not break until it
scaned all the 'usbx' that the board may have.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for v2:
1. fixed a typo in title.
2. Added some details in commit.

 arch/powerpc/cpu/mpc8xxx/fdt.c  |3 ++-
 board/freescale/corenet_ds/corenet_ds.c |1 +
 include/configs/corenet_ds.h|2 ++
 3 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index d9e3e7e..60cb210 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -164,7 +164,8 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
if (mode_idx  0  phy_idx  0)
printf(WARNING: invalid phy or mode\n);
} else {
-   break;
+   if (i  CONFIG_SYS_USB_DEVICE)
+   break;
}
}
if (!usb1_defined) {
diff --git a/board/freescale/corenet_ds/corenet_ds.c 
b/board/freescale/corenet_ds/corenet_ds.c
index cf9b7b8..b1e7823 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -236,6 +236,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 #endif
 
fdt_fixup_liodn(blob);
+   fdt_fixup_dr_usb(blob, bd);
 }
 
 int board_eth_init(bd_t *bis)
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index c9cc22a..2c86ba3 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -580,6 +580,8 @@
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_SYS_USB_DEVICE  2
 
 #define CONFIG_MMC
 
-- 
1.6.4


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[U-Boot] [PATCH] powerpc/85xx: enanle USB2 gadget mode for corenet ds board

[Shaohui Xie]

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 arch/powerpc/cpu/mpc8xxx/fdt.c  |3 ++-
 board/freescale/corenet_ds/corenet_ds.c |1 +
 include/configs/corenet_ds.h|2 ++
 3 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index d9e3e7e..60cb210 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -164,7 +164,8 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
if (mode_idx  0  phy_idx  0)
printf(WARNING: invalid phy or mode\n);
} else {
-   break;
+   if (i  CONFIG_SYS_USB_DEVICE)
+   break;
}
}
if (!usb1_defined) {
diff --git a/board/freescale/corenet_ds/corenet_ds.c 
b/board/freescale/corenet_ds/corenet_ds.c
index cf9b7b8..b1e7823 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -236,6 +236,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 #endif
 
fdt_fixup_liodn(blob);
+   fdt_fixup_dr_usb(blob, bd);
 }
 
 int board_eth_init(bd_t *bis)
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index c9cc22a..2c86ba3 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -580,6 +580,8 @@
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_SYS_USB_DEVICE  2
 
 #define CONFIG_MMC
 
-- 
1.6.4


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[U-Boot] [PATCH] powerpc/85xx: Add NAND boot support for P3041/P5020DS

[Shaohui Xie]

When booting from NAND we get the environment from NAND.

Signed-off-by: Shaohui Xie b21...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
 boards.cfg   |2 ++
 include/configs/corenet_ds.h |   29 +++--
 2 files changed, 25 insertions(+), 6 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index 9f2b118..21182b9 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -574,12 +574,14 @@ P2020RDB_SPIFLASHpowerpc mpc85xx 
p1_p2_rdb   freesca
 P3041DS  powerpc mpc85xx corenet_ds  
freescale
 P3041DS_SDCARD  powerpc mpc85xx corenet_ds  
freescale  -   P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
 P3041DS_SPIFLASHpowerpc mpc85xx corenet_ds  
freescale  -   P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
+P3041DS_NANDpowerpc mpc85xx corenet_ds  
freescale  -   P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
 P4080DS  powerpc mpc85xx corenet_ds  
freescale
 P4080DS_SDCARD  powerpc mpc85xx corenet_ds  
freescale  -   P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
 P4080DS_SPIFLASHpowerpc mpc85xx corenet_ds  
freescale  -   P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
 P5020DS  powerpc mpc85xx corenet_ds  
freescale
 P5020DS_SDCARD  powerpc mpc85xx corenet_ds  
freescale  -   P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
 P5020DS_SPIFLASHpowerpc mpc85xx corenet_ds  
freescale  -   P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
+P5020DS_NANDpowerpc mpc85xx corenet_ds  
freescale  -   P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
 mpq101   powerpc mpc85xx mpq101  
mercury-   mpq101
 stxgp3   powerpc mpc85xx stxgp3  stx
 stxssa   powerpc mpc85xx stxssa  stx   
 -   stxssa
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 9ba032b..2e45b92 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -91,6 +91,11 @@
 #define CONFIG_SYS_MMC_ENV_DEV  0
 #define CONFIG_ENV_SIZE0x2000
 #define CONFIG_ENV_OFFSET  (512 * 1097)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZECONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET  (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE - 
CONFIG_ENV_SECT_SIZE)
@@ -196,10 +201,10 @@
 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_SYS_BR0_PRELIM \
-   (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800)) | \
-BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR0_PRELIM  ((0xf8000ff7  ~OR_GPCM_SCY  ~OR_GPCM_EHTR) \
+#define CONFIG_SYS_FLASH_BR_PRELIM \
+   (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800)) \
+| BR_PS_16 | BR_V)
+#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7  ~OR_GPCM_SCY  
~OR_GPCM_EHTR) \
| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 
 #define CONFIG_SYS_BR1_PRELIM \
@@ -268,9 +273,21 @@
   | OR_FCM_TRLX \
   | OR_FCM_EHTR)
 
-#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address 
*/
-#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address 
*/
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address 
*/
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address 
*/
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address 
*/
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
 #endif /* CONFIG_NAND_FSL_ELBC */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address 
*/
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 #endif
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO
-- 
1.6.4


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[U-Boot] [PATCH][v2] powerpc/85xx: Add NAND boot support for P3041/P5020DS

[Shaohui Xie]

When booting from NAND we get the environment from NAND.

Signed-off-by: Shaohui Xie b21...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
changes for v2:
move _NAND up to sorted by alpha.

 boards.cfg   |2 ++
 include/configs/corenet_ds.h |   29 +++--
 2 files changed, 25 insertions(+), 6 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index 9f2b118..f170042 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -572,12 +572,14 @@ P2020RDB_NANDpowerpc mpc85xx 
p1_p2_rdb   freesca
 P2020RDB_SDCARD  powerpc mpc85xx p1_p2_rdb   
freescale  -   P1_P2_RDB:P2020RDB,SDCARD
 P2020RDB_SPIFLASHpowerpc mpc85xx p1_p2_rdb   
freescale  -   P1_P2_RDB:P2020RDB,SPIFLASH
 P3041DS  powerpc mpc85xx corenet_ds  
freescale
+P3041DS_NANDpowerpc mpc85xx corenet_ds  
freescale  -   P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
 P3041DS_SDCARD  powerpc mpc85xx corenet_ds  
freescale  -   P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
 P3041DS_SPIFLASHpowerpc mpc85xx corenet_ds  
freescale  -   P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
 P4080DS  powerpc mpc85xx corenet_ds  
freescale
 P4080DS_SDCARD  powerpc mpc85xx corenet_ds  
freescale  -   P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
 P4080DS_SPIFLASHpowerpc mpc85xx corenet_ds  
freescale  -   P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
 P5020DS  powerpc mpc85xx corenet_ds  
freescale
+P5020DS_NANDpowerpc mpc85xx corenet_ds  
freescale  -   P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
 P5020DS_SDCARD  powerpc mpc85xx corenet_ds  
freescale  -   P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
 P5020DS_SPIFLASHpowerpc mpc85xx corenet_ds  
freescale  -   P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
 mpq101   powerpc mpc85xx mpq101  
mercury-   mpq101
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 9ba032b..2e45b92 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -91,6 +91,11 @@
 #define CONFIG_SYS_MMC_ENV_DEV  0
 #define CONFIG_ENV_SIZE0x2000
 #define CONFIG_ENV_OFFSET  (512 * 1097)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZECONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET  (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE - 
CONFIG_ENV_SECT_SIZE)
@@ -196,10 +201,10 @@
 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_SYS_BR0_PRELIM \
-   (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800)) | \
-BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR0_PRELIM  ((0xf8000ff7  ~OR_GPCM_SCY  ~OR_GPCM_EHTR) \
+#define CONFIG_SYS_FLASH_BR_PRELIM \
+   (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800)) \
+| BR_PS_16 | BR_V)
+#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7  ~OR_GPCM_SCY  
~OR_GPCM_EHTR) \
| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 
 #define CONFIG_SYS_BR1_PRELIM \
@@ -268,9 +273,21 @@
   | OR_FCM_TRLX \
   | OR_FCM_EHTR)
 
-#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address 
*/
-#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address 
*/
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address 
*/
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address 
*/
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address 
*/
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
 #endif /* CONFIG_NAND_FSL_ELBC */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address 
*/
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 #endif
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO
-- 
1.6.4

[U-Boot] [PATCH 1/2] powerpc/85xx: Enable eSPI support on corenet ds boards

[Shaohui Xie]

Signed-off-by: Shaohui Xie b21...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
 include/configs/corenet_ds.h |   10 ++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index d1cda15..561f3c2 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -351,6 +351,16 @@
 #define CONFIG_SYS_SRIO2_MEM_SIZE  0x1000  /* 256M */
 
 /*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 1000
+#define CONFIG_SF_DEFAULT_MODE  0
+
+/*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-- 
1.6.4


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[U-Boot] [PATCH 2/2] powerpc/85xx: add support for env in MMC/SPI on corenet ds boards

[Shaohui Xie]

Signed-off-by: Shaohui Xie b21...@freescale.com
---
 board/freescale/common/Makefile |2 ++
 boards.cfg  |7 ++-
 include/configs/corenet_ds.h|   30 ++
 3 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index dbf1da8..c47d10d 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -36,7 +36,9 @@ COBJS-$(CONFIG_FSL_NGPIXIS)   += ngpixis.o
 COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
 COBJS-$(CONFIG_ID_EEPROM)  += sys_eeprom.o
 COBJS-$(CONFIG_FSL_SGMII_RISER)+= sgmii_riser.o
+ifndef CONFIG_RAMBOOT_PBL
 COBJS-$(CONFIG_ENV_IS_IN_MMC)  += sdhc_boot.o
+endif
 
 COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
 COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o
diff --git a/boards.cfg b/boards.cfg
index f0d3440..73fffaf 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -567,9 +567,14 @@ P2020RDB_NANDpowerpc mpc85xx 
p1_p2_rdb   freesca
 P2020RDB_SDCARD  powerpc mpc85xx p1_p2_rdb   
freescale  -   P1_P2_RDB:P2020RDB,SDCARD
 P2020RDB_SPIFLASHpowerpc mpc85xx p1_p2_rdb   
freescale  -   P1_P2_RDB:P2020RDB,SPIFLASH
 P3041DS  powerpc mpc85xx corenet_ds  
freescale
+P3041DS_SDCARD  powerpc mpc85xx corenet_ds  
freescale  -   P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
+P3041DS_SPIFLASHpowerpc mpc85xx corenet_ds  
freescale  -   P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
 P4080DS  powerpc mpc85xx corenet_ds  
freescale
-P4080DS_RAMBOOT_PBL  powerpc mpc85xx corenet_ds  
freescale  -   P4080DS:RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF8
+P4080DS_SDCARD  powerpc mpc85xx corenet_ds  
freescale  -   P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
+P4080DS_SPIFLASHpowerpc mpc85xx corenet_ds  
freescale  -   P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
 P5020DS  powerpc mpc85xx corenet_ds  
freescale
+P5020DS_SDCARD  powerpc mpc85xx corenet_ds  
freescale  -   P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
+P5020DS_SPIFLASHpowerpc mpc85xx corenet_ds  
freescale  -   P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
 mpq101   powerpc mpc85xx mpq101  
mercury-   mpq101
 stxgp3   powerpc mpc85xx stxgp3  stx
 stxssa   powerpc mpc85xx stxssa  stx   
 -   stxssa
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 561f3c2..9ba032b 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -68,17 +68,34 @@
 
 #define CONFIG_ENV_OVERWRITE
 
-#if defined(CONFIG_RAMBOOT_PBL)
-   #define CONFIG_SYS_NO_FLASH /* Store ENV in memory only */
-#endif
-
 #ifdef CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_IS_NOWHERE
 #else
-#define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS  0
+#define CONFIG_ENV_SPI_CS   0
+#define CONFIG_ENV_SPI_MAX_HZ   1000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000  /* 8KB */
+#define CONFIG_ENV_OFFSET   0x10/* 1MB */
+#define CONFIG_ENV_SECT_SIZE0x1
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV  0
+#define CONFIG_ENV_SIZE0x2000
+#define CONFIG_ENV_OFFSET  (512 * 1097)
+#else
+#define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE - 
CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE0x2000
+#define CONFIG_ENV_SECT_SIZE   0x2 /* 128K (one sector) */
 #endif
 
 #define CONFIG_SYS_CLK_FREQget_board_sys_clk() /* sysclk for MPC85xx */
@@ -513,9 +530,6 @@
 /*
  * Environment
  */
-#define CONFIG_ENV_SIZE0x2000
-#define CONFIG_ENV_SECT_SIZE   0x2 /* 128K (one sector) */
-
 #define CONFIG_LOADS_ECHO  /* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE   /* allow baudrate change */
 
-- 
1.6.4


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[U-Boot] [PATCH][v4] powerpc: eSPI and eSPI controller support

[Shaohui Xie]

From: Mingkai Hu mingkai...@freescale.com

Signed-off-by: Mingkai Hu mingkai...@freescale.com
Singed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Shaohui Xie b21...@freescale.com
Cc: Mike Frysinger vap...@gentoo.org

changes for v2:
remove #ifdef wrapper and refactor spi_xfer by use SPI_XFER(BEGIN | END).
remove 'volatile' use I/O accessors instead.

changes for v3:
move powerpc specific code to asm/config.h.
use spi_claim_bus() to setup hardware rather than spi_setup_slave().
use slave data rather than global.
drop useless return.

changes for v4:
use controller specific struct rather than put in common header.
merge read more than 0xfffa bytes patch.

 arch/powerpc/include/asm/config.h |7 +
 drivers/spi/Makefile  |1 +
 drivers/spi/fsl_espi.c|  337 +
 include/spi.h |9 +-
 4 files changed, 347 insertions(+), 7 deletions(-)
 create mode 100644 drivers/spi/fsl_espi.c

diff --git a/arch/powerpc/include/asm/config.h 
b/arch/powerpc/include/asm/config.h
index 624d8c2..9aad9be 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -29,6 +29,13 @@
 #include asm/config_mpc86xx.h
 #endif
 
+/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
+#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
+# ifndef CONFIG_HARD_SPI
+#  define CONFIG_HARD_SPI
+# endif
+#endif
+
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 #define CONFIG_SYS_BOOT_GET_CMDLINE
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d582fbb..74f1293 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
 COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
+COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
new file mode 100644
index 000..57e0466
--- /dev/null
+++ b/drivers/spi/fsl_espi.c
@@ -0,0 +1,337 @@
+/*
+ * eSPI controller driver.
+ *
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Mingkai Hu (mingkai...@freescale.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+
+#include malloc.h
+#include spi.h
+#include asm/immap_85xx.h
+
+struct fsl_spi_slave {
+   struct spi_slave slave;
+   unsigned intdiv16;
+   unsigned intpm;
+   unsigned intmode;
+   size_t  cmd_len;
+   u8  cmd_buf[16];
+   size_t  data_len;
+   unsigned intmax_transfer_length;
+};
+
+#define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
+
+#define ESPI_MAX_CS_NUM4
+
+#define ESPI_EV_RNE(1  9)
+#define ESPI_EV_TNF(1  8)
+
+#define ESPI_MODE_EN   (1  31)   /* Enable interface */
+#define ESPI_MODE_TXTHR(x) ((x)  8)  /* Tx FIFO threshold */
+#define ESPI_MODE_RXTHR(x) ((x)  0)  /* Rx FIFO threshold */
+
+#define ESPI_COM_CS(x) ((x)  30)
+#define ESPI_COM_TRANLEN(x)((x)  0)
+
+#define ESPI_CSMODE_CI_INACTIVEHIGH(1  31)
+#define ESPI_CSMODE_CP_BEGIN_EDGCLK(1  30)
+#define ESPI_CSMODE_REV_MSB_FIRST  (1  29)
+#define ESPI_CSMODE_DIV16  (1  28)
+#define ESPI_CSMODE_PM(x)  ((x)  24)
+#define ESPI_CSMODE_POL_ASSERTED_LOW   (1  20)
+#define ESPI_CSMODE_LEN(x) ((x)  16)
+#define ESPI_CSMODE_CSBEF(x)   ((x)  12)
+#define ESPI_CSMODE_CSAFT(x)   ((x)  8)
+#define ESPI_CSMODE_CSCG(x)((x)  3)
+
+#define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \
+   ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \
+   ESPI_CSMODE_CSCG(1))
+
+#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+   unsigned int max_hz, unsigned int mode)
+{
+   struct fsl_spi_slave *fsl;
+   sys_info_t sysinfo;
+   unsigned long spibrg = 0;
+   unsigned char pm = 0;
+
+   if (!spi_cs_is_valid(bus, cs))
+   return NULL;
+
+   fsl = malloc(sizeof(struct fsl_spi_slave));
+   if (!fsl)
+   return

[U-Boot] [PATCH][v5] powerpc: eSPI and eSPI controller support

[Shaohui Xie]

From: Mingkai Hu mingkai...@freescale.com

Signed-off-by: Mingkai Hu mingkai...@freescale.com
Singed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Shaohui Xie b21...@freescale.com
Cc: Mike Frysinger vap...@gentoo.org
---
changes for v2:
remove #ifdef wrapper and refactor spi_xfer by use SPI_XFER(BEGIN | END).
remove 'volatile' use I/O accessors instead.

changes for v3:
move powerpc specific code to asm/config.h.
use spi_claim_bus() to setup hardware rather than spi_setup_slave().
use slave data rather than global.
drop useless return.

changes for v4:
use controller specific struct rather than put in common header.
merge read more than 0xfffa bytes patch.

changes for v5:
fix code style.
drop flag check.
drop unnecessary copy right.

 arch/powerpc/include/asm/config.h |7 +
 drivers/spi/Makefile  |1 +
 drivers/spi/fsl_espi.c|  334 +
 include/spi.h |7 -
 4 files changed, 342 insertions(+), 7 deletions(-)
 create mode 100644 drivers/spi/fsl_espi.c

diff --git a/arch/powerpc/include/asm/config.h 
b/arch/powerpc/include/asm/config.h
index 624d8c2..9aad9be 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -29,6 +29,13 @@
 #include asm/config_mpc86xx.h
 #endif
 
+/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
+#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
+# ifndef CONFIG_HARD_SPI
+#  define CONFIG_HARD_SPI
+# endif
+#endif
+
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 #define CONFIG_SYS_BOOT_GET_CMDLINE
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d582fbb..74f1293 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
 COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
+COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
new file mode 100644
index 000..f872cd8
--- /dev/null
+++ b/drivers/spi/fsl_espi.c
@@ -0,0 +1,334 @@
+/*
+ * eSPI controller driver.
+ *
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Mingkai Hu (mingkai...@freescale.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+
+#include malloc.h
+#include spi.h
+#include asm/immap_85xx.h
+
+struct fsl_spi_slave {
+   struct spi_slave slave;
+   unsigned intdiv16;
+   unsigned intpm;
+   unsigned intmode;
+   size_t  cmd_len;
+   u8  cmd_buf[16];
+   size_t  data_len;
+   unsigned intmax_transfer_length;
+};
+
+#define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
+
+#define ESPI_MAX_CS_NUM4
+
+#define ESPI_EV_RNE(1  9)
+#define ESPI_EV_TNF(1  8)
+
+#define ESPI_MODE_EN   (1  31)   /* Enable interface */
+#define ESPI_MODE_TXTHR(x) ((x)  8)  /* Tx FIFO threshold */
+#define ESPI_MODE_RXTHR(x) ((x)  0)  /* Rx FIFO threshold */
+
+#define ESPI_COM_CS(x) ((x)  30)
+#define ESPI_COM_TRANLEN(x)((x)  0)
+
+#define ESPI_CSMODE_CI_INACTIVEHIGH(1  31)
+#define ESPI_CSMODE_CP_BEGIN_EDGCLK(1  30)
+#define ESPI_CSMODE_REV_MSB_FIRST  (1  29)
+#define ESPI_CSMODE_DIV16  (1  28)
+#define ESPI_CSMODE_PM(x)  ((x)  24)
+#define ESPI_CSMODE_POL_ASSERTED_LOW   (1  20)
+#define ESPI_CSMODE_LEN(x) ((x)  16)
+#define ESPI_CSMODE_CSBEF(x)   ((x)  12)
+#define ESPI_CSMODE_CSAFT(x)   ((x)  8)
+#define ESPI_CSMODE_CSCG(x)((x)  3)
+
+#define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \
+   ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \
+   ESPI_CSMODE_CSCG(1))
+
+#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+   unsigned int max_hz, unsigned int mode)
+{
+   struct fsl_spi_slave *fsl;
+   sys_info_t sysinfo;
+   unsigned long spibrg = 0;
+   unsigned char pm = 0;
+
+   if (!spi_cs_is_valid(bus, cs))
+   return NULL;
+
+   fsl

[U-Boot] [PATCH 1/2][v3] powerpc: eSPI and eSPI controller support

[Shaohui Xie]

From: Mingkai Hu mingkai...@freescale.com

Signed-off-by: Mingkai Hu mingkai...@freescale.com
Singed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Shaohui Xie b21...@freescale.com
Cc: Mike Frysinger vap...@gentoo.org
---
changes for v2:
remove #ifdef wrapper and refactor spi_xfer by use SPI_XFER(BEGIN | END).
remove 'volatile' use I/O accessors instead.

changes for v3:
move powerpc specific code to asm/config.h
use spi_claim_bus() to setup hardware rather than spi_setup_slave().
use slave data rather than global.
drop useless return.

 arch/powerpc/include/asm/config.h |7 +
 drivers/spi/Makefile  |1 +
 drivers/spi/fsl_espi.c|  305 +
 include/spi.h |   29 +++-
 4 files changed, 335 insertions(+), 7 deletions(-)
 create mode 100644 drivers/spi/fsl_espi.c

diff --git a/arch/powerpc/include/asm/config.h 
b/arch/powerpc/include/asm/config.h
index 624d8c2..9aad9be 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -29,6 +29,13 @@
 #include asm/config_mpc86xx.h
 #endif
 
+/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
+#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
+# ifndef CONFIG_HARD_SPI
+#  define CONFIG_HARD_SPI
+# endif
+#endif
+
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 #define CONFIG_SYS_BOOT_GET_CMDLINE
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d582fbb..74f1293 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
 COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
+COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
new file mode 100644
index 000..55b29cc
--- /dev/null
+++ b/drivers/spi/fsl_espi.c
@@ -0,0 +1,305 @@
+/*
+ * eSPI controller driver.
+ *
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Mingkai Hu (mingkai...@freescale.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+
+#include malloc.h
+#include spi.h
+#include asm/immap_85xx.h
+
+#define ESPI_MAX_CS_NUM4
+
+#define ESPI_EV_RNE(1  9)
+#define ESPI_EV_TNF(1  8)
+
+#define ESPI_MODE_EN   (1  31)   /* Enable interface */
+#define ESPI_MODE_TXTHR(x) ((x)  8)  /* Tx FIFO threshold */
+#define ESPI_MODE_RXTHR(x) ((x)  0)  /* Rx FIFO threshold */
+
+#define ESPI_COM_CS(x) ((x)  30)
+#define ESPI_COM_TRANLEN(x)((x)  0)
+
+#define ESPI_CSMODE_CI_INACTIVEHIGH(1  31)
+#define ESPI_CSMODE_CP_BEGIN_EDGCLK(1  30)
+#define ESPI_CSMODE_REV_MSB_FIRST  (1  29)
+#define ESPI_CSMODE_DIV16  (1  28)
+#define ESPI_CSMODE_PM(x)  ((x)  24)
+#define ESPI_CSMODE_POL_ASSERTED_LOW   (1  20)
+#define ESPI_CSMODE_LEN(x) ((x)  16)
+#define ESPI_CSMODE_CSBEF(x)   ((x)  12)
+#define ESPI_CSMODE_CSAFT(x)   ((x)  8)
+#define ESPI_CSMODE_CSCG(x)((x)  3)
+
+#define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \
+   ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \
+   ESPI_CSMODE_CSCG(1))
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+   unsigned int max_hz, unsigned int mode)
+{
+   struct spi_slave *slave;
+   sys_info_t sysinfo;
+   unsigned long spibrg = 0;
+   unsigned char pm = 0;
+
+   if (!spi_cs_is_valid(bus, cs))
+   return NULL;
+
+   slave = malloc(sizeof(struct spi_slave));
+   if (!slave)
+   return NULL;
+
+   slave-bus = bus;
+   slave-cs = cs;
+   slave-slave_data.mode = mode;
+
+   /* Set eSPI BRG clock source */
+   get_sys_info(sysinfo);
+   spibrg = sysinfo.freqSystemBus / 2;
+   slave-slave_data.div16 = 0;
+   if ((spibrg / max_hz)  32) {
+   slave-slave_data.div16 = ESPI_CSMODE_DIV16;
+   pm = spibrg / (max_hz * 16 * 2);
+   if (pm  16) {
+   pm = 16;
+   debug(Requested speed is too low: %d Hz
+%d

[U-Boot] [PATCH 2/2][v3] powerpc: make espi can read more than 0xFFFA bytes

[Shaohui Xie]

espi flash read returns invalid data if the read length is more than 0xFFFA
bytes, it supports maximum transaction of 2^16 bytes at a time, resister
spcom[TRANLEN] is 16 bits. If the transaction length is greater than  0x,
it need to be split into multiple transactions.

Signed-off-by: Shaohui Xie b21...@freescale.com
Cc: Mike Frysinger vap...@gentoo.org
---
changes for v2:
fix some compile warnings.
remove ifdef and use if else instead.

changes for v3:
rebased on first patch.

 drivers/mtd/spi/spi_flash.c |   39 +++
 drivers/spi/fsl_espi.c  |6 ++
 include/spi.h   |2 ++
 3 files changed, 43 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index c75b716..f90ef25 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1,6 +1,7 @@
 /*
  * SPI flash interface
  *
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  * Copyright (C) 2008 Atmel Corporation
  * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
  *
@@ -82,11 +83,41 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 
offset,
 {
u8 cmd[5];
 
-   cmd[0] = CMD_READ_ARRAY_FAST;
-   spi_flash_addr(offset, cmd);
-   cmd[4] = 0x00;
+   if (len = flash-spi-max_transfer_length) {
+   cmd[0] = CMD_READ_ARRAY_FAST;
+   spi_flash_addr(offset, cmd);
+   cmd[4] = 0x00;
+
+   return spi_flash_read_common(flash, cmd, sizeof(cmd), data, 
len);
+   } else {
+   int max_tran_len, num_chunks, tran_len, ret = 0;
+
+   max_tran_len = flash-spi-max_transfer_length;
+   num_chunks = len / max_tran_len + (len % max_tran_len ? 1 : 0);
+
+   while (num_chunks--) {
+   tran_len = min(len , max_tran_len);
+
+   cmd[0] = CMD_READ_ARRAY_FAST;
+   spi_flash_addr(offset, cmd);
+   cmd[4] = 0x00;
+
+   debug(READ: 0x%x = cmd = 
+   { 0x%02x 0x%02x%02x%02x%02x } tran_len = 0x%x\n,
+   offset, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], 
tran_len);
 
-   return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
+   ret = spi_flash_read_common(
+   flash, cmd, sizeof(cmd), data, tran_len);
+   if (ret  0)
+   return ret;
+
+   offset += max_tran_len;
+   data += max_tran_len;
+   len -= max_tran_len;
+   }
+
+   return ret;
+   }
 }
 
 int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index 55b29cc..5ed6a59 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -53,6 +53,8 @@
ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \
ESPI_CSMODE_CSCG(1))
 
+#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
+
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
 {
@@ -71,6 +73,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned 
int cs,
slave-bus = bus;
slave-cs = cs;
slave-slave_data.mode = mode;
+   slave-max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
 
/* Set eSPI BRG clock source */
get_sys_info(sysinfo);
@@ -174,6 +177,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 
const void *data_out,
u8 *cmd_buf = slave-slave_data.cmd_buf;
size_t cmd_len = slave-slave_data.cmd_len;
 
+   if (slave-max_transfer_length  ESPI_MAX_DATA_TRANSFER_LEN)
+   return -1;
+
switch (flags) {
case SPI_XFER_BEGIN:
cmd_len = slave-slave_data.cmd_len = bitlen / 8;
diff --git a/include/spi.h b/include/spi.h
index 213f6e6..c2c0d36 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -70,11 +70,13 @@ struct spi_slave_data {
  *   bus:  ID of the bus that the slave is attached to.
  *   cs:   ID of the chip select connected to the slave.
  *   slave_data: slave data for hardware and transfer.
+ *   max_transfer_length: maximum data transfer length supported by the slave.
  */
 struct spi_slave {
unsigned intbus;
unsigned intcs;
struct spi_slave_data slave_data;
+   unsigned intmax_transfer_length;
 };
 
 /*---
-- 
1.6.4


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[U-Boot] [PATCH 1/2][v2] powerpc: eSPI and eSPI controller support

[Shaohui Xie]

From: Mingkai Hu mingkai...@freescale.com

Signed-off-by: Mingkai Hu mingkai...@freescale.com
Singed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Shaohui Xie b21...@freescale.com
Cc: Mike Frysinger vap...@gentoo.org
---
changes for v2:
remove #ifdef wrapper and refactor spi_xfer by use SPI_XFER(BEGIN | END).
remove 'volatile' use I/O accessors instead.

 drivers/spi/Makefile   |1 +
 drivers/spi/fsl_espi.c |  297 
 include/spi.h  |4 +-
 3 files changed, 301 insertions(+), 1 deletions(-)
 create mode 100644 drivers/spi/fsl_espi.c

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d582fbb..74f1293 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
 COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
+COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
new file mode 100644
index 000..9b8ae9a
--- /dev/null
+++ b/drivers/spi/fsl_espi.c
@@ -0,0 +1,297 @@
+/*
+ * eSPI controller driver.
+ *
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Mingkai Hu (mingkai...@freescale.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+
+#include malloc.h
+#include spi.h
+#include asm/immap_85xx.h
+
+#define ESPI_MAX_CS_NUM4
+
+#define ESPI_EV_RNE(1  9)
+#define ESPI_EV_TNF(1  8)
+
+#define ESPI_MODE_EN   (1  31)   /* Enable interface */
+#define ESPI_MODE_TXTHR(x) ((x)  8)  /* Tx FIFO threshold */
+#define ESPI_MODE_RXTHR(x) ((x)  0)  /* Rx FIFO threshold */
+
+#define ESPI_COM_CS(x) ((x)  30)
+#define ESPI_COM_TRANLEN(x)((x)  0)
+
+#define ESPI_CSMODE_CI_INACTIVEHIGH(1  31)
+#define ESPI_CSMODE_CP_BEGIN_EDGCLK(1  30)
+#define ESPI_CSMODE_REV_MSB_FIRST  (1  29)
+#define ESPI_CSMODE_DIV16  (1  28)
+#define ESPI_CSMODE_PM(x)  ((x)  24)
+#define ESPI_CSMODE_POL_ASSERTED_LOW   (1  20)
+#define ESPI_CSMODE_LEN(x) ((x)  16)
+#define ESPI_CSMODE_CSBEF(x)   ((x)  12)
+#define ESPI_CSMODE_CSAFT(x)   ((x)  8)
+#define ESPI_CSMODE_CSCG(x)((x)  3)
+
+#define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \
+   ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \
+   ESPI_CSMODE_CSCG(1))
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+   unsigned int max_hz, unsigned int mode)
+{
+   ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+   struct spi_slave *slave;
+   sys_info_t sysinfo;
+   unsigned long spibrg = 0;
+   unsigned char pm = 0;
+   int i;
+
+   if (!spi_cs_is_valid(bus, cs))
+   return NULL;
+
+   slave = malloc(sizeof(struct spi_slave));
+   if (!slave)
+   return NULL;
+
+   slave-bus = bus;
+   slave-cs = cs;
+
+   /* Enable eSPI interface */
+   out_be32(espi-mode, ESPI_MODE_RXTHR(3)
+   | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
+
+   out_be32(espi-event, 0x); /* Clear all eSPI events */
+   out_be32(espi-mask, 0x); /* Mask  all eSPI interrupts */
+
+   /* Init CS mode interface */
+   for (i = 0; i  ESPI_MAX_CS_NUM; i++)
+   out_be32(espi-csmode[i], ESPI_CSMODE_INIT_VAL);
+
+   out_be32(espi-csmode[cs], in_be32(espi-csmode[cs]) 
+   ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
+   | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK
+   | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF)));
+
+   /* Set eSPI BRG clock source */
+   get_sys_info(sysinfo);
+   spibrg = sysinfo.freqSystemBus / 2;
+   if ((spibrg / max_hz)  32) {
+   out_be32(espi-csmode[cs], in_be32(espi-csmode[cs])
+   | ESPI_CSMODE_DIV16);
+   pm = spibrg / (max_hz * 16 * 2);
+   if (pm  16) {
+   pm = 16;
+   debug(Requested speed is too low: %d Hz
+%d Hz is used.\n, max_hz, spibrg

[U-Boot] [PATCH 2/2][v2] powerpc: make espi can read more than 0xFFFA bytes

[Shaohui Xie]

espi flash read returns invalid data if the read length is more than 0xFFFA
bytes, it supports maximum transaction of 2^16 bytes at a time, resister
spcom[TRANLEN] is 16 bits. If the transaction length is greater than  0x,
it need to be split into multiple transactions.

Signed-off-by: Shaohui Xie b21...@freescale.com
Cc: Mike Frysinger vap...@gentoo.org
---
changes for v2:
fix some compile warnings.
remove ifdef and use if else instead.

 drivers/mtd/spi/spi_flash.c |   39 +++
 drivers/spi/fsl_espi.c  |6 ++
 include/spi.h   |2 ++
 3 files changed, 43 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index c75b716..f90ef25 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1,6 +1,7 @@
 /*
  * SPI flash interface
  *
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  * Copyright (C) 2008 Atmel Corporation
  * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
  *
@@ -82,11 +83,41 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 
offset,
 {
u8 cmd[5];
 
-   cmd[0] = CMD_READ_ARRAY_FAST;
-   spi_flash_addr(offset, cmd);
-   cmd[4] = 0x00;
+   if (len = flash-spi-max_transfer_length) {
+   cmd[0] = CMD_READ_ARRAY_FAST;
+   spi_flash_addr(offset, cmd);
+   cmd[4] = 0x00;
+
+   return spi_flash_read_common(flash, cmd, sizeof(cmd), data, 
len);
+   } else {
+   int max_tran_len, num_chunks, tran_len, ret = 0;
+
+   max_tran_len = flash-spi-max_transfer_length;
+   num_chunks = len / max_tran_len + (len % max_tran_len ? 1 : 0);
+
+   while (num_chunks--) {
+   tran_len = min(len , max_tran_len);
+
+   cmd[0] = CMD_READ_ARRAY_FAST;
+   spi_flash_addr(offset, cmd);
+   cmd[4] = 0x00;
+
+   debug(READ: 0x%x = cmd = 
+   { 0x%02x 0x%02x%02x%02x%02x } tran_len = 0x%x\n,
+   offset, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], 
tran_len);
 
-   return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
+   ret = spi_flash_read_common(
+   flash, cmd, sizeof(cmd), data, tran_len);
+   if (ret  0)
+   return ret;
+
+   offset += max_tran_len;
+   data += max_tran_len;
+   len -= max_tran_len;
+   }
+
+   return ret;
+   }
 }
 
 int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index 9b8ae9a..7630fb3 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -53,6 +53,8 @@
ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \
ESPI_CSMODE_CSCG(1))
 
+#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
+
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
 {
@@ -72,6 +74,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned 
int cs,
 
slave-bus = bus;
slave-cs = cs;
+   slave-max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
 
/* Enable eSPI interface */
out_be32(espi-mode, ESPI_MODE_RXTHR(3)
@@ -165,6 +168,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 
const void *data_out,
unsigned char *buffer;
size_t buf_len;
 
+   if (slave-max_transfer_length  ESPI_MAX_DATA_TRANSFER_LEN)
+   return -1;
+
switch (flags) {
case SPI_XFER_BEGIN:
cmd_len = bitlen / 8;
diff --git a/include/spi.h b/include/spi.h
index c5da3ca..866b920 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -58,10 +58,12 @@
  *
  *   bus:  ID of the bus that the slave is attached to.
  *   cs:   ID of the chip select connected to the slave.
+ *   max_transfer_length: maximum data transfer length supported by the slave.
  */
 struct spi_slave {
unsigned intbus;
unsigned intcs;
+   unsigned intmax_transfer_length;
 };
 
 /*---
-- 
1.6.4


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[U-Boot] [PATCH] sf: spansion: add support for new spansion flash

[Shaohui Xie]

Signed-off-by: Shaohui Xie b21...@freescale.com
Cc: Mike Frysinger vap...@gentoo.org
---
 drivers/mtd/spi/spansion.c |9 +
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index a3401b3..8835e96 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -53,6 +53,7 @@
 #define SPSN_EXT_ID_S25FL128P_256KB0x0300
 #define SPSN_EXT_ID_S25FL128P_64KB 0x0301
 #define SPSN_EXT_ID_S25FL032P  0x4d00
+#define SPSN_EXT_ID_S25FL129P  0x4d01
 
 struct spansion_spi_flash_params {
u16 idcode1;
@@ -131,6 +132,14 @@ static const struct spansion_spi_flash_params 
spansion_spi_flash_table[] = {
.nr_sectors = 64,
.name = S25FL032P,
},
+   {
+   .idcode1 = SPSN_ID_S25FL128P,
+   .idcode2 = SPSN_EXT_ID_S25FL129P,
+   .page_size = 256,
+   .pages_per_sector = 256,
+   .nr_sectors = 256,
+   .name = S25FL129P_64K,
+   },
 };
 
 static int spansion_write(struct spi_flash *flash,
-- 
1.6.4


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[U-Boot] [PATCH 2/2] powerpc: make espi can read more than 0xFFFA bytes

[Shaohui Xie]

espi flash read returns invalid data if the read length is more than 0xFFFA
bytes, it supports maximum transaction of 2^16 bytes at a time, resister
spcom[TRANLEN] is 16 bits. If the transaction length is greater than  0x,
it need to be split into multiple transactions.

Signed-off-by: Shaohui Xie b21...@freescale.com
Cc: Mike Frysinger vap...@gentoo.org
---
this patch is rebased on Mike's sf unify patches.

 drivers/mtd/spi/spi_flash.c |   30 ++
 drivers/spi/fsl_espi.c  |6 ++
 include/spi.h   |2 ++
 3 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index f745def..f50ca63 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -127,11 +127,41 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 
offset,
 {
u8 cmd[5];
 
+#ifndef CONFIG_FSL_ESPI
cmd[0] = CMD_READ_ARRAY_FAST;
spi_flash_addr(offset, cmd);
cmd[4] = 0x00;
 
return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
+#else
+   int max_tran_len, num_chunks, tran_len, ret;
+
+   max_tran_len = flash-spi-max_transfer_length;
+   num_chunks = len / max_tran_len + (len % max_tran_len ? 1 : 0);
+
+   while (num_chunks--) {
+   tran_len = min(len , max_tran_len);
+
+   cmd[0] = CMD_READ_ARRAY_FAST;
+   spi_flash_addr(offset, cmd);
+   cmd[4] = 0x00;
+
+   debug(READ: 0x%x = cmd =
+   { 0x%02x 0x%02x%02x%02x%02x } tran_len = 0x%x\n,
+   offset, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], tran_len);
+
+   ret = spi_flash_read_common(
+   flash, cmd, sizeof(cmd), data, tran_len);
+   if (ret  0)
+   return ret;
+
+   offset += max_tran_len;
+   data += max_tran_len;
+   len -= max_tran_len;
+   }
+
+   return ret;
+#endif
 }
 
 int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index f4ff884..66ae1a8 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -53,6 +53,8 @@
ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \
ESPI_CSMODE_CSCG(1))
 
+#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
+
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
 {
@@ -72,6 +74,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned 
int cs,
 
slave-bus = bus;
slave-cs = cs;
+   slave-max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
 
/* Enable eSPI interface */
espi-mode = ESPI_MODE_RXTHR(3) | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN;
@@ -153,6 +156,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 
const void *data_out,
unsigned char *ch;
int num_bytes = len % 4;
 
+   if (t-data_len  ESPI_MAX_DATA_TRANSFER_LEN)
+   return -1;
+
debug(spi_xfer: slave %u:%u dout %08X(%08x) din %08X(%08x) len %u\n,
  slave-bus, slave-cs, *(uint *) dout,
  dout, *(uint *) din, din, len);
diff --git a/include/spi.h b/include/spi.h
index 423899f..b0e13d5 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -77,12 +77,14 @@ struct espi_transfer {
  *
  *   bus:  ID of the bus that the slave is attached to.
  *   cs:   ID of the chip select connected to the slave.
+ *   max_txn_length: maximum data transfer length supported by the slave.
  *   transfer: Represent an eSPI transaction.
  */
 struct spi_slave {
unsigned intbus;
unsigned intcs;
 
+   unsigned intmax_transfer_length;
struct espi_transfer *transfer;
 };
 
-- 
1.6.4


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[U-Boot] [PATCH 1/2] P4080/PBL: add support for boot from SPI flash.

[Shaohui Xie]

PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and
PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as 1M SRAM
where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL
completes RCW and PBI phases.

Signed-off-by: Chunhe Lan b25...@freescale.com
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Signed-off-by: Shaohui Xie b21...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c |   19 +++
 board/freescale/corenet_ds/tlb.c|   12 +++-
 boards.cfg  |1 +
 include/configs/corenet_ds.h|   27 ++-
 4 files changed, 57 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 8ece970..a977000 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -141,6 +141,22 @@ static void enable_cpc(void)
for (i = 0; i  CONFIG_SYS_NUM_CPC; i++, cpc++) {
u32 cpccfg0 = in_be32(cpc-cpccfg0);
size += CPC_CFG0_SZ_K(cpccfg0);
+#ifdef CONFIG_RAMBOOT_PBL
+   if (in_be32(cpc-cpcsrcr0)  CPC_SRCR0_SRAMEN) {
+   /* find and disable LAW of SRAM */
+   struct law_entry law = 
find_law(CONFIG_SYS_INIT_L3_ADDR);
+
+   if (law.index == -1) {
+   printf(\nFatal error happened\n);
+   return;
+   }
+   disable_law(law.index);
+
+   clrbits_be32(cpc-cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
+   out_be32(cpc-cpccsr0, 0);
+   out_be32(cpc-cpcsrcr0, 0);
+   }
+#endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
setbits_be32(cpc-cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
@@ -164,6 +180,9 @@ void invalidate_cpc(void)
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
for (i = 0; i  CONFIG_SYS_NUM_CPC; i++, cpc++) {
+   /* skip CPC when it used as all SRAM */
+   if (in_be32(cpc-cpcsrcr0)  CPC_SRCR0_SRAMEN)
+   continue;
/* Flash invalidate the CPC and clear all the locks */
out_be32(cpc-cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
while (in_be32(cpc-cpccsr0)  (CPC_CSR0_FI | CPC_CSR0_LFC))
diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c
index 1ae0416..fe77e79 100644
--- a/board/freescale/corenet_ds/tlb.c
+++ b/board/freescale/corenet_ds/tlb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
@@ -51,9 +51,19 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
/* TLB 1 */
/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT)  defined(CONFIG_SYS_INIT_L3_ADDR)
+   /*
+* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+* SRAM is at 0xfff0, it covered the 0xf000.
+*/
+   SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+   MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+   0, 0, BOOKE_PAGESZ_1M, 1),
+#else
SET_TLB_ENTRY(1, 0xf000, 0xf000,
  MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
 
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
diff --git a/boards.cfg b/boards.cfg
index 45c3102..f19cc34 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -529,6 +529,7 @@ P2020RDB_NANDpowerpc mpc85xx 
p1_p2_rdb   freesca
 P2020RDB_SDCARD  powerpc mpc85xx p1_p2_rdb   
freescale  -   P1_P2_RDB:P2020RDB,SDCARD
 P2020RDB_SPIFLASHpowerpc mpc85xx p1_p2_rdb   
freescale  -   P1_P2_RDB:P2020RDB,SPIFLASH
 P4080DS  powerpc mpc85xx corenet_ds  
freescale
+P4080DS_RAMBOOT_PBL  powerpc mpc85xx corenet_ds  
freescale  -   P4080DS:RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF8
 mpq101   powerpc mpc85xx mpq101  
mercury-   mpq101
 stxgp3   powerpc mpc85xx stxgp3  stx
 stxssa   powerpc mpc85xx stxssa  stx   
 -   stxssa
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index bff212e..8d10862 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -28,6 +28,11 @@
 
 #include ../board/freescale/common/ics307_clk.h
 
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE

[U-Boot] [PATCH 2/2] P4080/PBL: add tool to support pbl image build.

[Shaohui Xie]

The tool can build u-boot image which can be used by PBL,
run make P4080DS_RAMBOOT_PBL can make all works done,
the default output image is u-boot.pbl, for more details
please refer to doc/README.pblimage.

Signed-off-by: Shaohui Xie b21...@freescale.com
---
 Makefile|5 +
 board/freescale/corenet_ds/config.mk|   26 +++
 board/freescale/corenet_ds/pblimage.cfg |   59 ++
 common/image.c  |1 +
 doc/README.pblimage |   83 
 include/image.h |1 +
 tools/Makefile  |2 +
 tools/mkimage.c |5 +
 tools/mkimage.h |2 +
 tools/pblimage.c|  329 +++
 tools/pblimage.h|   36 
 11 files changed, 549 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/corenet_ds/config.mk
 create mode 100644 board/freescale/corenet_ds/pblimage.cfg
 create mode 100644 doc/README.pblimage
 create mode 100644 tools/pblimage.c
 create mode 100644 tools/pblimage.h

diff --git a/Makefile b/Makefile
index dc2e3d8..ca6078e 100644
--- a/Makefile
+++ b/Makefile
@@ -361,6 +361,10 @@ $(obj)u-boot.kwb:   $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $ $@
 
+$(obj)u-boot.pbl:   $(obj)u-boot.bin
+   $(obj)tools/mkimage -n $(PBL_CONFIG) -T pblimage \
+   -d $ $@
+
 $(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)tools/ubsha1 $(obj)u-boot.bin
 
@@ -1156,6 +1160,7 @@ clobber:  clean
$(obj)cscope.* $(obj)*.*~
@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
@rm -f $(obj)u-boot.kwb
+   @rm -f $(obj)u-boot.pbl
@rm -f $(obj)u-boot.imx
@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
diff --git a/board/freescale/corenet_ds/config.mk 
b/board/freescale/corenet_ds/config.mk
new file mode 100644
index 000..c94938f
--- /dev/null
+++ b/board/freescale/corenet_ds/config.mk
@@ -0,0 +1,26 @@
+#
+# Copyright 2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+ifeq ($(CONFIG_RAMBOOT_PBL), y)
+PBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/pblimage.cfg
+ALL += $(obj)u-boot.pbl
+endif
diff --git a/board/freescale/corenet_ds/pblimage.cfg 
b/board/freescale/corenet_ds/pblimage.cfg
new file mode 100644
index 000..96c55ee
--- /dev/null
+++ b/board/freescale/corenet_ds/pblimage.cfg
@@ -0,0 +1,59 @@
+#
+# Copyright 2011 Freescale Semiconductor, Inc.
+# Written-by: Shaohui Xieb21...@freescale.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+4c58  18185218 
+40464000 3c3c2000 5800 6100
+   008b6000
+   
+
+#PBI commands
+#Initialize CPC1
+0901 00200400
+09138000 
+091380c0 0100
+09010100 
+09010104 fffb
+09010f00 0800
+0901 8000
+#Configure LAW for CPC1
+09000d00 
+09000d04 fff0
+09000d08 8113
+0910 
+0914 ff00
+0918 8100
+#Initialize eSPI

[U-Boot] [PATCH 1/2] powerpc: eSPI and eSPI controller support

[Shaohui Xie]

From: Mingkai Hu mingkai...@freescale.com

This patch add espi support which is from MPC8536, and fixed some hunk
failed error, and rebased on Mike's sf unify patches.

Signed-off-by: Mingkai Hu mingkai...@freescale.com
Singed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Shaohui Xie b21...@freescale.com
Cc: Mike Frysinger vap...@gentoo.org
---
this patch is rebased on Mike's sf unify patches.

 drivers/mtd/spi/spi_flash.c |   45 
 drivers/spi/Makefile|1 +
 drivers/spi/fsl_espi.c  |  237 +++
 include/spi.h   |   26 +-
 4 files changed, 308 insertions(+), 1 deletions(-)
 create mode 100644 drivers/spi/fsl_espi.c

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 5c261f1..f745def 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1,6 +1,8 @@
 /*
  * SPI flash interface
+ * Add support for Freescale eSPI controller
  *
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  * Copyright (C) 2008 Atmel Corporation
  * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
  *
@@ -30,6 +32,7 @@ static int spi_flash_read_write(struct spi_slave *spi,
unsigned long flags = SPI_XFER_BEGIN;
int ret;
 
+#ifndef CONFIG_FSL_ESPI
if (data_len == 0)
flags |= SPI_XFER_END;
 
@@ -43,6 +46,48 @@ static int spi_flash_read_write(struct spi_slave *spi,
debug(SF: Failed to transfer %zu bytes of data: %d\n,
data_len, ret);
}
+#else
+   struct espi_transfer transfer[1];
+   unsigned char *buffer;
+   size_t buf_len;
+
+   if (data_in == NULL)
+   buf_len = cmd_len;
+   else
+   buf_len = 2 * cmd_len;
+
+   buffer = (unsigned char *)malloc(data_len + buf_len);
+   if (!buffer) {
+   debug(SF: Failed to malloc memory.\n);
+   return 1;
+   }
+
+   memcpy(buffer, cmd, cmd_len);
+   if (data_in == NULL)
+   memcpy(buffer + cmd_len, data_out, data_len);
+
+   transfer[0].cmd_len = cmd_len;
+   transfer[0].data_len = data_len;
+   transfer[0].tx_buf = buffer;
+   if (data_in == NULL)
+   transfer[0].rx_buf = NULL;
+   else
+   transfer[0].rx_buf = buffer + cmd_len;
+
+   transfer[0].flags = flags | SPI_XFER_END;
+
+   spi-transfer = transfer[0];
+   ret = spi_xfer(spi, 0, NULL, NULL, 0);
+   if (ret) {
+   debug(SF: Failed to send command %02x: %d\n, cmd, ret);
+   return ret;
+   }
+
+   if (data_in)
+   memcpy(data_in, transfer[0].rx_buf + cmd_len, data_len);
+
+   free(buffer);
+#endif
 
return ret;
 }
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d582fbb..74f1293 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
 COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
+COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
new file mode 100644
index 000..f4ff884
--- /dev/null
+++ b/drivers/spi/fsl_espi.c
@@ -0,0 +1,237 @@
+/*
+ * eSPI controller driver.
+ *
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Mingkai Hu (mingkai...@freescale.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+
+#include malloc.h
+#include spi.h
+#include asm/immap_85xx.h
+
+#define ESPI_MAX_CS_NUM4
+
+#define ESPI_EV_RNE(1  9)
+#define ESPI_EV_TNF(1  8)
+
+#define ESPI_MODE_EN   (1  31)   /* Enable interface */
+#define ESPI_MODE_TXTHR(x) ((x)  8)  /* Tx FIFO threshold */
+#define ESPI_MODE_RXTHR(x) ((x)  0)  /* Rx FIFO threshold */
+
+#define ESPI_COM_CS(x) ((x)  30)
+#define ESPI_COM_TRANLEN(x)((x)  0)
+
+#define ESPI_CSMODE_CI_INACTIVEHIGH(1  31)
+#define ESPI_CSMODE_CP_BEGIN_EDGCLK(1  30)
+#define ESPI_CSMODE_REV_MSB_FIRST  (1  29)
+#define ESPI_CSMODE_DIV16  (1  28)
+#define ESPI_CSMODE_PM(x)  ((x)  24)
+#define

[U-Boot] [PATCH][v3] PBL: add support for boot from SPI flash.

[Shaohui Xie]

PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and
PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as 1M SRAM
where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL
completes RCW and PBI phases.

Signed-off-by: Chunhe Lan b25...@freescale.com
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Signed-off-by: Shaohui Xie b21...@freescale.com
---
Use CONFIG_RAMBOOT_PBL instead of CONFIG_PBL_BOOT_INDIRECT according to Kumar's 
comment.

 arch/powerpc/cpu/mpc85xx/cpu_init.c  |   19 +++
 board/freescale/corenet_ds/config.mk |6 ++
 board/freescale/corenet_ds/tlb.c |9 +
 boards.cfg   |1 +
 include/configs/corenet_ds.h |   30 --
 5 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 4b8faa5..a58cd1a 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -139,6 +139,22 @@ static void enable_cpc(void)
for (i = 0; i  CONFIG_SYS_NUM_CPC; i++, cpc++) {
u32 cpccfg0 = in_be32(cpc-cpccfg0);
size += CPC_CFG0_SZ_K(cpccfg0);
+#ifdef CONFIG_RAMBOOT_PBL
+   if (in_be32(cpc-cpcsrcr0)  CPC_SRCR0_SRAMEN) {
+   /* find and disable LAW of SRAM */
+   struct law_entry law = 
find_law(CONFIG_SYS_INIT_L3_ADDR);
+
+   if (law.index == -1) {
+   printf(\nFatal error happened\n);
+   return;
+   }
+   disable_law(law.index);
+
+   clrbits_be32(cpc-cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
+   out_be32(cpc-cpccsr0, 0);
+   out_be32(cpc-cpcsrcr0, 0);
+   }
+#endif
 
out_be32(cpc-cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
/* Read back to sync write */
@@ -155,6 +171,9 @@ void invalidate_cpc(void)
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
for (i = 0; i  CONFIG_SYS_NUM_CPC; i++, cpc++) {
+   /* skip CPC when it used as all SRAM */
+   if (in_be32(cpc-cpcsrcr0)  CPC_SRCR0_SRAMEN)
+   continue;
/* Flash invalidate the CPC and clear all the locks */
out_be32(cpc-cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
while (in_be32(cpc-cpccsr0)  (CPC_CSR0_FI | CPC_CSR0_LFC))
diff --git a/board/freescale/corenet_ds/config.mk 
b/board/freescale/corenet_ds/config.mk
index 15bbf20..918775d 100644
--- a/board/freescale/corenet_ds/config.mk
+++ b/board/freescale/corenet_ds/config.mk
@@ -24,4 +24,10 @@
 # P4080DS board
 #
 
+ifeq ($(CONFIG_RAMBOOT_PBL), y)
+RESET_VECTOR_ADDRESS = 0xfffc
+endif
+
+ifndef RESET_VECTOR_ADDRESS
 RESET_VECTOR_ADDRESS = 0xeffc
+endif
diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c
index 1ae0416..08f91a7 100644
--- a/board/freescale/corenet_ds/tlb.c
+++ b/board/freescale/corenet_ds/tlb.c
@@ -51,9 +51,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
/* TLB 1 */
/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT)  defined(CONFIG_SYS_INIT_L3_ADDR)
+   /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+* SRAM is at 0xfff0, it covered the 0xf000.
+* */
+   SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+   MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+   0, 0, BOOKE_PAGESZ_1M, 1),
+#else
SET_TLB_ENTRY(1, 0xf000, 0xf000,
  MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
 
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
diff --git a/boards.cfg b/boards.cfg
index 94b8745..2052efc 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -502,6 +502,7 @@ P2020RDB_NANDpowerpc mpc85xx 
p1_p2_rdb   freesca
 P2020RDB_SDCARD  powerpc mpc85xx p1_p2_rdb   
freescale  -   P1_P2_RDB:P2020,SDCARD
 P2020RDB_SPIFLASHpowerpc mpc85xx p1_p2_rdb   
freescale  -   P1_P2_RDB:P2020,SPIFLASH
 P4080DS  powerpc mpc85xx corenet_ds  
freescale
+P4080DS_RAMBOOT_PBLpowerpc mpc85xx corenet_ds  freescale   
-   P4080DS:RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF8
 stxgp3   powerpc mpc85xx stxgp3  stx
 stxssa   powerpc mpc85xx stxssa  stx   
 -   stxssa
 stxssa_4Mpowerpc mpc85xx stxssa  stx   
 -   stxssa:STXSSA_4M
diff --git a/include/configs/corenet_ds.h b

[U-Boot] [PATCH 1/2][v2] PBL: add support for boot from SPI flash.

[Shaohui Xie]

PBL: SPI flash used as RCW and PBI source, CPC used as 1M SRAM
where PBL will copy whole U-BOOT image to, U-boot can boot from CPC
after PBL completes RCW and PBI phases.

Signed-off-by: Chunhe Lan b25...@freescale.com
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Signed-off-by: Shaohui Xie b21...@freescale.com
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c  |   17 +
 board/freescale/corenet_ds/config.mk |6 ++
 board/freescale/corenet_ds/tlb.c |9 +
 boards.cfg   |1 +
 include/configs/corenet_ds.h |   31 +--
 5 files changed, 62 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 27236a0..cff7ac3 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -139,6 +139,20 @@ static void enable_cpc(void)
for (i = 0; i  CONFIG_SYS_NUM_CPC; i++, cpc++) {
u32 cpccfg0 = in_be32(cpc-cpccfg0);
size += CPC_CFG0_SZ_K(cpccfg0);
+   if (in_be32(cpc-cpcsrcr0)  CPC_SRCR0_SRAMEN) {
+   /* find and disable LAW of SRAM */
+   struct law_entry law = 
find_law(CONFIG_SYS_INIT_L3_ADDR);
+
+   if (law.index == -1) {
+   printf(\nFatal error happened\n);
+   return;
+   } else
+   disable_law(law.index);
+
+   clrbits_be32(cpc-cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
+   out_be32(cpc-cpccsr0, 0);
+   out_be32(cpc-cpcsrcr0, 0);
+   }
 
out_be32(cpc-cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
/* Read back to sync write */
@@ -155,6 +169,9 @@ void invalidate_cpc(void)
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
for (i = 0; i  CONFIG_SYS_NUM_CPC; i++, cpc++) {
+   /* skip CPC when it used as all SRAM */
+   if (in_be32(cpc-cpcsrcr0)  CPC_SRCR0_SRAMEN)
+   continue;
/* Flash invalidate the CPC and clear all the locks */
out_be32(cpc-cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
while (in_be32(cpc-cpccsr0)  (CPC_CSR0_FI | CPC_CSR0_LFC))
diff --git a/board/freescale/corenet_ds/config.mk 
b/board/freescale/corenet_ds/config.mk
index 15bbf20..31b3379 100644
--- a/board/freescale/corenet_ds/config.mk
+++ b/board/freescale/corenet_ds/config.mk
@@ -24,4 +24,10 @@
 # P4080DS board
 #
 
+ifeq ($(CONFIG_PBL_BOOT_INDIRECT), y)
+RESET_VECTOR_ADDRESS = 0xfffc
+endif
+
+ifndef RESET_VECTOR_ADDRESS
 RESET_VECTOR_ADDRESS = 0xeffc
+endif
diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c
index 1ae0416..08f91a7 100644
--- a/board/freescale/corenet_ds/tlb.c
+++ b/board/freescale/corenet_ds/tlb.c
@@ -51,9 +51,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
/* TLB 1 */
/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT)  defined(CONFIG_SYS_INIT_L3_ADDR)
+   /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+* SRAM is at 0xfff0, it covered the 0xf000.
+* */
+   SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+   MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+   0, 0, BOOKE_PAGESZ_1M, 1),
+#else
SET_TLB_ENTRY(1, 0xf000, 0xf000,
  MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
 
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
diff --git a/boards.cfg b/boards.cfg
index 6c2a667..168d6f5 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -195,6 +195,7 @@ P1022DS powerpc mpc85xx p1022ds 
freescale
 P2020DSpowerpc mpc85xx p2020ds freescale
 stxgp3 powerpc mpc85xx stxgp3  stx
 P4080DSpowerpc mpc85xx corenet_ds  freescale
+P4080DS_PBL_BOOT_INDIRECT  powerpc mpc85xx corenet_ds  
freescale   -   P4080DS:PBL_BOOT_INDIRECT,SYS_TEXT_BASE=0xFFF8
 sbc8540powerpc mpc85xx sbc8560 -   
-   SBC8540
 sbc8548powerpc mpc85xx sbc8548 -   
-   sbc8548
 sbc8560powerpc mpc85xx sbc8560 -   
-   sbc8560
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 2ac59e5..0776c3b 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -28,6 +28,11 @@
 
 #include ../board/freescale/common/ics307_clk.h
 
+#ifdef CONFIG_PBL_BOOT_INDIRECT
+#define CONFIG_RAMBOOT_PBL 1
+#define CONFIG_RAMBOOT_TEXT_BASE0xfff8
+#endif
+
 /* High

[U-Boot] [PATCH 2/2][v2] Add readme of how to boot from espi flash for p4080ds.

[Shaohui Xie]

Signed-off-by: Shaohui Xie b21...@freescale.com
---
 doc/README.espi-boot-p4080ds |   85 ++
 1 files changed, 85 insertions(+), 0 deletions(-)
 create mode 100644 doc/README.espi-boot-p4080ds

diff --git a/doc/README.espi-boot-p4080ds b/doc/README.espi-boot-p4080ds
new file mode 100644
index 000..79ef459
--- /dev/null
+++ b/doc/README.espi-boot-p4080ds
@@ -0,0 +1,85 @@
+Overview:
+=
+The P4080 integrates a pre-boot-loader(PBL) which performs configuration
+registers read and write to initialize external memory devices such as I2c,
+eLBC FCM(NAND flash), eSDHC, or SPI interface, loads RCW and/or pre-boot
+initialization commands from those devices before the local cores are permitted
+to boot.
+
+Boot from SPI:
+==
+
+The P4080 is capable of booting from SPI. The bootup process can be divided 
into
+two stages: the first stage will load RCW and write configuration registers to
+initialize SPI interface, and configure one CPC as 1M SRAM, and loads U-boot 
image
+to CPC. The second stage will configure all the hardware and boot up to U-Boot
+command line.
+
+The PBL image contains three parts, the first is RCW, the second is PBI 
commands
+performs configuration registers write, the third is the 512KB u-boot image. 
The
+PBL image is produced by tool pbl_image_tool.html.
+
+Build and boot steps
+
+
+1. Producing RCW
+Copy RCW of u-boot dump and paste it to tab Tools of the tool and choose
+RCW[0:511] U-Boot CCSR Dump and then click button Decode PBL, switch to tab
+Boot and change PBI_SRC to 0b0101 - SPI 24b Addressing, change BOOT_LOC to
+0b1 - Memory Complex 1(if CPC2 is used as SRAM, this should be set as
+0b10001 - Memory Complex 2).
+
+2. Producing ACS File
+   make P4080DS_PBL_BOOT_INDIRECT_config
+   make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
+   xxd u-boot.bin  u-boot.xxd
+
+3. Producing PBI commands
+Switch to tab PBI and paste commands below into text field (please note these
+commands are for CPC1 used as SRAM only, change corresponding register setting
+if CPC2 need to be used as SRAM), then choose ACS File (XXD Object Dump),
+change Offset to f8, and click Browse to select the u-boot.xxd file
+produced in step 2, and click Add PBI Data, after it finished, paste
+09138000  and 091380c0  at the end.
+
+Below are Commands pasted before click Add PBI Data.
+
+   PBI DATA  | Description
+   -
+   |  0901 00200400  | CPCFI  |
+   |  09138000   | CPCLFC for CPC1 |
+   |  091380c0 0100  | |
+   -
+   |  09010100   | Configure   |
+   |  09010104 fffb  | CPC1 as |
+   |  09010f00 0800  | 1M SRAM |
+   |  0901 8000  | |
+   -
+   |  09000d00   | Configure   |
+   |  09000d04 fff0  | LAW for CPC1|
+   |  09000d08 8113  | |
+   -
+   |  0910   | Configure   |
+   |  0914 ff00  | Alternate   |
+   |  0918 8100  | for CPC1|
+   -
+   |  0911 8403  | Initialize  |
+   |  09110020 2d170008  | SPI interface   |
+   |  09110024 0018  | |
+   |  09110028 0018  | |
+   |  0911002c 0018  | |
+   -
+   |  09138000   | Flush command   |
+   |  091380c0   | |
+   -
+
+4. Producing PBL image
+   1. Switch to tab Tools and click Encode PBL, after it finished copy
+the encoded content to file and save as x.xxd.
+   2. xxd -r x.xxd  pbl_u-boot.bin
+
+5. Put image to SPI flash
+   Put the pbl_u-boot.bin to SPI flash from offset 0.
+
+6. Change dip-switch
+   Change SW1[2] = off, then power on.
-- 
1.6.4


___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH 2/2] Add readme of how to boot from espi flash for p4080ds.

[Shaohui Xie]

Signed-off-by: Shaohui Xie b21...@freescale.com
---
 doc/README.espi-boot-p4080ds |   82 ++
 1 files changed, 82 insertions(+), 0 deletions(-)
 create mode 100644 doc/README.espi-boot-p4080ds

diff --git a/doc/README.espi-boot-p4080ds b/doc/README.espi-boot-p4080ds
new file mode 100644
index 000..50447c1
--- /dev/null
+++ b/doc/README.espi-boot-p4080ds
@@ -0,0 +1,82 @@
+Overview:
+=
+The P4080 integrates a pre-boot-loader(PBL) which performs configuration
+registers read and write to initialize external memory devices such as I2c,
+eLBC FCM(NAND flash), eSDHC, or SPI interface, loads RCW and/or pre-boot
+initialization commands from those devices before the local cores are permitted
+to boot.
+
+Boot from SPI:
+==
+
+The P4080 is capable of booting from SPI. The bootup process can be divided 
into
+two stages: the first stage will load RCW and write configuration registers to
+initialize SPI interface, and configure CPC1 as 1M SRAM, and loads U-boot image
+to CPC1. The second stage will configure all the hardware and boot up to U-Boot
+command line.
+
+The PBL image contains three parts, the first is RCW, the second is PBI 
commands
+performs configuration registers write, the third is the 512KB u-boot image. 
The
+PBL image is produced by tool pbl_image_tool.html.
+
+Build and boot steps
+
+
+1. Producing RCW
+Copy RCW of u-boot dump and paste it to tab Tools of the tool and choose
+RCW[0:511] U-Boot CCSR Dump and then click button Decode PBL, switch to tab
+Boot and change PBI_SRC to 0b0101 - SPI 24b Addressing, change BOOT_LOC to
+0b1 - Memory Complex 1.
+
+2. Producing ACS File
+   make P4080DS_PBLSPI_config
+   make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
+   xxd u-boot.bin  u-boot.xxd
+
+3. Producing PBI commands
+Switch to tab PBI and paste commands below into text field, then choose
+ACS File (XXD Object Dump), change Offset to f8, and click Browse to
+select the u-boot.xxd file produced in step 2, and click Add PBI Data, after
+it finished, paste 09138000  and 091380c0  at the end.
+
+Below are Commands pasted before click Add PBI Data.
+
+   PBI DATA  | Description
+   -
+   |  0901 00200400  | CPCFI  |
+   |  09138000   | CPCLFC  |
+   |  091380c0 0100  | |
+   -
+   |  09010100   | Configure   |
+   |  09010104 fffb  | CPC1 as |
+   |  09010f00 0800  | 1M SRAM |
+   |  0901 8000  | |
+   -
+   |  09000d00   | Configure   |
+   |  09000d04 fff0  | LAW of  |
+   |  09000d08 8113  | CPC1|
+   -
+   |  0910   | Configure   |
+   |  0914 ff00  | Alternate   |
+   |  0918 8100  | |
+   -
+   |  0911 8403  | Initialize  |
+   |  09110020 2d170008  | SPI interface   |
+   |  09110024 0018  | |
+   |  09110028 0018  | |
+   |  0911002c 0018  | |
+   -
+   |  09138000   | Flush command   |
+   |  091380c0   | |
+   -
+
+4. Producing PBL image
+   1. Switch to tab Tools and click Encode PBL, after it finished copy
+the encoded content to file and save as x.xxd.
+   2. xxd -r x.xxd  pbl_u-boot.bin
+
+5. Put image to SPI flash
+   Put the pbl_u-boot.bin to SPI flash from offset 0.
+
+6. Change dip-switch
+   Change SW1[2] = off, then power on.
-- 
1.6.4


___
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[U-Boot] [PATCH 1/2] PBL: add support for boot from SPI flash.

[Shaohui Xie]

PBL: SPI flash used as RCW and PBI source, CPC1 used as 1M SRAM
where PBL will copy whole U-BOOT image to, U-boot can boot from CPC1
after PBL completes RCW and PBI phases.

To produces the U-boot image which can used by PBL, pbl_image_tool.html
is a necessary tool.

Signed-off-by: Chunhe Lan b25...@freescale.com
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Signed-off-by: Shaohui Xie b21...@freescale.com
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c  |   25 +
 board/freescale/corenet_ds/config.mk |   6 ++
 board/freescale/corenet_ds/tlb.c |9 +
 boards.cfg   |1 +
 include/configs/corenet_ds.h |   31 +--
 5 files changed, 70 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 27236a0..b5a90fb 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -136,6 +136,26 @@ static void enable_cpc(void)
 
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
+#if defined(CONFIG_SYS_RAMBOOT)  defined(CONFIG_SYS_INIT_L3_ADDR)
+   if (in_be32(cpc-cpccsr0)  CPC_CSR0_CE) {
+   /* find and disable LAW of SRAM */
+   struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
+
+   if (law.index == -1) {
+   printf(\nFatal error happened\n);
+   return;
+   } else
+   disable_law(law.index);
+
+#ifdef CONFIG_SYS_P4080_ERRATUM_CPC4
+   /* Disable workaround - only needed in all SRAM mode */
+   clrbits_be32(cpc-cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
+#endif
+   out_be32(cpc-cpccsr0, 0);
+   out_be32(cpc-cpcsrcr0, 0);
+   }
+#endif
+
for (i = 0; i  CONFIG_SYS_NUM_CPC; i++, cpc++) {
u32 cpccfg0 = in_be32(cpc-cpccfg0);
size += CPC_CFG0_SZ_K(cpccfg0);
@@ -155,6 +175,11 @@ void invalidate_cpc(void)
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
for (i = 0; i  CONFIG_SYS_NUM_CPC; i++, cpc++) {
+#if defined(CONFIG_SYS_RAMBOOT)  defined(CONFIG_SYS_INIT_L3_ADDR)
+   /* skip CPC1 when it used as all SRAM */
+   if (i == 0)
+   continue;
+#endif
/* Flash invalidate the CPC and clear all the locks */
out_be32(cpc-cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
while (in_be32(cpc-cpccsr0)  (CPC_CSR0_FI | CPC_CSR0_LFC))
diff --git a/board/freescale/corenet_ds/config.mk 
b/board/freescale/corenet_ds/config.mk
index 15bbf20..ece4578 100644
--- a/board/freescale/corenet_ds/config.mk
+++ b/board/freescale/corenet_ds/config.mk
@@ -24,4 +24,10 @@
 # P4080DS board
 #
 
+ifeq ($(CONFIG_PBLSPI), y)
+RESET_VECTOR_ADDRESS = 0xfffc
+endif
+
+ifndef RESET_VECTOR_ADDRESS
 RESET_VECTOR_ADDRESS = 0xeffc
+endif
diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c
index 1ae0416..08f91a7 100644
--- a/board/freescale/corenet_ds/tlb.c
+++ b/board/freescale/corenet_ds/tlb.c
@@ -51,9 +51,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
/* TLB 1 */
/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT)  defined(CONFIG_SYS_INIT_L3_ADDR)
+   /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+* SRAM is at 0xfff0, it covered the 0xf000.
+* */
+   SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+   MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+   0, 0, BOOKE_PAGESZ_1M, 1),
+#else
SET_TLB_ENTRY(1, 0xf000, 0xf000,
  MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
 
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
diff --git a/boards.cfg b/boards.cfg
index 6c2a667..562721f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -195,6 +195,7 @@ P1022DS powerpc mpc85xx p1022ds 
freescale
 P2020DSpowerpc mpc85xx p2020ds freescale
 stxgp3 powerpc mpc85xx stxgp3  stx
 P4080DSpowerpc mpc85xx corenet_ds  freescale
+P4080DS_PBLSPI powerpc mpc85xx corenet_ds  freescale   -   
P4080DS:PBLSPI,SYS_TEXT_BASE=0xFFF8
 sbc8540powerpc mpc85xx sbc8560 -   
-   SBC8540
 sbc8548powerpc mpc85xx sbc8548 -   
-   sbc8548
 sbc8560powerpc mpc85xx sbc8560 -   
-   sbc8560
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 2ac59e5..df03448 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -28,6 +28,11 @@
 
 #include ../board/freescale