test: py: CVE-2020-29651 Regular expression deinal of service in py
Hi Tom FYI, there is a CVE from the following file in U-Boot, CVE-2020-29651 Regular expression deinal of service in py. test/py/requirements.txt Regards Ley Foon
RE: [v1 17/17] arm: socfpga: Enable Intel N5X device build
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 31, 2021 10:39 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 17/17] arm: socfpga: Enable Intel N5X device build
>
> Add defconfig for N5X to support legacy, ATF and VAB boot flow.
>
> Signed-off-by: Siew Chin Lim
> ---
> arch/arm/mach-socfpga/Kconfig | 20 +++-
> arch/arm/mach-socfpga/Makefile | 22
> +-
> ...lex_atf_defconfig => socfpga_n5x_atf_defconfig} | 10 +-
> ...fpga_agilex_defconfig => socfpga_n5x_defconfig} | 15 ++-
> ...lex_vab_defconfig => socfpga_n5x_vab_defconfig} | 10 +-
> 5 files changed, 56 insertions(+), 21 deletions(-) copy
> configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_atf_defconfig} (89%)
> copy configs/{socfpga_agilex_defconfig => socfpga_n5x_defconfig} (80%)
> copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_vab_defconfig}
> (89%)
>
Reviewed-by: Ley Foon Tan
RE: [v1 16/17] include: configs: Add Intel N5X device CONFIGs
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 31, 2021 10:39 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 16/17] include: configs: Add Intel N5X device CONFIGs
>
> Add CONFIGs for N5X.
>
> Signed-off-by: Siew Chin Lim
> ---
> include/configs/socfpga_n5x_socdk.h | 45
> +
> 1 file changed, 45 insertions(+)
> create mode 100644 include/configs/socfpga_n5x_socdk.h
>
> diff --git a/include/configs/socfpga_n5x_socdk.h
> b/include/configs/socfpga_n5x_socdk.h
> new file mode 100644
> index 00..c295e91e3d
> --- /dev/null
> +++ b/include/configs/socfpga_n5x_socdk.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2020-2021 Intel Corporation
> + *
> + */
> +
> +#ifndef __CONFIG_SOCFGPA_N5X_H__
> +#define __CONFIG_SOCFGPA_N5X_H__
> +
> +#include
> +
> +#undef CONFIG_EXTRA_ENV_SETTINGS
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
> + "bootfile=" CONFIG_BOOTFILE "\0" \
> + "fdt_addr=110\0" \
> + "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
> + "mmcroot=/dev/mmcblk0p2\0" \
> + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
> + " root=${mmcroot} rw rootwait;" \
> + "booti ${loadaddr} - ${fdt_addr}\0" \
> + "mmcload=mmc rescan;" \
> + "load mmc 0:1 ${loadaddr} ${bootfile};" \
> + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
> + "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
> + " root=${mmcroot} rw rootwait;" \
> + "bootm ${loadaddr}\0" \
> + "mmcfitload=mmc rescan;" \
> + "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
> + "ramboot=setenv bootargs " CONFIG_BOOTARGS";" \
> + "booti ${loadaddr} - ${fdt_addr}\0" \
> + "linux_qspi_enable=if sf probe; then " \
> + "echo Enabling QSPI at Linux DTB...;" \
> + "fdt addr ${fdt_addr}; fdt resize;" \
> + "fdt set /soc/spi@ff8d2000 status okay;" \
> + "if fdt set /soc/clocks/qspi-clk clock-frequency" \
> + " ${qspi_clock}; then" \
> + " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
> + " ${qspi_clock}; fi; fi\0" \
> + "scriptaddr=0x0210\0" \
> + "scriptfile=u-boot.scr\0" \
> + "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
> +"then source ${scriptaddr}; fi\0"
> +
> +#endif /* __CONFIG_SOCFGPA_N5X_H__ */
> --
Reviewed-by: Ley Foon Tan
RE: [v1 15/17] arm: dts: Add base dtsi and devkit dts for Intel N5X device
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 31, 2021 10:39 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 15/17] arm: dts: Add base dtsi and devkit dts for Intel N5X
> device
>
> Add device tree for N5X.
>
> Signed-off-by: Siew Chin Lim
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/dts/Makefile | 1 +
> ..._agilex-u-boot.dtsi => socfpga_n5x-u-boot.dtsi} | 13 ++--
> .../dts/{socfpga_agilex.dtsi => socfpga_n5x.dtsi} | 90 +--
> ---
> arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 67
> ...fpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} | 10 ++-
> 5 files changed, 135 insertions(+), 46 deletions(-) copy
> arch/arm/dts/{socfpga_agilex-u-boot.dtsi => socfpga_n5x-u-boot.dtsi} (85%)
> copy arch/arm/dts/{socfpga_agilex.dtsi => socfpga_n5x.dtsi} (88%) create
> mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_n5x_socdk.dts}
> (92%)
>
Port dts/dtsi from Linux, then overwrite U-Boot specific settings with
u-boot.dtsi.
Uboot dts got a lot differences compare to Linux dts now. Example, Linux reuse
socfpga_agilex.dtsi.
RE: [v1 14/17] board: intel: Add socdk board support for Intel N5X device
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 31, 2021 10:39 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 14/17] board: intel: Add socdk board support for Intel N5X device
>
> Add N5X SoC devkit board.
>
> Signed-off-by: Siew Chin Lim
> ---
> board/intel/n5x-socdk/MAINTAINERS | 7 +++
> board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
> board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
> 3 files changed, 9 insertions(+), 2 deletions(-) create mode 100644
> board/intel/n5x-socdk/MAINTAINERS copy board/{altera/stratix10-socdk =>
> intel/n5x-socdk}/Makefile (50%) copy board/{altera/stratix10-socdk =>
> intel/n5x-socdk}/socfpga.c (52%)
>
> diff --git a/board/intel/n5x-socdk/MAINTAINERS b/board/intel/n5x-
> socdk/MAINTAINERS
> new file mode 100644
> index 00..c1059f092c
> --- /dev/null
> +++ b/board/intel/n5x-socdk/MAINTAINERS
> @@ -0,0 +1,7 @@
> +SOCFPGA BOARD
> +M: Chee Tien Fong
> +M: Lim Siew Chin
> +S: Maintained
> +F: board/intel/n5x-socdk/
> +F: include/configs/socfpga_n5x_socdk.h
> +F: configs/socfpga_n5x_atf_defconfig
> diff --git a/board/altera/stratix10-socdk/Makefile b/board/intel/n5x-
> socdk/Makefile similarity index 50% copy from board/altera/stratix10-
> socdk/Makefile
> copy to board/intel/n5x-socdk/Makefile
> index 02a9cadf76..accfdcddcb 100644
> --- a/board/altera/stratix10-socdk/Makefile
> +++ b/board/intel/n5x-socdk/Makefile
> @@ -1,5 +1,5 @@
> #
> -# Copyright (C) 2016-2017 Intel Corporation
> +# Copyright (C) 2020-2021 Intel Corporation
> #
> # SPDX-License-Identifier: GPL-2.0
> #
> diff --git a/board/altera/stratix10-socdk/socfpga.c b/board/intel/n5x-
> socdk/socfpga.c similarity index 52% copy from board/altera/stratix10-
> socdk/socfpga.c
> copy to board/intel/n5x-socdk/socfpga.c
> index 043fc543f1..985ba190d0 100644
> --- a/board/altera/stratix10-socdk/socfpga.c
> +++ b/board/intel/n5x-socdk/socfpga.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2016-2018 Intel Corporation
> + * Copyright (C) 2020-2021 Intel Corporation
> *
> */
>
Reviewed-by: Ley Foon Tan
RE: [v1 13/17] arm: socfpga: Add SPL for Intel N5X device
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 31, 2021 10:39 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 13/17] arm: socfpga: Add SPL for Intel N5X device
>
> Add SPL for N5X.
>
> Signed-off-by: Siew Chin Lim
> ---
> arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 ++--
> ---
> 1 file changed, 22 insertions(+), 15 deletions(-) copy arch/arm/mach-
> socfpga/{spl_agilex.c => spl_n5x.c} (83%)
>
> diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-
> socfpga/spl_n5x.c similarity index 83% copy from arch/arm/mach-
> socfpga/spl_agilex.c
> copy to arch/arm/mach-socfpga/spl_n5x.c
> index ee5a9dc1e2..d056871d29 100644
> --- a/arch/arm/mach-socfpga/spl_agilex.c
> +++ b/arch/arm/mach-socfpga/spl_n5x.c
> @@ -1,27 +1,26 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2019 Intel Corporation
> + * Copyright (C) 2020-2021 Intel Corporation
> *
> */
>
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> #include
Sort this.
> -#include
> -#include
> -#include
> #include
> #include
> #include
> #include
> #include
> #include
> -#include
> +#include
> +#include
> +#include
> +#include
> #include
> +#include
> +#include
> +#include
> +#include
> +#include
>
Regards
Ley Foon
RE: [v1 12/17] ddr: altera: Add SDRAM driver for Intel N5X device
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Wednesday, March 31, 2021 10:39 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v1 12/17] ddr: altera: Add SDRAM driver for Intel N5X device > > The DDR subsystem in Diamond Mesa is consisted of controller, PHY, > memory reset manager and memory clock manager. > > Configuration settings of controller, PHY and memory reset manager > is come from DDR handoff data in bitstream, which contain the register > base addresses and user settings from Quartus. > > Configuration settings of memory clock manager is come from the HPS > handoff data in bitstream, however the register base address is defined > in device tree. > > The calibration is fully done in HPS, which requires IMEM and DMEM > binaries loading to PHY SRAM for running this calibration, both > IMEM and DMEM binaries are also part of bitstream, this bitstream > would be loaded to OCRAM by SDM, and configured by DDR driver. > > Signed-off-by: Siew Chin Lim > Signed-off-by: Tien Fong Chee > --- > arch/arm/mach-socfpga/include/mach/firewall.h |6 + > .../include/mach/system_manager_soc64.h| 10 +- > drivers/ddr/altera/Makefile|3 +- > drivers/ddr/altera/sdram_n5x.c | 2316 > > drivers/ddr/altera/sdram_soc64.c | 10 +- > 5 files changed, 2342 insertions(+), 3 deletions(-) > create mode 100644 drivers/ddr/altera/sdram_n5x.c [...] > --- /dev/null > +++ b/drivers/ddr/altera/sdram_n5x.c > @@ -0,0 +1,2316 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2020-2021 Intel Corporation > + * > + */ > + > +#include Sorting this. > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "sdram_soc64.h" > +#include > + > +DECLARE_GLOBAL_DATA_PTR; > + > +/* MPFE NOC registers */ > +#define FPGA2SDRAM_MGR_MAIN_SIDEBANDMGR_FLAGOUTSET0 > 0xF8024050 > + > +/* Memory reset manager */ > +#define MEM_RST_MGR_STATUS 0x8 > + > +/* Register and bit in memory reset manager */ > +#define MEM_RST_MGR_STATUS_RESET_COMPLETEBIT(0) > +#define MEM_RST_MGR_STATUS_PWROKIN_STATUSBIT(1) > +#define MEM_RST_MGR_STATUS_CONTROLLER_RSTBIT(2) > +#define MEM_RST_MGR_STATUS_AXI_RST BIT(3) > + > +#define TIMEOUT_200MS 200 > +#define TIMEOUT_5000MS5000 > + > +/* DDR4 umctl2 */ > +#define DDR4_MSTR_OFFSET 0x0 > +#define DDR4_FREQ_RATIO BIT(22) > + > +#define DDR4_STAT_OFFSET 0x4 > +#define DDR4_STAT_SELFREF_TYPE (BIT(5) | BIT(4)) > +#define DDR4_STAT_SELFREF_TYPE_SHIFT 4 > +#define DDR4_STAT_OPERATING_MODE (BIT(2) | BIT(1) | BIT(0)) > + > +#define DDR4_MRCTRL0_OFFSET 0x10 > +#define DDR4_MRCTRL0_MR_TYPE BIT(0) > +#define DDR4_MRCTRL0_MPR_EN BIT(1) > +#define DDR4_MRCTRL0_MR_RANK (BIT(5) | BIT(4)) > +#define DDR4_MRCTRL0_MR_RANK_SHIFT 4 > +#define DDR4_MRCTRL0_MR_ADDR (BIT(15) | BIT(14) | BIT(13) | > BIT(12)) This is mask value? If yes, can use GENMASK() macro. Same for the defines below. > +#define DDR4_MRCTRL0_MR_ADDR_SHIFT 12 > +#define DDR4_MRCTRL0_MR_WR BIT(31) > + > +#define DDR4_MRCTRL1_OFFSET 0x14 > +#define DDR4_MRCTRL1_MR_DATA 0x3 > + > +#define DDR4_MRSTAT_OFFSET 0x18 > +#define DDR4_MRSTAT_MR_WR_BUSY BIT(0) > + > +#define DDR4_MRCTRL2_OFFSET 0x1C > + > +#define DDR4_PWRCTL_OFFSET 0x30 > +#define DDR4_PWRCTL_SELFREF_EN BIT(0) > +#define DDR4_PWRCTL_POWERDOWN_EN BIT(1) > +#define DDR4_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) > +#define DDR4_PWRCTL_SELFREF_SW BIT(5) > + > +#define DDR4_PWRTMG_OFFSET 0x34 > +#define DDR4_HWLPCTL_OFFSET 0x38 > +#define DDR4_RFSHCTL0_OFFSET 0x50 > +#define DDR4_RFSHCTL1_OFFSET 0x54 > + > +#define DDR4_RFSHCTL3_OFFSET 0x60 > +#define DDR4_RFSHCTL3_DIS_AUTO_REFRESH BIT(0) > +#define DDR4_RFSHCTL3_REFRESH_MODE (BIT(6) | BIT(5) | > BIT(4)) > +#define DDR4_RFSHCTL3_REFRESH_MODE_SHIFT 4 > + > +#define DDR4_ECCCFG0_OFFSET 0x70 > +#define DDR
RE: [v1 10/17] arm: socfpga: Add SDRAM driver helper function for Intel N5X device
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 31, 2021 10:39 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 10/17] arm: socfpga: Add SDRAM driver helper function for Intel
> N5X device
>
> Add is_ddr_init_skipped function to check if need to skip DDR initialization
> for N5X. This patch is preparation for N5X DDR driver support.
>
> Signed-off-by: Siew Chin Lim
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/mach-socfpga/include/mach/misc.h | 4 ++
> arch/arm/mach-socfpga/misc_soc64.c| 67
> ++-
> 2 files changed, 70 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-
> socfpga/include/mach/misc.h
> index 649d2f6ce2..c41b7c14cd 100644
> --- a/arch/arm/mach-socfpga/include/mach/misc.h
> +++ b/arch/arm/mach-socfpga/include/mach/misc.h
> @@ -44,6 +44,10 @@ void socfpga_sdram_remap_zero(void); int
> is_fpga_config_ready(void); #endif
>
> +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
> +bool is_ddr_init_skipped(void);
> +#endif
> +
> void do_bridge_reset(int enable, unsigned int mask); void
> socfpga_pl310_clear(void); void socfpga_get_managers_addr(void); diff --git
> a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-
> socfpga/misc_soc64.c
> index 7b973a79e8..d3945e55aa 100644
> --- a/arch/arm/mach-socfpga/misc_soc64.c
> +++ b/arch/arm/mach-socfpga/misc_soc64.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2016-2018 Intel Corporation
> + * Copyright (C) 2016-2021 Intel Corporation
> *
> */
>
> @@ -19,6 +19,13 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +/* Reset type */
> +enum reset_type {
> + POR_RESET,
> + WARM_RESET,
> + COLD_RESET
> +};
> +
> /*
> * FPGA programming support for SoC FPGA Stratix 10
> */
> @@ -88,3 +95,61 @@ void do_bridge_reset(int enable, unsigned int mask)
>
> socfpga_bridges_reset(enable);
> }
> +
> +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
> +static bool is_ddr_retention_enabled(u32 boot_scratch_cold0_reg) {
> + return boot_scratch_cold0_reg &
> +ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK;
> +}
> +
> +static bool is_ddr_bitstream_sha_matching(u32 boot_scratch_cold0_reg) {
> + return boot_scratch_cold0_reg &
> ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK;
> +}
> +
> +static enum reset_type get_reset_type(u32 boot_scratch_cold0_reg) {
> + return (boot_scratch_cold0_reg &
> + ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK) >>
> + ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT;
> +}
> +
> +bool is_ddr_init_skipped(void)
1. This function can move to DDR driver.
2. Change this function return true if need the DDR init, so that doesn't need
to invert checking when call to this function, more readable.
> +{
> + u32 reg = readl(socfpga_get_sysmgr_addr() +
> + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> +
> + if (get_reset_type(reg) == POR_RESET) {
Store reset type in a variable, don't call get_reset_type() multiple times.
> + debug("%s: POR reset is triggered\n", __func__);
> + debug("%s: DDR init is required\n", __func__);
> + return false;
> + }
> +
> + if (get_reset_type(reg) == WARM_RESET) {
> + debug("%s: Warm reset is triggered\n", __func__);
> + debug("%s: DDR init is skipped\n", __func__);
> + return true;
> + }
> +
> + if (get_reset_type(reg) == COLD_RESET) {
> + debug("%s: Cold reset is triggered\n", __func__);
> +
> + if (is_ddr_retention_enabled(reg)) {
> + debug("%s: DDR retention bit is set\n", __func__);
> +
> + if (is_ddr_bitstream_sha_matching(reg)) {
Combine this IF with parent IF with &&.
> + debug("%s: Matching in DDR bistream\n",
> + __func__);
> + debug("%s: DDR init is skipped\n", __func__);
> + return true;
> + }
> +
> + debug("%s: Mismatch in DDR bistream\n", __func__);
> + }
> + }
> +
> + debug("%s: DDR init is required\n", __func__);
> + return false;
> +}
> +#endif
> --
> 2.13.0
RE: [v1 11/17] ddr: socfpga: Enable memory test on memory size less than 1GB
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 31, 2021 10:39 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject: [v1 11/17] ddr: socfpga: Enable memory test on memory size less
> than 1GB
>
> From: Tien Fong Chee
>
> Minimum 1GB memory size is required in current memory test, so this patch
> improves the memory test for processing memory size less than 1GB, and
> the size in power of two.
>
> Signed-off-by: Tien Fong Chee
> ---
> drivers/ddr/altera/sdram_soc64.c | 18 --
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/ddr/altera/sdram_soc64.c
> b/drivers/ddr/altera/sdram_soc64.c
> index a08f0953e5..171cde0e6b 100644
> --- a/drivers/ddr/altera/sdram_soc64.c
> +++ b/drivers/ddr/altera/sdram_soc64.c
> @@ -182,6 +182,7 @@ void sdram_size_check(struct bd_info *bd)
> phys_size_t total_ram_check = 0;
> phys_size_t ram_check = 0;
> phys_addr_t start = 0;
> + phys_size_t size, total_size;
Use "remaining_size" is more suitable.
> int bank;
>
> /* Sanity check ensure correct SDRAM size specified */ @@ -189,10
> +190,23 @@ void sdram_size_check(struct bd_info *bd)
>
> for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
> start = bd->bi_dram[bank].start;
> + total_size = bd->bi_dram[bank].size;
> while (ram_check < bd->bi_dram[bank].size) {
> - ram_check += get_ram_size((void *)(start +
> ram_check),
> - (phys_size_t)SZ_1G);
> + size = min((phys_addr_t)SZ_1G,
> (phys_addr_t)total_size);
> +
> + /*
> + * Ensure the size is power of two, this is requirement
> to run
> + * get_ram_size() / memory test
> + */
> + if (size != 0 && ((size & (size - 1)) == 0)) {
> + ram_check += get_ram_size((void *)(start +
> ram_check), size);
> + total_size = bd->bi_dram[bank].size -
> ram_check;
> + } else {
> + puts("DDR: Memory test requires SDRAM
> size in power of two!\n");
> + hang();
> + }
> }
> +
> total_ram_check += ram_check;
> ram_check = 0;
> }
> --
> 2.13.0
RE: [v1 09/17] arm: socfpga: Changed misc_s10.c to misc_soc64.c
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Wednesday, March 31, 2021 10:39 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v1 09/17] arm: socfpga: Changed misc_s10.c to misc_soc64.c > > Rename to common file name to used by all SOC64 devices. > No functionality change. > > Signed-off-by: Siew Chin Lim > --- Reviewed-by: Ley Foon Tan
RE: [v1 08/17] arm: socfpga: Add clock manager for Intel N5X device
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 31, 2021 10:39 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 08/17] arm: socfpga: Add clock manager for Intel N5X device
>
> Add clock manager for N5X.
>
> Signed-off-by: Siew Chin Lim
> ---
> ...{clock_manager_agilex.c => clock_manager_n5x.c} | 32 ++---
> - arch/arm/mach-socfpga/include/mach/clock_manager.h | 2
> ++ .../mach-socfpga/include/mach/clock_manager_n5x.h | 12
> 3 files changed, 29 insertions(+), 17 deletions(-) copy arch/arm/mach-
> socfpga/{clock_manager_agilex.c => clock_manager_n5x.c} (64%) create
> mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
Reviewed-by: Ley Foon Tan
[GIT PULL] SoCFPGA changes for v2021.07-rc1
Hi Tom
Please pull the SoCFPGA changes for v2021.07.
Regards
Ley Foon
The following changes since commit e9c99db7787e3b5c2ef05701177c43ed1c023c27:
Merge branch '2021-04-07-CI-improvements' (2021-04-07 15:54:07 -0400)
are available in the Git repository at:
https://github.com/lftan/u-boot.git v2021.07-rc1
for you to fetch changes up to 96fe4f6485e92ed9da464c96c5f536698c5ee66d:
arm: socfpga: smc: Add function to get usercode (2021-04-08 17:29:13 +0800)
Siew Chin Lim (11):
arm: socfpga: smc: Remove unused SMC function ID
arm: socfpga: Move Stratix10 and Agilex SPL common code
arm: socfpga: Rename Stratix10 and Agilex handoff common macros
arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c
arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c
arm: socfpga: Rearrange sequence of macros in handoff_soc64.h
arm: socfpga: Restructure Stratix10 and Agilex handoff code
arm: socfpga: Move Stratix10 and Agilex clock manager common code
arm: socfpga: Changed to store QSPI reference clock in kHz
arm: socfpga: Enable FIT signature with crc32 for SOC64 devices
arm: socfpga: smc: Add function to get usercode
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 30 --
arch/arm/mach-socfpga/Makefile | 14 +++--
arch/arm/mach-socfpga/clock_manager.c | 43 +-
arch/arm/mach-socfpga/clock_manager_agilex.c | 6 --
arch/arm/mach-socfpga/clock_manager_s10.c | 8 +--
arch/arm/mach-socfpga/include/mach/clock_manager.h | 5 ++
.../include/mach/clock_manager_arria10.h | 2 -
.../mach-socfpga/include/mach/clock_manager_gen5.h | 1 -
.../mach-socfpga/include/mach/clock_manager_s10.h | 1 -
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39 -
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 62
arch/arm/mach-socfpga/include/mach/smc_api.h | 1 +
.../include/mach/system_manager_soc64.h| 20 +--
arch/arm/mach-socfpga/mailbox_s10.c| 17 +++---
arch/arm/mach-socfpga/smc_api.c| 17 ++
arch/arm/mach-socfpga/spl_agilex.c | 16 --
arch/arm/mach-socfpga/spl_s10.c| 17 --
arch/arm/mach-socfpga/spl_soc64.c | 25
...system_manager_s10.c => system_manager_soc64.c} | 55 +++---
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 66 ++
arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 56 --
...ap_pll_config_s10.c => wrap_pll_config_soc64.c} | 16 +++---
configs/socfpga_agilex_atf_defconfig | 4 ++
configs/socfpga_agilex_vab_defconfig | 4 ++
configs/socfpga_stratix10_atf_defconfig| 4 ++
include/configs/socfpga_soc64_common.h | 4 +-
include/linux/intel-smc.h | 52 +++--
27 files changed, 341 insertions(+), 244 deletions(-)
delete mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_soc64.h
create mode 100644 arch/arm/mach-socfpga/spl_soc64.c
rename arch/arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c}
(57%)
create mode 100644 arch/arm/mach-socfpga/wrap_handoff_soc64.c
delete mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
rename arch/arm/mach-socfpga/{wrap_pll_config_s10.c =>
wrap_pll_config_soc64.c} (74%)
RE: [v1 07/17] arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Wednesday, March 31, 2021 10:39 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v1 07/17] arm: socfpga: Move cm_get_mpu_clk_hz function > declaration to clock_manager.h > > Move cm_get_mpu_clk_hz function declaration from individual device's > clock manager header file to common clock_manager.h. > > Signed-off-by: Siew Chin Lim > --- > arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 + > arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 -- > arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h | 1 - > arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h| 1 - > arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 - > 5 files changed, 1 insertion(+), 5 deletions(-) > Reviewed-by: Ley Foon Tan
RE: [v1 05/17] arm: socfpga: Get clock manager base address for Intel N5X device
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 31, 2021 10:39 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 05/17] arm: socfpga: Get clock manager base address for Intel
> N5X device
>
> Add N5X clock manager to socfpga_get_managers_addr function.
>
> Signed-off-by: Siew Chin Lim
> ---
> arch/arm/mach-socfpga/misc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index 64a7c9d652..9305bec38a 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -254,6 +254,9 @@ void socfpga_get_managers_addr(void) #ifdef
> CONFIG_TARGET_SOCFPGA_AGILEX
> ret = socfpga_get_base_addr("intel,agilex-clkmgr",
> &socfpga_clkmgr_base);
> +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
> + ret = socfpga_get_base_addr("intel,n5x-clkmgr",
> + &socfpga_clkmgr_base);
> #else
> ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
> #endif
> --
> 2.13.0
Reviewed-by: Ley Foon Tan
RE: [v1 06/17] drivers: clk: Add memory clock driver for Intel N5X device
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 31, 2021 10:39 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 06/17] drivers: clk: Add memory clock driver for Intel N5X device
>
> Add memory clock manager driver for N5X. Provides memory clock
> initialization and enable functions.
>
> Signed-off-by: Siew Chin Lim
> ---
> drivers/clk/altera/Makefile | 1 +
> drivers/clk/altera/clk-mem-n5x.c | 136
> +++
> drivers/clk/altera/clk-mem-n5x.h | 84
> 3 files changed, 221 insertions(+)
> create mode 100644 drivers/clk/altera/clk-mem-n5x.c create mode 100644
> drivers/clk/altera/clk-mem-n5x.h
>
> diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index
> 38cd730685..33db092918 100644
> --- a/drivers/clk/altera/Makefile
> +++ b/drivers/clk/altera/Makefile
> @@ -6,3 +6,4 @@
> obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
> obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
> obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
> +obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o
> diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-
> n5x.c
> new file mode 100644
> index 00..ca44998641
> --- /dev/null
> +++ b/drivers/clk/altera/clk-mem-n5x.c
> @@ -0,0 +1,136 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020-2021 Intel Corporation */
> +
> +#include
> +#include
> +#include
> +#include
> +#include "clk-mem-n5x.h"
> +#include
> +#include
> +#include
> +#include
> +#include
Sorting the include name.
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct socfpga_mem_clk_plat {
> + void __iomem *regs;
> +};
> +
> +++ b/drivers/clk/altera/clk-mem-n5x.h
> @@ -0,0 +1,84 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2020-2021 Intel Corporation */
> +
> +#ifndef _CLK_MEM_N5X_
> +#define _CLK_MEM_N5X_
> +
> +#ifndef __ASSEMBLY__
> +#include
> +#endif
> +
> +/* Clock Manager registers */
> +#define MEMCLKMGR_STAT 4
> +#define MEMCLKMGR_INTRGEN8
> +#define MEMCLKMGR_INTRMSK0x0C
For consistency, use small letter for 0x0C.
> +#define MEMCLKMGR_INTRCLR0x10
> +#define MEMCLKMGR_INTRSTS0x14
> +#define MEMCLKMGR_INTRSTK0x18
> +#define MEMCLKMGR_INTRRAW0x1C
Same here.
> +
> +/* Memory Clock Manager PPL group registers */
> +#define MEMCLKMGR_MEMPLL_EN 0x20
> +#define MEMCLKMGR_MEMPLL_ENS 0x24
> +#define MEMCLKMGR_MEMPLL_ENR 0x28
> +#define MEMCLKMGR_MEMPLL_BYPASS 0x2c
> +#define MEMCLKMGR_MEMPLL_BYPASSS 0x30
> +#define MEMCLKMGR_MEMPLL_BYPASSR 0x34
> +#define MEMCLKMGR_MEMPLL_MEMDIV 0x38
> +#define MEMCLKMGR_MEMPLL_PLLGLOB 0x3c
> +#define MEMCLKMGR_MEMPLL_PLLCTRL 0x40
> +#define MEMCLKMGR_MEMPLL_PLLDIV 0x44
> +#define MEMCLKMGR_MEMPLL_PLLOUTDIV 0x48
> +#define MEMCLKMGR_MEMPLL_EXTCNTRST 0x4c
> +
> +#define MEMCLKMGR_CTRL_BOOTMODE BIT(0)
> +
> +#define MEMCLKMGR_STAT_MEMPLL_LOCKED BIT(8)
> +
> +#define MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK\
> + (MEMCLKMGR_STAT_MEMPLL_LOCKED)
> +
> +#define MEMCLKMGR_INTER_MEMPLLLOCKED_MASK
> 0x0001
> +#define MEMCLKMGR_INTER_MEMPLLLOST_MASK
> 0x0004
> +
> +#define MEMCLKMGR_BYPASS_MEMPLL_ALL 0x1
> +
> +#define MEMCLKMGR_MEMDIV_MPFEDIV_OFFSET 0
> +#define MEMCLKMGR_MEMDIV_APBDIV_OFFSET 4
> +#define MEMCLKMGR_MEMDIV_DFICTRLDIV_OFFSET 8
> +#define MEMCLKMGR_MEMDIV_DFIDIV_OFFSET 12
> +#define MEMCLKMGR_MEMDIV_DFICTRLDIV_MASK 0x1
> +#define MEMCLKMGR_MEMDIV_DIVIDER_MASK0x3
> +
> +#define MEMCLKMGR_PLLGLOB_PSRC_MASK
> GENMASK(17, 16)
> +#define MEMCLKMGR_PLLGLOB_PSRC_OFFSET16
> +#define MEMCLKMGR_PLLGLOB_LOSTLOCK_BYPASS_EN_MASKBIT(28)
> +#define MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29)
> +
> +
RE: [v1 04/17] drivers: clk: Add clock driver for Intel N5X device
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 31, 2021 10:39 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 04/17] drivers: clk: Add clock driver for Intel N5X device
>
> Add clock manager driver for N5X. Provides clock initialization and get_rate
> functions.
>
> Signed-off-by: Siew Chin Lim
> ---
> drivers/clk/altera/Makefile | 3 +-
> drivers/clk/altera/clk-n5x.c | 489
> ++
> drivers/clk/altera/clk-n5x.h | 217 +++
> include/dt-bindings/clock/n5x-clock.h | 71 +
> 4 files changed, 779 insertions(+), 1 deletion(-) create mode 100644
> drivers/clk/altera/clk-n5x.c create mode 100644 drivers/clk/altera/clk-n5x.h
> create mode 100644 include/dt-bindings/clock/n5x-clock.h
>
> diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index
> 96215ad5c4..38cd730685 100644
> --- a/drivers/clk/altera/Makefile
> +++ b/drivers/clk/altera/Makefile
> @@ -1,7 +1,8 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
> -# Copyright (C) 2018 Marek Vasut
> +# Copyright (C) 2018-2021 Marek Vasut
> #
>
> obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
> obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
> +obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
> diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c new
> file
> mode 100644 index 00..12e6aa9ac2
> --- /dev/null
> +++ b/drivers/clk/altera/clk-n5x.c
> @@ -0,0 +1,489 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020-2021 Intel Corporation */
> +
> +#include
Sorting the include name.
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
[...]
> +
> + /* Take all PLLs out of bypass */
> + clk_write_bypass_mainpll(plat, 0);
> + clk_write_bypass_perpll(plat, 0);
> +
> + /* Clear the loss of lock bits (write 1 to clear) */
> + CM_REG_CLRBITS(plat, CLKMGR_INTRCLR,
> +CLKMGR_INTER_PERPLLLOST_MASK |
> +CLKMGR_INTER_MAINPLLLOST_MASK);
Comment "write 1 to clear" is valid?
> +
> + /* Take all ping pong counters out of reset */
> + CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST,
> +CLKMGR_ALT_EXTCNTRST_ALLCNTRST_MASK);
> +
> + /* Out of boot mode */
> + clk_write_ctrl(plat,
> +CM_REG_READL(plat, CLKMGR_CTRL) &
> ~CLKMGR_CTRL_BOOTMODE); }
> +
> +static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u32 reg)
> +{
> + u32 clksrc = CM_REG_READL(plat, reg);
> +
> + return (clksrc & CLKMGR_CLKSRC_MASK) >>
> CLKMGR_CLKSRC_OFFSET; }
> +
> +static u64 clk_get_pll_output_hz(struct socfpga_clk_plat *plat,
> + u32 pllglob_reg, u32 plldiv_reg)
> +{
> + u64 clock = 0;
> + u32 clklsrc, divf, divr, divq, power = 1;
> +
> + /* Get input clock frequency */
> + clklsrc = (CM_REG_READL(plat, pllglob_reg) &
Redundant () can be removed. Same for other code in this source file.
> +CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
> +CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
> +
> + switch (clklsrc) {
> + case CLKMGR_VCO_PSRC_EOSC1:
> + clock = cm_get_osc_clk_hz();
> + break;
> + case CLKMGR_VCO_PSRC_INTOSC:
> + clock = cm_get_intosc_clk_hz();
> + break;
> + case CLKMGR_VCO_PSRC_F2S:
> + clock = cm_get_fpga_clk_hz();
> + break;
> + }
> +
Regards
Ley Foon
RE: [v1 03/17] arm: socfpga: Add handoff data support for Intel N5X device
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 31, 2021 10:39 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 03/17] arm: socfpga: Add handoff data support for Intel N5X
> device
>
> N5X support both HPS handoff data and DDR handoff data.
> HPS handoff data support re-use Straix10 and Agilex code. DDR handoff data
> is newly introduced for N5X.
>
> Signed-off-by: Siew Chin Lim
> ---
> arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 28
> +++
> arch/arm/mach-socfpga/wrap_handoff_soc64.c | 40
> ++
> 2 files changed, 68 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
[...]
> diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> index a7ad7a18ed..37b4c360fb 100644
> --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> @@ -60,6 +60,46 @@ int socfpga_handoff_read(void *handoff_address,
> void *table, u32 table_len,
> debug("at addr 0x%p\n", (u32 *)handoff_address);
> return -EPERM;
> }
> + } else {
> +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
> + temp = readl(handoff_address);
> + if (temp == SOC64_HANDOFF_DDR_UMCTL2_MAGIC) {
> + debug("%s: umctl2 handoff data =\n{\n",
> + __func__);
> + } else if (temp == SOC64_HANDOFF_DDR_PHY_MAGIC) {
> + debug("%s: PHY handoff data =\n{\n",
> + __func__);
> + } else if (temp ==
> SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC) {
> + debug("%s: PHY engine handoff data =\n{\n",
> + __func__);
> + }
> +
> + debug("handoff table address = 0x%p table length = 0x%x\n",
> + table_x32, table_len);
> +
> + if (temp == SOC64_HANDOFF_DDR_UMCTL2_MAGIC ||
> + temp == SOC64_HANDOFF_DDR_PHY_MAGIC ||
> + temp ==
> SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC) {
> + for (i = 0; i < table_len; i++) {
> + *table_x32 = readl(handoff_address +
> +
> SOC64_HANDOFF_OFFSET_DATA +
> + (i * 4));
> +
> + if (!(i % 2))
> + debug(" No.%d Addr 0x%08x: ", i,
> + *table_x32);
> + else
> + debug(" 0x%08x\n", *table_x32);
> +
> + table_x32++;
> + }
> + debug("\n}\n");
> + } else {
> + debug("%s: Cannot find HANDOFF MAGIC ",
> __func__);
> + debug("at addr 0x%p\n", (u32 *)handoff_address);
> + return -EPERM;
> + }
> +#endif
> }
>
> return 0;
1. Can we auto detect the endianness from the magic word?
2. Can merge or simplify the big and little endian flow? Do swap when it is
big endian.
Regards
Ley Foon
Regards
Ley Foon
RE: [v1 02/17] arm: socfpga: Add base address for Intel N5X device
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Wednesday, March 31, 2021 10:39 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v1 02/17] arm: socfpga: Add base address for Intel N5X device > > Reuse base_addr_soc64.h for Intel N5X device, the address is the same as > Agilex. > > Signed-off-by: Siew Chin Lim > --- > arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++- Reviewed-by: Ley Foon Tan
RE: [v1 01/17] arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 31, 2021 10:39 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 01/17] arm: socfpga: Changed base_addr_s10.h to
> base_addr_soc64.h
>
> Rename to common file name to used by all SOC64 devices and change
> "_S10_" to "_SOC64_" in base_addr_soc64.h.
>
> Signed-off-by: Siew Chin Lim
> ---
> .../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8 ---
> -
> include/configs/socfpga_soc64_common.h| 2 +-
> 2 files changed, 5 insertions(+), 5 deletions(-) rename arch/arm/mach-
> socfpga/include/mach/{base_addr_s10.h => base_addr_soc64.h} (89%)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
> similarity index 89%
> rename from arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> rename to arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
> index d3eca65e97..f89066d771 100644
> --- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
Reviewed-by: Ley Foon Tan
RE: [PATCH] arm: socfpga: Enable FIT signature with crc32 for SOC64 devices
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Wednesday, March 24, 2021 11:57 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [PATCH] arm: socfpga: Enable FIT signature with crc32 for SOC64 > devices > > Add signature with crc32 value for all images in binman node for FIT image in > device tree. And, enable FIT signature checking for Stratix10 and Agilex ATF > and VAB sdmmc boot. > > Signed-off-by: Siew Chin Lim > --- > arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 30 > +- > configs/socfpga_agilex_atf_defconfig | 4 > configs/socfpga_agilex_vab_defconfig | 4 > configs/socfpga_stratix10_atf_defconfig| 4 > 4 files changed, 37 insertions(+), 5 deletions(-) > Reviewed-by: Ley Foon Tan
RE: [v2 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Wednesday, March 24, 2021 1:12 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v2 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code > > Restructure Stratix10 and Agilex handoff code to used by all SOC64 devices, > in preparation to support handoff for Diamond Mesa. > > Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c which > contains the generic function to parse the handoff data. > > Update system_manager_soc64.c to use generic handoff function in > wrap_handoff_soc64.c. > > Signed-off-by: Siew Chin Lim > > --- > v2 > - Change "#ifdef" to "#if IS_ENABLED()" > - Change to use captial letter for enum macros (LITTLE_ENDIAN, BIG_ENDIAN) > - Soft include files by alphabetical order in system_manager_soc64.c > and wrap_handoff_soc64.c > - Simplify and clean up socfpga_get_handoff_size function > --- > arch/arm/mach-socfpga/Makefile | 4 +- > arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 23 +++- > .../include/mach/system_manager_soc64.h| 4 -- > arch/arm/mach-socfpga/system_manager_soc64.c | 55 +++ > --- > arch/arm/mach-socfpga/wrap_handoff_soc64.c | 66 > ++ Reviewed-by: Ley Foon Tan
RE: [v3 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Wednesday, March 24, 2021 5:17 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v3 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager > common code > > Move duplicated function cm_get_qspi_controller_clk_hz to > clock_manager.c. > > Signed-off-by: Siew Chin Lim > Signed-off-by: Tien Fong Chee > > --- > v3: > - Declare cm_get_qspi_controller_clk_hz function in clock_manager.h > to share by all Intel SOCFPGA. > - Remove cm_get_qspi_controller_clk_hz function declaration from > clock_manager_gen5.h and clock_manager_arria10.h. > --- Reviewed-by: Ley Foon Tan
RE: [PATCH] arm: socfpga: smc: Add function to get usercode
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Thursday, March 25, 2021 2:08 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [PATCH] arm: socfpga: smc: Add function to get usercode
>
> Add function to send mailbox command via SMC to get usercode from SDM.
>
> Signed-off-by: Siew Chin Lim
> ---
> arch/arm/mach-socfpga/include/mach/smc_api.h | 1 +
> arch/arm/mach-socfpga/smc_api.c | 17 +
> include/linux/intel-smc.h| 18 ++
> 3 files changed, 36 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/smc_api.h
> b/arch/arm/mach-socfpga/include/mach/smc_api.h
> index bbefdd8dd9..6b5b7eadc6 100644
> --- a/arch/arm/mach-socfpga/include/mach/smc_api.h
> +++ b/arch/arm/mach-socfpga/include/mach/smc_api.h
> @@ -9,5 +9,6 @@
> int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int
> ret_len);
> int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32
> *resp_buf_len,
>u32 *resp_buf);
> +int smc_get_usercode(u32 *usercode);
>
> #endif /* _SMC_API_H_ */
> diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-
> socfpga/smc_api.c index 085daba162..8ffc7a472b 100644
> --- a/arch/arm/mach-socfpga/smc_api.c
> +++ b/arch/arm/mach-socfpga/smc_api.c
> @@ -54,3 +54,20 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8
> urgent, u32 *resp_buf_len,
>
> return (int)resp[0];
> }
> +
> +int smc_get_usercode(u32 *usercode)
> +{
> + int ret;
> + u64 resp;
> +
> + if (!usercode)
> + return -EINVAL;
> +
> + ret = invoke_smc(INTEL_SIP_SMC_GET_USERCODE, NULL, 0,
> + &resp, 1);
> +
> + if (ret == INTEL_SIP_SMC_STATUS_OK)
> + *usercode = (u32)resp;
> +
> + return ret;
> +}
> diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h index
> 68d62be417..a54eff43ad 100644
> --- a/include/linux/intel-smc.h
> +++ b/include/linux/intel-smc.h
> @@ -518,4 +518,22 @@
> INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_
> COMPLETED_WRITE)
> #define INTEL_SIP_SMC_MBOX_SEND_CMD \
>
> INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_
> SEND_CMD)
>
> +/*
> + * Request INTEL_SIP_SMC_GET_USERCODE
> + *
> + * Send mailbox command to get usercode from SDM
> + *
> + * Call register usage:
> + * a0 INTEL_SIP_SMC_GET_USERCODE
> + * a1-7 not used.
> + *
> + * Return status
> + * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR
> + * a1 User code
> + * a2-3 not used.
> + */
> +#define INTEL_SIP_SMC_FUNCID_GET_USERCODE61
> +#define INTEL_SIP_SMC_GET_USERCODE \
> +
> INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_GET_US
> ERCODE)
> +
> #endif
> --
> 2.13.0
Reviewed-by: Ley Foon Tan
RE: [v2 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Wednesday, March 24, 2021 2:20 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v2 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz > > Changed to store QSPI reference clock in kHz instead of Hz in boot scratch > cold0 register for Stratix10 and Agilex. > > This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4 > bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI > reference clock. > Due to limited bits, QSPI reference clock frequency is converted to kHz from > Hz. > > Signed-off-by: Siew Chin Lim > Signed-off-by: Tien Fong Chee > > --- > v2: > - Rename mbox_qspi_set_controller_clk_hz function to > cm_set_qspi_controller_clk_hz function and move to clock_manager.c. > - Remove CLOCK_1K macro from socfpga_soc64_common.h > - Sort include file list by alphabetical order in mailbox_s10.c > --- > Reviewed-by: Ley Foon Tan
RE: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 24, 2021 1:25 PM
> To: Tan, Ley Foon ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject: RE: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager
> common code
>
> Hi Ley Foon,
>
> > -Original Message-
> > From: Tan, Ley Foon
> > Sent: Tuesday, March 23, 2021 6:34 PM
> > To: Lim, Elly Siew Chin ;
> > u-boot@lists.denx.de
> > Cc: Marek Vasut ; See, Chin Liang
> > ; Simon Goldschmidt
> > ; Chee, Tien Fong
> > ; Westergreen, Dalon
> > ; Simon Glass ; Gan,
> > Yau Wai
> > Subject: RE: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock
> > manager common code
> >
> >
> >
> > > -Original Message-
> > > From: Lim, Elly Siew Chin
> > > Sent: Monday, March 15, 2021 10:37 PM
> > > To: u-boot@lists.denx.de
> > > Cc: Marek Vasut ; Tan, Ley Foon
> > > ; See, Chin Liang
> > > ; Simon Goldschmidt
> > > ; Chee, Tien Fong
> > > ; Westergreen, Dalon
> > > ; Simon Glass ;
> Gan,
> > > Yau Wai ; Lim, Elly Siew Chin
> > >
> > > Subject: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock
> > > manager common code
> > >
> > > Move duplicated function cm_get_qspi_controller_clk_hz to
> > > clock_manager.c.
> > >
> > > Signed-off-by: Siew Chin Lim
> > > Signed-off-by: Tien Fong Chee
> > > ---
> > > arch/arm/mach-socfpga/clock_manager.c | 15
> > > --
> -
> > > arch/arm/mach-socfpga/clock_manager_agilex.c | 6 --
> > > arch/arm/mach-socfpga/clock_manager_s10.c | 6 --
> > > arch/arm/mach-socfpga/include/mach/clock_manager.h | 4
> > > arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 -
> > > 5 files changed, 16 insertions(+), 16 deletions(-)
> > >
> > [...]
> >
> >
> > > unsigned int cm_get_spi_controller_clk_hz(void)
> > > {
> > > u32 clock = cm_get_l3_main_clk_hz(); diff --git
> > > a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > index 1f734bcd65..0f0cb230fa 100644
> > > --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > @@ -12,6 +12,10 @@ phys_addr_t socfpga_get_clkmgr_addr(void); void
> > > cm_wait_for_lock(u32 mask); int cm_wait_for_fsm(void); void
> > > cm_print_clock_quick_summary(void);
> > > +
> > > +#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
> > > +unsigned int cm_get_qspi_controller_clk_hz(void);
> > > +#endif
> > > #endif
> > If this is for soc64, move to _SOC64.h file?
> >
> We do have clock_manager_soc64.h which shared by both stratix 10 and
> agilex.
>
> clock_manager_s10.h if specific for CONFIG_TARGET_SOCFPGA_STRATIX10.
> clock_manager_s10.h includes clock_manager_soc64.h and it contains
> additional struct and macro for s10.
> >
cm_get_qspi_controller_clk_hz() is for cyclone 5 and Arria 10 too, can just
function prototype in clock_manager.h and use for all devices.
Ley Foon
RE: [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 24, 2021 11:02 AM
> To: Tan, Ley Foon ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject: RE: [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff
> code
>
> Hi Ley Foon,
>
> > > +
> > > +int socfpga_handoff_read(void *handoff_address, void *table, u32
> > > table_len,
> > > + enum endianness big_endian)
> > > +{
> > > + u32 temp, i;
> > > + u32 *table_x32 = table;
> > > +
> > > + debug("%s: handoff addr = 0x%p ", __func__, (u32
> > > *)handoff_address);
> > > +
> > > + if (big_endian) {
> > > + if (swab32(readl(SOC64_HANDOFF_BASE)) ==
> > > SOC64_HANDOFF_MAGIC_BOOT) {
> > > + debug("Handoff table address = 0x%p ", table_x32);
> > > + debug("table length = 0x%x\n", table_len);
> > > + debug("%s: handoff data =\n{\n", __func__);
> > > +
> > > + for (i = 0; i < table_len; i++) {
> > > + temp = readl(handoff_address +
> > > + SOC64_HANDOFF_OFFSET_DATA +
> > > + (i * sizeof(u32)));
> > > + *table_x32 = swab32(temp);
> > > +
> > > + if (!(i % 2))
> > > + debug(" No.%d Addr 0x%08x: ", i,
> > > + *table_x32);
> > > + else
> > > + debug(" 0x%08x\n", *table_x32);
> > > +
> > > + table_x32++;
> > > + }
> > > + debug("\n}\n");
> > > + } else {
> > > + debug("%s: Cannot find
> > > SOC64_HANDOFF_MAGIC_BOOT ", __func__);
> > > + debug("at addr 0x%p\n", (u32 *)handoff_address);
> > > + return -EPERM;
> > > + }
> > > + }
> > How about if it is little endian, why don't need to fill up table_x32?
> >
> The little endian only needed in new Intel SOC N5X (Diamond Mesa) , we will
> upstream this part together with N5X patches later.
Then can return error if doesn't support little endian as now.
RE: [v1 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Monday, March 15, 2021 10:37 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz
>
> Changed to store QSPI reference clock in kHz instead of Hz in boot scratch
> cold0 register for Stratix10 and Agilex.
>
> This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4
> bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI
> reference clock.
> Due to limited bits, QSPI reference clock frequency is converted to kHz from
> Hz.
>
> Signed-off-by: Siew Chin Lim
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/mach-socfpga/clock_manager.c | 5 +--
> .../include/mach/system_manager_soc64.h| 16 -
> arch/arm/mach-socfpga/mailbox_s10.c| 40
> +++---
> include/configs/socfpga_soc64_common.h | 1 +
> 4 files changed, 55 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-
> socfpga/clock_manager.c
> index be426a5cfb..2783b9d18d 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -67,8 +67,9 @@ int set_cpu_clk_info(void) #if
> IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
> unsigned int cm_get_qspi_controller_clk_hz(void)
> {
> - return readl(socfpga_get_sysmgr_addr() +
> - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> + return (readl(socfpga_get_sysmgr_addr() +
> + SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &
> + SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) *
> CLOCK_1K;
> }
> #endif
>
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> index 1eb8e7a904..fc4e17821b 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> @@ -42,7 +42,10 @@ void populate_sysmgr_pinmux(void);
> #define SYSMGR_SOC64_GPO 0xe4
> #define SYSMGR_SOC64_GPI 0xe8
> #define SYSMGR_SOC64_MPU 0xf0
> -/* store qspi ref clock */
> +/*
> + * Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for
> +SOC 64-bit
> + * storing qspi ref clock (kHz)
> + */
> #define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200
> /* store osc1 clock freq */
> #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204
> @@ -85,6 +88,17 @@ void populate_sysmgr_pinmux(void);
> #define SYSMGR_SOC64_HPS_OSC_CLK 0x1358
> #define SYSMGR_SOC64_IODELAY00x1400
>
> +/*
> + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0
> + * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for
> +SOC 64-bit
> + * storing qspi ref clock (kHz)
> + */
> +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK
> GENMASK(27, 0)
> +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31)
> +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASKBIT(30)
> +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK
> (BIT(29) | BIT(28))
> +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT28
> +
> #define SYSMGR_SDMMC
> SYSMGR_SOC64_SDMMC
>
> #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
> diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-
> socfpga/mailbox_s10.c
> index 7dcdae8136..2a13fbb506 100644
> --- a/arch/arm/mach-socfpga/mailbox_s10.c
> +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> @@ -356,6 +356,38 @@ int mbox_qspi_close(void)
>0, NULL, 0, 0, NULL);
> }
>
> +int mbox_qspi_set_controller_clk_hz(int clk_hz) {
This function nothing related to mailbox. Change to other name and move the
function to the place read qspi clock.
Then can remove define CLOCK_1K from socfpga_soc64_common.h.
> + u32 reg;
> + u32 clk_khz;
> +
> + /* We are getting QSPI ref clock and set into sysmgr boot register */
> + /*
> + * Only clock freq in kHz degree is accepted due to limited bits[27:0]
> + * is reserved for storing the QSPI clock freq into boot scratch cold0
> + * register
> + */
> + if (clk_hz < CLOCK_1K)
> + return -EINVAL;
> +
> + clk_khz = clk_hz / CLOCK_1K;
> + printf("QSPI: Reference clock at %d kHz\n", clk_khz);
> +
> + /*
> + * DDR retent
RE: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Monday, March 15, 2021 10:37 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager
> common code
>
> Move duplicated function cm_get_qspi_controller_clk_hz to
> clock_manager.c.
>
> Signed-off-by: Siew Chin Lim
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/mach-socfpga/clock_manager.c | 15 ---
> arch/arm/mach-socfpga/clock_manager_agilex.c | 6 --
> arch/arm/mach-socfpga/clock_manager_s10.c | 6 --
> arch/arm/mach-socfpga/include/mach/clock_manager.h | 4
> arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 -
> 5 files changed, 16 insertions(+), 16 deletions(-)
>
[...]
> unsigned int cm_get_spi_controller_clk_hz(void)
> {
> u32 clock = cm_get_l3_main_clk_hz();
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> index 1f734bcd65..0f0cb230fa 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> @@ -12,6 +12,10 @@ phys_addr_t socfpga_get_clkmgr_addr(void); void
> cm_wait_for_lock(u32 mask); int cm_wait_for_fsm(void); void
> cm_print_clock_quick_summary(void);
> +
> +#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
> +unsigned int cm_get_qspi_controller_clk_hz(void);
> +#endif
> #endif
If this is for soc64, move to _SOC64.h file?
Regards
Ley Foon
RE: [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Monday, March 15, 2021 5:43 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code
>
> Restructure Stratix10 and Agilex handoff code to used by all SOC64 devices,
> in preparation to support handoff for Diamond Mesa.
>
> Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c which
> contains the generic function to parse the handoff data.
>
> Update system_manager_soc64.c to use generic handoff function in
> wrap_handoff_soc64.c.
>
> Signed-off-by: Siew Chin Lim
> ---
> arch/arm/mach-socfpga/Makefile | 4 +-
> arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 21 +++
> .../include/mach/system_manager_soc64.h| 4 --
> arch/arm/mach-socfpga/system_manager_soc64.c | 53 ++-
> -
> arch/arm/mach-socfpga/wrap_handoff_soc64.c | 73
> ++
>
> diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
> b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
> index 2561255712..f4c03688d6 100644
> --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
> +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
> @@ -11,6 +11,7 @@
> * Offset for HW handoff from Quartus tools
> */
> /* HPS handoff */
> +#define SOC64_HANDOFF_MAGIC_BOOT 0x424F4F54
> #define SOC64_HANDOFF_MAGIC_MUX 0x504D5558
> #define SOC64_HANDOFF_MAGIC_IOCTL0x494F4354
> #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
> @@ -38,4 +39,24 @@
> #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE +
> 0x600)
> #endif
>
> +#define SOC64_HANDOFF_MUX_LEN96
> +#define SOC64_HANDOFF_IOCTL_LEN 96
> +#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
Can change to #if CONFIG_IS_ENABLED()
> +#define SOC64_HANDOFF_FPGA_LEN 42
> +#else
> +#define SOC64_HANDOFF_FPGA_LEN 40
> +#endif
> +#define SOC64_HANDOFF_DELAY_LEN 96
> +
> +#ifndef __ASSEMBLY__
> +#include
> +enum endianness {
> + little_endian,
> + big_endian
> +};
Uses capital letter for enum macros.
> +
> +int socfpga_get_handoff_size(void *handoff_address, enum endianness
> +endian); int socfpga_handoff_read(void *handoff_address, void *table,
> u32 table_len,
> + enum endianness big_endian);
> +#endif
> #endif /* _HANDOFF_SOC64_H_ */
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> index 4949cae97a..1eb8e7a904 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> @@ -10,10 +10,6 @@
> void sysmgr_pinmux_init(void);
> void populate_sysmgr_fpgaintf_module(void);
> void populate_sysmgr_pinmux(void);
> -void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
> -void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
> -void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int
> *table_len); -void sysmgr_pinmux_table_delay(const u32 **table, unsigned
> int *table_len);
>
> #define SYSMGR_SOC64_WDDBG 0x08
> #define SYSMGR_SOC64_DMA 0x20
[...]
> diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> new file mode 100644
> index 00..ba168676e9
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> @@ -0,0 +1,73 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Intel Corporation
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include "log.h"
Sort this.
> +
> +int socfpga_get_handoff_size(void *handoff_address, enum endianness
> +endian) {
> + u32 handoff_size;
> +
> + if (endian == little_endian) {
> + handoff_size = (readl(handoff_address +
> SOC64_HANDOFF_OFFSET_LENGTH) -
> + SOC64_HANDOFF_OFFSET_DATA) /
> + sizeof(u32);
> + } else if (endian == big_endian) {
> + handoff_size = swab32(readl(handoff_address +
> +
Can merge this, just need do additional swab32 if it is bit endian.
[.]
> +
> +int socfpga_handoff_read(void *handoff_address, void *table, u32
> table_len,
> + enum endianness
RE: [v1 4/5] arm: socfpga: Rearrange sequence of macros in handoff_soc64.h
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Monday, March 15, 2021 5:43 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v1 4/5] arm: socfpga: Rearrange sequence of macros in > handoff_soc64.h > > Rearrange sequence of macros in handoff_soc64.h without any functionality > change. In preparation for Stratix10 and Agilex handoff function > restructuring. > > Signed-off-by: Siew Chin Lim > --- > arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 22 > -- > 1 file changed, 12 insertions(+), 10 deletions(-) > Reviewed-by: Ley Foon Tan
RE: [v1 3/5] arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Monday, March 15, 2021 5:43 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v1 3/5] arm: socfpga: Changed system_manager_s10.c to > system_manager_soc64.c > > Rename to common file name to used by all SOC64 devices. > No functionality change. > > Signed-off-by: Siew Chin Lim > --- Reviewed-by: Ley Foon Tan
RE: [v1 2/5] arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Monday, March 15, 2021 5:43 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v1 2/5] arm: socfpga: Changed wrap_pll_config_s10.c to > wrap_pll_config_soc64.c > > Rename to common file name to used by all SOC64 devices. > > Signed-off-by: Siew Chin Lim > --- Reviewed-by: Ley Foon Tan
RE: [v1 1/5] arm: socfpga: Rename Stratix10 and Agilex handoff common macros
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Monday, March 15, 2021 5:43 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v1 1/5] arm: socfpga: Rename Stratix10 and Agilex handoff common > macros > > Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from > S10_HANDOFF to SOC64_HANDOFF. > > Signed-off-by: Siew Chin Lim > --- Reviewed-by: Ley Foon Tan
RE: [PATCH] arm: socfpga: Move Stratix10 and Agilex SPL common code
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Monday, March 15, 2021 3:59 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [PATCH] arm: socfpga: Move Stratix10 and Agilex SPL common code > > Move Stratix10 and Agilex SPL common code to spl_soc64.c. > We are in preparation for new n5x device support. > No functional change in this patch. > > Signed-off-by: Siew Chin Lim Reviewed-by: Ley Foon Tan
[GIT PULL] SoCFPGA changes for v2021.04-rc5
Hi Tom Please pull one fix for v2021.04-rc5. Thanks. Regards Ley Foon The following changes since commit 1f9c3f13f6ad8595a0fb5ab2cb830583cdc0b60a: Merge tag 'efi-2021-04-rc5-2' of https://source.denx.de/u-boot/custodians/u-boot-efi (2021-03-20 08:55:18 -0400) are available in the Git repository at: https://github.com/lftan/u-boot.git v2021.04-rc5 for you to fetch changes up to 2dbcc037ccf3a16a2a0225133f8721b87ae7fffb: arm: socfpga: Only do 'is OS booted from FIT' checking when VAB is enabled (2021-03-23 14:46:35 +0800) Siew Chin Lim (1): arm: socfpga: Only do 'is OS booted from FIT' checking when VAB is enabled arch/arm/mach-socfpga/board.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
RE: [PATCH] arm: socfpga: Only do 'is OS booted from FIT' checking when VAB is enabled
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Monday, March 22, 2021 6:05 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [PATCH] arm: socfpga: Only do 'is OS booted from FIT' checking > when VAB is enabled > > Check CONFIG_SOCFPGA_SECURE_VAB_AUTH before perform 'is OS booted > from FIT' > checking in board_prep_linux function. And, fix typo of > CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE. > > CONFIG_FIT will be enabled in both ATF and VAB boot flow, thus, > board_prep_linux function will always be called by both ATF and VAB boot > flow. > > board_pre_linux function will do 'is OS booted from FIT' checking, and it will > be called before board_fit_image_post_process function. > > VAB boot flow expects the OS is always booted from FIT and with VAB signed > cerfiticate because the VAB authentication is implemented in > board_fit_image_post_process function. So, VAB needs the 'is OS booted > from FIT' checking in board_pre_linux function. > > However, for ATF boot flow, it is not a requirement that the OS must always > booted from FIT. The OS can be booted from individual Image and kernel dtb > file. Thus, we should not do 'if OS is booted from FIT' > checking in board_prep_linux function. > > Signed-off-by: Siew Chin Lim Reviewed-by: Ley Foon Tan
RE: [PATCH] arm: socfpga: smc: Remove unused SMC function ID
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Friday, March 12, 2021 5:51 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [PATCH] arm: socfpga: smc: Remove unused SMC function ID > > Remove unused SMC function ID 61 and 62. > > Signed-off-by: Siew Chin Lim > --- Reviewed-by: Ley Foon Tan
[GIT PULL] SoCFPGA changes for v2021.04-rc4
Hi Tom Please pull these changes for v2021.04-rc4. Thanks. Regards Ley Foon The following changes since commit e4dba4ba6f61e8128be0b4200ca2d8cebf62180b: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq (2021-03-06 07:25:04 -0500) are available in the Git repository at: https://github.com/lftan/u-boot.git v2021.04-rc4 for you to fetch changes up to 9773ebcfbca23c7d6fe1dc202913b005bc23cc89: Makefile: socfpga: Add target to generate hex output for combined spl and dtb (2021-03-08 10:59:12 +0800) Dalon Westergreen (1): Makefile: socfpga: Add target to generate hex output for combined spl and dtb Siew Chin Lim (6): arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 arm: socfpga: soc64: Support Vendor Authorized Boot (VAB) arm: socfpga: cmd: Support 'vab' command arm: socfpga: dts: soc64: Update filename in binman node of FIT image with VAB support configs: socfpga: soc64: Move CONFIG_BOOTCOMMAND to defconfig configs: socfpga: Add defconfig for Agilex with VAB support Makefile | 11 +- arch/arm/Kconfig | 6 +- arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 22 +++ arch/arm/mach-socfpga/Kconfig | 20 +++ arch/arm/mach-socfpga/Makefile | 3 + arch/arm/mach-socfpga/board.c | 45 - arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 + arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +- arch/arm/mach-socfpga/include/mach/secure_vab.h| 63 +++ .../arm/mach-socfpga/include/mach/system_manager.h | 3 +- arch/arm/mach-socfpga/secure_vab.c | 186 + arch/arm/mach-socfpga/vab.c| 34 common/Kconfig.boot| 2 +- configs/socfpga_agilex_atf_defconfig | 2 + configs/socfpga_agilex_defconfig | 2 + configs/socfpga_agilex_vab_defconfig | 75 + configs/socfpga_stratix10_atf_defconfig| 2 + configs/socfpga_stratix10_defconfig| 2 + drivers/ddr/altera/Kconfig | 6 +- drivers/fpga/Kconfig | 2 +- drivers/sysreset/Kconfig | 2 +- include/configs/socfpga_soc64_common.h | 10 +- scripts/Makefile.spl | 7 + 23 files changed, 479 insertions(+), 30 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/secure_vab.h create mode 100644 arch/arm/mach-socfpga/secure_vab.c create mode 100644 arch/arm/mach-socfpga/vab.c create mode 100644 configs/socfpga_agilex_vab_defconfig
RE: [v5 2/7] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Monday, March 1, 2021 8:04 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v5 2/7] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB) > > Vendor Authorized Boot is a security feature for authenticating the images > such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and > etc loaded from FIT. After those images are loaded from FIT, the VAB > certificate and signature block appended at the end of each image are sent > to Secure Device Manager (SDM) for authentication. U-Boot will validate the > SHA384 of the image against the SHA384 hash stored in the VAB certificate > before sending the image to SDM for authentication. > > Signed-off-by: Siew Chin Lim > > --- > v5: > - In arch/arm/mach-socfpga/board.c > - Move '#if IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)' inside > board_fit_image_post_process function. > - Move '#if IS_ENABLED(CONFIG_SPL_BUID)' outside board_prep_linux > function. > > v4: > - Move function 'board_fit_image_post_process' and 'board_prep_linux' > from secure_vab.c to board.c. > --- > arch/arm/mach-socfpga/Kconfig| 15 ++ > arch/arm/mach-socfpga/Makefile | 2 + > arch/arm/mach-socfpga/board.c| 45 +- > arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 + > arch/arm/mach-socfpga/include/mach/secure_vab.h | 63 > arch/arm/mach-socfpga/secure_vab.c | 186 > +++ > common/Kconfig.boot | 2 +- > 7 files changed, 309 insertions(+), 5 deletions(-) create mode 100644 > arch/arm/mach-socfpga/include/mach/secure_vab.h > create mode 100644 arch/arm/mach-socfpga/secure_vab.c > Reviewed-by: Ley Foon Tan
RE: [v4 2/7] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Monday, March 1, 2021 2:43 PM
> To: Tan, Ley Foon ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject: RE: [v4 2/7] arm: socfpga: soc64: Support Vendor Authorized Boot
> (VAB)
>
> Hi Ley Foon,
>
> > -Original Message-
> > From: Tan, Ley Foon
> > Sent: Monday, March 1, 2021 9:56 AM
> > To: Lim, Elly Siew Chin ;
> > u-boot@lists.denx.de
> > Cc: Marek Vasut ; See, Chin Liang
> > ; Simon Goldschmidt
> > ; Chee, Tien Fong
> > ; Westergreen, Dalon
> > ; Simon Glass ; Gan,
> > Yau Wai
> > Subject: RE: [v4 2/7] arm: socfpga: soc64: Support Vendor Authorized
> > Boot
> > (VAB)
> >
> >
> >
> > > -Original Message-
> > > From: Lim, Elly Siew Chin
> > > Sent: Saturday, February 27, 2021 12:11 AM
> > > To: u-boot@lists.denx.de
> > > Cc: Marek Vasut ; Tan, Ley Foon
> > > ; See, Chin Liang
> > > ; Simon Goldschmidt
> > > ; Chee, Tien Fong
> > > ; Westergreen, Dalon
> > > ; Simon Glass ;
> Gan,
> > > Yau Wai ; Lim, Elly Siew Chin
> > >
> > > Subject: [v4 2/7] arm: socfpga: soc64: Support Vendor Authorized
> > > Boot
> > > (VAB)
> > >
> > > Vendor Authorized Boot is a security feature for authenticating the
> > > images such as U-Boot, ARM trusted Firmware, Linux kernel, device
> > > tree blob and etc loaded from FIT. After those images are loaded
> > > from FIT, the VAB certificate and signature block appended at the
> > > end of each image are sent to Secure Device Manager (SDM) for
> authentication.
> > > U-Boot will validate the
> > > SHA384 of the image against the SHA384 hash stored in the VAB
> > > certificate before sending the image to SDM for authentication.
> > >
> > > Signed-off-by: Siew Chin Lim
> > >
> > > ---
> > > v4:
> > > - Move function 'board_fit_image_post_process' and 'board_prep_linux'
> > to
> > > arch/arm/mach-socfpga/board.c
> > >
> > > v3:
> > > - Add description for function 'socfpga_vendor_authentication'.
> > > - Relocate vab certificate to first memory bank before trigger SMC call
> > > to send mailbox command because ATF only able to access first
> > > memory bank.
> > > - Report error instead of bypass the authentication in SPL if
> > > Secure Device Manager (SDM) does not support VAB.
> > > - Print success string if VAB success.
> > > - Replace #ifdef with if(IS_ENABLED(CONFIG_...)).
> > > ---
> > > arch/arm/mach-socfpga/Kconfig| 15 ++
> > > arch/arm/mach-socfpga/Makefile | 2 +
> > > arch/arm/mach-socfpga/board.c| 43 +-
> > > arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 +
> > > arch/arm/mach-socfpga/include/mach/secure_vab.h | 63
> > > arch/arm/mach-socfpga/secure_vab.c | 186
> > > +++
> > > common/Kconfig.boot | 2 +-
> > > 7 files changed, 307 insertions(+), 5 deletions(-) create mode
> > > 100644 arch/arm/mach-socfpga/include/mach/secure_vab.h
> > > create mode 100644 arch/arm/mach-socfpga/secure_vab.c
> > >
> > > #include
> > > -#include
> > > -#include
> > > -#include
> > > -#include #include
> > > #include
> > > +#include #include
> > > +
> > > #include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > #include
> > > #include
> > > #include
> > > @@ -97,3 +100,35 @@ __weak int board_fit_config_name_match(const
> > char
> > > *name)
> > > return 0;
> > > }
> > > #endif
> > > +
> > > +#if IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)
> > > +void board_fit_image_post_process(void **p_image, size_t *p_size) {
> > > + if (socfpga_vendor_authentication(p_image, p_size))
> > > + hang();
> > > +}
> > > +
> > > +void board_prep_linux(bootm_headers_t *images) {
> >
> > Check CONFIG_SOCFPGA_SECURE_VAB_AUTH setting, then only include
> code
> > below.
> >
> > > + if (!IS_ENABLED(CONFIG_SPL
RE: [RESEND v4 7/7] Makefile: socfpga: Add target to generate hex output for combined spl and dtb
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Saturday, February 27, 2021 12:58 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [RESEND v4 7/7] Makefile: socfpga: Add target to generate hex > output for combined spl and dtb > > From: Dalon Westergreen > > Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel SOCFPGA > SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex" > is hex formatted spl with and offset of CONFIG_SPL_TEXT_BASE. It combines > the spl image and dtb. "u-boot-spl-dtb.hex" is needed to generate the final > configuration bitstream for Intel SOCFPGA SOC64 devices. > > Signed-off-by: Dalon Westergreen > Signed-off-by: Siew Chin Lim > > --- > v4: > - Replace CONFIG_TARGET_SOCFPGA_STRATIX10/AGILEX with > CONFIG_TARGET_SOCFPGA_SOC64. > - Add this patch into 'VAB' series because it is depending on > CONFIG_TARGET_SOCFPGA_SOC64 patch. > --- > Makefile | 11 ++- > include/configs/socfpga_soc64_common.h | 2 +- > scripts/Makefile.spl | 7 +++ > 3 files changed, 14 insertions(+), 6 deletions(-) Reviewed-by: Ley Foon Tan Regards Ley Foon
RE: [v4 2/7] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Saturday, February 27, 2021 12:11 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v4 2/7] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
>
> Vendor Authorized Boot is a security feature for authenticating the images
> such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and
> etc loaded from FIT. After those images are loaded from FIT, the VAB
> certificate and signature block appended at the end of each image are sent
> to Secure Device Manager (SDM) for authentication. U-Boot will validate the
> SHA384 of the image against the SHA384 hash stored in the VAB certificate
> before sending the image to SDM for authentication.
>
> Signed-off-by: Siew Chin Lim
>
> ---
> v4:
> - Move function 'board_fit_image_post_process' and 'board_prep_linux' to
> arch/arm/mach-socfpga/board.c
>
> v3:
> - Add description for function 'socfpga_vendor_authentication'.
> - Relocate vab certificate to first memory bank before trigger SMC call
> to send mailbox command because ATF only able to access first memory
> bank.
> - Report error instead of bypass the authentication in SPL if
> Secure Device Manager (SDM) does not support VAB.
> - Print success string if VAB success.
> - Replace #ifdef with if(IS_ENABLED(CONFIG_...)).
> ---
> arch/arm/mach-socfpga/Kconfig| 15 ++
> arch/arm/mach-socfpga/Makefile | 2 +
> arch/arm/mach-socfpga/board.c| 43 +-
> arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 +
> arch/arm/mach-socfpga/include/mach/secure_vab.h | 63
> arch/arm/mach-socfpga/secure_vab.c | 186
> +++
> common/Kconfig.boot | 2 +-
> 7 files changed, 307 insertions(+), 5 deletions(-) create mode 100644
> arch/arm/mach-socfpga/include/mach/secure_vab.h
> create mode 100644 arch/arm/mach-socfpga/secure_vab.c
>
> #include
> -#include
> -#include
> -#include
> -#include
> #include
> #include
> +#include
> +#include
> #include
> +#include
> +#include
> +#include
> +#include
> +#include
> #include
> #include
> #include
> @@ -97,3 +100,35 @@ __weak int board_fit_config_name_match(const char
> *name)
> return 0;
> }
> #endif
> +
> +#if IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)
> +void board_fit_image_post_process(void **p_image, size_t *p_size) {
> + if (socfpga_vendor_authentication(p_image, p_size))
> + hang();
> +}
> +
> +void board_prep_linux(bootm_headers_t *images) {
Check CONFIG_SOCFPGA_SECURE_VAB_AUTH setting, then only include code below.
> + if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
> + if
> (!IS_ENABLED(CONFIG_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
> + /*
> + * Ensure the OS is always booted from FIT and with
> + * VAB signed certificate
> + */
> + if (!images->fit_uname_cfg) {
> + printf("Please use FIT with VAB signed
> images!\n");
> + hang();
> + }
> +
> + env_set_hex("fdt_addr", (ulong)images->ft_addr);
> + debug("images->ft_addr = 0x%08lx\n",
> (ulong)images->ft_addr);
> + }
> +
> + if (IS_ENABLED(CONFIG_CADENCE_QSPI)) {
> + if (env_get("linux_qspi_enable"))
> +
> run_command(env_get("linux_qspi_enable"), 0);
Can always run " linux_qspi_enable" command for all target SOC64? Then can
remove linux_qspi_enable from BOOTCOMMAND.
Regards
Ley Foon
RE: [v3 3/6] arm: socfpga: cmd: Support 'vab' command
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Friday, February 5, 2021 6:52 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v3 3/6] arm: socfpga: cmd: Support 'vab' command > > Support 'vab' command to perform vendor authentication. > > Command format: vab addr len > Authorize 'len' bytes starting at 'addr' via vendor public key > > Signed-off-by: Siew Chin Lim > > --- > v3 > --- > - Remove the print in 'vab' command to avoid duplicated print out. > The 'socfpga_vendor_authntication' function in secure_vab.c will > print out the string if VAB success. > --- Reviewed-by: Ley Foon Tan
RE: [v3 2/6] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Friday, February 5, 2021 6:52 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v3 2/6] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
>
> Vendor Authorized Boot is a security feature for authenticating the images
> such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and
> etc loaded from FIT. After those images are loaded from FIT, the VAB
> certificate and signature block appended at the end of each image are sent
> to Secure Device Manager (SDM) for authentication. U-Boot will validate the
> SHA384 of the image against the SHA384 hash stored in the VAB certificate
> before sending the image to SDM for authentication.
>
> Signed-off-by: Siew Chin Lim
>
> ---
> v3
> ---
> - Add description for function 'socfpga_vendor_authentication'.
> - Relocate vab certificate to first memory bank before trigger SMC call
> to send mailbox command because ATF only able to access first memory
> bank.
> - Report error instead of bypass the authentication in SPL if
> Secure Device Manager (SDM) does not support VAB.
> - Print success string if VAB success.
> - Replace #ifdef with if(IS_ENABLED(CONFIG_...)).
> ---
> arch/arm/mach-socfpga/Kconfig| 15 ++
> arch/arm/mach-socfpga/Makefile | 2 +
> arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 +
> arch/arm/mach-socfpga/include/mach/secure_vab.h | 63 +++
> arch/arm/mach-socfpga/secure_vab.c | 218
> +++
[...]
> +void board_fit_image_post_process(void **p_image, size_t *p_size) {
> + if (socfpga_vendor_authentication(p_image, p_size))
> + hang();
> +}
> +
> +void board_prep_linux(bootm_headers_t *images) {
> + if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
> + if
> (!IS_ENABLED(CONFIG_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
> + /*
> + * Ensure the OS is always booted from FIT and with
> + * VAB signed certificate
> + */
> + if (!images->fit_uname_cfg) {
> + printf("Please use FIT with VAB signed
> images!\n");
> + hang();
> + }
> +
> + env_set_hex("fdt_addr", (ulong)images->ft_addr);
> + debug("images->ft_addr = 0x%08lx\n",
> (ulong)images->ft_addr);
> + }
> +
> + if (IS_ENABLED(CONFIG_CADENCE_QSPI)) {
> + if (env_get("linux_qspi_enable"))
> +
> run_command(env_get("linux_qspi_enable"), 0);
> + }
> + }
> +}
Move board_fit_image_post_process() and board_prep_linux() outside of this
file, can be in a new file.
These 2 functions should be common, and can be used without VAB is enabled.
Regards
Ley Foon
RE: [v2] Makefile: socfpga: Add target to generate hex output for combined spl and dtb
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, February 24, 2021 9:54 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v2] Makefile: socfpga: Add target to generate hex output for
> combined spl and dtb
>
> From: Dalon Westergreen
>
> Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel SOCFPGA
> SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex" is hex formatted
> spl with and offset of CONFIG_SPL_TEXT_BASE. It combines the spl image
> and dtb.
> "u-boot-spl-dtb.hex" is needed to generate the final configuration bitstream
> for Intel SOCFPGA SOC64 devices.
>
> Signed-off-by: Dalon Westergreen
> Signed-off-by: Siew Chin Lim
>
> ---
> v2: Update commit message
> ---
> ---
> Makefile | 11 ++-
> include/configs/socfpga_soc64_common.h | 2 +-
> scripts/Makefile.spl | 8
> 3 files changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index 4da46dea39..f1adc9aa23 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1263,11 +1263,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
> $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
> $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg
> -R .resetvec)
>
> -OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
> -
> -spl/u-boot-spl.hex: spl/u-boot-spl FORCE
> - $(call if_changed,objcopy)
> -
> binary_size_check: u-boot-nodtb.bin FORCE
> @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
> map_size=$(shell cat u-boot.map | \
> @@ -1935,6 +1930,12 @@ spl/u-boot-spl.bin: spl/u-boot-spl
> @:
> $(SPL_SIZE_CHECK)
>
> +spl/u-boot-spl-dtb.bin: spl/u-boot-spl
> + @:
> +
> +spl/u-boot-spl-dtb.hex: spl/u-boot-spl
> + @:
> +
> spl/u-boot-spl: tools prepare \
> $(if
> $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATD
> ATA),dts/dt.dtb) \
> $(if
> $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATD
> ATA),dts/dt.dtb)
> diff --git a/include/configs/socfpga_soc64_common.h
> b/include/configs/socfpga_soc64_common.h
> index fdcd7d3e9a..1af359466c 100644
> --- a/include/configs/socfpga_soc64_common.h
> +++ b/include/configs/socfpga_soc64_common.h
> @@ -200,7 +200,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
> * 0x8000_ .. End of SDRAM_1 (assume 2GB)
> *
> */
> -#define CONFIG_SPL_TARGET"spl/u-boot-spl.hex"
> +#define CONFIG_SPL_TARGET"spl/u-boot-spl-dtb.hex"
> #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
> #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
> #define CONFIG_SPL_BSS_MAX_SIZE 0x10/* 1 MB */
> diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index
> ea4e045769..625e06d0d9 100644
> --- a/scripts/Makefile.spl
> +++ b/scripts/Makefile.spl
> @@ -229,6 +229,9 @@ ifneq
> ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA
> 10),)
> INPUTS-y += $(obj)/$(SPL_BIN).sfp
> endif
>
> +INPUTS-$(CONFIG_TARGET_SOCFPGA_STRATIX10)+= $(obj)/u-boot-spl-
> dtb.hex
> +INPUTS-$(CONFIG_TARGET_SOCFPGA_AGILEX) += $(obj)/u-
> boot-spl-dtb.hex
Can use CONFIG_TARGET_SOCFPGA_SOC64.
Regards
Ley Foon
RE: [v2 2/6] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Monday, January 18, 2021 4:03 PM > To: Tan, Ley Foon ; u-boot@lists.denx.de > Cc: Marek Vasut ; See, Chin Liang > ; Simon Goldschmidt > ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai > Subject: RE: [v2 2/6] arm: socfpga: soc64: Support Vendor Authorized Boot > (VAB) > > Hi Ley Foon, > > > -Original Message- > > From: Tan, Ley Foon > > Sent: Monday, January 18, 2021 3:29 PM > > To: Lim, Elly Siew Chin ; > > u-boot@lists.denx.de > > Cc: Marek Vasut ; See, Chin Liang > > ; Simon Goldschmidt > > ; Chee, Tien Fong > > ; Westergreen, Dalon > > ; Simon Glass ; Gan, > > Yau Wai > > Subject: RE: [v2 2/6] arm: socfpga: soc64: Support Vendor Authorized > > Boot > > (VAB) > > > > > > > > > -Original Message- > > > From: Lim, Elly Siew Chin > > > Sent: Thursday, January 7, 2021 6:04 PM > > > To: u-boot@lists.denx.de > > > Cc: Marek Vasut ; Tan, Ley Foon > > > ; See, Chin Liang > > > ; Simon Goldschmidt > > > ; Chee, Tien Fong > > > ; Westergreen, Dalon > > > ; Simon Glass ; Gan, > > > Yau Wai ; Lim, Elly Siew Chin > > > > > > Subject: [v2 2/6] arm: socfpga: soc64: Support Vendor Authorized > > > Boot > > > (VAB) > > > > > > Vendor Authorized Boot is a security feature for authenticating the > > > images such as U-Boot, ARM trusted Firmware, Linux kernel, device > > > tree blob and etc loaded from FIT. After those images are loaded > > > from FIT, the VAB certificate and signature block appended at the > > > end of each image are sent to Secure Device Manager (SDM) for > authentication. > > > U-Boot will validate the > > > SHA384 of the image against the SHA384 hash stored in the VAB > > > certificate before sending the image to SDM for authentication. > > > > > > Signed-off-by: Siew Chin Lim > > > > > > --- > > > v2 > > > --- > > > - Renamed SECURE_VAB_AUTH* to SOCFPGA_SECURE_VAB_AUTH* > > > - Changes in secure_vab.c > > > - Changed to use SZ_1K for 1024 > > > - Updated comment in secure_vab.c of "... the certificate for T" > > > - The code will report error before end of the function if reach > > > maximum retry. > > > - In board_prep_linux function, only execute linux_qspi_enable > > > command if it exists in enviroment variable. It is optional. > > > --- > > > arch/arm/mach-socfpga/Kconfig| 15 ++ > > > arch/arm/mach-socfpga/Makefile | 2 + > > > arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 + > > > arch/arm/mach-socfpga/include/mach/secure_vab.h | 63 > > > arch/arm/mach-socfpga/secure_vab.c | 193 > > > +++ > > > common/Kconfig.boot | 2 +- > > > 6 files changed, 275 insertions(+), 1 deletion(-) create mode > > > 100644 arch/arm/mach-socfpga/include/mach/secure_vab.h > > > create mode 100644 arch/arm/mach-socfpga/secure_vab.c > > > > > > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach- > > > socfpga/Kconfig index 9b1abdaabd..0c35406232 100644 > > > --- a/arch/arm/mach-socfpga/Kconfig > > > +++ b/arch/arm/mach-socfpga/Kconfig > > > @@ -6,6 +6,21 @@ config ERR_PTR_OFFSET config NR_DRAM_BANKS > > > default 1 > > > > > > +config SOCFPGA_SECURE_VAB_AUTH > > > + bool "Enable boot image authentication with Secure Device > > > Manager" > > > + depends on TARGET_SOCFPGA_AGILEX > > > + select FIT_IMAGE_POST_PROCESS > > > + select SHA384 > > > + select SHA512_ALGO > > > + select SPL_FIT_IMAGE_POST_PROCESS > > > + help > > > + All images loaded from FIT will be authenticated by Secure Device > > > + Manager. > > > + > > > +config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE > > > + bool "Allow non-FIT VAB signed images" > > > + depends on SOCFPGA_SECURE_VAB_AUTH > > > + > > > config SPL_SIZE_LIMIT > > > default 0x1 if TARGET_SOCFPGA_GEN5 > > > > > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach- > > > socfpga/Makefile index 82b681d870..1f1e21766d 100644 > > > --- a/arch/arm/mach-socfpga/Makefile > > > +++ b/arch/arm/mach-socfpga/Makefile >
RE: [v2 6/6] configs: socfpga: Add defconfig for Agilex with VAB support
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Monday, January 18, 2021 4:07 PM
> To: Tan, Ley Foon ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject: RE: [v2 6/6] configs: socfpga: Add defconfig for Agilex with VAB
> support
>
> Hi Ley Foon,
>
> > -Original Message-
> > From: Tan, Ley Foon
> > Sent: Monday, January 18, 2021 3:34 PM
> > To: Lim, Elly Siew Chin ;
> > u-boot@lists.denx.de
> > Cc: Marek Vasut ; See, Chin Liang
> > ; Simon Goldschmidt
> > ; Chee, Tien Fong
> > ; Westergreen, Dalon
> > ; Simon Glass ; Gan,
> > Yau Wai
> > Subject: RE: [v2 6/6] configs: socfpga: Add defconfig for Agilex with
> > VAB support
> >
> >
> >
> > > -Original Message-----
> > > From: Lim, Elly Siew Chin
> > > Sent: Thursday, January 7, 2021 6:04 PM
> > > To: u-boot@lists.denx.de
> > > Cc: Marek Vasut ; Tan, Ley Foon
> > > ; See, Chin Liang
> > > ; Simon Goldschmidt
> > > ; Chee, Tien Fong
> > > ; Westergreen, Dalon
> > > ; Simon Glass ; Gan,
> > > Yau Wai ; Lim, Elly Siew Chin
> > >
> > > Subject: [v2 6/6] configs: socfpga: Add defconfig for Agilex with
> > > VAB support
> > >
> > > Booting Agilex with Vendor Authorized Boot.
> > >
> > > Signed-off-by: Siew Chin Lim
> > >
> > > ---
> > > v2
> > > ---
> > > - Renamed CONFIG_SECURE_VAB_AUTH to
> > > CONFIG_SOCFPGA_SECURE_VAB_AUTH
> > > - Add BOOTCOMMAND macro in defconfig
> > > ---
> > > .../{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig} |
> 5
> > > +++--
> > > 1 file changed, 3 insertions(+), 2 deletions(-) copy
> > > configs/{socfpga_agilex_atf_defconfig =>
> > > socfpga_agilex_vab_defconfig}
> > > (92%)
> > >
> > > diff --git a/configs/socfpga_agilex_atf_defconfig
> > > b/configs/socfpga_agilex_vab_defconfig
> > > similarity index 92%
> > > copy from configs/socfpga_agilex_atf_defconfig
> > > copy to configs/socfpga_agilex_vab_defconfig
> > > index 704a9d56b9..1e28efea5e 100644
> > > --- a/configs/socfpga_agilex_atf_defconfig
> > > +++ b/configs/socfpga_agilex_vab_defconfig
> > > @@ -1,5 +1,4 @@
> > > CONFIG_ARM=y
> > > -CONFIG_ARM_SMCCC=y
> > > CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
> > > CONFIG_ARCH_SOCFPGA=y
> > > CONFIG_SYS_TEXT_BASE=0x20
> > > @@ -8,6 +7,7 @@ CONFIG_ENV_SIZE=0x1000
> > > CONFIG_ENV_OFFSET=0x200
> > > CONFIG_DM_GPIO=y
> > > CONFIG_NR_DRAM_BANKS=2
> > > +CONFIG_SOCFPGA_SECURE_VAB_AUTH=y
> > > CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
> > > CONFIG_IDENT_STRING="socfpga_agilex"
> > > CONFIG_SPL_FS_FAT=y
> > > @@ -15,12 +15,13 @@ CONFIG_SPL_TEXT_BASE=0xFFE0
> CONFIG_FIT=y
> > > CONFIG_SPL_LOAD_FIT=y
> > > CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
> > > +# CONFIG_LEGACY_IMAGE_FORMAT is not set
> > > # CONFIG_USE_SPL_FIT_GENERATOR is not set
> > > CONFIG_BOOTDELAY=5
> > > CONFIG_USE_BOOTARGS=y
> > > CONFIG_BOOTARGS="earlycon"
> > > CONFIG_USE_BOOTCOMMAND=y
> > > -CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run
> > > linux_qspi_enable; run mmcfitboot"
> > > +CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run
> mmcfitboot"
> >
> > Don't need "run linux_qspi_enable"?
>
> In VAB flow, " linux_qspi_enable" will be handled in board_prep_linux
> function.
>
> +#ifdef CONFIG_CADENCE_QSPI
> + if (env_get("linux_qspi_enable"))
> + run_command(env_get("linux_qspi_enable"), 0); #endif
>
Okay.
Regards
Ley Foon
RE: [v2 6/6] configs: socfpga: Add defconfig for Agilex with VAB support
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Thursday, January 7, 2021 6:04 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v2 6/6] configs: socfpga: Add defconfig for Agilex with VAB support
>
> Booting Agilex with Vendor Authorized Boot.
>
> Signed-off-by: Siew Chin Lim
>
> ---
> v2
> ---
> - Renamed CONFIG_SECURE_VAB_AUTH to
> CONFIG_SOCFPGA_SECURE_VAB_AUTH
> - Add BOOTCOMMAND macro in defconfig
> ---
> .../{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig} | 5
> +++--
> 1 file changed, 3 insertions(+), 2 deletions(-) copy
> configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}
> (92%)
>
> diff --git a/configs/socfpga_agilex_atf_defconfig
> b/configs/socfpga_agilex_vab_defconfig
> similarity index 92%
> copy from configs/socfpga_agilex_atf_defconfig
> copy to configs/socfpga_agilex_vab_defconfig
> index 704a9d56b9..1e28efea5e 100644
> --- a/configs/socfpga_agilex_atf_defconfig
> +++ b/configs/socfpga_agilex_vab_defconfig
> @@ -1,5 +1,4 @@
> CONFIG_ARM=y
> -CONFIG_ARM_SMCCC=y
> CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
> CONFIG_ARCH_SOCFPGA=y
> CONFIG_SYS_TEXT_BASE=0x20
> @@ -8,6 +7,7 @@ CONFIG_ENV_SIZE=0x1000
> CONFIG_ENV_OFFSET=0x200
> CONFIG_DM_GPIO=y
> CONFIG_NR_DRAM_BANKS=2
> +CONFIG_SOCFPGA_SECURE_VAB_AUTH=y
> CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
> CONFIG_IDENT_STRING="socfpga_agilex"
> CONFIG_SPL_FS_FAT=y
> @@ -15,12 +15,13 @@ CONFIG_SPL_TEXT_BASE=0xFFE0
> CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y
> CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
> +# CONFIG_LEGACY_IMAGE_FORMAT is not set
> # CONFIG_USE_SPL_FIT_GENERATOR is not set
> CONFIG_BOOTDELAY=5
> CONFIG_USE_BOOTARGS=y
> CONFIG_BOOTARGS="earlycon"
> CONFIG_USE_BOOTCOMMAND=y
> -CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run
> linux_qspi_enable; run mmcfitboot"
> +CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
Don't need "run linux_qspi_enable"?
Regards
Ley Foon
RE: [v2 5/6] configs: socfpga: soc64: Move CONFIG_BOOTCOMMAND to defconfig
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Thursday, January 7, 2021 6:04 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v2 5/6] configs: socfpga: soc64: Move CONFIG_BOOTCOMMAND > to defconfig > > CONFIG_BOOTCOMMAND have been moved to Kconfig.boot. This patch > move the CONFIG_BOOTCOMMAND macro from socfpga_soc64_common.h > to *_defconfig file for both Stratix 10 and Agilex. > > Signed-off-by: Siew Chin Lim > Reviewed-by: Ley Foon Tan
RE: [v2 2/6] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Thursday, January 7, 2021 6:04 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v2 2/6] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
>
> Vendor Authorized Boot is a security feature for authenticating the images
> such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and
> etc loaded from FIT. After those images are loaded from FIT, the VAB
> certificate and signature block appended at the end of each image are sent
> to Secure Device Manager (SDM) for authentication. U-Boot will validate the
> SHA384 of the image against the SHA384 hash stored in the VAB certificate
> before sending the image to SDM for authentication.
>
> Signed-off-by: Siew Chin Lim
>
> ---
> v2
> ---
> - Renamed SECURE_VAB_AUTH* to SOCFPGA_SECURE_VAB_AUTH*
> - Changes in secure_vab.c
> - Changed to use SZ_1K for 1024
> - Updated comment in secure_vab.c of "... the certificate for T"
> - The code will report error before end of the function if reach
> maximum retry.
> - In board_prep_linux function, only execute linux_qspi_enable
> command if it exists in enviroment variable. It is optional.
> ---
> arch/arm/mach-socfpga/Kconfig| 15 ++
> arch/arm/mach-socfpga/Makefile | 2 +
> arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 +
> arch/arm/mach-socfpga/include/mach/secure_vab.h | 63
> arch/arm/mach-socfpga/secure_vab.c | 193
> +++
> common/Kconfig.boot | 2 +-
> 6 files changed, 275 insertions(+), 1 deletion(-) create mode 100644
> arch/arm/mach-socfpga/include/mach/secure_vab.h
> create mode 100644 arch/arm/mach-socfpga/secure_vab.c
>
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-
> socfpga/Kconfig index 9b1abdaabd..0c35406232 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -6,6 +6,21 @@ config ERR_PTR_OFFSET
> config NR_DRAM_BANKS
> default 1
>
> +config SOCFPGA_SECURE_VAB_AUTH
> + bool "Enable boot image authentication with Secure Device
> Manager"
> + depends on TARGET_SOCFPGA_AGILEX
> + select FIT_IMAGE_POST_PROCESS
> + select SHA384
> + select SHA512_ALGO
> + select SPL_FIT_IMAGE_POST_PROCESS
> + help
> + All images loaded from FIT will be authenticated by Secure Device
> + Manager.
> +
> +config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
> + bool "Allow non-FIT VAB signed images"
> + depends on SOCFPGA_SECURE_VAB_AUTH
> +
> config SPL_SIZE_LIMIT
> default 0x1 if TARGET_SOCFPGA_GEN5
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> socfpga/Makefile index 82b681d870..1f1e21766d 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -4,6 +4,7 @@
> # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
> #
> # Copyright (C) 2012-2017 Altera Corporation
> +# Copyright (C) 2017-2020 Intel Corporation
>
> obj-y+= board.o
> obj-y+= clock_manager.o
> @@ -47,6 +48,7 @@ obj-y += mailbox_s10.o
> obj-y+= misc_s10.o
> obj-y+= mmu-arm64_s10.o
> obj-y+= reset_manager_s10.o
> +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)+= secure_vab.o
> obj-y+= system_manager_s10.o
> obj-y+= timer_s10.o
> obj-y+= wrap_pinmux_config_s10.o
> diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> index 4d783119ea..fbaf11597e 100644
> --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> @@ -118,6 +118,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
> #define MBOX_RECONFIG_MSEL 7
> #define MBOX_RECONFIG_DATA 8
> #define MBOX_RECONFIG_STATUS 9
> +#define MBOX_VAB_SRC_CERT11
> #define MBOX_QSPI_OPEN 50
> #define MBOX_QSPI_CLOSE 51
> #define MBOX_QSPI_DIRECT 59
> diff --git a/arch/arm/mach-socfpga/include/mach/secure_vab.h
> b/arch/arm/mach-socfpga/include/mach/secure_vab.h
> new file mode 100644
> index 00..42588588e8
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/secure_vab.h
> @@ -0,0 +1,63 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2020 Intel Corporation
> + *
> + */
> +
> +#ifndef _SECURE_VAB_H_
> +#def
RE: [v2 1/6] arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Thursday, January 7, 2021 6:04 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v2 1/6] arm: socfpga: Move Stratix10 and Agilex to use > TARGET_SOCFPGA_SOC64 > > Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. > > Signed-off-by: Siew Chin Lim > Reviewed-by: Ley Foon Tan Regards Ley Foon
[GIT PULL] SoCFPGA changes for v2021.04-rc1
Hi Tom Please pull the SoCFPGA changes for v2021.04. Regards Ley Foon The following changes since commit ab1a425524a79eeca61e7b67fdf382c7a499346f: Merge tag 'u-boot-stm32-20210113' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm (2021-01-13 15:00:53 -0500) are available in the Git repository at: https://github.com/lftan/u-boot.git 2021.04-rc for you to fetch changes up to 40551cf99c237f93d9e0e07b6dd8f31b3868a0f0: tools: socfpgaimage: update padding flow (2021-01-15 17:48:39 +0800) - Add ATF flow for SoC64 devices - Update socfpgaimage to support print header and update padding flow Chee Hong Ang (14): arm: socfpga: Add function for checking description from FIT image arm: socfpga: soc64: Load FIT image with ATF support arm: socfpga: soc64: Override 'lowlevel_init' to support ATF arm: socfpga: Disable "spin-table" method for booting Linux arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services mmc: dwmmc: socfpga: Add ATF support for MMC driver net: designware: socfpga: Add ATF support for MAC driver arm: socfpga: soc64: Add ATF support for Reset Manager driver arm: socfpga: soc64: Add ATF support for FPGA reconfig driver arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() arm: socfpga: soc64: SSBL shall not setup stack on OCRAM arm: socfpga: soc64: Skip handoff data access in SSBL configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support Ley Foon Tan (3): tools: socfpgaimage: Print image header information configs: socfpga: Add CONFIG_SPL_PAD_TO tools: socfpgaimage: update padding flow Siew Chin Lim (4): arm: socfpga: Add secure register access helper functions for SoC 64bits mmc: dwmmc: Change designware MMC 'clksel' callback function to return status arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support arm: socfpga: soc64: Enable FIT image generation using binman Makefile | 5 +- arch/arm/dts/socfpga_agilex-u-boot.dtsi| 4 +- arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 120 + arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 8 + arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 +- arch/arm/mach-socfpga/Kconfig | 4 +- arch/arm/mach-socfpga/Makefile | 5 + arch/arm/mach-socfpga/board.c | 12 +- .../mach-socfpga/include/mach/secure_reg_helper.h | 19 + arch/arm/mach-socfpga/include/mach/smc_api.h | 13 + arch/arm/mach-socfpga/lowlevel_init_soc64.S| 76 +++ arch/arm/mach-socfpga/mailbox_s10.c| 5 + arch/arm/mach-socfpga/reset_manager_s10.c | 13 + arch/arm/mach-socfpga/secure_reg_helper.c | 89 arch/arm/mach-socfpga/smc_api.c| 56 ++ arch/arm/mach-socfpga/wrap_pll_config_s10.c| 3 +- configs/socfpga_agilex_atf_defconfig | 72 +++ configs/socfpga_stratix10_atf_defconfig| 74 +++ drivers/fpga/intel_sdm_mb.c| 139 + drivers/mmc/ca_dw_mmc.c| 4 +- drivers/mmc/dw_mmc.c | 9 +- drivers/mmc/exynos_dw_mmc.c| 4 +- drivers/mmc/nexell_dw_mmc.c| 4 +- drivers/mmc/socfpga_dw_mmc.c | 18 +- drivers/net/dwmac_socfpga.c| 37 +- include/configs/socfpga_common.h | 2 + include/configs/socfpga_soc64_common.h | 24 +- include/dwmmc.h| 2 +- include/linux/intel-smc.h | 573 + tools/socfpgaimage.c | 86 +++- 30 files changed, 1447 insertions(+), 37 deletions(-) create mode 100644 arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_stratix10-u-boot.dtsi create mode 100644 arch/arm/mach-socfpga/include/mach/secure_reg_helper.h create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h create mode 100644 arch/arm/mach-socfpga/lowlevel_init_soc64.S create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c create mode 100644 arch/arm/mach-socfpga/smc_api.c create mode 100644 configs/socfpga_agilex_atf_defconfig create mode 100644 configs/socfpga_stratix10_atf_defconfig create mode 100644 include/linux/intel-smc.h
RE: [v7 07/18] arm: socfpga: Add secure register access helper functions for SoC 64bits
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Thursday, December 24, 2020 6:21 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v7 07/18] arm: socfpga: Add secure register access helper functions > for SoC 64bits > > These secure register access functions allow U-Boot proper running at EL2 > (non-secure) to access System Manager's secure registers by calling the ATF's > PSCI runtime services (EL3/secure). > > Signed-off-by: Siew Chin Lim > > --- > v5 > --- > Return error code instead of hang the system if fail to access the secure > register. > > --- > v6 > --- > Directly return 'ret' after SMC call in write and update function. > > --- > v7 > --- > Simplify the code to "return invoke_smc(..." in write and update function. > --- > arch/arm/mach-socfpga/Makefile | 1 + > .../mach-socfpga/include/mach/secure_reg_helper.h | 19 + > arch/arm/mach-socfpga/secure_reg_helper.c | 89 Reviewed-by: Ley Foon Tan Regards Ley Foon
RE: [v6 10/18] net: designware: socfpga: Add ATF support for MAC driver
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Wednesday, December 23, 2020 10:56 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Ang, Chee Hong > ; Lim, Elly Siew Chin > > Subject: [v6 10/18] net: designware: socfpga: Add ATF support for MAC > driver > > From: Chee Hong Ang > > In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided > by ATF to setup the PHY interface. > > Signed-off-by: Chee Hong Ang > Signed-off-by: Siew Chin Lim > > --- > v5 > --- > Call secure register access helper function to write the secure register. > Return error if fail to write the PHY related secure register. > > --- > v6 > --- > Clean up the code and use socfpga_secure_reg_update32 to update PHY > related secure registers. Reviewed-by: Ley Foon Tan
RE: [v6 07/18] arm: socfpga: Add secure register access helper functions for SoC 64bits
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, December 23, 2020 10:56 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v6 07/18] arm: socfpga: Add secure register access helper functions
> for SoC 64bits
>
> These secure register access functions allow U-Boot proper running at EL2
> (non-secure) to access System Manager's secure registers by calling the ATF's
> PSCI runtime services (EL3/secure).
>
> Signed-off-by: Siew Chin Lim
>
> ---
> v5
> ---
> Return error code instead of hang the system if fail to access the secure
> register.
>
> ---
> v6
> ---
> Directly return 'ret' after SMC call in write and update function.
> ---
> arch/arm/mach-socfpga/Makefile | 1 +
> .../mach-socfpga/include/mach/secure_reg_helper.h | 19 +
> arch/arm/mach-socfpga/secure_reg_helper.c | 91
> ++
> 3 files changed, 111 insertions(+)
> create mode 100644 arch/arm/mach-
> socfpga/include/mach/secure_reg_helper.h
> create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> socfpga/Makefile index 0b05283a7a..82b681d870 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -73,6 +73,7 @@ obj-y += firewall.o
> obj-y+= spl_agilex.o
> endif
> else
> +obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
> obj-$(CONFIG_SPL_ATF) += smc_api.o
> endif
>
> diff --git a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
> b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
> new file mode 100644
> index 00..d5a11122c7
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2020 Intel Corporation
> + *
> + */
> +
> +#ifndef _SECURE_REG_HELPER_H_
> +#define _SECURE_REG_HELPER_H_
> +
> +#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1 #define
> +SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2 #define
> +SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3 #define
> +SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2 4
> +
> +int socfpga_secure_reg_read32(u32 id, u32 *val); int
> +socfpga_secure_reg_write32(u32 id, u32 val); int
> +socfpga_secure_reg_update32(u32 id, u32 mask, u32 val);
> +
> +#endif /* _SECURE_REG_HELPER_H_ */
> diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c b/arch/arm/mach-
> socfpga/secure_reg_helper.c
> new file mode 100644
> index 00..816006cb5a
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/secure_reg_helper.c
> @@ -0,0 +1,91 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Intel Corporation
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include #include
> +#include #include #include
> +
> +
> +int socfpga_secure_convert_reg_id_to_addr(u32 id, phys_addr_t
> +*reg_addr) {
> + switch (id) {
> + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC:
> + *reg_addr = socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_SDMMC;
> + break;
> + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0:
> + *reg_addr = socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_EMAC0;
> + break;
> + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1:
> + *reg_addr = socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_EMAC1;
> + break;
> + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2:
> + *reg_addr = socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_EMAC2;
> + break;
> + default:
> + return -EADDRNOTAVAIL;
> + }
> + return 0;
> +}
> +
> +int socfpga_secure_reg_read32(u32 id, u32 *val) {
> + int ret;
> + u64 ret_arg;
> + u64 args[1];
> +
> + phys_addr_t reg_addr;
> + ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
> + if (ret)
> + return ret;
> +
> + args[0] = (u64)reg_addr;
> + ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
> + if (ret)
> + return ret;
> +
> + *val = (u32)ret_arg;
> +
> + return 0;
> +}
> +
> +int socfpga_secure_reg_write32(u32 id, u32 val) {
> + int ret;
> + u64 args[2];
> +
> + phys_addr_t reg_addr;
> + ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
> + if (ret)
> + return ret;
RE: [v5 17/18] arm: socfpga: soc64: Enable FIT image generation using binman
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, December 22, 2020 12:50 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v5 17/18] arm: socfpga: soc64: Enable FIT image generation using > binman > > Enable BINMAN when using Arm-Trusted-Firmware (ATF) to generate FIT > images. > > Signed-off-by: Siew Chin Lim > > --- > v4 > --- > Adjust BINMAN sequence in code, sorted by alphabetical order. > > v5 > --- > Revert all changes in Makefile for BINMAN: > (1) Remove target "fit-itb", directly use binman command to generate fit > (2) Do not skip binman for ARCH_SOCFPGA in default Makefile flow. > Use "blob-ext" entry instead of "blob" in binman node in device tree, > binman will report warning instead of error in default Makefile flow. > So, it wouldn't fail the default compilation process. > --- > arch/arm/mach-socfpga/Kconfig | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Ley Foon Tan Regards Ley Foon
RE: [v5 16/18] arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, December 22, 2020 12:50 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v5 16/18] arm: socfpga: dts: soc64: Add binman node of FIT image > with ATF support > > Add binman node to device tree to generate the FIT image for u-boot > (u-boot.itb) and OS kernel (kernel.itb). > > u-boot.itb contains arm trusted firmware (ATF), u-boot proper and u-boot > device tree for ATF u-boot flow. > > kernel.itb contains Linux Image and Linux device tree. > > Signed-off-by: Siew Chin Lim > > --- > v5 > --- > Change 'blob' to 'blob-ext' entry in binman dts node for all input files. > The input files (u-boot proper, Linux image files) that required to build FIT > images may not yet ready during u-boot compilation. > By using 'blob-ext', binman will report warning instead of error during u-boot > compilation when the input files doesn't exist. > It wouldn't fail the u-boot compilation. Then, user can prepare the input > files > later, and use binman command to generate the FIT images. > --- > arch/arm/dts/socfpga_agilex-u-boot.dtsi | 4 +- > arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 120 > +++ > arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 8 ++ > arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 +- > 4 files changed, 134 insertions(+), 2 deletions(-) create mode 100644 > arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi Reviewed-by: Ley Foon Tan Regards Ley Foon
RE: [v5 10/18] net: designware: socfpga: Add ATF support for MAC driver
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Tuesday, December 22, 2020 12:50 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Ang, Chee Hong
> ; Lim, Elly Siew Chin
>
> Subject: [v5 10/18] net: designware: socfpga: Add ATF support for MAC
> driver
>
> From: Chee Hong Ang
>
> In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided
> by ATF to setup the PHY interface.
>
> Signed-off-by: Chee Hong Ang
> Signed-off-by: Siew Chin Lim
>
> ---
> v5
> ---
> Call secure register access helper function to write the secure register.
> Return error if fail to write the PHY related secure register.
> ---
> drivers/net/dwmac_socfpga.c | 38 --
>
> 1 file changed, 32 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
> index e93561dffa..8efb88c8fb 100644
> --- a/drivers/net/dwmac_socfpga.c
> +++ b/drivers/net/dwmac_socfpga.c
> @@ -6,6 +6,8 @@
> */
>
> #include
> +#include #include
> +
> #include
> #include
> #include
> @@ -17,8 +19,6 @@
> #include
> #include
>
> -#include
> -
> struct dwmac_socfpga_platdata {
> struct dw_eth_pdata dw_eth_pdata;
> void*phy_intf;
> @@ -64,6 +64,33 @@ static int dwmac_socfpga_ofdata_to_platdata(struct
> udevice *dev)
> return designware_eth_ofdata_to_platdata(dev);
> }
>
> +static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg) {
> + struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
> + u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK <<
> pdata->reg_shift;
> +
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
> + u32 val = (readl(pdata->phy_intf) & ~modemask) |
> + (modereg << pdata->reg_shift);
> +
> + u32 index = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() -
> + SYSMGR_SOC64_EMAC0) >> 2;
> +
> + u32 id = SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 + index;
> +
> + int ret = socfpga_secure_reg_write32(id, val);
Use _update function, need read back and modify register. Similar to
clrsetbits_le32().
> + if (ret) {
> + dev_err(dev, "Failed to set PHY register via SMC call\n");
> + return ret;
> + }
> +#else
> + clrsetbits_le32(pdata->phy_intf, modemask,
> + modereg << pdata->reg_shift);
> +#endif
> +
> + return 0;
> +}
> +
RE: [v5 09/18] mmc: dwmmc: socfpga: Add ATF support for MMC driver
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, December 22, 2020 12:50 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Ang, Chee Hong > ; Lim, Elly Siew Chin > > Subject: [v5 09/18] mmc: dwmmc: socfpga: Add ATF support for MMC driver > > From: Chee Hong Ang > > In non-secure mode (EL2), MMC driver calls the SMC/PSCI services provided > by ATF to set SDMMC's DRVSEL and SMPLSEL. > > Signed-off-by: Chee Hong Ang > Signed-off-by: Siew Chin Lim > Reviewed-by: Ley Foon Tan Regards Ley Foon
RE: [v5 08/18] mmc: dwmmc: Change designware MMC 'clksel' callback function to return status
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, December 22, 2020 12:50 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v5 08/18] mmc: dwmmc: Change designware MMC 'clksel' callback > function to return status > > Change 'clksel' callback function to allow the code to return a status. > > This patch is a preparation for enabling Arm-Trusted-Firmware (ATF) in Intel > SoC FPGA. This patch does not change functionality. > > When using Arm-Trusted-Firmware (ATF) in Intel SoC FPGA, the MMC clock > related register is secure register which is required to be written via > SMC/PCSI call. It is possible that U-Boot fail to write the register if there > is > unexpected error between U-Boot and ATF. > As a result, there maybe signal integrity on MMC connection due to clock. So, > the code should reports error to user when 'clksel' fail. > > Signed-off-by: Siew Chin Lim > --- Reviewed-by: Ley Foon Tan Regards Ley Foon
RE: [v5 07/18] arm: socfpga: Add secure register access helper functions for SoC 64bits
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Tuesday, December 22, 2020 12:50 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v5 07/18] arm: socfpga: Add secure register access helper functions
> for SoC 64bits
>
> These secure register access functions allow U-Boot proper running at EL2
> (non-secure) to access System Manager's secure registers by calling the ATF's
> PSCI runtime services (EL3/secure).
>
> Signed-off-by: Siew Chin Lim
>
> ---
> v5
> ---
> Return error code instead of hang the system if fail to access the secure
> register.
> ---
> arch/arm/mach-socfpga/Makefile | 1 +
> .../mach-socfpga/include/mach/secure_reg_helper.h | 19 +
> arch/arm/mach-socfpga/secure_reg_helper.c | 97
> ++
> 3 files changed, 117 insertions(+)
> create mode 100644 arch/arm/mach-
> socfpga/include/mach/secure_reg_helper.h
> create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> socfpga/Makefile index 0b05283a7a..82b681d870 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -73,6 +73,7 @@ obj-y += firewall.o
> obj-y+= spl_agilex.o
> endif
> else
> +obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
> obj-$(CONFIG_SPL_ATF) += smc_api.o
> endif
>
> diff --git a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
> b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
> new file mode 100644
> index 00..d5a11122c7
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2020 Intel Corporation
> + *
> + */
> +
> +#ifndef _SECURE_REG_HELPER_H_
> +#define _SECURE_REG_HELPER_H_
> +
> +#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1 #define
> +SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2 #define
> +SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3 #define
> +SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2 4
> +
> +int socfpga_secure_reg_read32(u32 id, u32 *val); int
> +socfpga_secure_reg_write32(u32 id, u32 val); int
> +socfpga_secure_reg_update32(u32 id, u32 mask, u32 val);
> +
> +#endif /* _SECURE_REG_HELPER_H_ */
> diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c b/arch/arm/mach-
> socfpga/secure_reg_helper.c
> new file mode 100644
> index 00..d9be45cc97
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/secure_reg_helper.c
> @@ -0,0 +1,97 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Intel Corporation
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include #include
> +#include #include #include
> +
> +
> +int socfpga_secure_convert_reg_id_to_addr(u32 id, phys_addr_t
> +*reg_addr) {
> + switch (id) {
> + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC:
> + *reg_addr = socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_SDMMC;
> + break;
> + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0:
> + *reg_addr = socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_EMAC0;
> + break;
> + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1:
> + *reg_addr = socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_EMAC1;
> + break;
> + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2:
> + *reg_addr = socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_EMAC2;
> + break;
> + default:
> + return -EADDRNOTAVAIL;
> + }
> + return 0;
> +}
> +
> +int socfpga_secure_reg_read32(u32 id, u32 *val) {
> + int ret;
> + u64 ret_arg;
> + u64 args[1];
> +
> + phys_addr_t reg_addr;
> + ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
> + if (ret)
> + return ret;
> +
> + args[0] = (u64)reg_addr;
> + ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
> + if (ret)
> + return ret;
> +
> + *val = (u32)ret_arg;
> +
> + return 0;
> +}
> +
> +int socfpga_secure_reg_write32(u32 id, u32 val) {
> + int ret;
> + u64 args[2];
> +
> + phys_addr_t reg_addr;
> + ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
> + if (ret)
> + return ret;
> +
> + args[0] = (u64)reg_addr;
> + args[1] = val;
> + ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args,
RE: [v4 07/17] arm: socfpga: Add secure register access helper functions for SoC 64bits
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Friday, December 18, 2020 11:29 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v4 07/17] arm: socfpga: Add secure register access helper functions
> for SoC 64bits
>
> These secure register access functions allow U-Boot proper running at EL2
> (non-secure) to access System Manager's secure registers by calling the ATF's
> PSCI runtime services (EL3/secure).
>
> Signed-off-by: Siew Chin Lim
> ---
> arch/arm/mach-socfpga/Makefile | 1 +
> .../mach-socfpga/include/mach/secure_reg_helper.h | 19 ++
> arch/arm/mach-socfpga/secure_reg_helper.c | 73
> ++
> 3 files changed, 93 insertions(+)
> create mode 100644 arch/arm/mach-
> socfpga/include/mach/secure_reg_helper.h
> create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> socfpga/Makefile index 0b05283a7a..82b681d870 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -73,6 +73,7 @@ obj-y += firewall.o
> obj-y+= spl_agilex.o
> endif
> else
> +obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
> obj-$(CONFIG_SPL_ATF) += smc_api.o
> endif
>
> diff --git a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
> b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
> new file mode 100644
> index 00..f959e6f802
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2020 Intel Corporation
> + *
> + */
> +
> +#ifndef _SECURE_REG_HELPER_H_
> +#define _SECURE_REG_HELPER_H_
> +
> +#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1 #define
> +SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2 #define
> +SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3 #define
> +SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2 4
> +
> +u32 socfpga_secure_reg_read32(u32 id);
> +void socfpga_secure_reg_write32(u32 val, u32 id); void
> +socfpga_secure_reg_update32(u32 id, u32 mask, u32 val);
> +
> +#endif /* _SECURE_REG_HELPER_H_ */
> diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c b/arch/arm/mach-
> socfpga/secure_reg_helper.c
> new file mode 100644
> index 00..286f597617
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/secure_reg_helper.c
> @@ -0,0 +1,73 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Intel Corporation
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include #include
> +#include #include
> +
> +phys_addr_t socfpga_secure_convert_reg_id_to_addr(u32 id) {
> + switch (id) {
> + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC:
> + return socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_SDMMC;
> + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0:
> + return socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_EMAC0;
> + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1:
> + return socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_EMAC1;
> + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2:
> + return socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_EMAC2;
> + default:
> + hang();
Don't hang the system when error. Same for functions below.
> + }
> +}
> +
> +u32 socfpga_secure_reg_read32(u32 id)
> +{
> + int ret;
> + u64 ret_arg;
> + u64 args[1];
> + phys_addr_t reg_addr = socfpga_secure_convert_reg_id_to_addr(id);
> +
> + args[0] = (u64)reg_addr;
> + ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
> + if (ret)
> + hang();
> +
> + return ret_arg;
> +}
> +
> +void socfpga_secure_reg_write32(u32 val, u32 id) {
> + int ret;
> + u64 args[2];
> + phys_addr_t reg_addr = socfpga_secure_convert_reg_id_to_addr(id);
> +
> + args[0] = (u64)reg_addr;
> + args[1] = val;
> + ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
> + if (ret)
> + hang();
> +}
> +
> +void socfpga_secure_reg_update32(u32 id, u32 mask, u32 val) {
> + int ret;
> + u64 args[3];
> + phys_addr_t reg_addr = socfpga_secure_convert_reg_id_to_addr(id);
> +
> + args[0] = (u64)reg_addr;
> + args[1] = mask;
> + args[2] = val;
> + ret = invoke_smc(INTEL_SIP_SMC_REG_UPDATE, args, 3, NULL, 0);
> + if (ret)
> + hang();
> +}
> --
> 2.13.0
Regards
Ley Foon
RE: [v1 5/5] configs: socfpga: Add defconfig for Agilex and Diamond Mesa with VAB support
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Tuesday, November 10, 2020 3:05 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 5/5] configs: socfpga: Add defconfig for Agilex and Diamond
> Mesa with VAB support
>
> Booting Agilex and Diamond Mesa with Vendor Authorized Boot.
>
> Signed-off-by: Siew Chin Lim
> ---
> configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig} |
> 3 ++-
> configs/{socfpga_dm_atf_defconfig => socfpga_dm_vab_defconfig} | 3
> ++-
> 2 files changed, 4 insertions(+), 2 deletions(-) copy
> configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}
> (96%) copy configs/{socfpga_dm_atf_defconfig =>
> socfpga_dm_vab_defconfig} (96%)
>
> diff --git a/configs/socfpga_agilex_atf_defconfig
> b/configs/socfpga_agilex_vab_defconfig
> similarity index 96%
> copy from configs/socfpga_agilex_atf_defconfig
> copy to configs/socfpga_agilex_vab_defconfig
> index ad87a8098f..d437f49ce0 100644
> --- a/configs/socfpga_agilex_atf_defconfig
> +++ b/configs/socfpga_agilex_vab_defconfig
> @@ -1,5 +1,4 @@
> CONFIG_ARM=y
> -CONFIG_ARM_SMCCC=y
> CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
> CONFIG_ARCH_SOCFPGA=y
> CONFIG_SYS_TEXT_BASE=0x20
> @@ -8,6 +7,7 @@ CONFIG_ENV_SIZE=0x1000
> CONFIG_ENV_OFFSET=0x200
> CONFIG_DM_GPIO=y
> CONFIG_NR_DRAM_BANKS=2
> +CONFIG_SECURE_VAB_AUTH=y
> CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
> CONFIG_IDENT_STRING="socfpga_agilex"
> CONFIG_SPL_FS_FAT=y
> @@ -15,6 +15,7 @@ CONFIG_SPL_TEXT_BASE=0xFFE0 CONFIG_FIT=y
> CONFIG_SPL_LOAD_FIT=y
> CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
> +# CONFIG_LEGACY_IMAGE_FORMAT is not set
> # CONFIG_USE_SPL_FIT_GENERATOR is not set
> CONFIG_BOOTDELAY=5
> CONFIG_USE_BOOTARGS=y
> diff --git a/configs/socfpga_dm_atf_defconfig
> b/configs/socfpga_dm_vab_defconfig
> similarity index 96%
> copy from configs/socfpga_dm_atf_defconfig copy to
> configs/socfpga_dm_vab_defconfig index 975f20c752..97dc269057 100644
> --- a/configs/socfpga_dm_atf_defconfig
> +++ b/configs/socfpga_dm_vab_defconfig
> @@ -1,5 +1,4 @@
> CONFIG_ARM=y
> -CONFIG_ARM_SMCCC=y
> CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
> CONFIG_ARCH_SOCFPGA=y
> CONFIG_SYS_TEXT_BASE=0x20
> @@ -8,6 +7,7 @@ CONFIG_ENV_SIZE=0x1000
> CONFIG_ENV_OFFSET=0x200
> CONFIG_DM_GPIO=y
> CONFIG_NR_DRAM_BANKS=2
> +CONFIG_SECURE_VAB_AUTH=y
> CONFIG_TARGET_SOCFPGA_DM_SOCDK=y
> CONFIG_IDENT_STRING="socfpga_dm"
> CONFIG_SPL_FS_FAT=y
> @@ -15,6 +15,7 @@ CONFIG_SPL_TEXT_BASE=0xFFE0 CONFIG_FIT=y
> CONFIG_SPL_LOAD_FIT=y
> CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
> +# CONFIG_LEGACY_IMAGE_FORMAT is not set
> # CONFIG_USE_SPL_FIT_GENERATOR is not set
> CONFIG_BOOTDELAY=5
> CONFIG_USE_BOOTARGS=y
See comment in Patch [4/5], this patch need to be updated.
Regards
Ley Foon
RE: [v1 4/5] configs: socfpga: soc64: Remove 'run linux_qspi_enable' from bootcommand
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 3:05 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v1 4/5] configs: socfpga: soc64: Remove 'run linux_qspi_enable' > from bootcommand > > Remove 'run linux_qspi_enable' from bootcommand. When using FIT for OS > boot, 'run linux_qspi_enable' will be called 'board_prep_linux' > function. > > Signed-off-by: Siew Chin Lim > --- > include/configs/socfpga_soc64_common.h | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/include/configs/socfpga_soc64_common.h > b/include/configs/socfpga_soc64_common.h > index 194df5940d..911c3a91fd 100644 > --- a/include/configs/socfpga_soc64_common.h > +++ b/include/configs/socfpga_soc64_common.h > @@ -86,8 +86,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > > #ifdef CONFIG_FIT > #define CONFIG_BOOTFILE "kernel.itb" > -#define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload;run > linux_qspi_enable;" \ > -"run mmcfitboot" > +#define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload; run > mmcfitboot" > #else > #define CONFIG_BOOTFILE "Image" > #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run > linux_qspi_enable;" \ Latest U-boot moves CONFIG_BOOTCOMMAND to Kconfig, this needs move to _defconfig. Regards Ley Foon
RE: [v1 3/5] arm: socfpga: dts: soc64: Update filename in binman node of FIT image with VAB support
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 3:05 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v1 3/5] arm: socfpga: dts: soc64: Update filename in binman node > of FIT image with VAB support > > FIT image of Vendor Authentication Coot (VAB) contains signed images. > > Signed-off-by: Siew Chin Lim > --- > arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 22 > ++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi > b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi > index 2d4d56a6df..a23b45575a 100644 > --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi > +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi Reviewed-by: Ley Foon Tan
RE: [v1 2/5] arm: socfpga: cmd: Support 'vab' command
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 3:05 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v1 2/5] arm: socfpga: cmd: Support 'vab' command > > Support 'vab' command to perform vendor authentication. > > Command format: vab addr len > Authorize 'len' bytes starting at 'addr' via vendor public key > > Signed-off-by: Siew Chin Lim > --- > arch/arm/mach-socfpga/Makefile | 2 ++ > arch/arm/mach-socfpga/vab.c| 37 > + Reviewed-by: Ley Foon Tan
RE: [v1 1/5] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Tuesday, November 10, 2020 3:05 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [v1 1/5] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
>
> Vendor Authorized Boot is a security feature for authenticating the images
> such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and
> etc loaded from FIT. After those images are loaded from FIT, the VAB
> certificate and signature block appended at the end of each image are sent
> to Secure Device Manager (SDM) for authentication. U-Boot will validate the
> SHA384 of the image against the SHA384 hash stored in the VAB certificate
> before sending the image to SDM for authentication.
>
> Signed-off-by: Siew Chin Lim
> ---
> arch/arm/mach-socfpga/Kconfig| 15 ++
> arch/arm/mach-socfpga/Makefile | 2 +
> arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 +
> arch/arm/mach-socfpga/include/mach/secure_vab.h | 63
> arch/arm/mach-socfpga/secure_vab.c | 188
> +++
> common/Kconfig.boot | 2 +-
> 6 files changed, 270 insertions(+), 1 deletion(-) create mode 100644
> arch/arm/mach-socfpga/include/mach/secure_vab.h
> create mode 100644 arch/arm/mach-socfpga/secure_vab.c
>
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-
> socfpga/Kconfig index 5dee193b31..1dfe08ec86 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -6,6 +6,21 @@ config ERR_PTR_OFFSET
> config NR_DRAM_BANKS
> default 1
>
> +config SECURE_VAB_AUTH
Add prefix SOCFPGA_ for socfpga config, same for config below.
> + bool "Enable boot image authentication with Secure Device
> Manager"
> + depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_DM
> + select FIT_IMAGE_POST_PROCESS
> + select SHA512_ALGO
> + select SHA384
Sort alphanumeric order
> + select SPL_FIT_IMAGE_POST_PROCESS
> + help
> + All images loaded from FIT will be authenticated by Secure Device
> + Manager.
> +
> +config SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
> + bool "Allow non-FIT VAB signed images"
> + depends on SECURE_VAB_AUTH
> +
> config SPL_SIZE_LIMIT
> default 0x1 if TARGET_SOCFPGA_GEN5
>
[...]
> +/*
> + * struct fcs_hps_vab_certificate_header
> + * @cert_magic_num: Certificate Magic Word (0x25D04E7F)
> + * @cert_data_sz: size of this certificate header (0x80)
> + * Includes magic number all the way to the certificate
> + * signing keychain (excludes cert. signing keychain)
> + * @cert_ver: Certificate Version
> + * @cert_type: Certificate Type
> + * @data: VAB HPS Image Certificate data */ struct
> +fcs_hps_vab_certificate_header {
> + u32 cert_magic_num; /* offset 0 */
> + u32 cert_data_sz;
> + u32 cert_ver;
> + u32 cert_type;
> + struct fcs_hps_vab_certificate_data d; /* offset 0x10 */
> + /* keychain starts at offset 0x50 */
> +};
> +
> +#define VAB_CERT_HEADER_SIZE sizeof(struct
> fcs_hps_vab_certificate_header)
> +#define VAB_CERT_MAGIC_OFFSEToffsetof \
> + (struct fcs_hps_vab_certificate_header, d)
> +#define VAB_CERT_FIT_SHA384_OFFSET offsetof \
> + (struct fcs_hps_vab_certificate_data,
> \
> + fcs_sha384[0])
> +
> +int socfpga_vendor_authentication(void **p_image, size_t *p_size);
> +
> +#endif /* _SECURE_VAB_H_ */
> diff --git a/arch/arm/mach-socfpga/secure_vab.c b/arch/arm/mach-
> socfpga/secure_vab.c
> new file mode 100644
> index 00..3dd4de127b
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/secure_vab.c
> @@ -0,0 +1,188 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Intel Corporation
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
Sort alphanumeric order
> +
> +#define CHUNKSZ_PER_WD_RESET (256 * 1024)
SZ_1K for 1024
> + /* We need to use the 4 bytes before the certificate for T */
What is "T"?
> + backup_word = *(u32 *)mbox_data_addr;
> + /* T = 0 */
> + *(u32 *)mbox_data_addr = 0;
> +
> + do {
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
> + /* Inv
RE: [RESEND v2 22/22] arm: socfpga: dm: Enable Intel Diamond Mesa build
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 2:45 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [RESEND v2 22/22] arm: socfpga: dm: Enable Intel Diamond Mesa > build > > Add defconfig for Diamond Mesa to support both legacy boot flow and ATF > boot flow. > > Legacy boot: > SPL -> U-Boot proper -> OS (Linux) > > ATF boot flow: > SPL -> ATF(BL31) -> U-Boot proper -> OS (Linux) > > Signed-off-by: Siew Chin Lim > --- > arch/arm/mach-socfpga/Kconfig| 19 ++ > arch/arm/mach-socfpga/Makefile | 18 ++ > configs/socfpga_dm_atf_defconfig | 76 > > configs/socfpga_dm_defconfig | 69 > > 4 files changed, 182 insertions(+) > create mode 100644 configs/socfpga_dm_atf_defconfig create mode > 100644 configs/socfpga_dm_defconfig > > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach- > socfpga/Kconfig index 4d061a9d0d..5dee193b31 100644 > --- a/arch/arm/mach-socfpga/Kconfig > +++ b/arch/arm/mach-socfpga/Kconfig > @@ -66,6 +66,22 @@ config TARGET_SOCFPGA_CYCLONE5 > bool > select TARGET_SOCFPGA_GEN5 > > +config TARGET_SOCFPGA_DM > + bool > + select TARGET_SOCFPGA_SOC64 > + select ARMV8_MULTIENTRY > + select ARMV8_SET_SMPEN > + select CLK > + select FPGA_INTEL_SDM_MAILBOX > + select NCORE_CACHE > + select SPL_ALTERA_SDRAM > + select SPL_CLK if SPL > + select BINMAN Sort in alphanumerical order. Regards Ley Foon
RE: [RESEND v2 21/22] configs: dm: Add Diamond Mesa CONFIGs
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Tuesday, November 10, 2020 2:45 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [RESEND v2 21/22] configs: dm: Add Diamond Mesa CONFIGs
>
> Add CONFIGs for Diamond Mesa.
>
> Signed-off-by: Siew Chin Lim
> ---
> include/configs/socfpga_dm_socdk.h | 46
> ++
> 1 file changed, 46 insertions(+)
> create mode 100644 include/configs/socfpga_dm_socdk.h
>
> diff --git a/include/configs/socfpga_dm_socdk.h
> b/include/configs/socfpga_dm_socdk.h
> new file mode 100644
> index 00..f0082b8d1d
> --- /dev/null
> +++ b/include/configs/socfpga_dm_socdk.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2020 Intel Corporation
> + *
> + */
> +
> +#ifndef __CONFIG_SOCFGPA_DM_H__
> +#define __CONFIG_SOCFGPA_DM_H__
> +
> +#include
> +
> +#undef CONFIG_BOOTARGS
> +#define CONFIG_BOOTARGS "earlycon panic=-1 earlyprintk=ttyS0,4800"
> +
> +#undef CONFIG_EXTRA_ENV_SETTINGS
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
> + "bootfile=Image\0" \
> + "fdt_addr=110\0" \
> + "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
> + "mmcroot=/dev/mmcblk0p2\0" \
> + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
> + " root=${mmcroot} rw rootwait;" \
> + "booti ${loadaddr} - ${fdt_addr}\0" \
> + "mmcload=mmc rescan;" \
> + "load mmc 0:1 ${loadaddr} ${bootfile};" \
> + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
> + "mmcvabboot=setenv bootargs " CONFIG_BOOTARGS \
> + " root=${mmcroot} rw rootwait;" \
> + "bootm ${loadaddr}\0" \
> + "mmcvabload=mmc rescan;" \
> + "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
VAB related shouldn't in this patchset?
Regards
Ley Foon
RE: [RESEND v2 20/22] arm: dts: dm: Add base dtsi and devkit dts for Diamond Mesa
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Tuesday, November 10, 2020 2:45 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [RESEND v2 20/22] arm: dts: dm: Add base dtsi and devkit dts for
> Diamond Mesa
>
> Add device tree for Diamond Mesa.
>
> Signed-off-by: Siew Chin Lim
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/socfpga_dm-u-boot.dtsi | 102 +
> arch/arm/dts/socfpga_dm.dtsi | 640
> ++
> arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi | 50 +++
> arch/arm/dts/socfpga_dm_socdk.dts | 144 +++
> 5 files changed, 937 insertions(+)
> create mode 100644 arch/arm/dts/socfpga_dm-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_dm.dtsi create mode 100644
> arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_dm_socdk.dts
>
> diff --git a/arch/arm/dts/socfpga_dm.dtsi b/arch/arm/dts/socfpga_dm.dtsi
Make sure sync latest from Linux.
[...]
> + };
> + gmac0: ethernet@ff80 {
Add new line before gmac0.
[...]
> diff --git a/arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi
> b/arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi
> new file mode 100644
> index 00..9dbcaf2eb0
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * U-Boot additions
> + *
> + * Copyright (C) 2020 Intel Corporation */
> +
> +#include "socfpga_dm-u-boot.dtsi"
> +
> +/{
> + aliases {
> + spi0 = &qspi;
> + i2c0 = &i2c1;
> + };
> +
> + memory {
> + /* 8GB */
> + reg = <0 0x 0 0x8000>,
> + <2 0x8000 1 0x8000>;
> + };
> +};
> +
> +&flash0 {
> + compatible = "jedec,spi-nor";
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + u-boot,dm-pre-reloc;
> +};
> +
> +&i2c1 {
> + status = "okay";
> +};
> +
> +&nand {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&mmc {
> + drvsel = <3>;
> + smplsel = <0>;
> + u-boot,dm-pre-reloc;
> +};
> +
> +&qspi {
> + status = "okay";
> +};
socfpga_dm_socdk.dts already set this.
Regards
Ley Foon
RE: [RESEND v2 19/22] board: intel: dm: Add socdk board support for Diamond Mesa
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 2:45 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [RESEND v2 19/22] board: intel: dm: Add socdk board support for > Diamond Mesa > > Add Diamond Mesa SoC devkit board. > > Signed-off-by: Siew Chin Lim > --- > board/intel/dm-socdk/MAINTAINERS | 7 +++ > board/intel/dm-socdk/Makefile| 7 +++ > board/intel/dm-socdk/socfpga.c | 7 +++ > 3 files changed, 21 insertions(+) > create mode 100644 board/intel/dm-socdk/MAINTAINERS create mode > 100644 board/intel/dm-socdk/Makefile create mode 100644 > board/intel/dm-socdk/socfpga.c > Reviewed-by: Ley Foon Tan
RE: [RESEND v2 18/22] arm: socfpga: dm: Add SPL for Diamond Mesa
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 2:45 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [RESEND v2 18/22] arm: socfpga: dm: Add SPL for Diamond Mesa > > Signed-off-by: Siew Chin Lim > --- > arch/arm/mach-socfpga/spl_dm.c | 93 > ++ > 1 file changed, 93 insertions(+) > create mode 100644 arch/arm/mach-socfpga/spl_dm.c > > diff --git a/arch/arm/mach-socfpga/spl_dm.c b/arch/arm/mach- > socfpga/spl_dm.c new file mode 100644 index 00..ef664f4426 > --- /dev/null > +++ b/arch/arm/mach-socfpga/spl_dm.c > @@ -0,0 +1,93 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2020 Intel Corporation > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include Sort alphanumerical order. Regards Ley Foon
RE: [RESEND v2 17/22] arm: socfpga: Move Stratix10 and Agilex SPL common code
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 2:45 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [RESEND v2 17/22] arm: socfpga: Move Stratix10 and Agilex SPL > common code > > Move Stratix10 and Agilex SPL common code to spl_soc64.c > > Signed-off-by: Siew Chin Lim > --- > arch/arm/mach-socfpga/Makefile | 2 ++ > arch/arm/mach-socfpga/spl_agilex.c | 16 > arch/arm/mach-socfpga/spl_s10.c| 17 - > arch/arm/mach-socfpga/spl_soc64.c | 26 ++ > 4 files changed, 28 insertions(+), 33 deletions(-) create mode 100644 > arch/arm/mach-socfpga/spl_soc64.c > Reviewed-by: Ley Foon Tan
RE: [RESEND v2 16/22] ddr: altera: dm: Add SDRAM driver for Diamond Mesa
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 2:45 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [RESEND v2 16/22] ddr: altera: dm: Add SDRAM driver for Diamond > Mesa > > The DDR subsystem in Diamond Mesa is consisted of controller, PHY, > memory reset manager and memory clock manager. > > Configuration settings of controller, PHY and memory reset manager is > come from DDR handoff data in bitstream, which contain the register base > addresses and user settings from Quartus. > > Configuration settings of memory clock manager is come from the HPS > handoff data in bitstream, however the register base address is defined in > device tree. > > The calibration is fully done in HPS, which requires IMEM and DMEM binaries > loading to PHY SRAM for running this calibration, both IMEM and DMEM > binaries are also part of bitstream, this bitstream would be loaded to OCRAM > by SDM, and configured by DDR driver. > > Signed-off-by: Siew Chin Lim > Signed-off-by: Tien Fong Chee > --- > arch/arm/mach-socfpga/include/mach/firewall.h |1 + > .../include/mach/system_manager_soc64.h|4 + > drivers/ddr/altera/Makefile|1 + > drivers/ddr/altera/sdram_dm.c | 1294 > > drivers/ddr/altera/sdram_soc64.c |6 + > 5 files changed, 1306 insertions(+) > create mode 100644 drivers/ddr/altera/sdram_dm.c > [...] > > /* Firewall MPFE SCR Registers */ > #define FW_MPFE_SCR_HMC 0x00 > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > index 1e2289e5f8..4fc1a158b7 100644 > --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > @@ -94,6 +94,10 @@ void populate_sysmgr_pinmux(void); > * storing qspi ref clock(kHz) > */ > #define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK > GENMASK(27, 0) > +#define SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK > BIT(31) > +#define SYSMGR_SCRATCH_REG_0_DDR_SHA_MASKBIT(30) > +#define SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | > BIT(28)) Change the order, from bit-28 to 31. > +#define SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT28 > > #define SYSMGR_SDMMC > SYSMGR_SOC64_SDMMC > [...] > +#define TIMEOUT_200MS 200 > +#define TIMEOUT_5000MS5000 > + > +/* DDR4 umctl2 */ > +#define DDR4_STAT_OFFSET 0x4 Change to 0x04. > +#define DDR4_STAT_SELFREF_TYPE (BIT(5) | BIT(4)) > +#define DDR4_STAT_SELFREF_TYPE_SHIFT 4 > +#define DDR4_STAT_OPERATING_MODE (BIT(2) | BIT(1) | BIT(0)) > + > +#define DDR4_MRCTRL0_OFFSET 0x10 > +#define DDR4_MRCTRL0_MR_TYPE BIT(0) > +#define DDR4_MRCTRL0_MPR_EN BIT(1) > +#define DDR4_MRCTRL0_MR_RANK (BIT(5) | BIT(4)) > +#define DDR4_MRCTRL0_MR_RANK_SHIFT 4 > +#define DDR4_MRCTRL0_MR_ADDR (BIT(15) | BIT(14) | BIT(13) | > BIT(12)) > +#define DDR4_MRCTRL0_MR_ADDR_SHIFT 12 > +#define DDR4_MRCTRL0_MR_WR BIT(31) > + > +#define DDR4_MRCTRL1_OFFSET 0x14 > +#define DDR4_MRCTRL1_MR_DATA 0x3 Follow other drivers use small letter for hex value. Check all in this file. > + > +#define DDR4_MRSTAT_OFFSET 0x18 > +#define DDR4_MRSTAT_MR_WR_BUSY BIT(0) > + > +#define DDR4_MRCTRL2_OFFSET 0x1C > + > +#define DDR4_PWRCTL_OFFSET 0x30 > +#define DDR4_PWRCTL_SELFREF_EN BIT(0) > +#define DDR4_PWRCTL_POWERDOWN_EN BIT(1) > +#define DDR4_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) > +#define DDR4_PWRCTL_SELFREF_SW BIT(5) > + > +#define DDR4_PWRTMG_OFFSET 0x34 > +#define DDR4_HWLPCTL_OFFSET 0x38 > +#define DDR4_RFSHCTL0_OFFSET 0x50 > +#define DDR4_RFSHCTL1_OFFSET 0x54 > + > +#define DDR4_RFSHCTL3_OFFSET 0x60 > +#define DDR4_RFSHCTL3_DIS_AUTO_REFRESH BIT(0) > +#define DDR4_RFSHCTL3_REFRESH_MODE (BIT(6) | BIT(5) | > BIT(4)) > +#define DDR4_RFSHCTL3_REFRESH_MODE_SHIFT 4 > + > +#define DDR4_ECCCFG0_OFFSET 0x70 > +#define DDR4_ECC_MODE(BIT(2) | BIT(1) | BIT(0)) > +#define DDR4_DIS_SCRUB BIT(4) > + > +#define DDR4_CRCPARCTL1_OFFSET
RE: [RESEND v2 15/22] arm: socfpga: dm: Add clock manager for Diamond Mesa
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 2:45 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [RESEND v2 15/22] arm: socfpga: dm: Add clock manager for > Diamond Mesa > > Add clock manager for Diamond Mesa. > > Signed-off-by: Siew Chin Lim > --- > arch/arm/mach-socfpga/clock_manager_dm.c | 79 > ++ > arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 + > .../mach-socfpga/include/mach/clock_manager_dm.h | 14 > 3 files changed, 95 insertions(+) > create mode 100644 arch/arm/mach-socfpga/clock_manager_dm.c > create mode 100644 arch/arm/mach- > socfpga/include/mach/clock_manager_dm.h > > diff --git a/arch/arm/mach-socfpga/clock_manager_dm.c > b/arch/arm/mach-socfpga/clock_manager_dm.c > new file mode 100644 > index 00..cdf096cd8b > --- /dev/null > +++ b/arch/arm/mach-socfpga/clock_manager_dm.c > @@ -0,0 +1,79 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2020 Intel Corporation > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include Try to sort alphanumerical order. [...] > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h > b/arch/arm/mach-socfpga/include/mach/clock_manager.h > index 0f0cb230fa..a164f47bda 100644 > --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h > @@ -26,6 +26,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > #include #elif > defined(CONFIG_TARGET_SOCFPGA_AGILEX) > #include > +#elif defined(CONFIG_TARGET_SOCFPGA_DM) #include > + > #endif > > #endif /* _CLOCK_MANAGER_H_ */ > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h > b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h > new file mode 100644 > index 00..a355fda692 > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h > @@ -0,0 +1,14 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (C) 2020 Intel Corporation */ > + > +#ifndef _CLOCK_MANAGER_DM_ > +#define _CLOCK_MANAGER_DM_ > + > +unsigned long cm_get_mpu_clk_hz(void); This can move to clock_manager.h, since all devices have this. Regards Ley Foon
RE: [RESEND v2 14/22] arm: socfpga: Changed to store QSPI reference clock in kHz
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Tuesday, November 10, 2020 2:45 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [RESEND v2 14/22] arm: socfpga: Changed to store QSPI reference
> clock in kHz
>
> Changed to store QSPI reference clock in kHz instead of Hz in boot scratch
> cold0 register for Stratix10 and Agilex.
>
> This patch is in preparation for Diamond Mesa SDRAM driver support.
> Reserved 4 bits for Diamond Mesa SDRAM driver, and there will be 28 bits to
> store QSPI reference clock.
> Due to limited bits, QSPI reference clock frequency is converted to kHz from
> Hz.
>
> Signed-off-by: Siew Chin Lim
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/mach-socfpga/clock_manager.c | 5 ++--
> .../include/mach/system_manager_soc64.h| 12 +-
> arch/arm/mach-socfpga/mailbox_s10.c| 28
> +++---
> 3 files changed, 39 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-
> socfpga/clock_manager.c
> index 2d0cc19f7a..8299d0956d 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -66,8 +66,9 @@ int set_cpu_clk_info(void) #if
> defined(CONFIG_TARGET_SOCFPGA_SOC64)
> unsigned int cm_get_qspi_controller_clk_hz(void)
> {
> - return readl(socfpga_get_sysmgr_addr() +
> - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> + return (readl(socfpga_get_sysmgr_addr() +
> + SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &
> + SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) * 1000;
> }
>
> #endif
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> index 1eb8e7a904..1e2289e5f8 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> @@ -42,7 +42,10 @@ void populate_sysmgr_pinmux(void);
> #define SYSMGR_SOC64_GPO 0xe4
> #define SYSMGR_SOC64_GPI 0xe8
> #define SYSMGR_SOC64_MPU 0xf0
> -/* store qspi ref clock */
> +/*
> + * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for
> +SOC 64-bit
> + * storing qspi ref clock(kHz)
Space after "(".
> + */
> #define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200
> /* store osc1 clock freq */
> #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204
> @@ -85,6 +88,13 @@ void populate_sysmgr_pinmux(void);
> #define SYSMGR_SOC64_HPS_OSC_CLK 0x1358
> #define SYSMGR_SOC64_IODELAY00x1400
>
> +/*
> + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0
> + * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for
> +SOC 64-bit
> + * storing qspi ref clock(kHz)
> + */
> +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK
> GENMASK(27, 0)
> +
> #define SYSMGR_SDMMC
> SYSMGR_SOC64_SDMMC
>
> #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
> diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-
> socfpga/mailbox_s10.c
> index 429444f069..2e43131c5d 100644
> --- a/arch/arm/mach-socfpga/mailbox_s10.c
> +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> @@ -359,7 +359,7 @@ int mbox_qspi_open(void) {
> int ret;
> u32 resp_buf[1];
> - u32 resp_buf_len;
> + u32 resp_buf_len, temp;
>
> ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN,
> MBOX_CMD_DIRECT,
> 0, NULL, 0, 0, NULL);
> @@ -384,8 +384,30 @@ int mbox_qspi_open(void)
> goto error;
>
> /* We are getting QSPI ref clock and set into sysmgr boot register */
> - printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
> - writel(resp_buf[0],
> + /*
> + * Only clock freq in kHz degree is accepted due to limited bits[27:0]
> + * is reserved for storing the QSPI clock freq into boot scratch cold0
> + * register
> + */
> + if (resp_buf[0] < 1000) {
> + ret = -EINVAL;
> + goto error;
> + } else {
> + resp_buf[0] /= 1000;
> + }
> +
> + printf("QSPI: Reference clock at %d kHz\n", resp_buf[0]);
> +
> + /*
> + * DDR retention bit, SHA comparison bit and reset type bits sharing
> the
> + * same scratch register in DM, ensure the content inside register is
> + * not overwritten by QSPI ref clock(kHz)
> + */
> + temp = readl(socfpga_get_sysmgr_addr() +
> + SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &
> + ~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);
> +
> + writel((resp_buf[0] &
Can help helper function to read and write boot scratch register.
Regards
Ley Foon
RE: [RESEND v2 13/22] arm: socfpga: Move Stratix10 and Agilex clock manager common code
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Tuesday, November 10, 2020 2:45 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [RESEND v2 13/22] arm: socfpga: Move Stratix10 and Agilex clock
> manager common code
>
> Move duplicated function cm_get_qspi_controller_clk_hz to
> clock_manager.c.
>
> Signed-off-by: Siew Chin Lim
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/mach-socfpga/clock_manager.c | 10 ++
> arch/arm/mach-socfpga/clock_manager_agilex.c | 6 --
> arch/arm/mach-socfpga/clock_manager_s10.c | 6 --
> arch/arm/mach-socfpga/include/mach/clock_manager.h | 4
> arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 -
> 5 files changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-
> socfpga/clock_manager.c
> index a4a97b6a0f..2d0cc19f7a 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -9,6 +9,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -62,6 +63,15 @@ int set_cpu_clk_info(void)
> return 0;
> }
>
> +#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
> +unsigned int cm_get_qspi_controller_clk_hz(void)
> +{
> + return readl(socfpga_get_sysmgr_addr() +
> + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); }
> +
> +#endif
> +
> #ifndef CONFIG_SPL_BUILD
> static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
>char *const argv[])
> diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
> b/arch/arm/mach-socfpga/clock_manager_agilex.c
> index 6188a8c3d2..86e00d7611 100644
> --- a/arch/arm/mach-socfpga/clock_manager_agilex.c
> +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
> @@ -64,12 +64,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
> return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
> }
>
> -u32 cm_get_qspi_controller_clk_hz(void)
> -{
> - return readl(socfpga_get_sysmgr_addr() +
> - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> -}
> -
> void cm_print_clock_quick_summary(void)
> {
> printf("MPU %10d kHz\n",
> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c
> b/arch/arm/mach-socfpga/clock_manager_s10.c
> index 431794e082..ef62c56ad9 100644
> --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> @@ -383,12 +383,6 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> return clock;
> }
>
> -unsigned int cm_get_qspi_controller_clk_hz(void)
> -{
> - return readl(socfpga_get_sysmgr_addr() +
> - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> -}
> -
> unsigned int cm_get_spi_controller_clk_hz(void)
> {
> u32 clock = cm_get_l3_main_clk_hz();
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> index 1f734bcd65..0f0cb230fa 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> @@ -12,6 +12,10 @@ phys_addr_t socfpga_get_clkmgr_addr(void); void
> cm_wait_for_lock(u32 mask); int cm_wait_for_fsm(void); void
> cm_print_clock_quick_summary(void);
> +
> +#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
> +unsigned int cm_get_qspi_controller_clk_hz(void);
> +#endif
> #endif
Cyclone 5 and Arria 10 also have this function.
This is also define in include/configs/*.h. Check where should add it.
Regards
Ley Foon
RE: [RESEND v2 12/22] drivers: clk: dm: Add memory clock driver for Diamond Mesa
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Tuesday, November 10, 2020 2:44 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [RESEND v2 12/22] drivers: clk: dm: Add memory clock driver for
> Diamond Mesa
>
> Add memory clock manager driver for Diamond Mesa. Provides clock
> initialization and enable functions.
>
> Signed-off-by: Siew Chin Lim
> ---
> drivers/clk/altera/Makefile | 2 +-
> drivers/clk/altera/clk-mem-dm.c | 135
>
> drivers/clk/altera/clk-mem-dm.h | 80
> 3 files changed, 216 insertions(+), 1 deletion(-) create mode 100644
> drivers/clk/altera/clk-mem-dm.c create mode 100644 drivers/clk/altera/clk-
> mem-dm.h
>
> diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index
> 08f16fd7cd..ad4ad5fb3d 100644
> --- a/drivers/clk/altera/Makefile
> +++ b/drivers/clk/altera/Makefile
> @@ -5,4 +5,4 @@
>
> obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
> obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
> -obj-$(CONFIG_TARGET_SOCFPGA_DM) += clk-dm.o
> +obj-$(CONFIG_TARGET_SOCFPGA_DM) += clk-dm.o clk-mem-dm.o
> diff --git a/drivers/clk/altera/clk-mem-dm.c b/drivers/clk/altera/clk-mem-
> dm.c new file mode 100644 index 00..827b8d3e95
> --- /dev/null
> +++ b/drivers/clk/altera/clk-mem-dm.c
> @@ -0,0 +1,135 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Intel Corporation */
> +
> +#include
> +#include
> +#include
> +#include "clk-mem-dm.h"
> +#include
> +#include #include #include
> + #include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct socfpga_mem_clk_platdata {
> + void __iomem *regs;
> +};
> +
> +void clk_mem_wait_for_lock(struct socfpga_mem_clk_platdata *plat, u32
> +mask) {
> + u32 inter_val;
> + u32 retry = 0;
> +
> + do {
> + inter_val = CM_REG_READL(plat, MEMCLKMGR_STAT) &
> mask;
> +
> + /* Wait for stable lock */
> + if (inter_val == mask)
> + retry++;
> + else
> + retry = 0;
> +
> + if (retry >= 10)
> + return;
> + } while (1);
> +}
This can use wait_for_bit_le32()?
> +
> +/*
> + * function to write the bypass register which requires a poll of the
> + * busy bit
> + */
> +void clk_mem_write_bypass_mempll(struct socfpga_mem_clk_platdata
> *plat,
> +u32 val) {
> + CM_REG_WRITEL(plat, val, MEMCLKMGR_MEMPLL_BYPASS); }
> +
> +/*
> + * Setup clocks while making no assumptions about previous state of the
> clocks.
> + */
> +static void clk_mem_basic_init(struct udevice *dev,
> +const struct cm_config * const cfg) {
> + struct socfpga_mem_clk_platdata *plat = dev_get_platdata(dev);
> +
> + if (!cfg)
> + return;
> +
> + /* Put PLLs in bypass */
> + clk_mem_write_bypass_mempll(plat,
> MEMCLKMGR_BYPASS_MEMPLL_ALL);
> +
> + /* Put PLLs in Reset */
> + CM_REG_SETBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
> +MEMCLKMGR_PLLCTRL_BYPASS_MASK);
> +
> + /* setup mem PLL */
> + CM_REG_WRITEL(plat, cfg->mem_memdiv,
> MEMCLKMGR_MEMPLL_MEMDIV);
> + CM_REG_WRITEL(plat, cfg->mem_pllglob,
> MEMCLKMGR_MEMPLL_PLLGLOB);
> + CM_REG_WRITEL(plat, cfg->mem_plldiv,
> MEMCLKMGR_MEMPLL_PLLDIV);
> + CM_REG_WRITEL(plat, cfg->mem_plloutdiv,
> MEMCLKMGR_MEMPLL_PLLOUTDIV);
> +
> + /* Take PLL out of reset and power up */
> + CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
> +MEMCLKMGR_PLLCTRL_BYPASS_MASK); }
> +
> +static int socfpga_mem_clk_enable(struct clk *clk) {
> + const struct cm_config *cm_default_cfg = cm_get_default_config();
> + struct socfpga_mem_clk_platdata *plat = dev_get_platdata(clk-
> >dev);
> +
> + clk_mem_basic_init(clk->dev, cm_default_cfg);
> +
> + clk_mem_wait_for_lock(plat,
> MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK);
> +
> + CM_REG_WRITEL(plat, CM_REG_READL(plat,
> MEMCLKMGR_MEMPLL_PLLGLOB) |
> + MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
> + MEMCLKMGR_MEMPLL_PLLGLOB);
> +
> + /* Take all PLLs out of bypass */
> + clk_mem_write_bypass_mempll(plat, 0);
> +
> + /* Clear the loss of lock bits (write 1 to clear) */
> + CM_REG_CLRBITS(plat, MEMCLKMGR_INTRCLR,
> +
RE: [RESEND v2 10/22] drivers: clk: dm: Add clock driver for Diamond Mesa
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Tuesday, November 10, 2020 2:44 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [RESEND v2 10/22] drivers: clk: dm: Add clock driver for Diamond
> Mesa
>
> Add clock manager driver for Diamond Mesa. Provides clock initialization and
> get_rate functions.
>
> Signed-off-by: Siew Chin Lim
> ---
> drivers/clk/altera/Makefile | 3 +-
> drivers/clk/altera/clk-dm.c | 504
> +++
> drivers/clk/altera/clk-dm.h | 213 +++
> include/dt-bindings/clock/dm-clock.h | 71 +
> 4 files changed, 790 insertions(+), 1 deletion(-) create mode 100644
> drivers/clk/altera/clk-dm.c create mode 100644 drivers/clk/altera/clk-dm.h
> create mode 100644 include/dt-bindings/clock/dm-clock.h
>
> diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index
> 96215ad5c4..08f16fd7cd 100644
> --- a/drivers/clk/altera/Makefile
> +++ b/drivers/clk/altera/Makefile
> @@ -1,7 +1,8 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
> -# Copyright (C) 2018 Marek Vasut
> +# Copyright (C) 2018-2020 Marek Vasut
> #
>
> obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
> obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
> +obj-$(CONFIG_TARGET_SOCFPGA_DM) += clk-dm.o
> diff --git a/drivers/clk/altera/clk-dm.c b/drivers/clk/altera/clk-dm.c new
> file
> mode 100644 index 00..c8421ed20b
> --- /dev/null
> +++ b/drivers/clk/altera/clk-dm.c
> @@ -0,0 +1,504 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Intel Corporation */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct socfpga_clk_platdata {
> + void __iomem *regs;
> +};
> +
> +/*
> + * function to write the bypass register which requires a poll of the
> + * busy bit
> + */
> +static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat,
> +u32 val) {
> + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
> + cm_wait_for_fsm();
> +}
> +
> +static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat,
> +u32 val) {
> + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
> + cm_wait_for_fsm();
> +}
> +
> +#ifndef CONFIG_TARGET_SOCFPGA_DM
> +/* function to write the ctrl register which requires a poll of the
> +busy bit */ static void clk_write_ctrl(struct socfpga_clk_platdata
> +*plat, u32 val) {
> + CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
> + cm_wait_for_fsm();
> +}
> +#endif
This .c file only get compiled when CONFIG_TARGET_SOCFPGA_DM is enabled. This
code will never get compiled.
Same for the similar #ifndef in this file.
[]
> +static u64 clk_get_pll_output_hz(struct socfpga_clk_platdata *plat,
> + u32 pllglob_reg, u32 plldiv_reg)
> +{
> + u64 clock = 0;
> + u32 clklsrc, divf, divr, divq, power = 1;
> +
> + /* Get input clock frequency */
> + clklsrc = (CM_REG_READL(plat, pllglob_reg) &
> +CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
> +CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
> +
> + switch (clklsrc) {
> + case CLKMGR_VCO_PSRC_EOSC1:
> + clock = cm_get_osc_clk_hz();
> + break;
> + case CLKMGR_VCO_PSRC_INTOSC:
> + clock = cm_get_intosc_clk_hz();
> + break;
> + case CLKMGR_VCO_PSRC_F2S:
> + clock = cm_get_fpga_clk_hz();
> + break;
> + }
> +
> + /* Calculate pll out clock frequency */
> + divf = (CM_REG_READL(plat, plldiv_reg) &
> + CLKMGR_PLLDIV_FDIV_MASK) >>
> + CLKMGR_PLLDIV_FDIV_OFFSET;
> +
> + divr = (CM_REG_READL(plat, plldiv_reg) &
> + CLKMGR_PLLDIV_REFCLKDIV_MASK) >>
> + CLKMGR_PLLDIV_REFCLKDIV_OFFSET;
> +
> + divq = (CM_REG_READL(plat, plldiv_reg) &
> + CLKMGR_PLLDIV_OUTDIV_QDIV_MASK) >>
> + CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET;
> +
> + while (divq) {
> + power *= 2;
> + divq--;
> + }
> +
> + return ((clock * 2 * (divf + 1)) / ((divr + 1) * power)); }
> +
> +static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32
> clksrc_reg,
> + u32 main_div, u32 per_div)
> +{
> + u64 clock = 0;
> + u32 clklsrc = clk_get_5_1_clk
RE: [RESEND v2 09/22] arm: socfpga: Add handoff data support for Diamond Mesa
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Tuesday, November 10, 2020 2:44 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [RESEND v2 09/22] arm: socfpga: Add handoff data support for
> Diamond Mesa
>
> Diamond Mesa support both HPS handoff data and DDR handoff data.
> HPS handoff data support re-use Straix10 and Agilex code. DDR handoff data
> is newly introduced in Diamond Mesa.
>
> Signed-off-by: Siew Chin Lim
> ---
> arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 19 ++
> arch/arm/mach-socfpga/wrap_handoff_soc64.c | 40
> ++
> 2 files changed, 59 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
> b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
> index 68e0278384..c38b232065 100644
> --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
> +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
[...]
> + } else {
> +#ifdef CONFIG_TARGET_SOCFPGA_DM
> + temp = readl(handoff_address);
> + if (temp == SOC64_HANDOFF_DDR_UMCTL2_MAGIC) {
> + debug("%s: umctl2 handoff data =\n{\n",
> + __func__);
> + } else if (temp == SOC64_HANDOFF_DDR_PHY_MAGIC) {
> + debug("%s: PHY handoff data =\n{\n",
> + __func__);
> + } else if (temp ==
> SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC) {
> + debug("%s: PHY engine handoff data =\n{\n",
> + __func__);
> + }
> +
> + debug("handoff table address = 0x%p table length = 0x%x\n",
> + table_x32, table_len);
> +
> + if (temp == SOC64_HANDOFF_DDR_UMCTL2_MAGIC ||
> + temp == SOC64_HANDOFF_DDR_PHY_MAGIC ||
> + temp ==
> SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC) {
> + /* Using handoff from Quartus tools if exists */
> + for (i = 0; i < table_len; i++) {
> + *table_x32 = readl(handoff_address +
> +
> SOC64_HANDOFF_OFFSET_DATA + (i * 4));
Change 4 to sizeof().
Regards
Ley Foon
RE: [RESEND v2 08/22] arm: socfpga: Restructure Stratix10 and Agilex handoff code
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 2:44 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [RESEND v2 08/22] arm: socfpga: Restructure Stratix10 and Agilex > handoff code > > Restructure Stratix10 and Agilex handoff code to used by all SOC64 devices, > in preparation to support handoff for Diamond Mesa. > > Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c which > contains the generic function to parse the handoff data. > > Update system_manager_soc64.c to use generic handoff function in > wrap_handoff_soc64.c. > > Signed-off-by: Siew Chin Lim > --- [] > diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c > b/arch/arm/mach-socfpga/system_manager_soc64.c > index cdda881efd..f94bf5ecd6 100644 > --- a/arch/arm/mach-socfpga/system_manager_soc64.c > +++ b/arch/arm/mach-socfpga/system_manager_soc64.c > @@ -1,12 +1,13 @@ > // SPDX-License-Identifier: GPL-2.0 > /* > - * Copyright (C) 2016-2018 Intel Corporation > + * Copyright (C) 2016-2020 Intel Corporation > * > */ > > #include > #include > #include > +#include Sort in alphanumerical order. [...] > } > diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c > b/arch/arm/mach-socfpga/wrap_handoff_soc64.c > new file mode 100644 > index 00..672bdd5230 > --- /dev/null > +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c > @@ -0,0 +1,73 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2020 Intel Corporation > + * > + */ > + > +#include > +#include > +#include > +#include > +#include "log.h" Sort in alphanumerical order. [...] Regards Ley Foon
RE: [RESEND v2 07/22] arm: socfpga: Rearrange sequence of macros in handoff_soc64.h
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 2:44 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [RESEND v2 07/22] arm: socfpga: Rearrange sequence of macros in > handoff_soc64.h > > No functionality change. In preparation for Stratix10 and Agilex handoff > function restructuring. > This patch adding new macros, please add description for this in commit message. Regards Ley Foon
RE: [RESEND v2 06/22] arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Tuesday, November 10, 2020 2:44 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [RESEND v2 06/22] arm: socfpga: Changed system_manager_s10.c
> to system_manager_soc64.c
>
> Rename to common file name to used by all SOC64 devices.
> No functionality change.
>
> Signed-off-by: Siew Chin Lim
> ---
> arch/arm/mach-socfpga/Makefile | 5
> +++--
> .../mach-socfpga/{system_manager_s10.c => system_manager_soc64.c}|
> 0
> 2 files changed, 3 insertions(+), 2 deletions(-) rename arch/arm/mach-
> socfpga/{system_manager_s10.c => system_manager_soc64.c} (100%)
Reviewed-by: Ley Foon Tan
Regards
Ley Foon
RE: [RESEND v2 05/22] arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Tuesday, November 10, 2020 2:44 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
>
> Subject: [RESEND v2 05/22] arm: socfpga: Changed wrap_pll_config_s10.c to
> wrap_pll_config_soc64.c
>
> Rename to common file name to used by all SOC64 devices.
>
> Signed-off-by: Siew Chin Lim
> ---
> arch/arm/mach-socfpga/Makefile| 4
> ++--
> .../mach-socfpga/{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} | 2
> +-
> 2 files changed, 3 insertions(+), 3 deletions(-) rename arch/arm/mach-
> socfpga/{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} (96%)
Reviewed-by: Ley Foon Tan
Regards
Ley Foon
RE: [RESEND v2 04/22] arm: socfpga: Rename Stratix10 and Agilex handoff common macros
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 2:44 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [RESEND v2 04/22] arm: socfpga: Rename Stratix10 and Agilex > handoff common macros > > Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from > S10_HANDOFF to SOC64_HANDOFF. > > Signed-off-by: Siew Chin Lim > --- > arch/arm/mach-socfpga/clock_manager_s10.c | 2 +- > arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39 --- > --- > arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 39 > ++ > arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 18 +- > arch/arm/mach-socfpga/wrap_pll_config_s10.c| 16 - > include/configs/socfpga_soc64_common.h | 4 +-- > 6 files changed, 59 insertions(+), 59 deletions(-) delete mode 100644 > arch/arm/mach-socfpga/include/mach/handoff_s10.h > create mode 100644 arch/arm/mach- > socfpga/include/mach/handoff_soc64.h Reviewed-by: Ley Foon Tan Regards Ley Foon
RE: [RESEND v2 03/22] arm: socfpga: dm: Add firewall support for Agilex and Diamond Mesa
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 2:44 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [RESEND v2 03/22] arm: socfpga: dm: Add firewall support for Agilex > and Diamond Mesa > > Disable the MPFE firewall for SMMU and HMC adapter for Agilex and > Diamond Mesa. > > Signed-off-by: Siew Chin Lim > --- > arch/arm/mach-socfpga/firewall.c | 10 ++ > arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 1 + > arch/arm/mach-socfpga/include/mach/firewall.h | 6 ++ > 3 files changed, 17 insertions(+) > > diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach- > socfpga/firewall.c > index 69229dc651..b87cc8aa69 100644 > --- a/arch/arm/mach-socfpga/firewall.c > +++ b/arch/arm/mach-socfpga/firewall.c > @@ -104,4 +104,14 @@ void firewall_setup(void) > socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA); > writel(SYSMGR_DMAPERIPH_ALL_NS, > socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH); > + > +#if defined(CONFIG_TARGET_SOCFPGA_AGILEX) || > defined(CONFIG_TARGET_SOCFPGA_DM) > + /* Disable the MPFE Firewall for SMMU */ > + writel(FIREWALL_MPFE_SCR_DISABLE_ALL, > SOCFPGA_FW_MPFE_SCR_ADDRESS + > + FW_MPFE_SCR_HMC); > + /* Disable MPFE Firewall for HMC adapter (ECC) */ > + writel(FIREWALL_MPFE_SCR_DISABLE_MPU, > SOCFPGA_FW_MPFE_SCR_ADDRESS + > + FW_MPFE_SCR_HMC_ADAPTOR); > +#endif Stratix 10 also has these registers. Why Stratix 10 doesn't need this? Regards Ley Foon
RE: [RESEND v2 02/22] arm: socfpga: dm: Add base address for Intel Diamond Mesa
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 2:44 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [RESEND v2 02/22] arm: socfpga: dm: Add base address for Intel > Diamond Mesa > > Reuse base_addr_s10.h for Diamond Mesa, the address is the same as Agilex. > > Signed-off-by: Siew Chin Lim > --- > arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 2 +- Can consider change filename to _soc64.h Regards Ley Foon
RE: [RESEND v2 01/22] arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 2:44 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [RESEND v2 01/22] arm: socfpga: Move Stratix10 and Agilex to use > TARGET_SOCFPGA_SOC64 > > Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. > > Signed-off-by: Siew Chin Lim > --- > arch/arm/Kconfig| 6 +++--- > arch/arm/mach-socfpga/Kconfig | 5 + > arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +-- > arch/arm/mach-socfpga/include/mach/system_manager.h | 3 +-- > drivers/ddr/altera/Kconfig | 6 +++--- > drivers/fpga/Kconfig| 2 +- > drivers/sysreset/Kconfig| 2 +- > 7 files changed, 15 insertions(+), 12 deletions(-) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > b2f7fcbd6e..663ea07341 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -974,7 +974,7 @@ config ARCH_SOCFPGA > bool "Altera SOCFPGA family" > select ARCH_EARLY_INIT_R > select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 > - select ARM64 if TARGET_SOCFPGA_STRATIX10 || > TARGET_SOCFPGA_AGILEX > + select ARM64 if TARGET_SOCFPGA_SOC64 > select CPU_V7A if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > select DM > select DM_SERIAL > @@ -986,7 +986,7 @@ config ARCH_SOCFPGA > select SPL_LIBGENERIC_SUPPORT > select SPL_NAND_SUPPORT if SPL_NAND_DENALI > select SPL_OF_CONTROL > - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || > TARGET_SOCFPGA_AGILEX > + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 > select SPL_SERIAL_SUPPORT > select SPL_SYSRESET > select SPL_WATCHDOG_SUPPORT > @@ -995,7 +995,7 @@ config ARCH_SOCFPGA > select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > select SYSRESET > select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 > || TARGET_SOCFPGA_AGILEX > + select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64 > imply CMD_DM > imply CMD_MTDPARTS > imply CRC32_VERIFY > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach- > socfpga/Kconfig index 7fdb52dd83..4d061a9d0d 100644 > --- a/arch/arm/mach-socfpga/Kconfig > +++ b/arch/arm/mach-socfpga/Kconfig > @@ -31,6 +31,7 @@ config SYS_TEXT_BASE > > config TARGET_SOCFPGA_AGILEX > bool > + select TARGET_SOCFPGA_SOC64 Sort by alphabetical order. > select ARMV8_MULTIENTRY > select ARMV8_SET_SMPEN > select CLK > @@ -75,8 +76,12 @@ config TARGET_SOCFPGA_GEN5 > imply SPL_SYS_MALLOC_SIMPLE > imply SPL_USE_TINY_PRINTF > > +config TARGET_SOCFPGA_SOC64 > + bool > + > config TARGET_SOCFPGA_STRATIX10 > bool > + select TARGET_SOCFPGA_SOC64 Sort by alphabetical order. > select ARMV8_MULTIENTRY > select ARMV8_SET_SMPEN > select FPGA_INTEL_SDM_MAILBOX Regards Ley Foon
RE: [v3 16/16] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Thursday, October 15, 2020 8:30 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Ang, > Chee Hong ; Lim, Elly Siew Chin > > Subject: [v3 16/16] configs: socfpga: Add defconfig for Agilex and Stratix 10 > with ATF support > > From: Chee Hong Ang > > Booting Agilex and Stratix 10 with ATF support. > > SPL now loads ATF (BL31), U-Boot proper and DTB from FIT image. The new > boot flow with ATF support is as follow: > > SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux) > > U-Boot proper now starts at 0x20 (CONFIG_SYS_TEXT_BASE). > ATF will occupy the address range starting from 0x1000. > > Signed-off-by: Chee Hong Ang > Signed-off-by: Siew Chin Lim > --- > configs/socfpga_agilex_atf_defconfig| 72 > > configs/socfpga_stratix10_atf_defconfig | 74 > + > 2 files changed, 146 insertions(+) > create mode 100644 configs/socfpga_agilex_atf_defconfig > create mode 100644 configs/socfpga_stratix10_atf_defconfig Reviewed-by: Ley Foon Tan Regards Ley Foon
RE: [v3 15/16] arm: socfpga: soc64: Enable FIT image generation using binman
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Thursday, October 15, 2020 8:30 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Lim, > Elly Siew Chin > Subject: [v3 15/16] arm: socfpga: soc64: Enable FIT image generation using > binman > > Add new build target "fit-itb" for FIT image generation. > > In preparation to support Vendor Authorized Boot (VAB) for Intel > SOC64 device in near future. With VAB, u-boot proper, dtb and arm trusted > firmware need to be signed before FIT image generation. > > To align user experience for ATF boot with and without VAB feature, we skip > binman for ARCH_SOCFPGA in default Makefile flow. User always use 'make > fit-itb' to generate FIT image after successfully compile u-boot. > > Signed-off-by: Siew Chin Lim > --- > Makefile | 7 +++ > arch/arm/mach-socfpga/Kconfig | 2 ++ > 2 files changed, 9 insertions(+) > > diff --git a/Makefile b/Makefile > index 28c9f31fb4..ed05becc9e 100644 > --- a/Makefile > +++ b/Makefile > @@ -1020,8 +1020,10 @@ inputs: $(INPUTS-y) > > all: .binman_stamp inputs > ifeq ($(CONFIG_BINMAN),y) > +ifneq ($(CONFIG_ARCH_SOCFPGA),y) > $(call if_changed,binman) > endif > +endif > > # Timestamp file to make sure that binman always runs > .binman_stamp: FORCE > @@ -1600,6 +1602,11 @@ cmd_socnandboot = cat u-boot-spl-padx4.sfp > u-boot.img > $@ || rm -f $@ > u-boot-with-nand-spl.sfp: u-boot-spl-padx4.sfp u-boot.img FORCE > $(call if_changed,socnandboot) > > +ifeq ($(CONFIG_FIT),y) > +fit-itb: > + $(call if_changed,binman) > +endif > + > endif > > ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach- > socfpga/Kconfig index 01f5a1fc41..7fdb52dd83 100644 > --- a/arch/arm/mach-socfpga/Kconfig > +++ b/arch/arm/mach-socfpga/Kconfig > @@ -37,6 +37,7 @@ config TARGET_SOCFPGA_AGILEX > select FPGA_INTEL_SDM_MAILBOX > select NCORE_CACHE > select SPL_CLK if SPL > + select BINMAN Sort by alphabetical order > config TARGET_SOCFPGA_ARRIA5 > bool > @@ -79,6 +80,7 @@ config TARGET_SOCFPGA_STRATIX10 > select ARMV8_MULTIENTRY > select ARMV8_SET_SMPEN > select FPGA_INTEL_SDM_MAILBOX > + select BINMAN Sort by alphabetical order Regards Ley Foon
RE: [v3 14/16] arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Thursday, October 15, 2020 8:30 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Lim, > Elly Siew Chin > Subject: [v3 14/16] arm: socfpga: dts: soc64: Add binman node of FIT image > with ATF support > > Add binman node to device tree to generate the FIT image for u-boot > (u-boot.itb) and OS kernel (kernel.itb). > > u-boot.itb contains arm trusted firmware (ATF), u-boot proper and u-boot > device tree for ATF u-boot flow. > > kernel.itb contains Linux Image and Linux device tree. > > Signed-off-by: Siew Chin Lim > --- > arch/arm/dts/socfpga_agilex-u-boot.dtsi | 4 +- > arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 120 > +++ > arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 8 ++ > arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 +- > 4 files changed, 134 insertions(+), 2 deletions(-) create mode 100644 > arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi > create mode 100644 arch/arm/dts/socfpga_stratix10-u-boot.dtsi Reviewed-by: Ley Foon Tan Regards Ley Foon
RE: [v3 09/16] arm: socfpga: soc64: Add ATF support for Reset Manager driver
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Thursday, October 15, 2020 8:30 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Ang, > Chee Hong ; Lim, Elly Siew Chin > > Subject: [v3 09/16] arm: socfpga: soc64: Add ATF support for Reset Manager > driver > > From: Chee Hong Ang > > In non-secure mode (EL2), Reset Manager driver calls the SMC/PSCI service > provided by ATF to enable/disable the SOCFPGA bridges. > > Signed-off-by: Chee Hong Ang > Signed-off-by: Siew Chin Lim > --- > arch/arm/mach-socfpga/reset_manager_s10.c | 13 + > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c > b/arch/arm/mach-socfpga/reset_manager_s10.c > index 3746e6a60c..af8f2c0873 100644 > --- a/arch/arm/mach-socfpga/reset_manager_s10.c > +++ b/arch/arm/mach-socfpga/reset_manager_s10.c > @@ -5,11 +5,14 @@ > */ > Reviewed-by: Ley Foon Tan
RE: [v3 08/16] net: designware: socfpga: Add ATF support for MAC driver
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Thursday, October 15, 2020 8:30 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Ang,
> Chee Hong ; Lim, Elly Siew Chin
>
> Subject: [v3 08/16] net: designware: socfpga: Add ATF support for MAC
> driver
>
> From: Chee Hong Ang
>
> In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided
> by ATF to setup the PHY interface.
>
> Signed-off-by: Chee Hong Ang
> Signed-off-by: Siew Chin Lim
> ---
> drivers/net/dwmac_socfpga.c | 30 ++
> 1 file changed, 26 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
> index e93561dffa..a2d09d5c4a 100644
> --- a/drivers/net/dwmac_socfpga.c
> +++ b/drivers/net/dwmac_socfpga.c
> @@ -17,7 +17,9 @@
> #include
> #include
>
> +#include
> #include
> +#include
Move this to after .
>
> struct dwmac_socfpga_platdata {
> struct dw_eth_pdata dw_eth_pdata;
> @@ -64,6 +66,27 @@ static int dwmac_socfpga_ofdata_to_platdata(struct
> udevice *dev)
> return designware_eth_ofdata_to_platdata(dev);
> }
>
> +static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg) {
> + struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
> +
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
> + u64 args[2];
> +
> + args[0] = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() -
> +SYSMGR_SOC64_EMAC0) >> 2;
> + args[1] = modereg;
> +
> + if (invoke_smc(INTEL_SIP_SMC_HPS_SET_PHYINTF, args, 2, NULL, 0))
> + return -EIO;
Can you if check ATF support this SMC call already? I didn't see it.
Regards
Ley Foon
RE: [v3 07/16] mmc: dwmmc: socfpga: Add ATF support for MMC driver
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Thursday, October 15, 2020 8:30 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Ang,
> Chee Hong ; Lim, Elly Siew Chin
>
> Subject: [v3 07/16] mmc: dwmmc: socfpga: Add ATF support for MMC driver
>
> From: Chee Hong Ang
>
> In non-secure mode (EL2), MMC driver calls the SMC/PSCI services provided
> by ATF to set SDMMC's DRVSEL and SMPLSEL.
>
> Signed-off-by: Chee Hong Ang
> Signed-off-by: Siew Chin Lim
> ---
> drivers/mmc/socfpga_dw_mmc.c | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/mmc/socfpga_dw_mmc.c
> b/drivers/mmc/socfpga_dw_mmc.c index 0022f943bd..e5f68fa7fb 100644
> --- a/drivers/mmc/socfpga_dw_mmc.c
> +++ b/drivers/mmc/socfpga_dw_mmc.c
> @@ -6,6 +6,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -13,6 +14,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -48,6 +50,10 @@ static void socfpga_dwmci_reset(struct udevice *dev)
>
> static void socfpga_dwmci_clksel(struct dwmci_host *host) {
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
> + u64 args[2];
> +#endif
> +
> struct dwmci_socfpga_priv_data *priv = host->priv;
> u32 sdmmc_mask = ((priv->smplsel & 0x7) <<
> SYSMGR_SDMMC_SMPLSEL_SHIFT) |
>((priv->drvsel & 0x7) <<
> SYSMGR_SDMMC_DRVSEL_SHIFT); @@ -58,10 +64,21 @@ static void
> socfpga_dwmci_clksel(struct dwmci_host *host)
>
> debug("%s: drvsel %d smplsel %d\n", __func__,
> priv->drvsel, priv->smplsel);
> +
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
> + /* drvsel */
> + args[0] = (sdmmc_mask >> SYSMGR_SDMMC_DRVSEL_SHIFT) & 0x7;
> + /* smplsel */
> + args[1] = (sdmmc_mask >> SYSMGR_SDMMC_SMPLSEL_SHIFT) & 0x7;
> + if (invoke_smc(INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK, args, 2,
> NULL, 0))
> + dev_err(host->mmc->dev, "SMC call failed in %s\n",
> __func__);
> +
> +#else
> writel(sdmmc_mask, socfpga_get_sysmgr_addr() +
> SYSMGR_SDMMC);
>
> debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
> readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
> +#endif
Can move these code to new function, easier to read.
Regards
Ley Foon
RE: [v3 02/16] arm: socfpga: soc64: Load FIT image with ATF support
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Thursday, October 15, 2020 8:30 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Ang, > Chee Hong ; Lim, Elly Siew Chin > > Subject: [v3 02/16] arm: socfpga: soc64: Load FIT image with ATF support > > From: Chee Hong Ang > > Instead of loading u-boot proper image (u-boot.img), SPL now loads FIT > image (u-boot.itb) which includes u-boot proper, ATF and u-boot proper's > DTB. > > For OS, u-boot now loads FIT images (kernel.itb) which includes Linux Image > and Linux's DTB. > > Signed-off-by: Chee Hong Ang > Signed-off-by: Siew Chin Lim Reviewed-by: Ley Foon Tan
RE: [PATCH 2/5] spl: mmc: extend spl_mmc_boot_mode() to take mmc argument
> -Original Message- > From: Andre Przywara > Sent: Sunday, November 8, 2020 9:14 PM > To: Jagan Teki > Cc: Petr Štetiar ; Sunil Mohan Adapa ; > Samuel Holland ; Aleksandr Aleksandrov > ; Icenowy Zheng ; > Simon Glass ; Tom Rini ; linux- > su...@googlegroups.com; u-boot@lists.denx.de; Stefano Babic > ; Fabio Estevam ; NXP i . MX U- > Boot Team ; Lokesh Vutla ; > Philipp Tomsich ; Kever Yang > ; Marek Vasut ; Simon > Goldschmidt ; Tan, Ley Foon > ; Patrick Delaunay ; > Patrice Chotard ; Andre Przywara > > Subject: [PATCH 2/5] spl: mmc: extend spl_mmc_boot_mode() to take mmc > argument > > Platforms can overwrite the weak definition of spl_mmc_boot_mode() to > determine where to load U-Boot proper from. > For most of them this is a trivial decision based on Kconfig variables, but it > might be desirable the probe the actual device to answer this question. > > Pass the pointer to the mmc struct to that function, so implementations can > make use of them. > > Compile-tested for all users changed. > > Cc: Stefano Babic > Cc: Fabio Estevam > Cc: NXP i.MX U-Boot Team > Cc: Lokesh Vutla > Cc: Philipp Tomsich > Cc: Kever Yang > Cc: Marek Vasut > Cc: Simon Goldschmidt > Cc: Ley Foon Tan > Cc: Patrick Delaunay > Cc: Patrice Chotard > Signed-off-by: Andre Przywara > --- > arch/arm/mach-imx/spl.c| 2 +- > arch/arm/mach-k3/am6_init.c| 2 +- > arch/arm/mach-k3/j721e_init.c | 2 +- > arch/arm/mach-omap2/boot-common.c | 2 +- > arch/arm/mach-rockchip/spl.c | 2 +- > arch/arm/mach-socfpga/spl_a10.c| 2 +- > arch/arm/mach-socfpga/spl_agilex.c | 2 +- > arch/arm/mach-socfpga/spl_gen5.c | 2 +- > arch/arm/mach-socfpga/spl_s10.c| 2 +- > arch/arm/mach-stm32mp/spl.c| 2 +- > arch/arm/mach-uniphier/mmc-boot-mode.c | 5 + > common/spl/spl_mmc.c | 4 ++-- > include/spl.h | 3 ++- > 13 files changed, 15 insertions(+), 17 deletions(-) > For SoCFPGA, Reviewed-by: Ley Foon Tan Regards Ley Foon
RE: [PATCH] lib: zlib: Use post-increment only in inffast.c
> -Original Message- > From: Tom Rini > Sent: Friday, October 23, 2020 9:52 AM > To: Tan, Ley Foon > Cc: Ley Foon Tan ; ZY - u-boot b...@lists.denx.de>; See, Chin Liang > Subject: Re: [PATCH] lib: zlib: Use post-increment only in inffast.c > > On Fri, Oct 23, 2020 at 01:41:57AM +, Tan, Ley Foon wrote: > > > > > > > -Original Message- > > > From: Tom Rini > > > Sent: Thursday, October 22, 2020 9:24 PM > > > To: Tan, Ley Foon > > > Cc: Ley Foon Tan ; ZY - u-boot > > b...@lists.denx.de>; See, Chin Liang > > > Subject: Re: [PATCH] lib: zlib: Use post-increment only in inffast.c > > > > > > On Wed, Oct 21, 2020 at 03:42:10AM +, Tan, Ley Foon wrote: > > > > > > > > > > > > > -Original Message- > > > > > From: Tom Rini > > > > > Sent: Friday, October 16, 2020 8:37 PM > > > > > To: Ley Foon Tan > > > > > Cc: Tan, Ley Foon ; ZY - u-boot > > > > b...@lists.denx.de>; See, Chin Liang > > > > > Subject: Re: [PATCH] lib: zlib: Use post-increment only in > > > > > inffast.c > > > > > > > > > > On Fri, Oct 16, 2020 at 04:40:00AM +0800, Ley Foon Tan wrote: > > > > > > On Fri, Jul 17, 2020 at 9:29 PM Tom Rini > wrote: > > > > > > > > > > > > > > On Wed, Jun 24, 2020 at 04:34:03PM +0800, Ley Foon Tan wrote: > > > > > > > > > > > > > > > From: Chin Liang See > > > > > > > > > > > > > > > > This fixes CVE-2016-9841. Changes integrated from [1], > > > > > > > > with changes make for Uboot code base. > > > > > > > > > > > > > > > > An old inffast.c optimization turns out to not be optimal > > > > > > > > anymore with modern compilers, and furthermore was not > > > > > > > > compliant with the C standard, for which decrementing a > > > > > > > > pointer before its allocated memory is undefined. Per the > > > > > > > > recommendation of a security audit of the zlib code by > > > > > > > > Trail of Bits and TrustInSoft, in support of the Mozilla > > > > > > > > Foundation, this "optimization" was removed, in order to > > > > > > > > avoid the possibility of > > > undefined behavior. > > > > > > > > > > > > > > > > [1]: > > > > > > > > > > > > > > > > > https://github.com/madler/zlib/commit/9aaec95e82117c1cb0f9624264c3 > > > > > > > > 618fc380cecb > > > > > > > > > > > > > > > > Signed-off-by: Mark Adler > > > > > > > > Signed-off-by: Chin Liang See > > > > > > > > Signed-off-by: Ley Foon Tan > > > > > > > > > > > > > > This breaks the following tests on sandbox: > > > > > > > FAILED test/py/tests/test_efi_fit.py::test_efi_fit_launch - > > > > > > > u_boot_spawn.Timeout FAILED > > > > > > > test/py/tests/test_fit.py::test_fit > > > > > > > - > > > > > > > OSError: [Errno 5] Input/output error > > > > > > > > > > > > > Hi Tom > > > > > > > > > > > > I have tried to run the sandtest, but it failed in different > > > > > > test cases. I am run this command "./test/py/test.py --bd sandbox -- > build". > > > > > > Error log at bottom of email. > > > > > > > > > > > > Found that > > > > > > https://gitlab.denx.de/u-boot/u-boot/-/blob/master/lib/zlib/zl > > > > > > ib.h always "#undef POSTINC", it is mean that U-boot can only > > > > > > support pre-increment? I have tried changing "#undef POSTINC" > > > > > > to "define POSTINC" and without this patch, the test failed at > > > > > > the same location. > > > > > > So, the failure is not caused by this patch. > > > > > > Note, this patch mainly changes to support post-increment only. > > > > > > > > > > > > Any suggestion to fix this? > > > > > > > > > > I'm not sure why the tests fail for you to start
RE: [PATCH] lib: zlib: Use post-increment only in inffast.c
> -Original Message- > From: Tom Rini > Sent: Thursday, October 22, 2020 9:24 PM > To: Tan, Ley Foon > Cc: Ley Foon Tan ; ZY - u-boot b...@lists.denx.de>; See, Chin Liang > Subject: Re: [PATCH] lib: zlib: Use post-increment only in inffast.c > > On Wed, Oct 21, 2020 at 03:42:10AM +, Tan, Ley Foon wrote: > > > > > > > -Original Message- > > > From: Tom Rini > > > Sent: Friday, October 16, 2020 8:37 PM > > > To: Ley Foon Tan > > > Cc: Tan, Ley Foon ; ZY - u-boot > > b...@lists.denx.de>; See, Chin Liang > > > Subject: Re: [PATCH] lib: zlib: Use post-increment only in inffast.c > > > > > > On Fri, Oct 16, 2020 at 04:40:00AM +0800, Ley Foon Tan wrote: > > > > On Fri, Jul 17, 2020 at 9:29 PM Tom Rini wrote: > > > > > > > > > > On Wed, Jun 24, 2020 at 04:34:03PM +0800, Ley Foon Tan wrote: > > > > > > > > > > > From: Chin Liang See > > > > > > > > > > > > This fixes CVE-2016-9841. Changes integrated from [1], with > > > > > > changes make for Uboot code base. > > > > > > > > > > > > An old inffast.c optimization turns out to not be optimal > > > > > > anymore with modern compilers, and furthermore was not > > > > > > compliant with the C standard, for which decrementing a > > > > > > pointer before its allocated memory is undefined. Per the > > > > > > recommendation of a security audit of the zlib code by Trail > > > > > > of Bits and TrustInSoft, in support of the Mozilla Foundation, > > > > > > this "optimization" was removed, in order to avoid the possibility > > > > > > of > undefined behavior. > > > > > > > > > > > > [1]: > > > > > > > > > > https://github.com/madler/zlib/commit/9aaec95e82117c1cb0f9624264c3 > > > > > > 618fc380cecb > > > > > > > > > > > > Signed-off-by: Mark Adler > > > > > > Signed-off-by: Chin Liang See > > > > > > Signed-off-by: Ley Foon Tan > > > > > > > > > > This breaks the following tests on sandbox: > > > > > FAILED test/py/tests/test_efi_fit.py::test_efi_fit_launch - > > > > > u_boot_spawn.Timeout FAILED test/py/tests/test_fit.py::test_fit > > > > > - > > > > > OSError: [Errno 5] Input/output error > > > > > > > > > Hi Tom > > > > > > > > I have tried to run the sandtest, but it failed in different test > > > > cases. I am run this command "./test/py/test.py --bd sandbox --build". > > > > Error log at bottom of email. > > > > > > > > Found that > > > > https://gitlab.denx.de/u-boot/u-boot/-/blob/master/lib/zlib/zlib.h > > > > always "#undef POSTINC", it is mean that U-boot can only support > > > > pre-increment? I have tried changing "#undef POSTINC" to "define > > > > POSTINC" and without this patch, the test failed at the same location. > > > > So, the failure is not caused by this patch. > > > > Note, this patch mainly changes to support post-increment only. > > > > > > > > Any suggestion to fix this? > > > > > > I'm not sure why the tests fail for you to start with. They all > > > pass inn the CI environment as well as locally. I would start by > > > seeing how your environment differs from those. > > > > Hi Tom > > > > My test is running on Ubuntu 20.04 Linux. > > > > Can you try change "#undef POSTINC" to "#define POSTINC" in > lib/zlib/zlib.h if you can see the error? > > I see: > FAILED test/py/tests/test_efi_fit.py::test_efi_fit_launch - assert 'Hello, > world' in "## Loa... > FAILED test/py/tests/test_fit.py::test_fit - OSError: [Errno 5] Input/output > error > > as new problems with that change. Just to confirm, this error is with this patch or change to "#define POSTINC"? Yours errors are different from my run. My run failed in these 2 testcases: test/py/tests/test_fs/test_squashfs/test_sqfs_load.py F test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py F Regards Ley Foon
[GIT PULL] SoCFPGA fix for v2021.01
Hi Tom Please pull one fix for 2021.01. Travis CI build: https://travis-ci.org/github/lftan/u-boot/builds/737650124 Regards Ley Foon The following changes since commit 7ec87e4192215815b658c3f8b34e4be010103149: Merge tag 'u-boot-atmel-2021.01-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel (2020-10-19 09:29:05 -0400) are available in the Git repository at: https://github.com/lftan/u-boot.git 2021.01-rc for you to fetch changes up to b0b08ce0b7b13520412f1768a0d3290d3c5f50fb: arm: socfpga: fix Gen5 enable of EMAC via FPGA (2020-10-21 11:45:54 +0800) Ralph Siemsen (1): arm: socfpga: fix Gen5 enable of EMAC via FPGA arch/arm/mach-socfpga/include/mach/system_manager_gen5.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
RE: [PATCH] lib: zlib: Use post-increment only in inffast.c
> -Original Message- > From: Tom Rini > Sent: Friday, October 16, 2020 8:37 PM > To: Ley Foon Tan > Cc: Tan, Ley Foon ; ZY - u-boot b...@lists.denx.de>; See, Chin Liang > Subject: Re: [PATCH] lib: zlib: Use post-increment only in inffast.c > > On Fri, Oct 16, 2020 at 04:40:00AM +0800, Ley Foon Tan wrote: > > On Fri, Jul 17, 2020 at 9:29 PM Tom Rini wrote: > > > > > > On Wed, Jun 24, 2020 at 04:34:03PM +0800, Ley Foon Tan wrote: > > > > > > > From: Chin Liang See > > > > > > > > This fixes CVE-2016-9841. Changes integrated from [1], with > > > > changes make for Uboot code base. > > > > > > > > An old inffast.c optimization turns out to not be optimal anymore > > > > with modern compilers, and furthermore was not compliant with the > > > > C standard, for which decrementing a pointer before its allocated > > > > memory is undefined. Per the recommendation of a security audit of > > > > the zlib code by Trail of Bits and TrustInSoft, in support of the > > > > Mozilla Foundation, this "optimization" was removed, in order to > > > > avoid the possibility of undefined behavior. > > > > > > > > [1]: > > > > > https://github.com/madler/zlib/commit/9aaec95e82117c1cb0f9624264c3 > > > > 618fc380cecb > > > > > > > > Signed-off-by: Mark Adler > > > > Signed-off-by: Chin Liang See > > > > Signed-off-by: Ley Foon Tan > > > > > > This breaks the following tests on sandbox: > > > FAILED test/py/tests/test_efi_fit.py::test_efi_fit_launch - > > > u_boot_spawn.Timeout FAILED test/py/tests/test_fit.py::test_fit - > > > OSError: [Errno 5] Input/output error > > > > > Hi Tom > > > > I have tried to run the sandtest, but it failed in different test > > cases. I am run this command "./test/py/test.py --bd sandbox --build". > > Error log at bottom of email. > > > > Found that > > https://gitlab.denx.de/u-boot/u-boot/-/blob/master/lib/zlib/zlib.h > > always "#undef POSTINC", it is mean that U-boot can only support > > pre-increment? I have tried changing "#undef POSTINC" to "define > > POSTINC" and without this patch, the test failed at the same location. > > So, the failure is not caused by this patch. > > Note, this patch mainly changes to support post-increment only. > > > > Any suggestion to fix this? > > I'm not sure why the tests fail for you to start with. They all pass inn the > CI > environment as well as locally. I would start by seeing how your > environment differs from those. Hi Tom My test is running on Ubuntu 20.04 Linux. Can you try change "#undef POSTINC" to "#define POSTINC" in lib/zlib/zlib.h if you can see the error? Regards Ley Foon
