Re: [PATCH 08/35] common: Move relocate_code() to init.h
On 12/11/19 6:47 PM, Simon Glass wrote: - * void relocate_code (addr_moni) + * void relocate_code(addr_moni) Is this really necessary? I think you're bloating your patch with these comment changes. Your patch would be half the size without these changes, so I don't think this really qualifies as "while we are here".
Re: [U-Boot] [PATCH 1/2] p1022ds: Change Timur's email address
On 05/02/2018 06:12 PM, Fabio Estevam wrote: ti...@freescale.com is not a valid email for quite some time, so change it to Timur's updated email. Signed-off-by: Fabio Estevam Acked-by: Timur Tabi ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] MAINTAINERS: Switch nxp.com domain
On 5/1/18 1:54 PM, Fabio Estevam wrote: Timur, would you like to keep maintaining p1022ds? If so, then please send an email switching your address toti...@tabi.org. Ok. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] ACPI in general
Bin Meng wrote: >I believe that ACPI systems generally expect EFI runtime services to >be present as well. I know ours does. This is not true. ACPI does not require any EFI runtime services. Please re-read my sentence. I said "generally expect". If you guys want to spend the man-years necessary to get ACPI and ARM working in U-Boot, go right on ahead. I think it's a fool's errand. I work on ARM Servers, so I know the pain that is ACPI. You don't want it. If your system works with device tree, stick with that. ACPI has no value outside of ARM servers, and ARM servers already have UEFI. -- Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ACPI in general
On Wed, Oct 5, 2016 at 8:58 PM, Tom Rini wrote: > > I think that takes too narrow of a view. If silicon is sold, someone > will put it somewhere. And if there's firmware that works, and the > buyer can modify to suit their design, they'll use it. I believe that ACPI systems generally expect EFI runtime services to be present as well. I know ours does. -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ACPI in general
Tom Rini wrote: Well, I wouldn't phrase it quite like that. I would ask, do we want to go down this path? How far down would we want to go, if so? ACPI is pretty complicated, more so than DT. UEFI is also open source. I think you need to find a very compelling reason to reinvent the wheel. ACPI on ARM is reserved for ARM Servers, which is a small market (in term of number of units) compared to all other ARM chips. -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ACPI in general
On Wed, Oct 5, 2016 at 9:46 AM, Simon Glass wrote: >> Is there any activity to bring ACPI to other than x86 arch? If not, do >> we have a plan to do so? > > Not that I know of, sorry. Note that ACPI for ARM exists on Linux already, and as far as I know, all ARM ACPI systems use UEFI, not U-Boot. -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] dm: gpio: Add driver for MPC85XX GPIO controller
Mario Six wrote: On Tue, May 10, 2016 at 2:30 PM, Timur Tabi mailto:ti...@tabi.org>> wrote: Mario Six wrote: + addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset, + "reg", 0, &size); Why can't you use platform_get_resource()? platform_get_resource is from the kernel, not U-Boot ;-) (Unless I've missed something and it has been implemented without me noticing). Ugh, sorry. I thought this was kernel code. I make that mistake a lot. Now everything makes more sense. I think fdtdec_get_addr_size_auto_noparent() is correct. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] dm: gpio: Add driver for MPC85XX GPIO controller
Mario Six wrote: + addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset, + "reg", 0, &size); Why can't you use platform_get_resource()? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] dm: gpio: Add driver for MPC85XX GPIO controller
Mario Six wrote: The problem is that in 36-bit mode the physical addresses are 64-bit, which means that you get 64-bit integers when you read something from the device tree with fdtdec_get_addr. But the device tree addresses themselves seem to be 32-bit, because if I read a property like 'reg = <0xf000 0x100>', I get a 64-bit value that contains two 32-bit values, so I have to do 'addr = reg >> 32; size = reg & 0x;' to extract them (see the patch). Doing that poses a problem if you use the 32-bit mode, though, since then the physical addresses are 32-bit. After reading your comment (and a bit of digging), I found the fdtdec_get_addr_size_auto_noparent function, which seems to fix that problem (by taking the parent's address-size values into account). I'll respin the patches with that function and Simon's concerns addressed. Addresses from the reg properties should be read with functions like platform_get_resource(). You're not supposed to be reading the device tree properties directly. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] dm: gpio: Add driver for MPC85XX GPIO controller
On Mon, May 2, 2016 at 6:43 AM, Mario Six wrote: > Regarding the address width discrepancy: The system I'm working on is a > P1022 Qoriq, which has 36 bit width, which implies that phys_addr_t needs > to be 64 bit. But the everything else (including the GPIO controller) uses > 32 bits, thus the device tree addresses are 32 bit wide. I'm not quite sure > how to handle this difference; DM support for this platform is brand-new, > so there are no drivers to look to for guidance. I did primary development on the P1022DS, so maybe I can help. It's been a while since I've worked on it, though. First, note that there are two versions of the P1022DS DTS: one is 32-bit, and the other is 36-bit. This was back when Freescale's SOCs were transitioning to 36-bit physical addresses. So if you're never going to have more than 2GB of RAM in your system, you can use 32-bit physical addresses in the DTS. Can you explain the problem again? Like I said, it's been a while, but I have a hard time believing that you've discovered a new problem on the P1022 that hasn't already been solved. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] drivers/elbc:Memory leak fix
On Fri, May 22, 2015 at 9:55 PM, Kushwaha Prabhakar wrote: > > It is not getting catch during GCC build. But during static analysis using > Klockwork, this is shown as error. Then Klockwork is wrong. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/t1040qds: Remove Video - HDMI support
On Fri, Apr 18, 2014 at 4:32 AM, dongsheng.w...@freescale.com wrote: > > If we have, why kernel doesn't support DIU on T1040QDS? That I must remove it > reason. Because no one added that support yet. You should finish the job by fixing the kernel. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 03/11] kconfig: add board Kconfig and defconfig files
On Thu, Apr 24, 2014 at 12:04 AM, Masahiro Yamada wrote: > diff --git a/board/freescale/p1022ds/Kconfig b/board/freescale/p1022ds/Kconfig > new file mode 100644 > index 000..773ea52 > --- /dev/null > +++ b/board/freescale/p1022ds/Kconfig > @@ -0,0 +1,251 @@ > +if TARGET_P1022DS > + > +config SYS_CPU > + string > + default "mpc85xx" > + > +config SYS_BOARD > + string > + default "p1022ds" > + > +config SYS_VENDOR > + string > + default "freescale" > + > +config SYS_CONFIG_NAME > + string > + default "P1022DS" > + > +config BOARD_MAINTAINER > + string > + default "Timur Tabi " My new email address is now ti...@tabi.org. I don't work for Freescale any more. You could also assign the board maintainer to someone else (York?) instead. I don't actually expect to maintain this board any more. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] Powerpc/QE: Add QE support for T1040
On Mon, Jan 27, 2014 at 2:14 AM, Zhao Qiang wrote: > +#ifndef CONFIG_PPC_T1040 Nack. You need to write this code without all this T1040-specific #ifdefs everywhere. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Powerpc/QE: Add QE support for T1040
qiang.z...@freescale.com wrote: T1040QDS has microcode for Fman and another microcode for QE. The two microcodes is different. QE microcode is needed. Then why do you have an #else statement: +#ifdef CONFIG_PPC_T1040 + qe_upload_firmware((const void *)CONFIG_SYS_QE_UCODE_FW_ADDR); +#else qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR); +#endif On the T1040, you're uploading only the QE firmware. I think you're going to have to do a lot of work to fix this. "#ifdef CONFIG_PPC_T1040" is not acceptable. 1. Replace CONFIG_SYS_QE_FMAN_FW_ADDR with CONFIG_SYS_QE_FW_ADDR and CONFIG_SYS_FMAN_FW_ADDR. Any board that uses CONFIG_SYS_QE_FMAN_FW_ADDR for QE firmware will use CONFIG_SYS_QE_FW_ADDR instead. Any board that uses CONFIG_SYS_QE_FMAN_FW_ADDR for Fman firmware will use CONFIG_SYS_FMAN_FW_ADDR instead. 2. Modify the QE code to use CONFIG_SYS_QE_FW_ADDR to upload the QE firmware. Modify the Fman code to use CONFIG_SYS_FMAN_FW_ADDR to upload the Fman firmwre. Then you can do this: #ifdef CONFIG_SYS_QE_FW_ADDR qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); #endif #ifdef CONFIG_SYS_FMAN_FW_ADDR qe_upload_firmware((const void *)CONFIG_SYS_FMAN_FW_ADDR); +#endif 3. Update the README This way, you can support all SoCs that have QE and/or Fman, without making the code work only on the T1040. Don't forget to test other boards with QE and Fman before posting patches so that you know you didn't break any other boards. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Powerpc/QE: Add QE support for T1040
qiang.z...@freescale.com wrote: Other boards have either Fman or QE, So CONFIG_SYS_QE_FMAN_FW_ADDR can be used either Fman or QE. But T1040QDS have both Fman and QE. Does the T1040QDS have microcode for both Fman and QE? Normally, QE microcode is not needed. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Powerpc/QE: Add QE support for T1040
qiang.z...@freescale.com wrote: CONFIG_SYS_QE_FMAN_FW_ADDR is used for Fman microcode while CONFIG_SYS_QE_UCODE_FW_ADDR used For QE microcode. No, CONFIG_SYS_QE_FMAN_FW_ADDR is used for both QE and Fman microcode. That's why it says "QE_FMAN" in it. This is documented in the README. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Powerpc/QE: Add QE support for T1040
On Fri, Jan 24, 2014 at 3:05 AM, Zhao Qiang wrote: > +#ifdef CONFIG_PPC_T1040 > + qe_upload_firmware((const void *)CONFIG_SYS_QE_UCODE_FW_ADDR); > +#else > qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR); > +#endif > It's been a while since I looked at the QE code in U-Boot, but this should be unnecessary. CONFIG_SYS_QE_FMAN_FW_ADDR is supposed to point to the QE microcode blob. Why do you need to define CONFIG_SYS_QE_UCODE_FW_ADDR? That's redundant. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] T4QDS e6500 core and U-Boot 64-bit
On Fri, Jan 24, 2014 at 7:45 AM, Wolfgang Denk wrote: > > For the "test" > part, it is probably much easier to add a customized memory test (or > fix just the existing memory test such that it can be built for a 64 > bit mode) and use this, then trying to run all of U-Boot in 64 bit > mode. There already is PowerPC memory test code in U-Boot that supports more than 2GB. It uses sliding TLB windows. If it doesn't already support 12GB, then it should be easy to add that support. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/9][v2] net: tsec: Use portable types and accessors for BDs
Claudiu Manoil wrote: I think you're suggesting that virt_to_phys() should be used to fix that, right? Yes. However, virt_to_phys() is equivalent to that simple cast in most cases as there's no CONFIG_PHYS_64BIT for the platforms with eTSEC. I'm actually not sure if there's a platform with eTSEC for which that cast wouldn't be enough. Freescale might create a eTSEC-compatible 10G NIC one day that does run on e6500 cores. If so, it should be a separate patch as this fix would apply to existing (old) code and is out of the scope of this patch about portable accessors. Fair enough. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/9][v2] net: tsec: Use portable types and accessors for BDs
On Sat, Oct 5, 2013 at 9:31 AM, Timur Tabi wrote: > > + out_be32(®s->tbase, (u32)&txbd[0]); > + out_be32(®s->rbase, (u32)&rxbd[0]); > > &rxbd[0] is a virtual address. > > Doesn't rbase require a physical address? You're assuming that virt == phys. Also: - out_be32(®s->tbase, (unsigned int)(&rtx.txbd[tx_idx])); - out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rx_idx])); + out_be32(®s->tbase, (u32)&txbd[0]); + out_be32(®s->rbase, (u32)&rxbd[0]); Are you assuming that rx_idx will always be zero in this case? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/9][v2] net: tsec: Use portable types and accessors for BDs
On Fri, Oct 4, 2013 at 11:25 AM, Claudiu Manoil wrote: > [v3] declaring the BDs as __iomem to avoid casting submitted: > http://patchwork.ozlabs.org/patch/280664/ + out_be32(®s->tbase, (u32)&txbd[0]); + out_be32(®s->rbase, (u32)&rxbd[0]); &rxbd[0] is a virtual address. Doesn't rbase require a physical address? You're assuming that virt == phys. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/9] net: tsec: Use portable types and accessors for BDs
On Mon, Sep 30, 2013 at 4:44 AM, Claudiu Manoil wrote: > +#define GET_BD_STAT(T, i) be16_to_cpu((__force __be16)T##BD(i).status) > +#define SET_BD_STAT(T, i, v) T##BD(i).status = (__force __u16)cpu_to_be16(v) > +#define GET_BD_BLEN(T, i) be16_to_cpu((__force __be16)T##BD(i).length) > +#define SET_BD_BLEN(T, i, v) T##BD(i).length = (__force __u16)cpu_to_be16(v) > +#define GET_BD_BPTR(T, i) be32_to_cpu((__force __be32)T##BD(i).bufptr) > +#define SET_BD_BPTR(T, i, v) T##BD(i).bufptr = (__force __u32)cpu_to_be32(v) This is pretty ugly. There's got to be a better way to handle this. Are you going to be doing stuff like this for every driver for bi-endian hardware? Some time ago I suggest that we re-purpose iowrite() and ioread() to be native-endian, and not just little endian. I think something like that would make more sense than hacky macros like this. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] declaring and initializing variables
On Mon, Sep 30, 2013 at 7:04 PM, York Sun wrote: > > struct ccsr_ddr __iomem *ddr = (void *) CONFIG_FOO_ADDR; > struct ccsr_ddr __iomem *ddr = > (struct ccsr_ddr __iomem *) CONFIG_FOO_ADDR; > > You have told me the second format is preferred. I have been using this > format since. But in practice, the second format is often too long and I > have to wrap to next line. It's not a problem for new code. As I am > trying to cleanup the existing code, I would have to make more changes. > So I am back to this question. Is the first format (using void *) > accetable in long term? I think you can blame me for the first version. I started doing that years ago exactly because the second version is too long. I think the first version is preferred because the second version is unnecessarily complex. The reason you need to cast the macro to a pointer is because it's defined as an integer, which is the real "bug" here. All of these macros should be defined as pointers, but that's a huge change that causes problems elsewhere. Since you're already "cheating" by making them integers, you would just be pretending to do the right thing by using the "proper" cast. By using "(void *)", you're saying that you are "fixing" the integer by making it into a pointer. I don't know if this makes any sense. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] How do ARM platform initialize DDR?
On Thu, Sep 19, 2013 at 3:57 PM, Tom Rini wrote: > > Thinking back, as a rule of thumb, PowerPC has SPD I2C data > available, usually. That's not the rule for ARM. One of a few choices > happen: Even if you do have SPD on your ARM chip, that's still no guarantee that you can program the DDR controller properly. On our chips, we have to have a table of 300+ for each frequency that we support, and the SPD only lets us tweak a few registers to account for different size DIMMs. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] How do ARM platform initialize DDR?
On Tue, Sep 17, 2013 at 10:59 AM, York Sun wrote: > I am wondering if there is generic > DDR driver used by many ARM platforms, like the one we have for > powerpc/mpc85xx SoCs. Sadly, no such thing exists. There is no generic DDR controller for ARM. I'm working on DDR controller support for our ARM chips, and it's nowhere near as elegant as Freescale's PowerPC parts. In our case, we have firmware running in the chip that does DDR initialization and then loads u-boot.bin from a SPI flash into DDR, and then it boots the main processor. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] powerpc/c29xpcie: Getting DDR SPD image from 16-bit sub-address EEPROM
On Sat, Sep 21, 2013 at 8:31 PM, Po Liu wrote:
> +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
> +{
> + int ret = i2c_read(i2c_address, 0, 2, (uchar *)spd,
(uchar) is wrong.
int i2c_read(uint8_t chip, unsigned int addr, int alen,
uint8_t *buffer, int len);
The type for this parameter is uint8_t.
The proper fix is to change the i2c_read() function should be changed
to take a void*.
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Re: [U-Boot] [PATCH] Enable the DIU for P1022DS board.
On Fri, Sep 6, 2013 at 4:21 AM, Jason Jin wrote: > > #ifndef CONFIG_FSL_DIU_FB > +#define CONFIG_ATI > #endif Is this really necessary? If the DIU is disabled, why would someone use a PCI video controller? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/eeprom: update MAX_NUM_PORTS to adapt non-256-bytes EEPROM
On Fri, Aug 30, 2013 at 5:07 AM, Shengzhou Liu wrote: > #ifdef CONFIG_SYS_I2C_EEPROM_NXID > +/* some boards with non-256-bytes EEPROM have special define */ > +/* for MAX_NUM_PORTS in board-specific file */ > +#ifndef MAX_NUM_PORTS > #define MAX_NUM_PORTS 23 > +#endif > #define NXID_VERSION 1 > #endif I'll have to think about this. On one hand, this works. As long as the board-specific value of MAX_NUM_PORTS is valid, then it will work. On the other hand, it's fragile and violates the specification. An NXID v1 EEPROM has the CRC at offset 0xFC. I'm just not sure it really matters. York, I'm okay with this patch if you are. You're the one maintaining this code now. Is there anyone left at Freescale who cares about the integrity of the EEPROM specification? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fsl: Fix compiler warnings from gcc-4.4 in sys_eeprom code
On Mon, Jul 6, 2009 at 10:11 AM, Kumar Gala wrote:
>
> #ifdef CONFIG_SYS_I2C_EEPROM_NXID
> /* Is this a valid NXID EEPROM? */
> -#define is_valid (*((u32 *)e.id) == (('N' << 24) | ('X' << 16) | ('I' << 8)
> | 'D'))
> +#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \
> + (e.id[2] == 'I') || (e.id[3] == 'D'))
> #endif
Four years later, I just noticed that this code is wrong. It should
be && instead of ||.
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Re: [U-Boot] [PATCH] powerpc/eeprom: update MAX_NUM_PORTS to fix program failure
On 08/30/2013 06:04 AM, Liu Shengzhou-B36685 wrote: >> Actually, the 23 should be changed to 31. York, this patch needs to be >> applied: http://patchwork.ozlabs.org/patch/170753/ > > According to AN3638, it should be 30 rather than 31 for 256-bytes EEPROM. Are you talking about the C struct? That's just an example. Besides, the C struct has an error in it: unsigned char res_u[7]; // F6-FB: reserved this should be res_u[6]. Besides, the appnote says elsewhere: "0xA2 – 0xFB reserved Reserved for additional MAC addresses or other data. NXID readers need only consider the MACSIZE field to determine if this space is used for additional MAC addresses." Which means that you can fill the EEPROM with MAC addresses. If you do the math, that means 31 addresses. -- Timur Tabi ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/eeprom: update MAX_NUM_PORTS to fix program failure
On 08/29/2013 04:56 AM, Liu Shengzhou-B36685 wrote: >> If the EEPROM is 128 bytes, then you have a non-conformant EEPROM. > What is a conformant EEPROM? A conformant EEPROM has a size of 256 bytes . > The size of struct of EEPROM_NXID should be able to conform to real size of > EEPROM, regardless it's 128 or 256 EEPROM. The problem is that the CRC is at the end of the structure, so that > It's not reasonable to limit MAX_NUM_PORTS to 23, generally we don't need 23 > MAC addresses to store in EEPROM. > 23 is just suitable to 256 bytes EEPROM. Actually, the 23 should be changed to 31. York, this patch needs to be applied: http://patchwork.ozlabs.org/patch/170753/ >> And using the #ifdef to determine this is definitely the wrong way. > Why? What's your way? If you need to define a new EEPROM format, then the version number needs to be changed to v2, and the code needs to dynamically handle v1 and v2. BTW, your patch breaks EVERY OTHER BOARD. You can't just change the 23 to a 9 for every board. Did you test your patch on other boards? -- Timur Tabi ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/eeprom: update MAX_NUM_PORTS to fix program failure
On Thu, Aug 8, 2013 at 5:14 AM, Shengzhou Liu wrote: > On some boards, the size of EEPROM is 128 Bytes instead of 256. > so we set default MAX_NUM_PORTS to 9 rather than previous 23 to > avoid the programming failure, we can define MAX_NUM_PORTS in > board-specific header file to overwrite the default value. NACK. If the EEPROM is 128 bytes, then you have a non-conformant EEPROM. And using the #ifdef to determine this is definitely the wrong way. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2 V3] PPC MPC83xx: Fix MPC8323ERDB build warning
Wolfgang Denk wrote: mpc8323erdb.c: In function 'mac_read_from_eeprom': mpc8323erdb.c:198:3: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Wolfgang Denk cc: Timur Tabi cc: Kim Phillips Ack. -- Timur Tabi ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2 V2] PPC MPC83xx: Fix MPC8323ERDB build warning
On 07/08/2013 01:19 PM, Wolfgang Denk wrote: > + uint32_t crc_buf; > + > + memcpy(&crc_buf, &buf[24], sizeof(unsigned int)); Well, this is wrong, because it should be sizeof(uint32_t). Or maybe sizeof(crc_buf). -- Timur Tabi ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] PPC MPC83xx: Fix MPC8323ERDB build warning
On Fri, Jun 14, 2013 at 3:21 AM, Wolfgang Denk wrote:
> diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c
> b/board/freescale/mpc8323erdb/mpc8323erdb.c
> index f29b2f4..533cb08 100644
> --- a/board/freescale/mpc8323erdb/mpc8323erdb.c
> +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
> @@ -195,7 +195,11 @@ int mac_read_from_eeprom(void)
> printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
>CONFIG_SYS_I2C_EEPROM_ADDR);
> } else {
> - if (crc32(crc, buf, 24) == *(unsigned int *)&buf[24]) {
> + unsigned int crc_buf;
This should be a uint32_t, because you specifically want only four bytes.
If you fix that,
Acked-by: Timur Tabi
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Re: [U-Boot] [PATCH 2/2] PPC MPC83xx: Fix MPC8323ERDB build warning
On Fri, Jun 28, 2013 at 4:47 PM, Andy Fleming wrote: > Well, he hasn't been at Freescale for years, now, so that's not surprising. > It's not entirely clear to me whether that board is one we actively > support, but I suspect we can get away with maintenance moving over to Kim. > That said, I guess I shouldn't volunteer him. :) There's been a lot of churn at Freescale over the past couple years. I think a lot of the email addresses are no longer valid. It's probably time for an update. For the record, I actually have an mpc8323erdb. I'm not sure if I want to be the maintainer for it, though. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 10/10] powerpc: p1022ds: support TPL on the P1022DS
On Tue, Jun 18, 2013 at 5:39 AM, wrote: > From: Ying Zhang > > Support TPL on the P1022DS. Please define "TPL". I have no idea what it is. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/85xx: Add P1023RDB board support
On Tue, Apr 16, 2013 at 4:00 AM, Chunhe Lan wrote:
>
> +#define CONFIG_SYS_BAUDRATE_TABLE \
> + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
It's amazing that Freescale is still producing board files that are
missing 57,600 baud.
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Re: [U-Boot] [u-boot-release] [PATCH 1/3] powerpc/p5040: enable NAND boot support
Shaohui Xie wrote: > Signed-off-by: Shaohui Xie > --- These patches only add one line each, and each depends on the previous anyway. They should be merged into one patch. > boards.cfg |1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/boards.cfg b/boards.cfg > index e4b0d44..8cf4936 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -855,6 +855,7 @@ P5020DS_SECURE_BOOT powerpc mpc85xx > corenet_ds freesca > P5020DS_SPIFLASH powerpc mpc85xx corenet_ds > freescale - > P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8 > P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds > freescale - > P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF8 > P5040DS powerpc mpc85xx corenet_ds > freescale > +P5040DS_NAND powerpc mpc85xx corenet_ds > freescale - P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8 > BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb > freescale - BSC9131RDB:BSC9131RDB,SPIFLASH > stxgp3 powerpc mpc85xx stxgp3 stx > stxssa powerpc mpc85xx stxssa stx >- stxssa > -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Introduce a global bool type
Wolfgang Denk wrote: > You are right. And I wrote that it's a bug. But this is what you can > easily get from using boolean types. This is example has not been > invented by me. I don't even claim that this was good programming > style - all I want to say is that from what I have seen the boolean > types are not a panacea; they cause new problems as well. I don't disagree with any of that, but I don't see what your point is. Every time you use a new feature, there are also new ways to use it incorrectly. By your logic, we should use no new features of the C language that were invented in the past 20 years. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Introduce a global bool type
Wolfgang Denk wrote: > Dear Tabi Timur-B04825, > > In message > <6ae080b68d46fc4ba2d2769e68d765b708205...@039-sn2mpn1-023.039d.mgd.msft.net> > you wrote: >>> >>> This seems broken to me. Can we rather try8 and get rid of all this >>> "bool" stuff instead? It's just obfuscating the code... >> >> Like Scott said, we sometimes copy code from Linux that uses 'bool', >> so it's simpler if we just retain this commonly-used type. If it's >> part of the language, how is it obfuscating? Maybe the Linux > > _Bool has been introduced very late to any C standard, and you can > still see this from the ugly, unnatural name. It was introduced in C99, which is over 12 years old. > It is my personal firm conviction that the people pushed it were not > the ones who have been using C right from the beginning, say from the > times of Unix v6 or so. > > IMHO it is much better to rely on '0' meaning "false" and anything > else meaning "true" instead of insisting on one specific value of > "true". Yes, people claim the code is easier to read and understand, > but these are the same people who claim drop-down menues are easier to > work wit than a CLI. And I've seen more than one case where bugs were > caused by using "proper bool types" like this: > > i = 0; > j = 0; > k = 2; > > if ((i | j | k) == true) ... Ok, but this is just wrong. i, j, and k are not boolean types, so they should not be compared with 'true' or 'false'. I don't think you'll find any disagreement with that. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot-release] [PATCH] Introduce a global bool type
York Sun wrote: > 'bool' is defined in random places. This patch consolidates them into a > single typedef. ... and defines 'bool' in a completely different way, so it doesn't just "consolidate" the definitions. I would add a comment that says that _Bool was introduced in C99, so it should be safe to use this new definition instead of a hand-coded enum. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot-release] [PATCH 6/7] getenv_f() env variable exist w/o needing a buffer
York Sun wrote: > From: James Yang > > getenv_f() searches the environment for a variable name and copies the > value of the variable to a buffer pointed to by one of the function's > parameters. However, this means that the buffer needs to exist and > needs to be of sufficient length (passed as another parameter to > getenv_f()) to hold the requested variable's value, even if all that is > desired is the mere detection of the existence of the variable itself. > > This patch removes the requirement that the buffer needs to exist. If > the pointer to the buffer is set to NULL and the requested variable is > found, getenv_f() returns 1, else it returns -1. The buffer length > parameter is ignored if the pointer is set to NULL. The original > functionality of getenv_f() is retained (return number of bytes copied > if variable is found, -1 if not), other than being able to copy the > variable's value to the address 0. > > Signed-off-by: James Yang Acked-by: Timur Tabi -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot-release] [PATCH] boards/T4240qds:Fix IFC AMASK init as per FPGA register space
Prabhakar Kushwaha wrote: > +#define CONFIG_SYS_AMASK3IFC_AMASK(4*1024) IFC_AMASK(4 * 1024) Spaces around binary operators, please. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/t4qds: move VSC3316 config data from t4qds.h to t4qds.c
Static variables should be defined in C files, not header files, because
otherwise every C file that #includes the header file will generate a
duplicate of the variables. Since the vsc3316_xxx[] arrays are only
used by t4qds.c anyway, just put the variables there.
Signed-off-by: Timur Tabi
---
board/freescale/t4qds/t4qds.c | 12
board/freescale/t4qds/t4qds.h | 11 ---
2 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index 88b8ced..392c8c0 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -42,6 +42,18 @@
DECLARE_GLOBAL_DATA_PTR;
+static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+ {8, 8}, {9, 9}, {14, 14}, {15, 15} };
+
+static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+ {10, 10}, {11, 11}, {12, 12}, {13, 13} };
+
+static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+ {10, 11}, {11, 10}, {12, 2}, {13, 3} };
+
+static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+ {8, 9}, {9, 8}, {14, 1}, {15, 0} };
+
int checkboard(void)
{
u8 sw;
diff --git a/board/freescale/t4qds/t4qds.h b/board/freescale/t4qds/t4qds.h
index c6a3492..f290f3c 100644
--- a/board/freescale/t4qds/t4qds.h
+++ b/board/freescale/t4qds/t4qds.h
@@ -23,15 +23,4 @@
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
- {8, 8}, {9, 9}, {14, 14}, {15, 15} };
-
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
- {10, 10}, {11, 11}, {12, 12}, {13, 13} };
-
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
- {10, 11}, {11, 10}, {12, 2}, {13, 3} };
-
-static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
- {8, 9}, {9, 8}, {14, 1}, {15, 0} };
#endif
--
1.7.3.4
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[U-Boot] [PATCH 1/2] powerpc/85xx: update the work-around for P4080 erratum SERDES-9
The documented work-around for P4080 erratum SERDES-9 has been updated.
It is now compatible with the work-around for erratum A-4580.
This requires adding a few bitfield macros for the BnTTLCRy0 register.
Signed-off-by: Timur Tabi
---
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 20 +---
arch/powerpc/include/asm/immap_85xx.h |3 +++
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index e6b1b1b..fcd3bff 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -714,9 +714,13 @@ void fsl_serdes_init(void)
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
/*
-* Set BnTTLCRy0[FLT_SEL] = 11 and set BnTTLCRy0[17] = 1 for
-* each of the SerDes lanes selected as SGMII, XAUI, SRIO, or
-* AURORA before the device is initialized.
+* Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
+* for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
+* or AURORA before the device is initialized.
+*
+* Note that this part of the SERDES-9 work-around is
+* redundant if the work-around for A-4580 has already been
+* applied via PBI.
*/
switch (lane_prtcl) {
case SGMII_FM1_DTSEC1:
@@ -733,10 +737,12 @@ void fsl_serdes_init(void)
case SRIO1:
case SRIO2:
case AURORA:
- clrsetbits_be32(&srds_regs->lane[idx].ttlcr0,
- SRDS_TTLCR0_FLT_SEL_MASK,
- SRDS_TTLCR0_FLT_SEL_750PPM |
- SRDS_TTLCR0_PM_DIS);
+ out_be32(&srds_regs->lane[idx].ttlcr0,
+SRDS_TTLCR0_FLT_SEL_KFR_26 |
+SRDS_TTLCR0_FLT_SEL_KPH_28 |
+SRDS_TTLCR0_FLT_SEL_750PPM |
+SRDS_TTLCR0_FREQOVD_EN);
+ break;
default:
break;
}
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 969f726..128a4ae 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2637,8 +2637,11 @@ typedef struct serdes_corenet {
u32 res3;
u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f00
+#define SRDS_TTLCR0_FLT_SEL_KFR_26 0x1000
+#define SRDS_TTLCR0_FLT_SEL_KPH_28 0x0800
#define SRDS_TTLCR0_FLT_SEL_750PPM 0x0300
#define SRDS_TTLCR0_PM_DIS 0x4000
+#define SRDS_TTLCR0_FREQOVD_EN 0x0001
u32 res4[7];
} lane[24];
u32 res6[384];
--
1.7.3.4
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[U-Boot] [PATCH 2/2] powerpc/85xx: implement check for erratum A-004580 work-around
The work-around for erratum A-004580 ("Internal tracking loop can falsely
lock causing unrecoverable bit errors") is implemented via the PBI
(pre-boot initialization code, typically attached to the RCW binary).
This is because the work-around is easier to implement in PBI than in
U-Boot itself.
It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied. For A-004580, we can do this by verifying
that the values in the specific registers that the work-around says to
update.
This change requires access to the SerDes lane sub-structure in
serdes_corenet_t, so we make it a named struct.
Signed-off-by: Timur Tabi
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 48 +
arch/powerpc/include/asm/config_mpc85xx.h |1 +
arch/powerpc/include/asm/immap_85xx.h |2 +-
3 files changed, 50 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index ccfad56..7d38e1c 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include "fsl_corenet_serdes.h"
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
/*
@@ -84,6 +85,49 @@ static void check_erratum_a4849(uint32_t svr)
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
+/*
+ * This work-around is implemented in PBI, so just check to see if the
+ * work-around was actually applied. To do this, we check for specific data
+ * at specific addresses in the SerDes register block.
+ *
+ * The work-around says that for each SerDes lane, write BnTTLCRy0 =
+ * 0x1B00_0001, Register 2 = 0x0088_, and Register 3 = 0x4000_.
+
+ */
+static void check_erratum_a4580(uint32_t svr)
+{
+ const serdes_corenet_t __iomem *srds_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ unsigned int lane;
+
+ for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+ if (serdes_lane_enabled(lane)) {
+ const struct serdes_lane __iomem *srds_lane =
+ &srds_regs->lane[serdes_get_lane_idx(lane)];
+
+ /*
+* Verify that the values we were supposed to write in
+* the PBI are actually there. Also, the lower 15
+* bits of res4[3] should be the same as the upper 15
+* bits of res4[1].
+*/
+ if ((in_be32(&srds_lane->ttlcr0) != 0x1b01) ||
+ (in_be32(&srds_lane->res4[1]) != 0x88) ||
+ (in_be32(&srds_lane->res4[3]) != 0x4044)) {
+ printf("Work-around for Erratum A004580 is "
+ "not enabled\n");
+ return;
+ }
+ }
+ }
+
+ /* Everything matches, so the erratum work-around was applied */
+
+ printf("Work-around for Erratum A004580 enabled\n");
+}
+#endif
+
static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
@@ -200,6 +244,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
/* This work-around is implemented in PBI, so just check for it */
check_erratum_a4849(svr);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
+ /* This work-around is implemented in PBI, so just check for it */
+ check_erratum_a4580(svr);
+#endif
return 0;
}
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 3bde0f4..35a8ad1 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -420,6 +420,7 @@
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff00
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ERRATUM_A004580
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
#define CONFIG_SYS_PPC64 /* 64-bit core */
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 128a4ae..2bac331 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2619,7 +2619,7 @@ typedef struct serdes_corenet {
#define SRDS_PCCR2_RST_XGMII1 0x0080
#define SRDS_PCCR2_RST_XGMII2 0x0040
u32 res5[197];
- struct {
+ struct serdes_lane {
u32 gcr0; /* General Control Register 0 */
#define SRDS_GCR0_RRST 0x0040
#define SRDS_GCR0_1STLANE 0x0001
--
1.7.3.4
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[U-Boot] [PATCH] powerpc/85xx: implement check for erratum A-004849 work-around
The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a
deadlock under certain traffic patterns causing the system to hang") is
implemented via the PBI (pre-boot initialization code, typically attached
to the RCW binary). This is because the work-around is easier to implement
in PBI than in U-Boot itself.
It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied. For A-004849, we can do this by verifying
that the values in the specific registers that the work-around says to
update.
Signed-off-by: Timur Tabi
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 63 +
arch/powerpc/include/asm/config_mpc85xx.h |3 +
2 files changed, 66 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 2be192d..ccfad56 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -25,6 +25,65 @@
#include
#include
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
+/*
+ * This work-around is implemented in PBI, so just check to see if the
+ * work-around was actually applied. To do this, we check for specific data
+ * at specific addresses in DCSR.
+ *
+ * Array offsets[] contains a list of offsets within DCSR. According to the
+ * erratum document, the value at each offset should be 2.
+ */
+static void check_erratum_a4849(uint32_t svr)
+{
+ void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb;
+ unsigned int i;
+
+#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
+ static const uint8_t offsets[] = {
+ 0x50, 0x54, 0x58, 0x90, 0x94, 0x98
+ };
+#endif
+#ifdef CONFIG_PPC_P4080
+ static const uint8_t offsets[] = {
+ 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
+ };
+#endif
+ uint32_t x108; /* The value that should be at offset 0x108 */
+
+ for (i = 0; i < ARRAY_SIZE(offsets); i++) {
+ if (in_be32(dcsr + offsets[i]) != 2) {
+ printf("Work-around for Erratum A004849 is not
enabled\n");
+ return;
+ }
+ }
+
+#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
+ x108 = 0x12;
+#endif
+
+#ifdef CONFIG_PPC_P4080
+ /*
+* For P4080, the erratum document says that the value at offset 0x108
+* should be 0x12 on rev2, or 0x1c on rev3.
+*/
+ if (SVR_MAJ(svr) == 2)
+ x108 = 0x12;
+ if (SVR_MAJ(svr) == 3)
+ x108 = 0x1c;
+#endif
+
+ if (in_be32(dcsr + 0x108) != x108) {
+ printf("Work-around for Erratum A004849 is not enabled\n");
+ return;
+ }
+
+ /* Everything matches, so the erratum work-around was applied */
+
+ printf("Work-around for Erratum A004849 enabled\n");
+}
+#endif
+
static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
@@ -137,6 +196,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
puts("Work-around for Erratum A004934 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
+ /* This work-around is implemented in PBI, so just check for it */
+ check_erratum_a4849(svr);
+#endif
return 0;
}
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 03baaee..3bde0f4 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -343,6 +343,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV20x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+#define CONFIG_SYS_FSL_ERRATUM_A004849
#elif defined(CONFIG_PPC_P3041)
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -375,6 +376,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV20x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+#define CONFIG_SYS_FSL_ERRATUM_A004849
#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -417,6 +419,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff00
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+#define CONFIG_SYS_FSL_ERRATUM_A004849
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
#define CONFIG_SYS_PPC64 /* 64-bit core */
--
1.7.3.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/85xx/p5040: add CONFIG_SYS_PPC64, del CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
The P5040 has an e5500 core, so CONFIG_SYS_PPC64 should be defined in config_mpc85xx.h. This macro was absent in the initial P5040 patch because it crossed paths with the patch that introduced the macro. Also delete CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC, since it's not used in the upstream U-Boot. It's a holdover from the SDK. Signed-off-by: Timur Tabi --- This patch should be applied before "[v4] powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board" arch/powerpc/include/asm/config_mpc85xx.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 03baaee..d3d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -449,6 +449,7 @@ #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #elif defined(CONFIG_PPC_P5040) +#define CONFIG_SYS_PPC64 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_MAX_CPUS4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 @@ -472,7 +473,6 @@ #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_ERRATUM_A004699 -#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC #define CONFIG_SYS_FSL_ERRATUM_A004510 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000 -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] [v4] powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi
Signed-off-by: Shaohui Xie
---
board/freescale/common/Makefile |2 +
board/freescale/common/ngpixis.h|2 +-
board/freescale/corenet_ds/Makefile |2 +
board/freescale/corenet_ds/corenet_ds.c | 22 +-
board/freescale/corenet_ds/eth_superhydra.c | 722 +++
board/freescale/corenet_ds/p5040ds_ddr.c| 18 +
boards.cfg |1 +
drivers/net/fm/Makefile |1 +
drivers/net/fm/p5040.c | 113 +
include/configs/P5040DS.h | 40 ++
10 files changed, 916 insertions(+), 7 deletions(-)
create mode 100644 board/freescale/corenet_ds/eth_superhydra.c
create mode 100644 board/freescale/corenet_ds/p5040ds_ddr.c
create mode 100644 drivers/net/fm/p5040.c
create mode 100644 include/configs/P5040DS.h
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 36f7c4f..75725b4 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -53,6 +53,7 @@ COBJS-$(CONFIG_P2020DS) += ics307_clk.o
COBJS-$(CONFIG_P3041DS)+= ics307_clk.o
COBJS-$(CONFIG_P4080DS)+= ics307_clk.o
COBJS-$(CONFIG_P5020DS)+= ics307_clk.o
+COBJS-$(CONFIG_P5040DS)+= ics307_clk.o
COBJS-$(CONFIG_VSC_CROSSBAR)+= vsc3316_3308.o
# deal with common files for P-series corenet based devices
@@ -60,6 +61,7 @@ SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o
+SUBLIB-$(CONFIG_P5040DS) += p_corenet/libp_corenet.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h
index 1d4483d..a239ee3 100644
--- a/board/freescale/common/ngpixis.h
+++ b/board/freescale/common/ngpixis.h
@@ -45,7 +45,7 @@ typedef struct ngpixis {
struct {
u8 sw;
u8 en;
- } s[8];
+ } s[9]; /* s[0]..s[7] is SW1..SW8, and s[8] is SW11 */
} __attribute__ ((packed)) ngpixis_t;
/* Pointer to the PIXIS register set */
diff --git a/board/freescale/corenet_ds/Makefile
b/board/freescale/corenet_ds/Makefile
index 1fdf8b7..d79193a 100644
--- a/board/freescale/corenet_ds/Makefile
+++ b/board/freescale/corenet_ds/Makefile
@@ -31,9 +31,11 @@ COBJS-y += ddr.o
COBJS-$(CONFIG_P3041DS)+= eth_hydra.o
COBJS-$(CONFIG_P4080DS)+= eth_p4080.o
COBJS-$(CONFIG_P5020DS)+= eth_hydra.o
+COBJS-$(CONFIG_P5040DS)+= eth_superhydra.o
COBJS-$(CONFIG_P3041DS)+= p3041ds_ddr.o
COBJS-$(CONFIG_P4080DS)+= p4080ds_ddr.o
COBJS-$(CONFIG_P5020DS)+= p5020ds_ddr.o
+COBJS-$(CONFIG_P5040DS)+= p5040ds_ddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/freescale/corenet_ds/corenet_ds.c
b/board/freescale/corenet_ds/corenet_ds.c
index a33c936..21428e3 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -45,6 +45,7 @@ int checkboard (void)
struct cpu_type *cpu = gd->cpu;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
unsigned int i;
+ static const char * const freq[] = {"100", "125", "156.25", "212.5" };
printf("Board: %sDS, ", cpu->name);
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
@@ -83,20 +84,28 @@ int checkboard (void)
* don't match.
*/
puts("SERDES Reference Clocks: ");
-#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
+#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
+ || defined(CONFIG_P5040DS)
sw = in_8(&PIXIS_SW(5));
for (i = 0; i < 3; i++) {
- static const char *freq[] = {"100", "125", "156.25", "212.5" };
unsigned int clock = (sw >> (6 - (2 * i))) & 3;
printf("Bank%u=%sMhz ", i+1, freq[clock]);
}
+#ifdef CONFIG_P5040DS
+ /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
+ sw = in_8(&PIXIS_SW(9));
+ printf("Bank4=%sMhz ", freq[sw & 3]);
+#endif
puts("\n");
#else
sw = in_8(&PIXIS_SW(3));
- printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100);
- printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125");
- printf("Bank3=%sMHz\n", (sw & 0x
Re: [U-Boot] Please pull u-boot-mpc85xx.git
Fleming Andy-AFLEMING wrote: > Ah, I knew there was one more I needed to send a mail about. The 5040 > patch wouldn't apply anymore. Could you rebase? I was unable to > determine how to fix it. Rebase again? Ugh. > The CRC patch met with fierce opposition, so I > haven't applied it. The only opposition was from Wolfgang, and he was opposed to our EEPROM format as a whole, not to our patch. He doesn't like the idea that the only way to know the location of the CRC is to first read the ID field. Scott and I explained to him that we don't control this format, we just implement it. So I don't think there is any reasonable objection to my patch. Please apply it. Without it, we have a broken implementation of the EEPROM parser, and *that* is not acceptable. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/fm: fix TBI PHY address settings
Xie Shaohui-B21989 wrote: >> Is this still true with Fman v3? > [S.H] No. Fman V3 does not need to set TBIPA on FM1@DTSEC1. Does this patch break Fman V3? -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/7] [v5] powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi
---
v5: fixed all the LIODNs, for real this time.
arch/powerpc/cpu/mpc85xx/Makefile |3 +
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 70 ++
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h |5 +
arch/powerpc/cpu/mpc85xx/p5040_ids.c | 127 +
arch/powerpc/cpu/mpc85xx/p5040_serdes.c | 117 +++
arch/powerpc/cpu/mpc85xx/speed.c |2 +
arch/powerpc/cpu/mpc8xxx/cpu.c|2 +
arch/powerpc/include/asm/config_mpc85xx.h | 29 ++
arch/powerpc/include/asm/immap_85xx.h | 15 +++
arch/powerpc/include/asm/processor.h |2 +
10 files changed, 372 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/p5040_ids.c
create mode 100644 arch/powerpc/cpu/mpc85xx/p5040_serdes.c
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile
b/arch/powerpc/cpu/mpc85xx/Makefile
index 33e93c8..aad50f3 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -66,6 +66,7 @@ COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o
COBJS-$(CONFIG_BSC9131)+= ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
@@ -80,6 +81,7 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o
@@ -110,6 +112,7 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
COBJS = $(COBJS-y)
COBJS += cpu.o
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 2a68060..e6b1b1b 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -92,10 +92,17 @@ static const struct {
{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
+#ifdef CONFIG_PPC_P4080
{ 20, 170, FSL_SRDS_BANK_3 },
{ 21, 171, FSL_SRDS_BANK_3 },
{ 22, 172, FSL_SRDS_BANK_3 },
{ 23, 173, FSL_SRDS_BANK_3 },
+#else
+ { 20, 166, FSL_SRDS_BANK_3 },
+ { 21, 167, FSL_SRDS_BANK_3 },
+ { 22, 168, FSL_SRDS_BANK_3 },
+ { 23, 169, FSL_SRDS_BANK_3 },
+#endif
};
int serdes_get_lane_idx(int lane)
@@ -493,6 +500,9 @@ void fsl_serdes_init(void)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int cfg;
serdes_corenet_t *srds_regs;
+#ifdef CONFIG_PPC_P5040
+ serdes_corenet_t *srds2_regs;
+#endif
int lane, bank, idx;
int have_bank[SRDS_MAX_BANK] = {};
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -574,6 +584,34 @@ void fsl_serdes_init(void)
}
}
+#ifdef CONFIG_PPC_P5040
+ /*
+* Lanes on bank 4 on P5040 are commented-out, but for some SERDES
+* protocols
Re: [U-Boot] [PATCH 6/7] [v4] powerpc/85xx: Add P5040 processor support
Kim Phillips wrote: > need another two DECO entries. Doh, I merged the change into the wrong commit. Ugh. Thanks for catching that. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/7] [v4] powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi
---
v4: forgot a couple LIODN updates
arch/powerpc/cpu/mpc85xx/Makefile |3 +
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 70 +
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h |5 +
arch/powerpc/cpu/mpc85xx/p5040_ids.c | 131 +
arch/powerpc/cpu/mpc85xx/p5040_serdes.c | 117 ++
arch/powerpc/cpu/mpc85xx/speed.c |2 +
arch/powerpc/cpu/mpc8xxx/cpu.c|2 +
arch/powerpc/include/asm/config_mpc85xx.h | 29 ++
arch/powerpc/include/asm/immap_85xx.h | 15 +++
arch/powerpc/include/asm/processor.h |2 +
10 files changed, 376 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/p5040_ids.c
create mode 100644 arch/powerpc/cpu/mpc85xx/p5040_serdes.c
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile
b/arch/powerpc/cpu/mpc85xx/Makefile
index 33e93c8..aad50f3 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -66,6 +66,7 @@ COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o
COBJS-$(CONFIG_BSC9131)+= ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
@@ -80,6 +81,7 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o
@@ -110,6 +112,7 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
COBJS = $(COBJS-y)
COBJS += cpu.o
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 2a68060..e6b1b1b 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -92,10 +92,17 @@ static const struct {
{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
+#ifdef CONFIG_PPC_P4080
{ 20, 170, FSL_SRDS_BANK_3 },
{ 21, 171, FSL_SRDS_BANK_3 },
{ 22, 172, FSL_SRDS_BANK_3 },
{ 23, 173, FSL_SRDS_BANK_3 },
+#else
+ { 20, 166, FSL_SRDS_BANK_3 },
+ { 21, 167, FSL_SRDS_BANK_3 },
+ { 22, 168, FSL_SRDS_BANK_3 },
+ { 23, 169, FSL_SRDS_BANK_3 },
+#endif
};
int serdes_get_lane_idx(int lane)
@@ -493,6 +500,9 @@ void fsl_serdes_init(void)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int cfg;
serdes_corenet_t *srds_regs;
+#ifdef CONFIG_PPC_P5040
+ serdes_corenet_t *srds2_regs;
+#endif
int lane, bank, idx;
int have_bank[SRDS_MAX_BANK] = {};
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -574,6 +584,34 @@ void fsl_serdes_init(void)
}
}
+#ifdef CONFIG_PPC_P5040
+ /*
+* Lanes on bank 4 on P5040 are commented-out, but for some SERDES
+* protocols, these lanes are
[U-Boot] [PATCH 7/7] [v3] powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi
Signed-off-by: Shaohui Xie
---
arch/powerpc/cpu/mpc85xx/p5040_ids.c| 66 ++--
board/freescale/common/Makefile |2 +
board/freescale/common/ngpixis.h|2 +-
board/freescale/corenet_ds/Makefile |2 +
board/freescale/corenet_ds/corenet_ds.c | 22 +-
board/freescale/corenet_ds/eth_superhydra.c | 722 +++
board/freescale/corenet_ds/p5040ds_ddr.c| 18 +
boards.cfg |1 +
drivers/net/fm/Makefile |1 +
drivers/net/fm/p5040.c | 113 +
include/configs/P5040DS.h | 40 ++
11 files changed, 947 insertions(+), 42 deletions(-)
create mode 100644 board/freescale/corenet_ds/eth_superhydra.c
create mode 100644 board/freescale/corenet_ds/p5040ds_ddr.c
create mode 100644 drivers/net/fm/p5040.c
create mode 100644 include/configs/P5040DS.h
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c
b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
index 8060962..612c3b0 100644
--- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
@@ -35,17 +35,11 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
SET_QP_INFO(11, 12, 6, 1),
SET_QP_INFO(13, 14, 7, 2),
SET_QP_INFO(15, 16, 8, 3),
- SET_QP_INFO(17, 18, 9, 0),
- SET_QP_INFO(19, 20, 10, 0),
+ SET_QP_INFO(17, 18, 9, 0), /* for now, set sdest to 0 */
+ SET_QP_INFO(19, 20, 10, 0), /* for now, set sdest to 0 */
};
#endif
-struct srio_liodn_id_table srio_liodn_tbl[] = {
- SET_SRIO_LIODN_2(1, 199, 200),
- SET_SRIO_LIODN_2(2, 201, 202),
-};
-int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
-
struct liodn_id_table liodn_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN
SET_QMAN_LIODN(31),
@@ -54,40 +48,40 @@ struct liodn_id_table liodn_tbl[] = {
SET_SDHC_LIODN(1, 64),
- SET_USB_LIODN(1, "fsl-usb2-mph", 125),
- SET_USB_LIODN(2, "fsl-usb2-dr", 126),
+ SET_USB_LIODN(1, "fsl-usb2-mph", 93),
+ SET_USB_LIODN(2, "fsl-usb2-dr", 94),
- SET_SATA_LIODN(1, 127),
- SET_SATA_LIODN(2, 128),
+ SET_SATA_LIODN(1, 95),
+ SET_SATA_LIODN(2, 96),
- SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
- SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
- SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 195),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 196),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 197),
- SET_DMA_LIODN(1, 197),
- SET_DMA_LIODN(2, 198),
+ SET_DMA_LIODN(1, 193),
+ SET_DMA_LIODN(2, 194),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
#ifdef CONFIG_SYS_DPAA_FMAN
struct liodn_id_table fman1_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(1, 0, 10),
- SET_FMAN_RX_1G_LIODN(1, 1, 11),
- SET_FMAN_RX_1G_LIODN(1, 2, 12),
- SET_FMAN_RX_1G_LIODN(1, 3, 13),
- SET_FMAN_RX_1G_LIODN(1, 4, 14),
- SET_FMAN_RX_10G_LIODN(1, 0, 15),
+ SET_FMAN_RX_1G_LIODN(1, 0, 6),
+ SET_FMAN_RX_1G_LIODN(1, 1, 7),
+ SET_FMAN_RX_1G_LIODN(1, 2, 8),
+ SET_FMAN_RX_1G_LIODN(1, 3, 9),
+ SET_FMAN_RX_1G_LIODN(1, 4, 10),
+ SET_FMAN_RX_10G_LIODN(1, 0, 11),
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#if (CONFIG_SYS_NUM_FMAN == 2)
struct liodn_id_table fman2_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(2, 0, 16),
- SET_FMAN_RX_1G_LIODN(2, 1, 17),
- SET_FMAN_RX_1G_LIODN(2, 2, 18),
- SET_FMAN_RX_1G_LIODN(2, 3, 19),
- SET_FMAN_RX_1G_LIODN(2, 4, 20),
- SET_FMAN_RX_10G_LIODN(2, 0, 21),
+ SET_FMAN_RX_1G_LIODN(2, 0, 12),
+ SET_FMAN_RX_1G_LIODN(2, 1, 13),
+ SET_FMAN_RX_1G_LIODN(2, 2, 14),
+ SET_FMAN_RX_1G_LIODN(2, 3, 15),
+ SET_FMAN_RX_1G_LIODN(2, 4, 16),
+ SET_FMAN_RX_10G_LIODN(2, 0, 17),
};
int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
#endif
@@ -98,12 +92,14 @@ struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
- SET_SEC_RTIC_LIODN_ENTRY(a, 154),
- SET_SEC_RTIC_LIODN_ENTRY(b, 155),
- SET_SEC_RTIC_LIODN_ENTRY(c, 156),
- SET_SEC_RTIC_LIODN_ENTRY(d, 157),
- SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
- SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 89),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 90),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 91),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 92),
+ SET_SEC_DECO_LIODN_ENTRY(0, 139, 140),
+ SET_SEC_DECO_LIODN_ENTRY(1, 141, 142),
+ SET_SEC_DECO_LIODN_ENTRY(2, 143, 1
[U-Boot] [PATCH 6/7] [v3] powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi
---
arch/powerpc/cpu/mpc85xx/Makefile |3 +
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 70 +
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h |5 +
arch/powerpc/cpu/mpc85xx/p5040_ids.c | 131 +
arch/powerpc/cpu/mpc85xx/p5040_serdes.c | 117 ++
arch/powerpc/cpu/mpc85xx/speed.c |2 +
arch/powerpc/cpu/mpc8xxx/cpu.c|2 +
arch/powerpc/include/asm/config_mpc85xx.h | 29 ++
arch/powerpc/include/asm/immap_85xx.h | 15 +++
arch/powerpc/include/asm/processor.h |2 +
10 files changed, 376 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/p5040_ids.c
create mode 100644 arch/powerpc/cpu/mpc85xx/p5040_serdes.c
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile
b/arch/powerpc/cpu/mpc85xx/Makefile
index 33e93c8..aad50f3 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -66,6 +66,7 @@ COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o
COBJS-$(CONFIG_BSC9131)+= ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
@@ -80,6 +81,7 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o
@@ -110,6 +112,7 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
COBJS = $(COBJS-y)
COBJS += cpu.o
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 2a68060..e6b1b1b 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -92,10 +92,17 @@ static const struct {
{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
+#ifdef CONFIG_PPC_P4080
{ 20, 170, FSL_SRDS_BANK_3 },
{ 21, 171, FSL_SRDS_BANK_3 },
{ 22, 172, FSL_SRDS_BANK_3 },
{ 23, 173, FSL_SRDS_BANK_3 },
+#else
+ { 20, 166, FSL_SRDS_BANK_3 },
+ { 21, 167, FSL_SRDS_BANK_3 },
+ { 22, 168, FSL_SRDS_BANK_3 },
+ { 23, 169, FSL_SRDS_BANK_3 },
+#endif
};
int serdes_get_lane_idx(int lane)
@@ -493,6 +500,9 @@ void fsl_serdes_init(void)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int cfg;
serdes_corenet_t *srds_regs;
+#ifdef CONFIG_PPC_P5040
+ serdes_corenet_t *srds2_regs;
+#endif
int lane, bank, idx;
int have_bank[SRDS_MAX_BANK] = {};
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -574,6 +584,34 @@ void fsl_serdes_init(void)
}
}
+#ifdef CONFIG_PPC_P5040
+ /*
+* Lanes on bank 4 on P5040 are commented-out, but for some SERDES
+* protocols, these lanes are routed to SATA. We use
[U-Boot] [PATCH 3/7] powerpc/85xx: define SRIO LIODN functions only if SRIO is defined
The P5040 does not have SRIO support, so there are no SRIO LIODNs.
Therefore, the functions that set the SRIO LIODNs should not be compiled.
Signed-off-by: Timur Tabi
---
arch/powerpc/cpu/mpc85xx/liodn.c |8
arch/powerpc/include/asm/fsl_liodn.h |4 +++-
2 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 11881c9..e97388c 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -40,6 +40,7 @@ int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns,
int liodn_offset)
return liodn_bases[dpaa_dev].num_ids;
}
+#ifdef CONFIG_SYS_SRIO
static void set_srio_liodn(struct srio_liodn_id_table *tbl, int size)
{
int i;
@@ -54,6 +55,7 @@ static void set_srio_liodn(struct srio_liodn_id_table *tbl,
int size)
}
}
}
+#endif
static void set_liodn(struct liodn_id_table *tbl, int size)
{
@@ -181,8 +183,10 @@ void set_liodns(void)
/* setup general liodn offsets */
set_liodn(liodn_tbl, liodn_tbl_sz);
+#ifdef CONFIG_SYS_SRIO
/* setup SRIO port liodns */
set_srio_liodn(srio_liodn_tbl, srio_liodn_tbl_sz);
+#endif
/* setup SEC block liodn bases & offsets if we have one */
if (IS_E_PROCESSOR(get_svr())) {
@@ -219,6 +223,7 @@ void set_liodns(void)
#endif
}
+#ifdef CONFIG_SYS_SRIO
static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
{
int i, srio_off;
@@ -247,6 +252,7 @@ static void fdt_fixup_srio_liodn(void *blob, struct
srio_liodn_id_table *tbl)
}
}
}
+#endif
static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
{
@@ -277,7 +283,9 @@ static void fdt_fixup_liodn_tbl(void *blob, struct
liodn_id_table *tbl, int sz)
void fdt_fixup_liodn(void *blob)
{
+#ifdef CONFIG_SYS_SRIO
fdt_fixup_srio_liodn(blob, srio_liodn_tbl);
+#endif
fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz);
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/arch/powerpc/include/asm/fsl_liodn.h
b/arch/powerpc/include/asm/fsl_liodn.h
index a37983e..e591e67 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -189,11 +189,13 @@ extern void fdt_fixup_liodn(void *blob);
extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
extern struct liodn_id_table raide_liodn_tbl[];
extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
+#ifdef CONFIG_SYS_SRIO
extern struct srio_liodn_id_table srio_liodn_tbl[];
+extern int srio_liodn_tbl_sz;
+#endif
extern struct liodn_id_table rman_liodn_tbl[];
extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz;
extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
-extern int srio_liodn_tbl_sz;
extern int rman_liodn_tbl_sz;
#endif
--
1.7.3.4
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[U-Boot] [PATCH 2/7] powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs
From: Laurentiu Tudor
The liodn for the new PCIE controller included in P5040DS is no longer set
through a register in the guts register block but with one in the PCIE
register block itself. Update the PCIE CCSR structure to add the new liodn
register and add a new dedicated SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.
Signed-off-by: Laurentiu Tudor
Signed-off-by: Timur Tabi
---
arch/powerpc/include/asm/fsl_liodn.h |5 +
arch/powerpc/include/asm/immap_85xx.h |4 +++-
2 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_liodn.h
b/arch/powerpc/include/asm/fsl_liodn.h
index a9973b8..a37983e 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -94,6 +94,11 @@ extern void fdt_fixup_liodn(void *blob);
SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
+ SET_LIODN_ENTRY_1(compat, liodn,\
+ offsetof(ccsr_pcix_t, liodn_base) +
CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+ CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+
/* reg nodes for DMA start @ 0x300 */
#define SET_DMA_LIODN(dmaNum, liodn) \
SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 7de33a7..6c11178 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -296,7 +296,9 @@ typedef struct ccsr_pcix {
u32 cfg_addr; /* PCIX Configuration Addr */
u32 cfg_data; /* PCIX Configuration Data */
u32 int_ack;/* PCIX IRQ Acknowledge */
- u8 res1[3060];
+ u8 res000c[52];
+ u32 liodn_base; /* PCIX LIODN base register */
+ u8 res0044[3004];
u32 potar0; /* PCIX Outbound Transaction Addr 0 */
u32 potear0;/* PCIX Outbound Translation Extended Addr 0 */
u32 powbar0;/* PCIX Outbound Window Base Addr 0 */
--
1.7.3.4
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[U-Boot] [PATCH 5/7] powerpc/p5040ds: add per pci endpoint liodn offset list
From: Laurentiu Tudor
Add a new device tree property named "fsl,liodn-offset-list"
holding a list of per pci endpoint permitted liodn offsets.
This property is useful in virtualization scenarios
that implement per pci endpoint partitioning.
The final liodn of a partitioned pci endpoint is
calculated by the hardware, by adding these offsets
to pci controller's base liodn, stored in the
"fsl,liodn" property of its node.
The liodn offsets are interleaved to get better cache
utilization. As an example, given 3 pci controllers,
the following liodns are generated for the pci endpoints:
pci0: 193 256 259 262 265 268 271 274 277
pci1: 194 257 260 263 266 269 272 275 278
pci2: 195 258 261 264 267 270 273 276 279
Signed-off-by: Laurentiu Tudor
---
arch/powerpc/cpu/mpc85xx/liodn.c | 52 ++
1 files changed, 52 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index e97388c..2e53367 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -254,6 +254,56 @@ static void fdt_fixup_srio_liodn(void *blob, struct
srio_liodn_id_table *tbl)
}
#endif
+#define CONFIG_SYS_MAX_PCI_EPS 8
+#define CONFIG_SYS_PCI_EP_LIODN_START 256
+
+static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
+{
+ int off, pci_idx = 0, pci_cnt = 0, i, rc;
+ const uint32_t *base_liodn;
+ uint32_t liodn_offs[CONFIG_SYS_MAX_PCI_EPS + 1] = { 0 };
+
+ /*
+* Count the number of pci nodes.
+* It's needed later when the interleaved liodn offsets are generated.
+*/
+ off = fdt_node_offset_by_compatible(fdt, -1, compat);
+ while (off != -FDT_ERR_NOTFOUND) {
+ pci_cnt++;
+ off = fdt_node_offset_by_compatible(fdt, off, compat);
+ }
+
+ for (off = fdt_node_offset_by_compatible(fdt, -1, compat);
+off != -FDT_ERR_NOTFOUND;
+off = fdt_node_offset_by_compatible(fdt, off, compat)) {
+ base_liodn = fdt_getprop(fdt, off, "fsl,liodn", &rc);
+ if (!base_liodn) {
+ char path[64];
+
+ if (fdt_get_path(fdt, off, path, sizeof(path)) < 0)
+ strcpy(path, "(unknown)");
+ printf("WARNING Could not get liodn of node %s: %s\n",
+ path, fdt_strerror(rc));
+ continue;
+ }
+ for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++)
+ liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START +
+ i * pci_cnt + pci_idx - *base_liodn;
+ rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list",
+liodn_offs, sizeof(liodn_offs));
+ if (rc) {
+ char path[64];
+
+ if (fdt_get_path(fdt, off, path, sizeof(path)) < 0)
+ strcpy(path, "(unknown)");
+ printf("WARNING Unable to set fsl,liodn-offset-list for
"
+ "node %s: %s\n", path, fdt_strerror(rc));
+ continue;
+ }
+ pci_idx++;
+ }
+}
+
static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
{
int i;
@@ -303,4 +353,6 @@ void fdt_fixup_liodn(void *blob)
#ifdef CONFIG_SYS_DPAA_RMAN
fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
#endif
+
+ fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4");
}
--
1.7.3.4
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[U-Boot] [PATCH 1/7] powerpc/mpc85xx: fix Unicode characters in release.S
Commit 709389b6 unintentionally used the Unicode version of the apostrophy. Replace it with the normal ASCII version. Signed-off-by: Timur Tabi --- arch/powerpc/cpu/mpc85xx/release.S | 24 1 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 22e73e0..8662ae4 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -159,20 +159,20 @@ __secondary_start_page: /* * PIR definition for E6500 * 0-17 Reserved (logic 0s) - * 8-19 CHIP_ID,2’b00 - SoC 1 + * 8-19 CHIP_ID,2'b00 - SoC 1 * all others - reserved - * 20-24 CLUSTER_ID 5’b0 - CCM 1 + * 20-24 CLUSTER_ID 5'b0 - CCM 1 * all others - reserved - * 25-26 CORE_CLUSTER_ID 2’b00 - cluster 1 - * 2’b01 - cluster 2 - * 2’b10 - cluster 3 - * 2’b11 - cluster 4 - * 27-28 CORE_ID 2’b00 - core 0 - * 2’b01 - core 1 - * 2’b10 - core 2 - * 2’b11 - core 3 - * 29-31 THREAD_ID 3’b000 - thread 0 - * 3’b001 - thread 1 + * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1 + * 2'b01 - cluster 2 + * 2'b10 - cluster 3 + * 2'b11 - cluster 4 + * 27-28 CORE_ID 2'b00 - core 0 + * 2'b01 - core 1 + * 2'b10 - core 2 + * 2'b11 - core 3 + * 29-31 THREAD_ID 3'b000 - thread 0 + * 3'b001 - thread 1 */ rlwinm r4,r0,29,25,31 #elif defined(CONFIG_E500MC) -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/7] powerpc/85xx: move SRIO configuration out of corenet_ds.h
The P5040 does not have SRIO, so don't put the SRIO definitions in corenet_ds.h. They belong in the board-specific header files. Signed-off-by: Timur Tabi --- include/configs/P3041DS.h|4 include/configs/P4080DS.h|4 include/configs/P5020DS.h|4 include/configs/corenet_ds.h |4 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index 98e7a42..cf184e7 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -36,6 +36,10 @@ #define CONFIG_PCIE4 #define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ2500 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index d6f2f5c..53979dd 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -33,6 +33,10 @@ #define CONFIG_MMC #define CONFIG_PCIE3 +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ3000 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 8625f76..7018d7a 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -37,6 +37,10 @@ #define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ2500 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f4f9bd1..0f59fb2 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -76,10 +76,6 @@ #define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ - #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/6] [v2] powerpc/85xx: Add P5040 processor support
Kim Phillips wrote: >> > Support for hardware virtualization and partitioning enforcement >> > Extra privileged level for hypervisor support >> > QorIQ Trust Architecture 1.1 >> > Secure boot, secure debug, tamper detection, volatile key storage > same comment as I made before - make this marketing text relevant to > u-boot, e.g., list what devices this patch supports. I guess we'll have to agree to disagree. I always put information like this when adding new soc/board support. >> +SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), >> +SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), >> +}; > NACK - the SEC in the p5040 has four DECOs, not two. I should have the proper LIODN information later today. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot-release] [RFC PATCH 17/17] ns16550: wait for TENT before initializing
Scott Wood wrote:
> This prevents output problems (including a loss of synchronization
> observed on p2020 that persisted for quite a while) if SPL has output
> still on its way out. I'm not sure why this is only now beginning to
> happen, though.
The subject line says "TENT", but the macro says "TEMT".
Also, it would be nice to see a description of this bit somewhere.
>
> Signed-off-by: Scott Wood
> ---
> drivers/serial/ns16550.c |3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> index 0c23955..66201b6 100644
> --- a/drivers/serial/ns16550.c
> +++ b/drivers/serial/ns16550.c
> @@ -36,6 +36,9 @@
>
> void NS16550_init(NS16550_t com_port, int baud_divisor)
> {
> + while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
> + ;
> +
> serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
> #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
> defined(CONFIG_AM33XX)
--
Timur Tabi
Linux kernel developer at Freescale
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[U-Boot] [PATCH 3/6] powerpc/85xx: move SRIO configuration out of corenet_ds.h
The P5040 does not have SRIO, so don't put the SRIO definitions in corenet_ds.h. They belong in the board-specific header files. Signed-off-by: Timur Tabi --- include/configs/P3041DS.h|4 include/configs/P4080DS.h|4 include/configs/P5020DS.h|4 include/configs/corenet_ds.h |4 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index 98e7a42..cf184e7 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -36,6 +36,10 @@ #define CONFIG_PCIE4 #define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ2500 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index d6f2f5c..53979dd 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -33,6 +33,10 @@ #define CONFIG_MMC #define CONFIG_PCIE3 +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ3000 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 8625f76..7018d7a 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -37,6 +37,10 @@ #define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ2500 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f4f9bd1..0f59fb2 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -76,10 +76,6 @@ #define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ - #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/6] [v2] powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi
Signed-off-by: Shaohui Xie
---
board/freescale/common/Makefile |2 +
board/freescale/common/ngpixis.h|2 +-
board/freescale/corenet_ds/Makefile |2 +
board/freescale/corenet_ds/corenet_ds.c | 22 +-
board/freescale/corenet_ds/eth_superhydra.c | 722 +++
board/freescale/corenet_ds/p5040ds_ddr.c| 18 +
boards.cfg |1 +
drivers/net/fm/Makefile |1 +
drivers/net/fm/p5040.c | 113 +
include/configs/P5040DS.h | 40 ++
10 files changed, 916 insertions(+), 7 deletions(-)
create mode 100644 board/freescale/corenet_ds/eth_superhydra.c
create mode 100644 board/freescale/corenet_ds/p5040ds_ddr.c
create mode 100644 drivers/net/fm/p5040.c
create mode 100644 include/configs/P5040DS.h
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 54cb098..dd93b32 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -53,12 +53,14 @@ COBJS-$(CONFIG_P2020DS) += ics307_clk.o
COBJS-$(CONFIG_P3041DS)+= ics307_clk.o
COBJS-$(CONFIG_P4080DS)+= ics307_clk.o
COBJS-$(CONFIG_P5020DS)+= ics307_clk.o
+COBJS-$(CONFIG_P5040DS)+= ics307_clk.o
# deal with common files for P-series corenet based devices
SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o
+SUBLIB-$(CONFIG_P5040DS) += p_corenet/libp_corenet.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h
index 1d4483d..a239ee3 100644
--- a/board/freescale/common/ngpixis.h
+++ b/board/freescale/common/ngpixis.h
@@ -45,7 +45,7 @@ typedef struct ngpixis {
struct {
u8 sw;
u8 en;
- } s[8];
+ } s[9]; /* s[0]..s[7] is SW1..SW8, and s[8] is SW11 */
} __attribute__ ((packed)) ngpixis_t;
/* Pointer to the PIXIS register set */
diff --git a/board/freescale/corenet_ds/Makefile
b/board/freescale/corenet_ds/Makefile
index 1fdf8b7..d79193a 100644
--- a/board/freescale/corenet_ds/Makefile
+++ b/board/freescale/corenet_ds/Makefile
@@ -31,9 +31,11 @@ COBJS-y += ddr.o
COBJS-$(CONFIG_P3041DS)+= eth_hydra.o
COBJS-$(CONFIG_P4080DS)+= eth_p4080.o
COBJS-$(CONFIG_P5020DS)+= eth_hydra.o
+COBJS-$(CONFIG_P5040DS)+= eth_superhydra.o
COBJS-$(CONFIG_P3041DS)+= p3041ds_ddr.o
COBJS-$(CONFIG_P4080DS)+= p4080ds_ddr.o
COBJS-$(CONFIG_P5020DS)+= p5020ds_ddr.o
+COBJS-$(CONFIG_P5040DS)+= p5040ds_ddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/freescale/corenet_ds/corenet_ds.c
b/board/freescale/corenet_ds/corenet_ds.c
index a33c936..21428e3 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -45,6 +45,7 @@ int checkboard (void)
struct cpu_type *cpu = gd->cpu;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
unsigned int i;
+ static const char * const freq[] = {"100", "125", "156.25", "212.5" };
printf("Board: %sDS, ", cpu->name);
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
@@ -83,20 +84,28 @@ int checkboard (void)
* don't match.
*/
puts("SERDES Reference Clocks: ");
-#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
+#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
+ || defined(CONFIG_P5040DS)
sw = in_8(&PIXIS_SW(5));
for (i = 0; i < 3; i++) {
- static const char *freq[] = {"100", "125", "156.25", "212.5" };
unsigned int clock = (sw >> (6 - (2 * i))) & 3;
printf("Bank%u=%sMhz ", i+1, freq[clock]);
}
+#ifdef CONFIG_P5040DS
+ /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
+ sw = in_8(&PIXIS_SW(9));
+ printf("Bank4=%sMhz ", freq[sw & 3]);
+#endif
puts("\n");
#else
sw = in_8(&PIXIS_SW(3));
- printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100);
- printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125");
- printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125");
+ /* SW3[2]: 0
[U-Boot] [PATCH 2/6] powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs
From: Laurentiu Tudor
The liodn for the new PCIE controller included in P5040DS is no longer set
through a register in the guts register block but with one in the PCIE
register block itself. Update the PCIE CCSR structure to add the new liodn
register and add a new dedicated SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.
Signed-off-by: Laurentiu Tudor
Signed-off-by: Timur Tabi
---
arch/powerpc/include/asm/fsl_liodn.h |5 +
arch/powerpc/include/asm/immap_85xx.h |4 +++-
2 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_liodn.h
b/arch/powerpc/include/asm/fsl_liodn.h
index a9973b8..a37983e 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -94,6 +94,11 @@ extern void fdt_fixup_liodn(void *blob);
SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
+ SET_LIODN_ENTRY_1(compat, liodn,\
+ offsetof(ccsr_pcix_t, liodn_base) +
CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+ CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+
/* reg nodes for DMA start @ 0x300 */
#define SET_DMA_LIODN(dmaNum, liodn) \
SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 7de33a7..6c11178 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -296,7 +296,9 @@ typedef struct ccsr_pcix {
u32 cfg_addr; /* PCIX Configuration Addr */
u32 cfg_data; /* PCIX Configuration Data */
u32 int_ack;/* PCIX IRQ Acknowledge */
- u8 res1[3060];
+ u8 res000c[52];
+ u32 liodn_base; /* PCIX LIODN base register */
+ u8 res0044[3004];
u32 potar0; /* PCIX Outbound Transaction Addr 0 */
u32 potear0;/* PCIX Outbound Translation Extended Addr 0 */
u32 powbar0;/* PCIX Outbound Window Base Addr 0 */
--
1.7.3.4
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[U-Boot] [PATCH 4/6] [v2] powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi
---
The LIODNs for the SEC's DECOs are apparently wrong, but the correct
values are not available. They will be fixed later.
arch/powerpc/cpu/mpc85xx/Makefile |3 +
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 70 +
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h |5 +
arch/powerpc/cpu/mpc85xx/p5040_ids.c | 131 +
arch/powerpc/cpu/mpc85xx/p5040_serdes.c | 117 ++
arch/powerpc/cpu/mpc85xx/speed.c |2 +
arch/powerpc/cpu/mpc8xxx/cpu.c|2 +
arch/powerpc/include/asm/config_mpc85xx.h | 28 +
arch/powerpc/include/asm/immap_85xx.h | 15 +++
arch/powerpc/include/asm/processor.h |2 +
10 files changed, 375 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/p5040_ids.c
create mode 100644 arch/powerpc/cpu/mpc85xx/p5040_serdes.c
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile
b/arch/powerpc/cpu/mpc85xx/Makefile
index 33e93c8..aad50f3 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -66,6 +66,7 @@ COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o
COBJS-$(CONFIG_BSC9131)+= ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
@@ -80,6 +81,7 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o
@@ -110,6 +112,7 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
COBJS = $(COBJS-y)
COBJS += cpu.o
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 2a68060..e6b1b1b 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -92,10 +92,17 @@ static const struct {
{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
+#ifdef CONFIG_PPC_P4080
{ 20, 170, FSL_SRDS_BANK_3 },
{ 21, 171, FSL_SRDS_BANK_3 },
{ 22, 172, FSL_SRDS_BANK_3 },
{ 23, 173, FSL_SRDS_BANK_3 },
+#else
+ { 20, 166, FSL_SRDS_BANK_3 },
+ { 21, 167, FSL_SRDS_BANK_3 },
+ { 22, 168, FSL_SRDS_BANK_3 },
+ { 23, 169, FSL_SRDS_BANK_3 },
+#endif
};
int serdes_get_lane_idx(int lane)
@@ -493,6 +500,9 @@ void fsl_serdes_init(void)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int cfg;
serdes_corenet_t *srds_regs;
+#ifdef CONFIG_PPC_P5040
+ serdes_corenet_t *srds2_regs;
+#endif
int lane, bank, idx;
int have_bank[SRDS_MAX_BANK] = {};
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -574,6 +584,34 @@ void fsl_serdes_init(void)
}
}
+#ifdef CONFIG_PPC_P5040
+ /*
+* Lanes on b
[U-Boot] [PATCH 5/6] powerpc/p5040ds: add per pci endpoint liodn offset list
From: Laurentiu Tudor
Add a new device tree property named "fsl,liodn-offset-list"
holding a list of per pci endpoint permitted liodn offsets.
This property is useful in virtualization scenarios
that implement per pci endpoint partitioning.
The final liodn of a partitioned pci endpoint is
calculated by the hardware, by adding these offsets
to pci controller's base liodn, stored in the
"fsl,liodn" property of its node.
The liodn offsets are interleaved to get better cache
utilization. As an example, given 3 pci controllers,
the following liodns are generated for the pci endpoints:
pci0: 193 256 259 262 265 268 271 274 277
pci1: 194 257 260 263 266 269 272 275 278
pci2: 195 258 261 264 267 270 273 276 279
Signed-off-by: Laurentiu Tudor
---
arch/powerpc/cpu/mpc85xx/liodn.c | 52 ++
1 files changed, 52 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 11881c9..97d6904 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -248,6 +248,56 @@ static void fdt_fixup_srio_liodn(void *blob, struct
srio_liodn_id_table *tbl)
}
}
+#define CONFIG_SYS_MAX_PCI_EPS 8
+#define CONFIG_SYS_PCI_EP_LIODN_START 256
+
+static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
+{
+ int off, pci_idx = 0, pci_cnt = 0, i, rc;
+ const uint32_t *base_liodn;
+ uint32_t liodn_offs[CONFIG_SYS_MAX_PCI_EPS + 1] = { 0 };
+
+ /*
+* Count the number of pci nodes.
+* It's needed later when the interleaved liodn offsets are generated.
+*/
+ off = fdt_node_offset_by_compatible(fdt, -1, compat);
+ while (off != -FDT_ERR_NOTFOUND) {
+ pci_cnt++;
+ off = fdt_node_offset_by_compatible(fdt, off, compat);
+ }
+
+ for (off = fdt_node_offset_by_compatible(fdt, -1, compat);
+off != -FDT_ERR_NOTFOUND;
+off = fdt_node_offset_by_compatible(fdt, off, compat)) {
+ base_liodn = fdt_getprop(fdt, off, "fsl,liodn", &rc);
+ if (!base_liodn) {
+ char path[64];
+
+ if (fdt_get_path(fdt, off, path, sizeof(path)) < 0)
+ strcpy(path, "(unknown)");
+ printf("WARNING Could not get liodn of node %s: %s\n",
+ path, fdt_strerror(rc));
+ continue;
+ }
+ for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++)
+ liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START +
+ i * pci_cnt + pci_idx - *base_liodn;
+ rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list",
+liodn_offs, sizeof(liodn_offs));
+ if (rc) {
+ char path[64];
+
+ if (fdt_get_path(fdt, off, path, sizeof(path)) < 0)
+ strcpy(path, "(unknown)");
+ printf("WARNING Unable to set fsl,liodn-offset-list for
"
+ "node %s: %s\n", path, fdt_strerror(rc));
+ continue;
+ }
+ pci_idx++;
+ }
+}
+
static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
{
int i;
@@ -295,4 +345,6 @@ void fdt_fixup_liodn(void *blob)
#ifdef CONFIG_SYS_DPAA_RMAN
fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
#endif
+
+ fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4");
}
--
1.7.3.4
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[U-Boot] [PATCH 1/6] powerpc/mpc85xx: fix Unicode characters in release.S
Commit 709389b6 unintentionally used the Unicode version of the apostrophy. Replace it with the normal ASCII version. Signed-off-by: Timur Tabi --- arch/powerpc/cpu/mpc85xx/release.S | 24 1 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 22e73e0..8662ae4 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -159,20 +159,20 @@ __secondary_start_page: /* * PIR definition for E6500 * 0-17 Reserved (logic 0s) - * 8-19 CHIP_ID,2’b00 - SoC 1 + * 8-19 CHIP_ID,2'b00 - SoC 1 * all others - reserved - * 20-24 CLUSTER_ID 5’b0 - CCM 1 + * 20-24 CLUSTER_ID 5'b0 - CCM 1 * all others - reserved - * 25-26 CORE_CLUSTER_ID 2’b00 - cluster 1 - * 2’b01 - cluster 2 - * 2’b10 - cluster 3 - * 2’b11 - cluster 4 - * 27-28 CORE_ID 2’b00 - core 0 - * 2’b01 - core 1 - * 2’b10 - core 2 - * 2’b11 - core 3 - * 29-31 THREAD_ID 3’b000 - thread 0 - * 3’b001 - thread 1 + * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1 + * 2'b01 - cluster 2 + * 2'b10 - cluster 3 + * 2'b11 - cluster 4 + * 27-28 CORE_ID 2'b00 - core 0 + * 2'b01 - core 1 + * 2'b10 - core 2 + * 2'b11 - core 3 + * 29-31 THREAD_ID 3'b000 - thread 0 + * 3'b001 - thread 1 */ rlwinm r4,r0,29,25,31 #elif defined(CONFIG_E500MC) -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] SBx81CFC960: embed Fman microcode in the bootloader
Chris Packham wrote: > Good point. I got the firmware out of the SDK that came with our > P2041RDB. I believe the intent was that the Fman microcode is written to > a reserved flash block and downloaded to the frame manager by the OS > when needed. As a Freescale customer I would actually prefer to have the > source released under the GPL and build everything into the u-boot image. For the record, Freescale considers embedding Fman or QE microcode into a "GPL binary" (e.g. a compiled U-boot or Linux image) to be a GPL violation. I'm sure there might be some linker or compiler tricks that some people would say are not GPL violations, but I'm not going to debate any of that. I'm just stating what our official position is. Having said that, I do realize that Freescale still ships some QE firmware binaries as C header/source files that are supposed to be #included into customer code. Unfortunately, not all Freescale developers have gotten the message. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] SBx81CFC960: embed Fman microcode in the bootloader
Wolfgang Denk wrote: > Dear judge.pack...@gmail.com, > > In message <1348216335-18105-1-git-send-email-judge.pack...@gmail.com> you > wrote: >> From: Chris Packham >> >> Instead of storing the mircocode in a separate flash block simply embed >> the image as C code array of bytes. > > What exactly is the licensing of this code? It's not GPL-compatible, so linking the code with U-boot and shipping the binary as one blob is probably a GPL violation. That's why I created the "QE firmware binary format" and wrote all that code to treat the firmware as a separate binary blob. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] arch/powerpc/lib/board.c:get_effective_memsize() for 4GB+ systems
Robert Thorhuus wrote: > Sorry. But this is were I disagree with you. Of course its prime > function is to boot an operating system. And usually in a desktop > environment that is what you need. But if you have newly developed > hardware it is very seldom everything works all the time. There are a > lot of debugging hardware sessions before you have stable hardware. So > in embedded systems I would say U-Boot can very well be a primary > choice of testing platform in the beginning of a development. Mainly > because sucessfully booting U-Boot demands less of the hardware than > sucessfully boot an OS. Say you have a NOR and 1 MB L3 cache but no > DDR3, U-Boot is set, OS not. If you really want to turn U-Boot into a testing platform, feel free to post patches that implement those features. But don't be surprised if your patches are rejected. > And what test platform would you suggest? And what if your extended > testing needs to be a viable option at every boot and that you have > boot time requirements? You can create U-boot "applications" that test your hardware, if you want to test from within U-Boot. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] arch/powerpc/lib/board.c:get_effective_memsize() for 4GB+ systems
Robert Thorhuus wrote: > Still I wonder why the choice was made to have U-Boot relocate in high > memory rather than low memory and also not making it easy to configure > the relocation. U-Boot relocates in high memory so that you can load your operating system at address 0. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] arch/powerpc/lib/board.c:get_effective_memsize() for 4GB+ systems
Robert Thorhuus wrote: > No I will not be using much memory at all for functionality. But the > memory needs to be tested. What is your proposal for that then? We have that already. Look at CONFIG_SYS_POST_MEMORY. It uses sliding 2GB TLBs to test all of DDR. > And I see U-Boot as the first software place for test and debug. Maybe I want > to read out RAM contents? It's a boot loader, not a testing platform. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] QE firmware/microcode handling
Scott Wood wrote: > The 512K limit is arbitrary and can be changed. It exists just to > provide a stable start address on something that grows from the end of > flash. True, but we haven't actually done changed it. Instead of allowing for a larger u-boot.bin, we have ALWAYS disabled features or rewritten code to make it smaller. If making U-boot larger were so simple, it would have been done by now, I think. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] QE firmware/microcode handling
Gerlando Falauto wrote: > Hi everyone, > > following up Timur's patch on QE microcode: > > http://marc.info/?l=u-boot&m=132197537730440&w=2 > > I was wondering, would it make any sense to *embed* QE's firmware within > u-boot image itself? There are three problems: 1) A lot of U-Boot images are already very close to the 512KB limit. We often have to disable features in U-Boot to get it to build properly. An additional 64KB would be prohibitive. 2) The firmware license is not exactly GPL-compatible. The firmware files themselves are freely distributable, but the source code is closed. I'm not sure how that would work in a GPL U-Boot. 3) For Fman, at least, we often update the firmware after the board ships, which means you would need to update U-Boot to get a new firmware. So no one might actually use this feature because they're afraid they won't be able to update the firmware. If you can do it, go ahead. I would approve a patch that adds the ability to inject a firmware binary into u-boot.bin, provided it's controlled via a build or CONFIG_SYS_xxx option. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] video/powerpc: don't touch DIU registers that we don't need
Several DIU registers were being initialized either unnecessarily or to
wrong values.
1) All interrupts were enabled even though there's no interrupt handler.
Interrupts were left enabled when booting Linux.
2) Don't configure a dummy area descriptor, since we don't support ADs
in U-Boot.
3) Don't configure any write-back buffer registers, since we don't use
that mode.
4) The default values for the THRESHOLDS, SYN_POL, and PLUT registers
should be used, so don't touch those registers either.
Signed-off-by: Timur Tabi
---
drivers/video/fsl_diu_fb.c | 21 ++---
1 files changed, 2 insertions(+), 19 deletions(-)
diff --git a/drivers/video/fsl_diu_fb.c b/drivers/video/fsl_diu_fb.c
index 648ffa3..a98cb67 100644
--- a/drivers/video/fsl_diu_fb.c
+++ b/drivers/video/fsl_diu_fb.c
@@ -271,7 +271,6 @@ int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int
gamma_fix)
struct diu *hw = (struct diu *)CONFIG_SYS_DIU_ADDR;
u8 *gamma_table_base;
unsigned int i, j;
- struct diu_ad *dummy_ad;
struct diu_addr gamma;
struct diu_addr cursor;
@@ -302,14 +301,6 @@ int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int
gamma_fix)
return -1;
}
- /* The AD struct for the dummy framebuffer and the FB itself */
- dummy_ad = allocate_fb(2, 4, 4, NULL);
- if (!dummy_ad) {
- printf("DIU: Out of memory\n");
- return -1;
- }
- dummy_ad->pix_fmt = 0x3316;
-
/* read mode info */
info.var.xres = fsl_diu_mode_db->xres;
info.var.yres = fsl_diu_mode_db->yres;
@@ -376,10 +367,7 @@ int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int
gamma_fix)
out_be32(&hw->gamma, gamma.paddr);
out_be32(&hw->cursor, cursor.paddr);
out_be32(&hw->bgnd, 0x007F7F7F);
- out_be32(&hw->bgnd_wb, 0);
out_be32(&hw->disp_size, info.var.yres << 16 | info.var.xres);
- out_be32(&hw->wb_size, 0);
- out_be32(&hw->wb_mem_addr, 0);
out_be32(&hw->hsyn_para, info.var.left_margin << 22 |
info.var.hsync_len << 11 |
info.var.right_margin);
@@ -388,18 +376,13 @@ int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format,
int gamma_fix)
info.var.vsync_len << 11 |
info.var.lower_margin);
- out_be32(&hw->syn_pol, 0);
- out_be32(&hw->thresholds, 0x00037800);
- out_be32(&hw->int_status, 0);
- out_be32(&hw->int_mask, 0);
- out_be32(&hw->plut, 0x01F5F666);
/* Pixel Clock configuration */
diu_set_pixel_clock(info.var.pixclock);
/* Set the frame buffers */
out_be32(&hw->desc[0], virt_to_phys(ad));
- out_be32(&hw->desc[1], virt_to_phys(dummy_ad));
- out_be32(&hw->desc[2], virt_to_phys(dummy_ad));
+ out_be32(&hw->desc[1], 0);
+ out_be32(&hw->desc[2], 0);
/* Enable the DIU, set display to all three planes */
out_be32(&hw->diu_mode, 1);
--
1.7.3.4
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Re: [U-Boot] [u-boot-release] [PATCH 4/5] powerpc/85xx: Add P5040 processor support
Kim Phillips wrote: > no, my patch to add the two extra DECOs was rejected because the > values chosen were based on those in this patch, which were deemed > incorrect by people familiar with LIODN assignment expertise (not > me - I've just identified these values equal to those that were > identified as wrong). Plus, if I'd had reviewed this, it would have > four DECOs by now. Ok, I'll just wait until someone tells me what changes to make to this code. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/5] powerpc/mpc85xx: fix Unicode characters in release.S
The previous commit unintentionally used the Unicode version of the apostrophy. Replace it with the normal ASCII version. Signed-off-by: Timur Tabi --- arch/powerpc/cpu/mpc85xx/release.S | 24 1 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 22e73e0..8662ae4 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -159,20 +159,20 @@ __secondary_start_page: /* * PIR definition for E6500 * 0-17 Reserved (logic 0s) - * 8-19 CHIP_ID,2’b00 - SoC 1 + * 8-19 CHIP_ID,2'b00 - SoC 1 * all others - reserved - * 20-24 CLUSTER_ID 5’b0 - CCM 1 + * 20-24 CLUSTER_ID 5'b0 - CCM 1 * all others - reserved - * 25-26 CORE_CLUSTER_ID 2’b00 - cluster 1 - * 2’b01 - cluster 2 - * 2’b10 - cluster 3 - * 2’b11 - cluster 4 - * 27-28 CORE_ID 2’b00 - core 0 - * 2’b01 - core 1 - * 2’b10 - core 2 - * 2’b11 - core 3 - * 29-31 THREAD_ID 3’b000 - thread 0 - * 3’b001 - thread 1 + * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1 + * 2'b01 - cluster 2 + * 2'b10 - cluster 3 + * 2'b11 - cluster 4 + * 27-28 CORE_ID 2'b00 - core 0 + * 2'b01 - core 1 + * 2'b10 - core 2 + * 2'b11 - core 3 + * 29-31 THREAD_ID 3'b000 - thread 0 + * 3'b001 - thread 1 */ rlwinm r4,r0,29,25,31 #elif defined(CONFIG_E500MC) -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/5] powerpc/85xx: move SRIO configuration out of corenet_ds.h
The P5040 does not have SRIO, so don't put the SRIO definitions in corenet_ds.h. They belong in the board-specific header files. Signed-off-by: Timur Tabi --- include/configs/P3041DS.h|4 include/configs/P4080DS.h|4 include/configs/P5020DS.h|4 include/configs/corenet_ds.h |4 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index 98e7a42..cf184e7 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -36,6 +36,10 @@ #define CONFIG_PCIE4 #define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ2500 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index d6f2f5c..53979dd 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -33,6 +33,10 @@ #define CONFIG_MMC #define CONFIG_PCIE3 +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ3000 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 8625f76..7018d7a 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -37,6 +37,10 @@ #define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ2500 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f4f9bd1..0f59fb2 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -76,10 +76,6 @@ #define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ - #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/5] powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi
---
board/freescale/common/Makefile |2 +
board/freescale/corenet_ds/Makefile |2 +
board/freescale/corenet_ds/eth_superhydra.c | 722 +++
board/freescale/corenet_ds/p5040ds_ddr.c| 18 +
boards.cfg |1 +
drivers/net/fm/Makefile |1 +
drivers/net/fm/p5040.c | 113 +
include/configs/P5040DS.h | 40 ++
8 files changed, 899 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/corenet_ds/eth_superhydra.c
create mode 100644 board/freescale/corenet_ds/p5040ds_ddr.c
create mode 100644 drivers/net/fm/p5040.c
create mode 100644 include/configs/P5040DS.h
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 54cb098..dd93b32 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -53,12 +53,14 @@ COBJS-$(CONFIG_P2020DS) += ics307_clk.o
COBJS-$(CONFIG_P3041DS)+= ics307_clk.o
COBJS-$(CONFIG_P4080DS)+= ics307_clk.o
COBJS-$(CONFIG_P5020DS)+= ics307_clk.o
+COBJS-$(CONFIG_P5040DS)+= ics307_clk.o
# deal with common files for P-series corenet based devices
SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o
+SUBLIB-$(CONFIG_P5040DS) += p_corenet/libp_corenet.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/freescale/corenet_ds/Makefile
b/board/freescale/corenet_ds/Makefile
index 1fdf8b7..d79193a 100644
--- a/board/freescale/corenet_ds/Makefile
+++ b/board/freescale/corenet_ds/Makefile
@@ -31,9 +31,11 @@ COBJS-y += ddr.o
COBJS-$(CONFIG_P3041DS)+= eth_hydra.o
COBJS-$(CONFIG_P4080DS)+= eth_p4080.o
COBJS-$(CONFIG_P5020DS)+= eth_hydra.o
+COBJS-$(CONFIG_P5040DS)+= eth_superhydra.o
COBJS-$(CONFIG_P3041DS)+= p3041ds_ddr.o
COBJS-$(CONFIG_P4080DS)+= p4080ds_ddr.o
COBJS-$(CONFIG_P5020DS)+= p5020ds_ddr.o
+COBJS-$(CONFIG_P5040DS)+= p5040ds_ddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/freescale/corenet_ds/eth_superhydra.c
b/board/freescale/corenet_ds/eth_superhydra.c
new file mode 100644
index 000..ef9de25
--- /dev/null
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -0,0 +1,722 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ * Author: Srikanth Srinivasan
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file handles the board muxing between the Fman Ethernet MACs and
+ * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference
+ * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
+ * provided by the standard Freescale four-port SGMII riser card. The 10Gb
+ * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans
+ * and 5 1G interfaces and 10G interface per FMan. Based on the options in
+ * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time.
+ *
+ * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
+ * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
+ * always the same (0). The value for SGMII depends on which slot the riser is
+ * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
+ * the value is based on which slot the XAUI is inserted in.
+ *
+ * The SERDES configuration is used to determine where the SGMII and XAUI cards
+ * exist, and also which Fman's MACs are routed to which PHYs. So for a given
+ * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
+ * to PHYs dynamically.
+ *
+ *
+ * This file also updates the device tree in three ways:
+ *
+ * 1) The status of each virtual
[U-Boot] [PATCH 4/5] powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi
---
arch/powerpc/cpu/mpc85xx/Makefile |3 +
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 43
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h | 11 ++
arch/powerpc/cpu/mpc85xx/p5040_ids.c | 131 +
arch/powerpc/cpu/mpc85xx/p5040_serdes.c | 110 +
arch/powerpc/cpu/mpc85xx/speed.c |2 +
arch/powerpc/cpu/mpc8xxx/cpu.c|2 +
arch/powerpc/include/asm/config_mpc85xx.h | 28 +
arch/powerpc/include/asm/immap_85xx.h | 12 +++
arch/powerpc/include/asm/processor.h |2 +
10 files changed, 344 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/p5040_ids.c
create mode 100644 arch/powerpc/cpu/mpc85xx/p5040_serdes.c
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile
b/arch/powerpc/cpu/mpc85xx/Makefile
index 33e93c8..aad50f3 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -66,6 +66,7 @@ COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o
COBJS-$(CONFIG_BSC9131)+= ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
@@ -80,6 +81,7 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o
@@ -110,6 +112,7 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
COBJS = $(COBJS-y)
COBJS += cpu.o
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 2a68060..efafbd0 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -92,10 +92,21 @@ static const struct {
{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
+#ifdef CONFIG_PPC_P4080
{ 20, 170, FSL_SRDS_BANK_3 },
{ 21, 171, FSL_SRDS_BANK_3 },
{ 22, 172, FSL_SRDS_BANK_3 },
{ 23, 173, FSL_SRDS_BANK_3 },
+#else
+ { 20, 166, FSL_SRDS_BANK_3 },
+ { 21, 167, FSL_SRDS_BANK_3 },
+ { 22, 168, FSL_SRDS_BANK_3 },
+ { 23, 169, FSL_SRDS_BANK_3 },
+#endif
+#if SRDS_MAX_BANK > 3
+ { 24, 175, FSL_SRDS_BANK_4 },
+ { 25, 176, FSL_SRDS_BANK_4 },
+#endif
};
int serdes_get_lane_idx(int lane)
@@ -617,6 +628,38 @@ void fsl_serdes_init(void)
}
}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004699
+ /*
+* To avoid the situation that resulted in the P4080 erratum
+* SERDES-8, a given SerDes bank will use the PLLs from the previous
+* bank if one of the PLL frequencies is a multiple of the other. For
+* instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz,
+* then bank 3 will use bank 2's PLL. P5040 Erratum A-004
[U-Boot] [PATCH 2/5] powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs
From: Laurentiu Tudor
The liodn for the new PCIE controller included in P5040DS is no longer set
through a register in the guts register block but with one in the PCIE
register block itself. Update the PCIE CCSR structure to add the new liodn
register and add a new dedicated SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.
Signed-off-by: Laurentiu Tudor
Signed-off-by: Timur Tabi
---
arch/powerpc/include/asm/fsl_liodn.h |5 +
arch/powerpc/include/asm/immap_85xx.h |4 +++-
2 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_liodn.h
b/arch/powerpc/include/asm/fsl_liodn.h
index a9973b8..a37983e 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -94,6 +94,11 @@ extern void fdt_fixup_liodn(void *blob);
SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
+ SET_LIODN_ENTRY_1(compat, liodn,\
+ offsetof(ccsr_pcix_t, liodn_base) +
CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+ CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+
/* reg nodes for DMA start @ 0x300 */
#define SET_DMA_LIODN(dmaNum, liodn) \
SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 7de33a7..6c11178 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -296,7 +296,9 @@ typedef struct ccsr_pcix {
u32 cfg_addr; /* PCIX Configuration Addr */
u32 cfg_data; /* PCIX Configuration Data */
u32 int_ack;/* PCIX IRQ Acknowledge */
- u8 res1[3060];
+ u8 res000c[52];
+ u32 liodn_base; /* PCIX LIODN base register */
+ u8 res0044[3004];
u32 potar0; /* PCIX Outbound Transaction Addr 0 */
u32 potear0;/* PCIX Outbound Translation Extended Addr 0 */
u32 powbar0;/* PCIX Outbound Window Base Addr 0 */
--
1.7.3.4
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Re: [U-Boot] [PATCH 6/7] powerpc/85xx: update P4080DS MDIO bus multiplexer support
Kumar Gala wrote: > I think we need to hold on this patch until we have a kernel somewhere that > can actually utilize it. *sigh* And here I was hoping I would get this done for the next release. > I'm guessing this would break the SDK mux support for p4080ds? Assuming we don't back-port the kernel code, which I've already done for my testing. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/7] powerpc/85xx: add support for FM2 DTSEC5
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.
Signed-off-by: Timur Tabi
---
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c |6 ++
arch/powerpc/include/asm/fsl_serdes.h |1 +
arch/powerpc/include/asm/immap_85xx.h |1 +
drivers/net/fm/init.c |3 +++
include/fm_eth.h |1 +
5 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 4b52dad..8aac1de 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -68,6 +68,7 @@ static const char *serdes_prtcl_str[] = {
[SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
[SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
[SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
+ [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
[XAUI_FM1] = "XAUI_FM1",
[XAUI_FM2] = "XAUI_FM2",
[AURORA] = "DEBUG",
@@ -658,6 +659,7 @@ void fsl_serdes_init(void)
case SGMII_FM2_DTSEC2:
case SGMII_FM2_DTSEC3:
case SGMII_FM2_DTSEC4:
+ case SGMII_FM2_DTSEC5:
case XAUI_FM1:
case XAUI_FM2:
case SRIO1:
@@ -717,6 +719,10 @@ void fsl_serdes_init(void)
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
FSL_CORENET_DEVDISR2_DTSEC2_4;
break;
+ case SGMII_FM2_DTSEC5:
+ serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
+ FSL_CORENET_DEVDISR2_DTSEC2_5;
+ break;
case XAUI_FM1:
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1|
FSL_CORENET_DEVDISR2_10GEC1;
diff --git a/arch/powerpc/include/asm/fsl_serdes.h
b/arch/powerpc/include/asm/fsl_serdes.h
index 0f31af1..22525f1 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -41,6 +41,7 @@ enum srds_prtcl {
SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3,
SGMII_FM2_DTSEC4,
+ SGMII_FM2_DTSEC5,
SGMII_TSEC1,
SGMII_TSEC2,
SGMII_TSEC3,
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 53d563e..42dd89c 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1729,6 +1729,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x4000
#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x2000
#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x1000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x0800
#define FSL_CORENET_NUM_DEVDISR2
u8 res7[8];
u32 powmgtcsr; /* Power management status & control */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 953c359..9834cd9 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -50,6 +50,9 @@ struct fm_eth_info fm_info[] = {
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
FM_DTSEC_INFO_INITIALIZER(2, 4),
#endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
+ FM_DTSEC_INFO_INITIALIZER(2, 5),
+#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(1, 1),
#endif
diff --git a/include/fm_eth.h b/include/fm_eth.h
index c7c6882..05121ea 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -35,6 +35,7 @@ enum fm_port {
FM2_DTSEC2,
FM2_DTSEC3,
FM2_DTSEC4,
+ FM2_DTSEC5,
FM2_10GEC1,
NUM_FM_PORTS,
};
--
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[U-Boot] [PATCH 6/7] powerpc/85xx: update P4080DS MDIO bus multiplexer support
The Freescale P4080DS has a complex multiplexed MDIO bus, where the
muxing varies per SerDes protocol. This is because the protocol
determines in which PCI slot the various SGMII and XGMII interface
cards belong, as well as whether the RGMII ports are enabled.
The Freescale SDK includes support for MDIO bus multiplexing, but the
upstream Linux kernel uses David Daney's (Cavium) method instead.
Therefore, the P4080 code needs to be migrated to the new method.
The device tree contains two top-level mdio-mux nodes, one for EMI1
(RGMII and SGMII) and the other for EMI2 (XGMII). The U-boot code
depends on several device tree aliases to help it find the nodes that
need to be updated.
Signed-off-by: Timur Tabi
---
board/freescale/corenet_ds/eth_p4080.c | 172
1 files changed, 129 insertions(+), 43 deletions(-)
diff --git a/board/freescale/corenet_ds/eth_p4080.c
b/board/freescale/corenet_ds/eth_p4080.c
index 2c69c51..3c1c3a1 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -53,7 +53,7 @@
#define EMI1_MASK 0xc000
#define EMI2_MASK 0x3000
-static int mdio_mux[NUM_FM_PORTS];
+static u32 mdio_mux[NUM_FM_PORTS];
static char *mdio_names[16] = {
"P4080DS_MDIO0",
@@ -232,73 +232,159 @@ static int p4080ds_mdio_init(char *realbusname, u32
muxval)
return mdio_register(bus);
}
-void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
- enum fm_port port, int offset)
+/*
+ * Given the following ...
+ *
+ * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
+ * compatible string and 'addr' physical address)
+ *
+ * 2) An Fman port
+ *
+ * ... update the phy-handle property of the Ethernet node to point to the
+ * right PHY. This assumes that we already know the PHY for each port.
+ *
+ * The PHY type (RGMII, SGMII, XGMII) is already set via a prior call to
+ * fdt_fixup_phy_connection(). The parent mdio-mux node will be enabled later
+ * in fdt_fixup_board_enet().
+ *
+ * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
+ * Inside the Fman, "ports" are things that connect to MACs. We only call
+ * them ports in U-Boot because on previous Ethernet devices (e.g. Gianfar),
+ * MACs and ports are the same thing.
+ *
+ * XGMII Ethernet nodes are already mapped correctly, so we ignore those.
+ */
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
{
- if (mdio_mux[port] == EMI1_RGMII)
- fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
-
- if (mdio_mux[port] == EMI1_SLOT3) {
- int idx = port - FM2_DTSEC1 + 5;
- char phy[16];
+ phy_interface_t phyc = fm_info_get_enet_if(port);
+ enum srds_prtcl device;
+ int lane;
+ int ret = 0;
+
+ switch (phyc) {
+ case PHY_INTERFACE_MODE_RGMII:
+ debug("Setting phy-handle for ethernet@%llx to RGMII\n", addr);
+ ret = fdt_set_phy_handle(fdt, compat, addr, "phy_rgmii");
+ break;
+
+ case PHY_INTERFACE_MODE_SGMII:
+ device = serdes_device_from_fm_port(port);
+ lane = serdes_get_first_lane(device);
+
+ if (lane >= 0) {
+ unsigned int slot = lane_to_slot[lane];
+ int phy = fm_info_get_phy_address(port);
+ char alias[32];
+
+ debug("Setting phy-handle for ethernet@%llx to slot %u,"
+ " addr %x\n", addr, slot, phy);
+ sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy);
+ ret = fdt_set_phy_handle(fdt, compat, addr, alias);
+ }
+ break;
- sprintf(phy, "phy%d_slot3", idx);
+ default:
+ /* XGMII nodes are already linked in the DTS */
+ debug("Skipping phy-handle setup for %s ethernet@%llx\n",
+ phy_interface_strings[phyc], addr);
+ break;
+ }
- fdt_set_phy_handle(blob, prop, pa, phy);
+ if (ret < 0) {
+ printf("Fman: could not set phy-handle for ethernet@%llx "
+ "(%s)\n", addr, fdt_strerror(ret));
}
}
void fdt_fixup_board_enet(void *fdt)
{
- int i;
-
- /*
-* P4080DS can be configured in many different ways, supporting a number
-* of combinations of ethernet devices and phy types. In order to
-* have just one device tree for all of those configurations, we fix up
-* the tree here. By default, the device tree configures FM1 and FM2
-* for SGMII, and configures XAUI on b
[U-Boot] [PATCH 3/7] [v2] powerpc/85xx: introduce function serdes_device_from_fm_port()
In order to figure out which SerDes lane a given Fman port is connected
to, we need a function that maps the fm_port namespace to the srds_prtcl
namespace.
Signed-off-by: Timur Tabi
---
board/freescale/common/fman.c | 31 +++
board/freescale/common/fman.h |2 ++
2 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c
index 6ddf816..3ef4936 100644
--- a/board/freescale/common/fman.c
+++ b/board/freescale/common/fman.c
@@ -25,6 +25,9 @@
#include
#include
+#include
+#include
+
/*
* Given the following ...
*
@@ -67,3 +70,31 @@ int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t
addr,
return fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph));
}
+
+/*
+ * Return the SerDes device enum for a given Fman port
+ *
+ * This function just maps the fm_port namespace to the srds_prtcl namespace.
+ */
+enum srds_prtcl serdes_device_from_fm_port(enum fm_port port)
+{
+ static const enum srds_prtcl srds_table[] = {
+ [FM1_DTSEC1] = SGMII_FM1_DTSEC1,
+ [FM1_DTSEC2] = SGMII_FM1_DTSEC2,
+ [FM1_DTSEC3] = SGMII_FM1_DTSEC3,
+ [FM1_DTSEC4] = SGMII_FM1_DTSEC4,
+ [FM1_DTSEC5] = SGMII_FM1_DTSEC5,
+ [FM1_10GEC1] = XAUI_FM1,
+ [FM2_DTSEC1] = SGMII_FM2_DTSEC1,
+ [FM2_DTSEC2] = SGMII_FM2_DTSEC2,
+ [FM2_DTSEC3] = SGMII_FM2_DTSEC3,
+ [FM2_DTSEC4] = SGMII_FM2_DTSEC4,
+ [FM2_DTSEC5] = SGMII_FM2_DTSEC5,
+ [FM2_10GEC1] = XAUI_FM2,
+ };
+
+ if ((port < FM1_DTSEC1) || (port > FM2_10GEC1))
+ return NONE;
+ else
+ return srds_table[port];
+}
diff --git a/board/freescale/common/fman.h b/board/freescale/common/fman.h
index d39ef08..734b1da 100644
--- a/board/freescale/common/fman.h
+++ b/board/freescale/common/fman.h
@@ -23,4 +23,6 @@
int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
const char *alias);
+enum srds_prtcl serdes_device_from_fm_port(enum fm_port port);
+
#endif
--
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[U-Boot] [PATCH 4/7] fm-eth: use fdt_status_disabled() function in ft_fixup_port()
We have a dedicated function for setting the node status now, so use it.
Also improve a comment and fix the type of the phandle variable.
Signed-off-by: Timur Tabi
---
drivers/net/fm/init.c | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 8a5311c..736b8b9 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -200,7 +200,8 @@ void board_ft_fman_fixup_port(void *blob, char * prop,
phys_addr_t pa,
static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
{
- int off, ph;
+ int off;
+ uint32_t ph;
phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
@@ -217,12 +218,10 @@ static void ft_fixup_port(void *blob, struct fm_eth_info
*info, char *prop)
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
/* Don't disable FM1-DTSEC1 MAC as its used for MDIO */
- if (paddr != dtsec1_addr) {
- /* disable the mac node */
- fdt_setprop_string(blob, off, "status", "disabled");
- }
+ if (paddr != dtsec1_addr)
+ fdt_status_disabled(blob, off); /* disable the MAC node */
- /* disable the node point to the mac */
+ /* disable the fsl,dpa-ethernet node that points to the MAC */
ph = fdt_get_phandle(blob, off);
do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph),
"status", "disabled", strlen("disabled") + 1, 1);
--
1.7.3.4
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[U-Boot] [PATCH 2/7] fm-eth: add function fm_info_get_phy_address()
Function fm_info_get_phy_address() returns the PHY address for a given
Fman port. This is handy when the MDIO code needs to fixup the Ethernet
nodes in the device tree to point to PHY nodes for a specific PHY address.
Signed-off-by: Timur Tabi
---
drivers/net/fm/init.c | 16
include/fm_eth.h |1 +
2 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 9834cd9..8a5311c 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -155,6 +155,22 @@ void fm_info_set_phy_address(enum fm_port port, int
address)
}
/*
+ * Returns the PHY address for a given Fman port
+ *
+ * The port must be set via a prior call to fm_info_set_phy_address().
+ * A negative error code is returned if the port is invalid.
+ */
+int fm_info_get_phy_address(enum fm_port port)
+{
+ int i = fm_port_to_index(port);
+
+ if (i == -1)
+ return -1;
+
+ return fm_info[i].phy_addr;
+}
+
+/*
* Returns the type of the data interface between the given MAC and its PHY.
* This is typically determined by the RCW.
*/
diff --git a/include/fm_eth.h b/include/fm_eth.h
index 05121ea..e56541d 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -110,6 +110,7 @@ void fman_enet_init(void);
void fdt_fixup_fman_ethernet(void *fdt);
phy_interface_t fm_info_get_enet_if(enum fm_port port);
void fm_info_set_phy_address(enum fm_port port, int address);
+int fm_info_get_phy_address(enum fm_port port);
void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
void fm_disable_port(enum fm_port port);
--
1.7.3.4
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[U-Boot] [PATCH 5/7] powerpc/85xx: get rid of enum board_slots in P4080 MDIO driver
enum board_slots contained six values, where SLOT1 == 1, SLOT2 == 2, and
so on. This is pointless, so remove it. Also move the lane_to_slot[]
array to the top of the file so that it can be used by other functions.
Signed-off-by: Timur Tabi
---
board/freescale/corenet_ds/eth_p4080.c | 59 ++-
1 files changed, 19 insertions(+), 40 deletions(-)
diff --git a/board/freescale/corenet_ds/eth_p4080.c
b/board/freescale/corenet_ds/eth_p4080.c
index b87b092..2c69c51 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -68,6 +68,15 @@ static char *mdio_names[16] = {
NULL, NULL, NULL,
};
+/*
+ * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot.
+ */
+static u8 lane_to_slot[] = {
+ 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
+};
+
static char *p4080ds_mdio_name_for_muxval(u32 muxval)
{
return mdio_names[(muxval & EMI_MASK) >> 28];
@@ -290,15 +299,6 @@ void fdt_fixup_board_enet(void *fdt)
}
}
-enum board_slots {
- SLOT1 = 1,
- SLOT2,
- SLOT3,
- SLOT4,
- SLOT5,
- SLOT6,
-};
-
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
@@ -307,27 +307,6 @@ int board_eth_init(bd_t *bis)
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
- u8 lane_to_slot[] = {
- SLOT1, /* 0 - Bank 1:A */
- SLOT1, /* 1 - Bank 1:B */
- SLOT2, /* 2 - Bank 1:C */
- SLOT2, /* 3 - Bank 1:D */
- SLOT3, /* 4 - Bank 1:E */
- SLOT3, /* 5 - Bank 1:F */
- SLOT3, /* 6 - Bank 1:G */
- SLOT3, /* 7 - Bank 1:H */
- SLOT6, /* 8 - Bank 1:I */
- SLOT6, /* 9 - Bank 1:J */
- SLOT4, /* 10 - Bank 2:A */
- SLOT4, /* 11 - Bank 2:B */
- SLOT4, /* 12 - Bank 2:C */
- SLOT4, /* 13 - Bank 2:D */
- SLOT5, /* 14 - Bank 3:A */
- SLOT5, /* 15 - Bank 3:B */
- SLOT5, /* 16 - Bank 3:C */
- SLOT5, /* 17 - Bank 3:D */
- };
-
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
@@ -380,17 +359,17 @@ int board_eth_init(bd_t *bis)
break;
slot = lane_to_slot[lane];
switch (slot) {
- case SLOT3:
+ case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
- case SLOT4:
+ case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
- case SLOT5:
+ case 5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
@@ -417,12 +396,12 @@ int board_eth_init(bd_t *bis)
break;
slot = lane_to_slot[lane];
switch (slot) {
- case SLOT4:
+ case 4:
mdio_mux[i] = EMI2_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
- case SLOT5:
+ case 5:
mdio_mux[i] = EMI2_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
@@ -444,17 +423,17 @@ int board_eth_init(bd_t *bis)
break;
slot = lane_to_slot[lane];
switch (slot) {
- case SLOT3:
+ case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
- case SLOT4:
+ case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
-
Re: [U-Boot] [u-boot-release] [PATCH 3/6] powerpc/85xx: introduce function serdes_device_from_fm_port()
Kim Phillips wrote: > it's ~30% less lines of code, and the maps lie on the same line, > which helps when grepping. OK. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot-release] [PATCH 3/6] powerpc/85xx: introduce function serdes_device_from_fm_port()
Kim Phillips wrote:
> please don't post patches upstream with '[u-boot-release]' in the
> subject.
I didn't.
http://lists.denx.de/pipermail/u-boot/2012-August/130618.html
Your mailer is confused. I bcc the u-boot-release mailing list, and I
presume your mailer (or our mail server) sent you that copy of the mail
instead of the "real" one.
> shouldn't this be a static const array lookup?
The compiler should convert it into an array lookup automatically, but I
can change it if you insist. Since I don't like writing code that depends
on the values of an enum, the array will look like this:
static const enum srds_prtcl srds_table[] = {
[FM1_DTSEC1] = SGMII_FM1_DTSEC1,
[FM1_DTSEC2] = SGMII_FM1_DTSEC2,
[FM1_DTSEC3] = SGMII_FM1_DTSEC3,
[FM1_DTSEC4] = SGMII_FM1_DTSEC4,
[FM1_DTSEC5] = SGMII_FM1_DTSEC5,
[FM1_10GEC1] = XAUI_FM1,
[FM2_DTSEC1] = SGMII_FM2_DTSEC1,
[FM2_DTSEC2] = SGMII_FM2_DTSEC2,
[FM2_DTSEC3] = SGMII_FM2_DTSEC3,
[FM2_DTSEC4] = SGMII_FM2_DTSEC4,
[FM2_DTSEC5] = SGMII_FM2_DTSEC5,
[FM2_10GEC1] = XAUI_FM2,
};
if ((port < FM1_DTSEC1) || (port > FM2_10GEC1))
return NONE;
else
return srds_table[port];
I'm not sure that's an improvement.
--
Timur Tabi
Linux kernel developer at Freescale
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[U-Boot] [PATCH 3/6] powerpc/85xx: introduce function serdes_device_from_fm_port()
In order to figure out which SerDes lane a given Fman port is connected
to, we need a function that maps the fm_port namespace to the srds_prtcl
namespace.
Signed-off-by: Timur Tabi
---
board/freescale/common/fman.c | 40
board/freescale/common/fman.h |2 ++
2 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c
index 6ddf816..58b7c44 100644
--- a/board/freescale/common/fman.c
+++ b/board/freescale/common/fman.c
@@ -25,6 +25,9 @@
#include
#include
+#include
+#include
+
/*
* Given the following ...
*
@@ -67,3 +70,40 @@ int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t
addr,
return fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph));
}
+
+/*
+ * Return the SerDes device enum for a given Fman port
+ *
+ * This function just maps the fm_port namespace to the srds_prtcl namespace.
+ */
+enum srds_prtcl serdes_device_from_fm_port(enum fm_port port)
+{
+ switch (port) {
+ case FM1_DTSEC1:
+ return SGMII_FM1_DTSEC1;
+ case FM1_DTSEC2:
+ return SGMII_FM1_DTSEC2;
+ case FM1_DTSEC3:
+ return SGMII_FM1_DTSEC3;
+ case FM1_DTSEC4:
+ return SGMII_FM1_DTSEC4;
+ case FM1_DTSEC5:
+ return SGMII_FM1_DTSEC5;
+ case FM1_10GEC1:
+ return XAUI_FM1;
+ case FM2_DTSEC1:
+ return SGMII_FM2_DTSEC1;
+ case FM2_DTSEC2:
+ return SGMII_FM2_DTSEC2;
+ case FM2_DTSEC3:
+ return SGMII_FM2_DTSEC3;
+ case FM2_DTSEC4:
+ return SGMII_FM2_DTSEC4;
+ case FM2_DTSEC5:
+ return SGMII_FM2_DTSEC5;
+ case FM2_10GEC1:
+ return XAUI_FM2;
+ default:
+ return NONE;
+ }
+}
diff --git a/board/freescale/common/fman.h b/board/freescale/common/fman.h
index d39ef08..734b1da 100644
--- a/board/freescale/common/fman.h
+++ b/board/freescale/common/fman.h
@@ -23,4 +23,6 @@
int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
const char *alias);
+enum srds_prtcl serdes_device_from_fm_port(enum fm_port port);
+
#endif
--
1.7.3.4
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[U-Boot] [PATCH 5/6] powerpc/85xx: get rid of enum board_slots in P4080 MDIO driver
enum board_slots contained six values, where SLOT1 == 1, SLOT2 == 2, and
so on. This is pointless, so remove it. Also move the lane_to_slot[]
array to the top of the file so that it can be used by other functions.
Signed-off-by: Timur Tabi
---
board/freescale/corenet_ds/eth_p4080.c | 59 ++-
1 files changed, 19 insertions(+), 40 deletions(-)
diff --git a/board/freescale/corenet_ds/eth_p4080.c
b/board/freescale/corenet_ds/eth_p4080.c
index b87b092..2c69c51 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -68,6 +68,15 @@ static char *mdio_names[16] = {
NULL, NULL, NULL,
};
+/*
+ * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot.
+ */
+static u8 lane_to_slot[] = {
+ 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
+};
+
static char *p4080ds_mdio_name_for_muxval(u32 muxval)
{
return mdio_names[(muxval & EMI_MASK) >> 28];
@@ -290,15 +299,6 @@ void fdt_fixup_board_enet(void *fdt)
}
}
-enum board_slots {
- SLOT1 = 1,
- SLOT2,
- SLOT3,
- SLOT4,
- SLOT5,
- SLOT6,
-};
-
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
@@ -307,27 +307,6 @@ int board_eth_init(bd_t *bis)
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
- u8 lane_to_slot[] = {
- SLOT1, /* 0 - Bank 1:A */
- SLOT1, /* 1 - Bank 1:B */
- SLOT2, /* 2 - Bank 1:C */
- SLOT2, /* 3 - Bank 1:D */
- SLOT3, /* 4 - Bank 1:E */
- SLOT3, /* 5 - Bank 1:F */
- SLOT3, /* 6 - Bank 1:G */
- SLOT3, /* 7 - Bank 1:H */
- SLOT6, /* 8 - Bank 1:I */
- SLOT6, /* 9 - Bank 1:J */
- SLOT4, /* 10 - Bank 2:A */
- SLOT4, /* 11 - Bank 2:B */
- SLOT4, /* 12 - Bank 2:C */
- SLOT4, /* 13 - Bank 2:D */
- SLOT5, /* 14 - Bank 3:A */
- SLOT5, /* 15 - Bank 3:B */
- SLOT5, /* 16 - Bank 3:C */
- SLOT5, /* 17 - Bank 3:D */
- };
-
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
@@ -380,17 +359,17 @@ int board_eth_init(bd_t *bis)
break;
slot = lane_to_slot[lane];
switch (slot) {
- case SLOT3:
+ case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
- case SLOT4:
+ case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
- case SLOT5:
+ case 5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
@@ -417,12 +396,12 @@ int board_eth_init(bd_t *bis)
break;
slot = lane_to_slot[lane];
switch (slot) {
- case SLOT4:
+ case 4:
mdio_mux[i] = EMI2_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
- case SLOT5:
+ case 5:
mdio_mux[i] = EMI2_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
@@ -444,17 +423,17 @@ int board_eth_init(bd_t *bis)
break;
slot = lane_to_slot[lane];
switch (slot) {
- case SLOT3:
+ case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
- case SLOT4:
+ case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
-
[U-Boot] [PATCH 4/6] fm-eth: use fdt_status_disabled() function in ft_fixup_port()
We have a dedicated function for setting the node status now, so use it.
Also improve a comment and fix the type of the phandle variable.
Signed-off-by: Timur Tabi
---
drivers/net/fm/init.c | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 8a5311c..736b8b9 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -200,7 +200,8 @@ void board_ft_fman_fixup_port(void *blob, char * prop,
phys_addr_t pa,
static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
{
- int off, ph;
+ int off;
+ uint32_t ph;
phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
@@ -217,12 +218,10 @@ static void ft_fixup_port(void *blob, struct fm_eth_info
*info, char *prop)
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
/* Don't disable FM1-DTSEC1 MAC as its used for MDIO */
- if (paddr != dtsec1_addr) {
- /* disable the mac node */
- fdt_setprop_string(blob, off, "status", "disabled");
- }
+ if (paddr != dtsec1_addr)
+ fdt_status_disabled(blob, off); /* disable the MAC node */
- /* disable the node point to the mac */
+ /* disable the fsl,dpa-ethernet node that points to the MAC */
ph = fdt_get_phandle(blob, off);
do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph),
"status", "disabled", strlen("disabled") + 1, 1);
--
1.7.3.4
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[U-Boot] [PATCH 6/6] powerpc/85xx: update P4080DS MDIO bus multiplexer support
The Freescale P4080DS has a complex multiplexed MDIO bus, where the
muxing varies per SerDes protocol. This is because the protocol
determines in which PCI slot the various SGMII and XGMII interface
cards belong, as well as whether the RGMII ports are enabled.
The Freescale SDK includes support for MDIO bus multiplexing, but the
upstream Linux kernel uses David Daney's (Cavium) method instead.
Therefore, the P4080 code needs to be migrated to the new method.
The device tree contains two top-level mdio-mux nodes, one for EMI1
(RGMII and SGMII) and the other for EMI2 (XGMII). The U-boot code
depends on several device tree aliases to help it find the nodes that
need to be updated.
Signed-off-by: Timur Tabi
---
board/freescale/corenet_ds/eth_p4080.c | 172
1 files changed, 129 insertions(+), 43 deletions(-)
diff --git a/board/freescale/corenet_ds/eth_p4080.c
b/board/freescale/corenet_ds/eth_p4080.c
index 2c69c51..3c1c3a1 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -53,7 +53,7 @@
#define EMI1_MASK 0xc000
#define EMI2_MASK 0x3000
-static int mdio_mux[NUM_FM_PORTS];
+static u32 mdio_mux[NUM_FM_PORTS];
static char *mdio_names[16] = {
"P4080DS_MDIO0",
@@ -232,73 +232,159 @@ static int p4080ds_mdio_init(char *realbusname, u32
muxval)
return mdio_register(bus);
}
-void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
- enum fm_port port, int offset)
+/*
+ * Given the following ...
+ *
+ * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
+ * compatible string and 'addr' physical address)
+ *
+ * 2) An Fman port
+ *
+ * ... update the phy-handle property of the Ethernet node to point to the
+ * right PHY. This assumes that we already know the PHY for each port.
+ *
+ * The PHY type (RGMII, SGMII, XGMII) is already set via a prior call to
+ * fdt_fixup_phy_connection(). The parent mdio-mux node will be enabled later
+ * in fdt_fixup_board_enet().
+ *
+ * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
+ * Inside the Fman, "ports" are things that connect to MACs. We only call
+ * them ports in U-Boot because on previous Ethernet devices (e.g. Gianfar),
+ * MACs and ports are the same thing.
+ *
+ * XGMII Ethernet nodes are already mapped correctly, so we ignore those.
+ */
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
{
- if (mdio_mux[port] == EMI1_RGMII)
- fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
-
- if (mdio_mux[port] == EMI1_SLOT3) {
- int idx = port - FM2_DTSEC1 + 5;
- char phy[16];
+ phy_interface_t phyc = fm_info_get_enet_if(port);
+ enum srds_prtcl device;
+ int lane;
+ int ret = 0;
+
+ switch (phyc) {
+ case PHY_INTERFACE_MODE_RGMII:
+ debug("Setting phy-handle for ethernet@%llx to RGMII\n", addr);
+ ret = fdt_set_phy_handle(fdt, compat, addr, "phy_rgmii");
+ break;
+
+ case PHY_INTERFACE_MODE_SGMII:
+ device = serdes_device_from_fm_port(port);
+ lane = serdes_get_first_lane(device);
+
+ if (lane >= 0) {
+ unsigned int slot = lane_to_slot[lane];
+ int phy = fm_info_get_phy_address(port);
+ char alias[32];
+
+ debug("Setting phy-handle for ethernet@%llx to slot %u,"
+ " addr %x\n", addr, slot, phy);
+ sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy);
+ ret = fdt_set_phy_handle(fdt, compat, addr, alias);
+ }
+ break;
- sprintf(phy, "phy%d_slot3", idx);
+ default:
+ /* XGMII nodes are already linked in the DTS */
+ debug("Skipping phy-handle setup for %s ethernet@%llx\n",
+ phy_interface_strings[phyc], addr);
+ break;
+ }
- fdt_set_phy_handle(blob, prop, pa, phy);
+ if (ret < 0) {
+ printf("Fman: could not set phy-handle for ethernet@%llx "
+ "(%s)\n", addr, fdt_strerror(ret));
}
}
void fdt_fixup_board_enet(void *fdt)
{
- int i;
-
- /*
-* P4080DS can be configured in many different ways, supporting a number
-* of combinations of ethernet devices and phy types. In order to
-* have just one device tree for all of those configurations, we fix up
-* the tree here. By default, the device tree configures FM1 and FM2
-* for SGMII, and configures XAUI on b
[U-Boot] [PATCH 1/6] powerpc/85xx: add support for FM2 DTSEC5
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.
Signed-off-by: Timur Tabi
---
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c |6 ++
arch/powerpc/include/asm/fsl_serdes.h |1 +
arch/powerpc/include/asm/immap_85xx.h |1 +
drivers/net/fm/init.c |3 +++
include/fm_eth.h |1 +
5 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 4b52dad..8aac1de 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -68,6 +68,7 @@ static const char *serdes_prtcl_str[] = {
[SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
[SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
[SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
+ [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
[XAUI_FM1] = "XAUI_FM1",
[XAUI_FM2] = "XAUI_FM2",
[AURORA] = "DEBUG",
@@ -658,6 +659,7 @@ void fsl_serdes_init(void)
case SGMII_FM2_DTSEC2:
case SGMII_FM2_DTSEC3:
case SGMII_FM2_DTSEC4:
+ case SGMII_FM2_DTSEC5:
case XAUI_FM1:
case XAUI_FM2:
case SRIO1:
@@ -717,6 +719,10 @@ void fsl_serdes_init(void)
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
FSL_CORENET_DEVDISR2_DTSEC2_4;
break;
+ case SGMII_FM2_DTSEC5:
+ serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
+ FSL_CORENET_DEVDISR2_DTSEC2_5;
+ break;
case XAUI_FM1:
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1|
FSL_CORENET_DEVDISR2_10GEC1;
diff --git a/arch/powerpc/include/asm/fsl_serdes.h
b/arch/powerpc/include/asm/fsl_serdes.h
index 0f31af1..22525f1 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -41,6 +41,7 @@ enum srds_prtcl {
SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3,
SGMII_FM2_DTSEC4,
+ SGMII_FM2_DTSEC5,
SGMII_TSEC1,
SGMII_TSEC2,
SGMII_TSEC3,
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 53d563e..42dd89c 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1729,6 +1729,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x4000
#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x2000
#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x1000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x0800
#define FSL_CORENET_NUM_DEVDISR2
u8 res7[8];
u32 powmgtcsr; /* Power management status & control */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 953c359..9834cd9 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -50,6 +50,9 @@ struct fm_eth_info fm_info[] = {
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
FM_DTSEC_INFO_INITIALIZER(2, 4),
#endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
+ FM_DTSEC_INFO_INITIALIZER(2, 5),
+#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(1, 1),
#endif
diff --git a/include/fm_eth.h b/include/fm_eth.h
index c7c6882..05121ea 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -35,6 +35,7 @@ enum fm_port {
FM2_DTSEC2,
FM2_DTSEC3,
FM2_DTSEC4,
+ FM2_DTSEC5,
FM2_10GEC1,
NUM_FM_PORTS,
};
--
1.7.3.4
___
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