[PATCH v2] clk: imx8mp: add pwm clocks support
Add clocks support for the PWM controllers. This is ported from
Linux v6.3.0-rc1
Signed-off-by: Tommaso Merciai
---
Changes since v1:
- Use static const char instead of static const char * const on sels
drivers/clk/imx/clk-imx8mp.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index ffbc1d1ba9..9dc26bd156 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -122,6 +122,22 @@ static const char *imx8mp_gic_sels[] = {"clock-osc-24m",
"sys_pll2_200m", "sys_p
"sys_pll2_100m", "sys_pll1_800m",
"sys_pll2_500m", "clk_ext4",
"audio_pll2_out" };
+static const char *imx8mp_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m",
+ "sys_pll1_40m", "sys_pll3_out",
"clk_ext1",
+ "sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mp_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m",
+ "sys_pll1_40m", "sys_pll3_out",
"clk_ext1",
+ "sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mp_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m",
+ "sys_pll1_40m", "sys_pll3_out",
"clk_ext2",
+ "sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mp_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m",
+ "sys_pll1_40m", "sys_pll3_out",
"clk_ext2",
+ "sys_pll1_80m", "video_pll1_out", };
+
static const char *imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m",
"sys_pll1_40m",
"sys_pll1_160m",
"sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m",
"audio_pll2_out", };
@@ -270,6 +286,10 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic",
imx8mp_gic_sels, base + 0xb200));
clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite("ecspi1",
imx8mp_ecspi1_sels, base + 0xb280));
clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite("ecspi2",
imx8mp_ecspi2_sels, base + 0xb300));
+ clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical("pwm1",
imx8mp_pwm1_sels, base + 0xb380));
+ clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical("pwm2",
imx8mp_pwm2_sels, base + 0xb400));
+ clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical("pwm3",
imx8mp_pwm3_sels, base + 0xb480));
+ clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical("pwm4",
imx8mp_pwm4_sels, base + 0xb500));
clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite("ecspi3",
imx8mp_ecspi3_sels, base + 0xc180));
clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels,
base + 0xb900));
@@ -292,6 +312,10 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2",
base + 0x4180, 0));
clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3",
base + 0x4190, 0));
clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4",
base + 0x41a0, 0));
+ clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4("pwm1_root_clk", "pwm1",
base + 0x4280, 0));
+ clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4("pwm2_root_clk", "pwm2",
base + 0x4290, 0));
+ clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4("pwm3_root_clk", "pwm3",
base + 0x42a0, 0));
+ clk_dm(IMX8MP_CLK_PWM4_ROOT, imx_clk_gate4("pwm4_root_clk", "pwm4",
base + 0x42b0, 0));
clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi",
base + 0x42f0, 0));
clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5",
base + 0x4330, 0));
clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6",
base + 0x4340, 0));
--
2.34.1
[PATCH] clk: imx8mp: add pwm clocks support
Add clocks support for the PWM controllers. This is ported from
Linux v6.3.0-rc1
Signed-off-by: Tommaso Merciai
---
drivers/clk/imx/clk-imx8mp.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index ffbc1d1ba9..fac87ff505 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -122,6 +122,22 @@ static const char *imx8mp_gic_sels[] = {"clock-osc-24m",
"sys_pll2_200m", "sys_p
"sys_pll2_100m", "sys_pll1_800m",
"sys_pll2_500m", "clk_ext4",
"audio_pll2_out" };
+static const char * const imx8mp_pwm1_sels[] = {"clock-osc-24m",
"sys_pll2_100m", "sys_pll1_160m",
+ "sys_pll1_40m", "sys_pll3_out",
"clk_ext1",
+ "sys_pll1_80m", "video_pll1_out", };
+
+static const char * const imx8mp_pwm2_sels[] = {"clock-osc-24m",
"sys_pll2_100m", "sys_pll1_160m",
+ "sys_pll1_40m", "sys_pll3_out",
"clk_ext1",
+ "sys_pll1_80m", "video_pll1_out", };
+
+static const char * const imx8mp_pwm3_sels[] = {"clock-osc-24m",
"sys_pll2_100m", "sys_pll1_160m",
+ "sys_pll1_40m", "sys_pll3_out",
"clk_ext2",
+ "sys_pll1_80m", "video_pll1_out", };
+
+static const char * const imx8mp_pwm4_sels[] = {"clock-osc-24m",
"sys_pll2_100m", "sys_pll1_160m",
+ "sys_pll1_40m", "sys_pll3_out",
"clk_ext2",
+ "sys_pll1_80m", "video_pll1_out", };
+
static const char *imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m",
"sys_pll1_40m",
"sys_pll1_160m",
"sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m",
"audio_pll2_out", };
@@ -270,6 +286,10 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic",
imx8mp_gic_sels, base + 0xb200));
clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite("ecspi1",
imx8mp_ecspi1_sels, base + 0xb280));
clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite("ecspi2",
imx8mp_ecspi2_sels, base + 0xb300));
+ clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical("pwm1",
imx8mp_pwm1_sels, base + 0xb380));
+ clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical("pwm2",
imx8mp_pwm2_sels, base + 0xb400));
+ clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical("pwm3",
imx8mp_pwm3_sels, base + 0xb480));
+ clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical("pwm4",
imx8mp_pwm4_sels, base + 0xb500));
clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite("ecspi3",
imx8mp_ecspi3_sels, base + 0xc180));
clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels,
base + 0xb900));
@@ -292,6 +312,10 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2",
base + 0x4180, 0));
clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3",
base + 0x4190, 0));
clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4",
base + 0x41a0, 0));
+ clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4("pwm1_root_clk", "pwm1",
base + 0x4280, 0));
+ clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4("pwm2_root_clk", "pwm2",
base + 0x4290, 0));
+ clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4("pwm3_root_clk", "pwm3",
base + 0x42a0, 0));
+ clk_dm(IMX8MP_CLK_PWM4_ROOT, imx_clk_gate4("pwm4_root_clk", "pwm4",
base + 0x42b0, 0));
clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi",
base + 0x42f0, 0));
clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5",
base + 0x4330, 0));
clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6",
base + 0x4340, 0));
--
2.34.1
Re: imx8mm: Invalid IVT structure
Hi, On Wed, Jun 08, 2022 at 04:14:51PM +0200, Michael Nazzareno Trimarchi wrote: > Hi > > On Wed, Jun 8, 2022 at 4:13 PM Fabio Estevam wrote: > > > > Hi, > > > > On top of tree U-Boot, when CONFIG_IMX_HAB=y is selected in > > imx8mm_evk_defconfig, the following error messages are seen: > > > > U-Boot SPL 2022.07-rc3-00097-g26aa5e5c3fbc-dirty (Jun 08 2022 - 10:59:56 > > -0300) > > SEC0: RNG instantiated > > Normal Boot > > WDT: Started watchdog@3028 with servicing (60s timeout) > > Trying to boot from MMC1 > > hab fuse not enabled > > > > Authenticate image from DDR location 0x401fcdc0... > > bad magic magic=0x0 length=0x00 version=0x0 > > bad length magic=0x0 length=0x00 version=0x0 > > bad version magic=0x0 length=0x00 version=0x0 > > Error: Invalid IVT structure > > You need to have a sign image Agree Maybe this page can help you Fabio https://boundarydevices.com/high-assurance-boot-hab-i-mx8m-edition/ Regards, Tommaso > > Michael > > > NOTICE: BL31: v2.4(release):lf-5.15.5-1.0.0-10-gcb51a0faa4b6 > > NOTICE: BL31: Built : 10:50:11, Jun 8 2022 > > > > The boot proceeds normally, despite the error messages above. > > > > Does anyone know how we could fix these errors? > > > > Thanks, > > > > Fabio Estevam > > > > -- > Michael Nazzareno Trimarchi > Co-Founder & Chief Executive Officer > M. +39 347 913 2170 > mich...@amarulasolutions.com > __ > > Amarula Solutions BV > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > T. +31 (0)85 111 9172 > i...@amarulasolutions.com > www.amarulasolutions.com -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH 2/2] clk: imx8mp: use usb_core_ref for usb_root_clk
On Fri, Jun 3, 2022, 17:16 Andrey Zhizhikin <
andrey.zhizhi...@leica-geosystems.com> wrote:
> Upstream commit 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY,
> HSIOMIX clock") added usb_core_ref for USB Controller but never set it
> to be used as a clock source, using rather "osc_32k" instead.
>
> This produces following boot log message:
> "clk_register: failed to get osc_32k device (parent of usb_root_clk)"
>
> Fix the USB controller clock source by using usb_core_ref instead of
> osc_32k.
>
> Fixes: 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX
> clock")
> Signed-off-by: Andrey Zhizhikin
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> ---
> drivers/clk/imx/clk-imx8mp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index cbed86a684..ffbc1d1ba9 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -300,7 +300,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
> clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk",
> "uart2", base + 0x44a0, 0));
> clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk",
> "uart3", base + 0x44b0, 0));
> clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk",
> "uart4", base + 0x44c0, 0));
> - clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> "osc_32k", base + 0x44d0, 0));
> + clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> "usb_core_ref", base + 0x44d0, 0));
> clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk",
> "usb_phy_ref", base + 0x44f0, 0));
> clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk",
> "usdhc1", base + 0x4510, 0));
> clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk",
> "usdhc2", base + 0x4520, 0));
> --
> 2.25.1
>
> Reviewed-by: Tommaso Merciai
Re: [PATCH] include/configs: Remove rootwait=1 to all the affected boards
quot;nandrootfstype=ubifs rootwait=1\0" \
> + "nandrootfstype=ubifs rootwait\0" \
> "nandboot=echo Booting from nand ...; " \
> "run nandargs; " \
> "nand read ${fdt_addr_r} nanddtb; " \
> diff --git a/include/configs/siemens-am33x-common.h
> b/include/configs/siemens-am33x-common.h
> index 08c4d52d65..9f1a6cd51b 100644
> --- a/include/configs/siemens-am33x-common.h
> +++ b/include/configs/siemens-am33x-common.h
> @@ -237,7 +237,7 @@
> "nand_active_ubi_vol=rootfs_a\0" \
> "nand_active_ubi_vol_A=rootfs_a\0" \
> "nand_active_ubi_vol_B=rootfs_b\0" \
> - "nand_root_fs_type=ubifs rootwait=1\0" \
> + "nand_root_fs_type=ubifs rootwait\0" \
> "nand_src_addr=0x28\0" \
> "nand_src_addr_A=0x28\0" \
> "nand_src_addr_B=0x78\0" \
> @@ -314,7 +314,7 @@
> "nand_active_ubi_vol=rootfs_a\0" \
> "rootfs_name=rootfs\0" \
> "kernel_name=uImage\0"\
> - "nand_root_fs_type=ubifs rootwait=1\0" \
> + "nand_root_fs_type=ubifs rootwait\0" \
> "nand_args=run bootargs_defaults;" \
> "mtdparts default;" \
> "setenv ${partitionset_active} true;" \
> diff --git a/include/configs/ti_armv7_keystone2.h
> b/include/configs/ti_armv7_keystone2.h
> index 57f013cbf8..133daecf71 100644
> --- a/include/configs/ti_armv7_keystone2.h
> +++ b/include/configs/ti_armv7_keystone2.h
> @@ -180,7 +180,7 @@
> "sf write ${loadaddr} 0 ${filesize}\0" \
> "burn_uboot_nand=nand erase 0 0x10; " \
> "nand write ${loadaddr} 0 ${filesize}\0"\
> - "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1 " \
> + "args_all=setenv bootargs console=ttyS0,115200n8 rootwait " \
> KERNEL_MTD_PARTS\
> "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
> "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
> --
> 2.25.1
>
Hi Michael,
Looks goot to me.
Reviewed-by: Tommaso Merciai
--
Tommaso Merciai
Embedded Linux Engineer
tommaso.merc...@amarulasolutions.com
__
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
i...@amarulasolutions.com
www.amarulasolutions.com
Re: i.MX8MP usb status
On Mon, May 16, 2022 at 12:50:34PM -0300, Fabio Estevam wrote: > Hi Marcel, > > On 16/05/2022 12:41, Marcel Ziswiler wrote: > > > Talking about uuu, has anybody managed to get that going on the i.MX > > 8M Mini yet? Regular USB device/host > > functionality works great but last I tried gadget functionality in SPL > > it gave me quite some grief. > > Please see this series: > https://patchwork.ozlabs.org/project/uboot/list/?series=251796&state=* > > I haven't had a chance to rework it. Feel free to work to submit it > if you have a chance. > > Tommaso has recently tested it: > https://www.mail-archive.com/search?l=u-boot@lists.denx.de&q=subject:%22Re%5C%3A+iMX8MM+USB+support%5C%3F%22&o=newest&f=1 Hi Fabio, I share here a more recent version of your series: https://patchwork.amarulasolutions.com/project/linux-amarula/list/?series=371 This series brings USB gadget support for i.MX8MM and allows the usage of the Serial Download Protocol, which is a convenient way for loading U-Boot via the 'uuu' tool and and flashing the eMMC via the U-Boot 'ums' command. Tested on board based on iMX8MM SOC: U-Boot SPL 2022.04-00114-gd04ac0fd3a-dirty (May 20 2022 - 10:12:08 +0200) DEBUG Normal Boot WDT: Started watchdog@3028 with servicing (60s timeout) Trying to boot from USB SDP SDP: initialize... SDP: handle requests... Downloading file of size 2366576 to 0x4040... done Jumping to header at 0x4040 Header Tag is not an IMX image Found header at 0x4041e1a0 NOTICE: BL31: v2.2(release):android-11.0.0_1.2.0-rc2-0-gcb435ee78 NOTICE: BL31: Built : 16:43:13, Feb 1 2022 welcome to lk/MP boot args 0x200 0xbe00 0x2000 0x0 initializing trusty (Built: 12:13:25 Nov 19 2020) Initializing Trusted OS SMC handler avb: Initializing AVB App hwcrypto: Initializing caam_drv: 318: job failed (0x255b) trusty_gatekeeper: Initializing hwrng_caam: Init HWRNG service provider hwrng_srv: Start HWRNG service hwcrypto_caam: Init HWCRYPTO service provider hwcrypto_srv: Start HWCRYPTO service hwkey_caam: Init HWKEY service provider hwkey_caam: 183: Invalid magic, unpack key package fail. hwkey_srv: Start HWKEY service hwcrypto: enter main event loop U-Boot 2022.04-00114-gd04ac0fd3a-dirty (May 20 2022 - 10:12:08 +0200) CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz Reset cause: POR Model: FSL i.MX8MM EVK board DRAM: 2 GiB References: - https://patchwork.ozlabs.org/project/uboot/list/?series=251796&state=* - https://www.mail-archive.com/u-boot@lists.denx.de/msg410536.html Hope this could be helpfull. Regards, Tommaso > > Someone needs to rework this series and resubmit it. > > Regards, > > Fabio Estevam > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-60 Fax: (+49)-8142-66989-80 Email: feste...@denx.de -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
Re: i.MX8MP usb status
On Mon, May 16, 2022 at 12:50:34PM -0300, Fabio Estevam wrote: > Hi Marcel, > > On 16/05/2022 12:41, Marcel Ziswiler wrote: > > > Talking about uuu, has anybody managed to get that going on the i.MX > > 8M Mini yet? Regular USB device/host > > functionality works great but last I tried gadget functionality in SPL > > it gave me quite some grief. > > Please see this series: > https://patchwork.ozlabs.org/project/uboot/list/?series=251796&state=* > > I haven't had a chance to rework it. Feel free to work to submit it > if you have a chance. > > Tommaso has recently tested it: > https://www.mail-archive.com/search?l=u-boot@lists.denx.de&q=subject:%22Re%5C%3A+iMX8MM+USB+support%5C%3F%22&o=newest&f=1 > > Someone needs to rework this series and resubmit it. Hi All, Confirm that uuu works on iMX8MM U-Boot Mainline. I have locally a patchset suggested by Fabio that make uuu works on iMX8MM SOC. Regards, Tommaso > > Regards, > > Fabio Estevam > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-60 Fax: (+49)-8142-66989-80 Email: feste...@denx.de -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
Re: imx8mm eLCDIF clock
On Thu, Apr 21, 2022 at 08:09:59PM -0400, Sean Anderson wrote: > On 4/21/22 2:48 AM, Tommaso Merciai wrote: > > Hi, > > I'm working on drivers/clk/imx/clk-imx8mm.c to port and bring up eLCDIF > > clocks. After port all necessary clocks needed by eLCDIF I found that > > IMX8MM_VIDEO_PLL1 clock is not enabled and need the following code to enable > > it at the end of the clk-imx8mm probe: > > > > struct clk *clkp; > > > > clk_get_by_id(IMX8MM_VIDEO_PLL1, &clkp); > > clk_set_rate(clkp, 59400UL); > > clk_enable(clkp); > > > > What do you think about this solution? > > There is a more standard way to do this? > > PLL1 should be a parent of one of the clocks required by the eLCDIF. That > clock > should call clk_enable() on PLL1 when it is enabled itself. If you want to set > a specific rate, you can do that with assigned-clock-rates in either the > clock's > DT node, or the eLCDIF's DT node. Hi Sean, Thanks for your suggestion, I need only to enable it, I have already assign the right rate from dts. The doubt at this point is: it's right call clk_enable from clk-imx8mm.c? I think yes because it handle by "fsl,imx8mm-ccm" driver, maybe protected by CONFIG_DM_VIDEO could be a good solution. Let me know. Thanks, Tommaso > > --Sean -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
Re: imx8mm eLCDIF clock
On Thu, Apr 21, 2022 at 01:20:58PM +0200, Marek Vasut wrote: > On 4/21/22 13:14, Adam Ford wrote: > > On Thu, Apr 21, 2022 at 5:29 AM Tommaso Merciai > > wrote: > > > > > > On Thu, Apr 21, 2022 at 08:48:05AM +0200, Tommaso Merciai wrote: > > > > > > + Fabio > > > + Tim > > > + Michael > > > + Marek > > > + Adam > > > > > > > Hi, > > > > I'm working on drivers/clk/imx/clk-imx8mm.c to port and bring up eLCDIF > > > > clocks. After port all necessary clocks needed by eLCDIF I found that > > > > IMX8MM_VIDEO_PLL1 clock is not enabled and need the clk_enable to enable > > > > it at the end of the clk-imx8mm probe: > > > > > > > > struct clk *clkp; > > > > > > > > clk_get_by_id(IMX8MM_VIDEO_PLL1, &clkp); > > > > clk_set_rate(clkp, 59400UL); > > > > clk_enable(clkp); > > > > > > > > What do you think about this solution? > > > > There is a more standard way to do this? > > > > I'm missing somethings? > > > > I think the LCD driver should request the clock and clock rate based > > on settings the device tree. However, I think the bigger issues is > > that you might run into issues with the lack of a disp-blkctrl driver. > > Marek enable the GPC driver fairly recently, but the blkctrl driver > > will be needed to enable the LCD and DSI portions or the system may > > hang. > > Just boot quickly and init the graphics pipeline in Linux ? Hi Marek, Thanks for your feedback. You think make no sense to enable support for the graphics pipeline at U-Boot level? Some customers want this feature for that I think is better to have support for that. What do you think about? Thanks, Tommaso -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
Re: imx8mm eLCDIF clock
On Thu, Apr 21, 2022 at 06:14:58AM -0500, Adam Ford wrote: > On Thu, Apr 21, 2022 at 5:29 AM Tommaso Merciai > wrote: > > > > On Thu, Apr 21, 2022 at 08:48:05AM +0200, Tommaso Merciai wrote: > > > > + Fabio > > + Tim > > + Michael > > + Marek > > + Adam > > > > > Hi, > > > I'm working on drivers/clk/imx/clk-imx8mm.c to port and bring up eLCDIF > > > clocks. After port all necessary clocks needed by eLCDIF I found that > > > IMX8MM_VIDEO_PLL1 clock is not enabled and need the clk_enable to enable > > > it at the end of the clk-imx8mm probe: > > > > > > struct clk *clkp; > > > > > > clk_get_by_id(IMX8MM_VIDEO_PLL1, &clkp); > > > clk_set_rate(clkp, 59400UL); > > > clk_enable(clkp); > > > > > > What do you think about this solution? > > > There is a more standard way to do this? > > > I'm missing somethings? > > I think the LCD driver should request the clock and clock rate based > on settings the device tree. However, I think the bigger issues is > that you might run into issues with the lack of a disp-blkctrl driver. > Marek enable the GPC driver fairly recently, but the blkctrl driver > will be needed to enable the LCD and DSI portions or the system may > hang. Hi Adam, Thanks for the tips, I will investigate on that. Tommaso > > adam > > > > > > Thanks, > > > Tommmaso > > > -- > > > Tommaso Merciai > > > Embedded Linux Engineer > > > tommaso.merc...@amarulasolutions.com > > > __ > > > > > > Amarula Solutions SRL > > > Via Le Canevare 30, 31100 Treviso, Veneto, IT > > > T. +39 042 243 5310 > > > i...@amarulasolutions.com > > > www.amarulasolutions.com > > > > -- > > Tommaso Merciai > > Embedded Linux Engineer > > tommaso.merc...@amarulasolutions.com > > __ > > > > Amarula Solutions SRL > > Via Le Canevare 30, 31100 Treviso, Veneto, IT > > T. +39 042 243 5310 > > i...@amarulasolutions.com > > www.amarulasolutions.com -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
Re: imx8mm eLCDIF clock
On Thu, Apr 21, 2022 at 08:48:05AM +0200, Tommaso Merciai wrote: + Fabio + Tim + Michael + Marek + Adam > Hi, > I'm working on drivers/clk/imx/clk-imx8mm.c to port and bring up eLCDIF > clocks. After port all necessary clocks needed by eLCDIF I found that > IMX8MM_VIDEO_PLL1 clock is not enabled and need the clk_enable to enable > it at the end of the clk-imx8mm probe: > > struct clk *clkp; > > clk_get_by_id(IMX8MM_VIDEO_PLL1, &clkp); > clk_set_rate(clkp, 59400UL); > clk_enable(clkp); > > What do you think about this solution? > There is a more standard way to do this? > I'm missing somethings? > > Thanks, > Tommmaso > -- > Tommaso Merciai > Embedded Linux Engineer > tommaso.merc...@amarulasolutions.com > __ > > Amarula Solutions SRL > Via Le Canevare 30, 31100 Treviso, Veneto, IT > T. +39 042 243 5310 > i...@amarulasolutions.com > www.amarulasolutions.com -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
Re: im8mn: Loading U-Boot via serial download mode
On Thu, Apr 21, 2022 at 08:53:57AM +0200, Michael Nazzareno Trimarchi wrote: > Hi > > On Wed, Apr 20, 2022 at 11:29 PM Adam Ford wrote: > > > > On Wed, Apr 20, 2022 at 3:16 PM Fabio Estevam wrote: > > > > > > Hi Michael, > > > > > > On Wed, Apr 20, 2022 at 4:53 PM Michael Nazzareno Trimarchi > > > wrote: > > > > > > >> Set CONFIG_ENV_IS_NOWHERE=y and rebuild. It will likely boot. > > > > > > > > > > > > That code should be dropped because it's really buggy. We already sent > > > > several patches. I prefer some registered mechanism and not those > > > > board, arch etc function definition. > > > > > > Just to confirm: you are saying adding CONFIG_ENV_IS_NOWHERE=y is not > > > an acceptable solution and that a > > > a better solution needs to be implemented, correct? > > > > > > Care to point to previous patches that were sent to address this issue? > > > > This problem is the code in arch/arm/mach-imx/imx8m/soc.c: > > > > #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) > > struct rom_api *g_rom_api = (struct rom_api *)0x980; > > > > enum boot_device get_boot_device(void) > > > > > > get_boot_device() assumes that all users want the environmental > > variables to be stored in a different location depending on the boot > > device. When booting from USB, none of the environmental variable > > locations are given, so nowhere is the only option. > > > > There is another issue where some people want their environmental > > variables in the same place all the time regardless of what the boot > > device was. This code also breaks that functionality. > > For some reason it's only applied to 8MN and 8MP, so only their > > environment settings are affected and not 8MQ or 8MM. > > > > When I build, I just delete the function, so my environment is where I > > want it. It's far from ideal, but there doesn't seem to be consensus. > > > > This was the code posted to address it > > https://www.mail-archive.com/u-boot@lists.denx.de/msg430587.html > > If I remember Hi All, Right, patchset can be found here https://patchwork.ozlabs.org/project/uboot/list/?series=283787&state=%2A&archive=both Regards, Tommaso > > Michael > > > adam > > > > > > > > Thanks > > > > -- > Michael Nazzareno Trimarchi > Co-Founder & Chief Executive Officer > M. +39 347 913 2170 > mich...@amarulasolutions.com > __ > > Amarula Solutions BV > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > T. +31 (0)85 111 9172 > i...@amarulasolutions.com > www.amarulasolutions.com -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
imx8mm eLCDIF clock
Hi, I'm working on drivers/clk/imx/clk-imx8mm.c to port and bring up eLCDIF clocks. After port all necessary clocks needed by eLCDIF I found that IMX8MM_VIDEO_PLL1 clock is not enabled and need the following code to enable it at the end of the clk-imx8mm probe: struct clk *clkp; clk_get_by_id(IMX8MM_VIDEO_PLL1, &clkp); clk_set_rate(clkp, 59400UL); clk_enable(clkp); What do you think about this solution? There is a more standard way to do this? Thanks, Tommmaso -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
[PATCH] common: fdt: introduce fdt_fixup_reserved_memory
The intent of fdt_fixup_reserved_memory is to reserve memory and prevent it from
being included in the kernel's linear map from U-Boot. This is done by creating
a no-map zone into reserved-memory region
no-map (optional) - empty property
Indicates the operating system must not create a virtual mapping of the region
as part of its standard mapping of system memory, nor permit speculative access
to it under any circumstances other than under the control of the device driver
using the region.
References:
- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
Signed-off-by: Tommaso Merciai
Developed-by: Michael Trimarchi
Tested-by: Tommaso Merciai
---
common/fdt_support.c | 53 +++
include/fdt_support.h | 11 +
2 files changed, 64 insertions(+)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index ea18ea3f04..7cfaf4310c 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -412,6 +412,59 @@ static int fdt_pack_reg(const void *fdt, void *buf, u64
*address, u64 *size,
return p - (char *)buf;
}
+int fdt_fixup_reserved_memory(void *blob, const char *name, u64 start[], u64
size[])
+{
+ int offs, len, err;
+ const char *subpath;
+ const char *path = "/reserved-memory";
+ fdt32_t address_cells = cpu_to_fdt32(fdt_address_cells(blob, 0));
+ fdt32_t size_cells = cpu_to_fdt32(fdt_size_cells(blob, 0));
+ u8 temp[16]; /* Up to 64-bit address + 64-bit size */
+
+ offs = fdt_path_offset(blob, path);
+ if (offs < 0) {
+ debug("Node %s not found\n", path);
+ path = "/";
+ subpath = "reserved-memory";
+ offs = fdt_path_offset(blob, path);
+ offs = fdt_add_subnode(blob, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s%s node.\n", path, subpath);
+ return -1;
+ }
+ path = "/reserved-memory";
+ offs = fdt_path_offset(blob, path);
+
+ fdt_setprop(blob, offs, "#address-cells", &address_cells,
sizeof(address_cells));
+ fdt_setprop(blob, offs, "#size-cells", &size_cells,
sizeof(size_cells));
+ fdt_setprop(blob, offs, "ranges", NULL, 0);
+ }
+
+ offs = fdt_add_subnode(blob, offs, name ? : "private");
+ if (offs < 0) {
+ printf("Could not create %s%s node.\n", path, subpath);
+ return -1;
+ }
+
+ err = fdt_setprop(blob, offs, "no-map", NULL, 0);
+ if (err < 0) {
+ printf("WARNING: could not set %s %s.\n",
+ "no-map", fdt_strerror(err));
+ return err;
+ }
+
+ len = fdt_pack_reg(blob, temp, start, size, 1);
+
+ err = fdt_setprop(blob, offs, "reg", temp, len);
+ if (err < 0) {
+ printf("WARNING: could not set %s %s.\n",
+ "reg", fdt_strerror(err));
+ return err;
+ }
+
+ return 0;
+}
+
#if CONFIG_NR_DRAM_BANKS > 4
#define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
#else
diff --git a/include/fdt_support.h b/include/fdt_support.h
index ac76939e81..0ade91a08f 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -93,6 +93,17 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat,
*/
int fdt_fixup_memory(void *blob, u64 start, u64 size);
+/**
+ * Setup the memory reserved node in the DT. Creates one if none was existing
before.
+ *
+ * @param blob FDT blob to update
+ * @param name Reserved area name
+ * @param startBegin of DRAM mapping in physical memory
+ * @param size Size of the single memory bank
+ * @return 0 if ok, or -1 or -FDT_ERR_... on error
+ */
+int fdt_fixup_reserved_memory(void *blob, const char *name, u64 start[], u64
size[]);
+
/**
* Fill the DT memory node with multiple memory banks.
* Creates the node if none was existing before.
--
2.25.1
Re: [PATCH v5 0/9] imx8mm: add pwm-imx backlight support
Hi, Gentle ping on this v5. Regards, Tommaso On Sat, Mar 26, 2022 at 12:19:01PM +0100, Tommaso Merciai wrote: > Hi, > This series add support for pwm/backlight on i.MX8MM evk, > separe also CONFIG_DM_PWM pwm-imx implementation from non dm > implementation moving pwm-imx-util into pwm-imx with driver > refactoring. > > 1. add pwm ctrl registers fields for i.MX8MM SOC > 2. add pwm_regs struct for i.MX8MM SOC > 3. add pwm clocks support for i.MX8MM SOC > 4. move pwm-imx-util into pwm-imx > 5. get and enable per/ipg clock using dm > 6. introduce pwm_dm_imx_get_parms > 7. separe dm from non dm implementation into pwm-imx driver > 8. add pwm1/backlight dts support for imx8mm_evk > 9. add pwm backlight configs support for imx8mm_evk > > Tommaso Merciai (9): > arch: mach-imx: imx8m: add pwm ctrl registers fields defines > arch: mach-imx: imx8m: add pwm_regs struct in imx-regs > clk: imx8mm: add pwm clocks support > drivers: pwm: pwm-imx: move pwm-imx-util into pwm-imx > driver: pwm: pwm-imx: get and enable per/ipg clock using dm > driver: pwm: pwm-imx: introduce pwm_dm_imx_get_parms > driver: pwm: pwm-imx: separe dm from non dm implementation > arm: dts: imx8mm_evk: add pwm1/backlight support > configs: imx8mm_evk: add pwm backlight support > > arch/arm/dts/imx8mm-evk.dtsi | 21 +++ > arch/arm/include/asm/arch-imx8m/imx-regs.h | 17 +++ > configs/imx8mm_evk_defconfig | 4 + > drivers/clk/imx/clk-imx8mm.c | 28 > drivers/pwm/Makefile | 2 +- > drivers/pwm/pwm-imx-util.c | 80 --- > drivers/pwm/pwm-imx-util.h | 15 -- > drivers/pwm/pwm-imx.c | 155 +++-- > 8 files changed, 212 insertions(+), 110 deletions(-) > delete mode 100644 drivers/pwm/pwm-imx-util.c > delete mode 100644 drivers/pwm/pwm-imx-util.h > > -- > 2.25.1 > -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH 5/8] usb: ehci-mx6: Allow building SDP for imx8mm
A is not set > # CONFIG_RTC_MC146818 is not set > # CONFIG_RTC_M41T62 is not set > # CONFIG_SCSI is not set > # CONFIG_DM_SCSI is not set > CONFIG_SERIAL=y > CONFIG_BAUDRATE=115200 > CONFIG_SPECIFY_CONSOLE_INDEX=y > CONFIG_CONS_INDEX=1 > # CONFIG_DM_SERIAL is not set > # CONFIG_ARM_DCC is not set > # CONFIG_ATMEL_USART is not set > # CONFIG_FSL_LPUART is not set > # CONFIG_MVEBU_A3700_UART is not set > # CONFIG_MCFUART is not set > CONFIG_MXC_UART=y > # CONFIG_NULLDEV_SERIAL is not set > # CONFIG_SYS_NS16550 is not set > # CONFIG_NS16550_DYNAMIC is not set > # CONFIG_PL011_SERIAL is not set > # CONFIG_MSM_GENI_SERIAL is not set > # CONFIG_PXA_SERIAL is not set > # CONFIG_SMEM is not set > > # > # Sound support > # > # CONFIG_SOUND is not set > > # > # SOC (System On Chip) specific Drivers > # > # CONFIG_SOC_DEVICE is not set > # CONFIG_SOC_TI is not set > # CONFIG_SPI is not set > > # > # SPMI support > # > # CONFIG_SPMI is not set > # CONFIG_SYSINFO is not set > > # > # System reset device drivers > # > # CONFIG_SYSRESET is not set > # CONFIG_TEE is not set > CONFIG_DM_THERMAL=y > # CONFIG_IMX_TMU is not set > # CONFIG_TI_DRA7_THERMAL is not set > > # > # Timer Support > # > # CONFIG_TIMER is not set > > # > # TPM support > # > CONFIG_USB=y > CONFIG_DM_USB=y > # CONFIG_DM_USB_GADGET is not set > > # > # USB Host Controller Drivers > # > CONFIG_USB_HOST=y > CONFIG_USB_XHCI_HCD=y > CONFIG_USB_XHCI_DWC3=y > # CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set > # CONFIG_USB_XHCI_PCI is not set > # CONFIG_USB_XHCI_FSL is not set > # CONFIG_USB_XHCI_BRCM is not set > # CONFIG_USB_EHCI_HCD is not set > # CONFIG_USB_OHCI_HCD is not set > # CONFIG_USB_UHCI_HCD is not set > # CONFIG_USB_DWC2 is not set > # CONFIG_USB_R8A66597_HCD is not set > # CONFIG_USB_CDNS3 is not set > CONFIG_USB_DWC3=y > # CONFIG_USB_DWC3_GADGET is not set > > # > # Platform Glue Driver Support > # > # CONFIG_USB_DWC3_OMAP is not set > # CONFIG_USB_DWC3_LAYERSCAPE is not set > > # > # PHY Subsystem > # > # CONFIG_USB_DWC3_PHY_OMAP is not set > # CONFIG_USB_DWC3_PHY_SAMSUNG is not set > > # > # Legacy MUSB Support > # > # CONFIG_USB_MUSB_HCD is not set > # CONFIG_USB_MUSB_UDC is not set > > # > # MUSB Controller Driver > # > # CONFIG_USB_MUSB_HOST is not set > # CONFIG_USB_MUSB_GADGET is not set > # CONFIG_USB_MUSB_PIO_ONLY is not set > > # > # USB Phy > # > # CONFIG_TWL4030_USB is not set > # CONFIG_ROCKCHIP_USB2_PHY is not set > > # > # ULPI drivers > # > > # > # USB peripherals > # > CONFIG_USB_STORAGE=y > # CONFIG_USB_KEYBOARD is not set > # CONFIG_USB_HOST_ETHER is not set > CONFIG_USB_GADGET=y > CONFIG_USB_GADGET_MANUFACTURER="U-Boot" > CONFIG_USB_GADGET_VENDOR_NUM=0x0 > CONFIG_USB_GADGET_PRODUCT_NUM=0x0 > # CONFIG_USB_GADGET_ATMEL_USBA is not set > # CONFIG_USB_GADGET_BCM_UDC_OTG_PHY is not set > CONFIG_USB_GADGET_DWC2_OTG=y > # CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8 is not set > # CONFIG_USB_GADGET_OS_DESCRIPTORS is not set > # CONFIG_CI_UDC is not set > CONFIG_USB_GADGET_VBUS_DRAW=2 > CONFIG_SDP_LOADADDR=0 > CONFIG_USB_GADGET_DUALSPEED=y > CONFIG_USB_GADGET_DOWNLOAD=y > # CONFIG_USB_FUNCTION_MASS_STORAGE is not set > # CONFIG_USB_FUNCTION_ROCKUSB is not set > CONFIG_USB_FUNCTION_SDP=y > # CONFIG_USB_FUNCTION_THOR is not set > # CONFIG_USB_FUNCTION_ACM is not set > # CONFIG_USB_ETHER is not set > > # > # UFS Host Controller Support > # > # CONFIG_TI_J721E_UFS is not set > > # > # Graphics support > # > # CONFIG_DM_VIDEO is not set > # CONFIG_SYS_WHITE_ON_BLACK is not set > # CONFIG_NO_FB_CLEAR is not set > > # > # TrueType Fonts > # > # CONFIG_VIDEO_VESA is not set > # CONFIG_VIDEO_LCD_ANX9804 is not set > # CONFIG_VIDEO_LCD_SSD2828 is not set > # CONFIG_VIDEO_LCD_HITACHI_TX18D42VM is not set > # CONFIG_VIDEO_MVEBU is not set > # CONFIG_I2C_EDID is not set > # CONFIG_DISPLAY is not set > # CONFIG_ATMEL_HLCD is not set > # CONFIG_AM335X_LCD is not set > # CONFIG_VIDEO_TEGRA20 is not set > # CONFIG_VIDEO_BRIDGE is not set > # CONFIG_VIDEO is
[PATCH v5 9/9] configs: imx8mm_evk: add pwm backlight support
Enable support for backlight/pwm-imx driver Signed-off-by: Tommaso Merciai --- Changes since v4: - Drop off CONFIG_DM_VIDEO configs/imx8mm_evk_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 01395fc7eb..db0d19c38d 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -84,3 +84,7 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y +CONFIG_BACKLIGHT=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_DM_PWM=y +CONFIG_PWM_IMX=y \ No newline at end of file -- 2.25.1
[PATCH v5 8/9] arm: dts: imx8mm_evk: add pwm1/backlight support
Add pwm1/backlight support nodes for imx8mm_evk board
Signed-off-by: Tommaso Merciai
---
arch/arm/dts/imx8mm-evk.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
index 60179e006d..e7a2bd8a64 100644
--- a/arch/arm/dts/imx8mm-evk.dtsi
+++ b/arch/arm/dts/imx8mm-evk.dtsi
@@ -41,6 +41,15 @@
enable-active-high;
};
+ backlight: backlight {
+ status = "disabled";
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 500>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <255>;
+ default-brightness-level = <250>;
+ };
+
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
@@ -350,6 +359,12 @@
status = "okay";
};
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ status = "disabled";
+};
+
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
@@ -491,4 +506,10 @@
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B0x166
>;
};
+
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT0x06
+ >;
+ };
};
--
2.25.1
[PATCH v5 6/9] driver: pwm: pwm-imx: introduce pwm_dm_imx_get_parms
Introduce pwm_dm_imx_get_parms, dm version of pwm_imx_get_parms.
This function get clock rate using clk dm api
Signed-off-by: Tommaso Merciai
---
Changes since v3:
- Fix clk_get_rate call
drivers/pwm/pwm-imx.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 74b0817a05..1d656e726f 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -153,6 +153,36 @@ struct imx_pwm_priv {
struct clk ipg_clk;
};
+int pwm_dm_imx_get_parms(struct imx_pwm_priv *priv, int period_ns,
+ int duty_ns, unsigned long *period_c, unsigned long
*duty_c,
+ unsigned long *prescale)
+{
+ unsigned long long c;
+
+ c = clk_get_rate(&priv->per_clk);
+ c = c * period_ns;
+ do_div(c, 10);
+ *period_c = c;
+
+ *prescale = *period_c / 0x1 + 1;
+
+ *period_c /= *prescale;
+ c = *period_c * (unsigned long long)duty_ns;
+ do_div(c, period_ns);
+ *duty_c = c;
+
+ /*
+* according to imx pwm RM, the real period value should be
+* PERIOD value in PWMPR plus 2.
+*/
+ if (*period_c > 2)
+ *period_c -= 2;
+ else
+ *period_c = 0;
+
+ return 0;
+}
+
static int imx_pwm_set_invert(struct udevice *dev, uint channel,
bool polarity)
{
@@ -173,7 +203,7 @@ static int imx_pwm_set_config(struct udevice *dev, uint
channel,
debug("%s: Config '%s' channel: %d\n", __func__, dev->name, channel);
- pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
+ pwm_dm_imx_get_parms(priv, period_ns, duty_ns, &period_cycles,
&duty_cycles,
&prescale);
return pwm_config_internal(regs, period_cycles, duty_cycles, prescale);
--
2.25.1
[PATCH v5 7/9] driver: pwm: pwm-imx: separe dm from non dm implementation
Separe dm implementation from non dm implementation of pwm-imx
driver using CONFIG_DM_PWM
Signed-off-by: Tommaso Merciai
---
drivers/pwm/pwm-imx.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 1d656e726f..9b8a8c189d 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -13,17 +13,6 @@
#include
#include
#include
-
-int pwm_init(int pwm_id, int div, int invert)
-{
- struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
-
- if (!pwm)
- return -1;
-
- writel(0, &pwm->ir);
- return 0;
-}
#include
int pwm_config_internal(struct pwm_regs *pwm, unsigned long period_cycles,
@@ -44,6 +33,7 @@ int pwm_config_internal(struct pwm_regs *pwm, unsigned long
period_cycles,
return 0;
}
+#ifndef CONFIG_DM_PWM
/* pwm_id from 0..7 */
struct pwm_regs *pwm_id_to_reg(int pwm_id)
{
@@ -110,6 +100,17 @@ int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned
long *period_c,
return 0;
}
+int pwm_init(int pwm_id, int div, int invert)
+{
+ struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
+
+ if (!pwm)
+ return -1;
+
+ writel(0, &pwm->ir);
+ return 0;
+}
+
int pwm_config(int pwm_id, int duty_ns, int period_ns)
{
struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
@@ -145,7 +146,7 @@ void pwm_disable(int pwm_id)
clrbits_le32(&pwm->cr, PWMCR_EN);
}
-#if defined(CONFIG_DM_PWM)
+#else
struct imx_pwm_priv {
struct pwm_regs *regs;
bool invert;
--
2.25.1
[PATCH v5 5/9] driver: pwm: pwm-imx: get and enable per/ipg clock using dm
Get and enable ipg/per pwms clocks using dm api into imx_pwm_of_to_plat
and imx_pwm_probe driver function
Signed-off-by: Tommaso Merciai
---
Changes since v3:
- Fix ipg/per clk declaration
- Fix clk_get_by_name call
- Fix clk_enable call
drivers/pwm/pwm-imx.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 67dad21295..74b0817a05 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -24,6 +24,7 @@ int pwm_init(int pwm_id, int div, int invert)
writel(0, &pwm->ir);
return 0;
}
+#include
int pwm_config_internal(struct pwm_regs *pwm, unsigned long period_cycles,
unsigned long duty_cycles, unsigned long prescale)
@@ -148,6 +149,8 @@ void pwm_disable(int pwm_id)
struct imx_pwm_priv {
struct pwm_regs *regs;
bool invert;
+ struct clk per_clk;
+ struct clk ipg_clk;
};
static int imx_pwm_set_invert(struct udevice *dev, uint channel,
@@ -193,15 +196,43 @@ static int imx_pwm_set_enable(struct udevice *dev, uint
channel, bool enable)
static int imx_pwm_of_to_plat(struct udevice *dev)
{
+ int ret;
struct imx_pwm_priv *priv = dev_get_priv(dev);
priv->regs = dev_read_addr_ptr(dev);
+ ret = clk_get_by_name(dev, "per", &priv->per_clk);
+ if (ret) {
+ printf("Failed to get per_clk\n");
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
+ if (ret) {
+ printf("Failed to get ipg_clk\n");
+ return ret;
+ }
+
return 0;
}
static int imx_pwm_probe(struct udevice *dev)
{
+ int ret;
+ struct imx_pwm_priv *priv = dev_get_priv(dev);
+
+ ret = clk_enable(&priv->per_clk);
+ if (ret) {
+ printf("Failed to enable per_clk\n");
+ return ret;
+ }
+
+ ret = clk_enable(&priv->ipg_clk);
+ if (ret) {
+ printf("Failed to enable ipg_clk\n");
+ return ret;
+ }
+
return 0;
}
--
2.25.1
[PATCH v5 4/9] drivers: pwm: pwm-imx: move pwm-imx-util into pwm-imx
Move pwm_imx_get_parms, pwm_id_to_reg functions into pwm-imx.c
and drop off pwm-imx-util.c
Signed-off-by: Tommaso Merciai
---
drivers/pwm/Makefile | 2 +-
drivers/pwm/pwm-imx-util.c | 80 --
drivers/pwm/pwm-imx-util.h | 15 ---
drivers/pwm/pwm-imx.c | 67 ++-
4 files changed, 67 insertions(+), 97 deletions(-)
delete mode 100644 drivers/pwm/pwm-imx-util.c
delete mode 100644 drivers/pwm/pwm-imx-util.h
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 55f2bc081d..5d696ec49c 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_DM_PWM) += pwm-uclass.o
obj-$(CONFIG_PWM_AT91) += pwm-at91.o
obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o
obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
-obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
+obj-$(CONFIG_PWM_IMX) += pwm-imx.o
obj-$(CONFIG_PWM_MESON)+= pwm-meson.o
obj-$(CONFIG_PWM_MTK) += pwm-mtk.o
obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o
diff --git a/drivers/pwm/pwm-imx-util.c b/drivers/pwm/pwm-imx-util.c
deleted file mode 100644
index 823a9d2d6b..00
--- a/drivers/pwm/pwm-imx-util.c
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * (C) Copyright 2014
- * Heiko Schocher, DENX Software Engineering, h...@denx.de.
- *
- * Basic support for the pwm module on imx6.
- *
- * Based on linux:drivers/pwm/pwm-imx.c
- * from
- * Sascha Hauer
- */
-
-#include
-#include
-#include
-
-/* pwm_id from 0..7 */
-struct pwm_regs *pwm_id_to_reg(int pwm_id)
-{
- switch (pwm_id) {
- case 0:
- return (struct pwm_regs *)PWM1_BASE_ADDR;
- case 1:
- return (struct pwm_regs *)PWM2_BASE_ADDR;
-#ifdef CONFIG_MX6
- case 2:
- return (struct pwm_regs *)PWM3_BASE_ADDR;
- case 3:
- return (struct pwm_regs *)PWM4_BASE_ADDR;
-#endif
-#ifdef CONFIG_MX6SX
- case 4:
- return (struct pwm_regs *)PWM5_BASE_ADDR;
- case 5:
- return (struct pwm_regs *)PWM6_BASE_ADDR;
- case 6:
- return (struct pwm_regs *)PWM7_BASE_ADDR;
- case 7:
- return (struct pwm_regs *)PWM8_BASE_ADDR;
-#endif
- default:
- printf("unknown pwm_id: %d\n", pwm_id);
- break;
- }
- return NULL;
-}
-
-int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c,
- unsigned long *duty_c, unsigned long *prescale)
-{
- unsigned long long c;
-
- /*
-* we have not yet a clock framework for imx6, so add the clock
-* value here as a define. Replace it when we have the clock
-* framework.
-*/
- c = CONFIG_IMX6_PWM_PER_CLK;
- c = c * period_ns;
- do_div(c, 10);
- *period_c = c;
-
- *prescale = *period_c / 0x1 + 1;
-
- *period_c /= *prescale;
- c = *period_c * (unsigned long long)duty_ns;
- do_div(c, period_ns);
- *duty_c = c;
-
- /*
-* according to imx pwm RM, the real period value should be
-* PERIOD value in PWMPR plus 2.
-*/
- if (*period_c > 2)
- *period_c -= 2;
- else
- *period_c = 0;
-
- return 0;
-}
diff --git a/drivers/pwm/pwm-imx-util.h b/drivers/pwm/pwm-imx-util.h
deleted file mode 100644
index 82c61d774d..00
--- a/drivers/pwm/pwm-imx-util.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2014
- * Heiko Schocher, DENX Software Engineering, h...@denx.de.
- *
- * Basic support for the pwm module on imx6.
- */
-
-#ifndef _pwm_imx_util_h_
-#define _pwm_imx_util_h_
-
-struct pwm_regs *pwm_id_to_reg(int pwm_id);
-int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c,
- unsigned long *duty_c, unsigned long *prescale);
-#endif
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 2008c1520e..67dad21295 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -13,7 +13,6 @@
#include
#include
#include
-#include "pwm-imx-util.h"
int pwm_init(int pwm_id, int div, int invert)
{
@@ -44,6 +43,72 @@ int pwm_config_internal(struct pwm_regs *pwm, unsigned long
period_cycles,
return 0;
}
+/* pwm_id from 0..7 */
+struct pwm_regs *pwm_id_to_reg(int pwm_id)
+{
+
+ switch (pwm_id) {
+ case 0:
+ return (struct pwm_regs *)PWM1_BASE_ADDR;
+ case 1:
+ return (struct pwm_regs *)PWM2_BASE_ADDR;
+#ifdef CONFIG_MX6
+ case 2:
+ return (struct pwm_regs *)PWM3_BASE_ADDR;
+ case 3:
+ return (struct pwm_regs *)PWM4_BASE_ADDR;
+#endif
+#ifdef CONFIG_MX6SX
+ case 4:
+ return (struct pwm_regs *)PWM5_BASE_ADDR;
+ case 5:
+ return (struct pw
[PATCH v5 3/9] clk: imx8mm: add pwm clocks support
Add clocks support for the PWM controllers. This is ported from
Linux v5.17-rc8.
Signed-off-by: Tommaso Merciai
---
drivers/clk/imx/clk-imx8mm.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 3aa8c641f9..964a778934 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -116,6 +116,18 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m",
"sys_pll1_160m", "sys_
static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m",
"sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out",
"sys_pll1_133m", };
+static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
+
static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m",
"sys_pll1_160m", "vpu_pll_out",
"sys_pll2_125m", "sys_pll3_out",
"sys_pll1_80m", "sys_pll2_166m", };
@@ -391,6 +403,14 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
clk_dm(IMX8MM_CLK_I2C4,
imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
+ clk_dm(IMX8MM_CLK_PWM1,
+ imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380));
+ clk_dm(IMX8MM_CLK_PWM2,
+ imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400));
+ clk_dm(IMX8MM_CLK_PWM3,
+ imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480));
+ clk_dm(IMX8MM_CLK_PWM4,
+ imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500));
clk_dm(IMX8MM_CLK_WDOG,
imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
clk_dm(IMX8MM_CLK_USDHC3,
@@ -425,6 +445,14 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
clk_dm(IMX8MM_CLK_OCOTP_ROOT,
imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+ clk_dm(IMX8MM_CLK_PWM1_ROOT,
+ imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
+ clk_dm(IMX8MM_CLK_PWM2_ROOT,
+ imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
+ clk_dm(IMX8MM_CLK_PWM3_ROOT,
+ imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+ clk_dm(IMX8MM_CLK_PWM4_ROOT,
+ imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
clk_dm(IMX8MM_CLK_USDHC1_ROOT,
imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
clk_dm(IMX8MM_CLK_USDHC2_ROOT,
--
2.25.1
[PATCH v5 2/9] arch: mach-imx: imx8m: add pwm_regs struct in imx-regs
Add pwm_regs struct for i.MX8MM SOC
Signed-off-by: Tommaso Merciai
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 57a95de1b8..f31f54ad0c 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -359,6 +359,15 @@ struct src {
#define PWMCR_CLKSRC_IPG (1 << 16)
#define PWMCR_EN (1 << 0)
+struct pwm_regs {
+ u32 cr;
+ u32 sr;
+ u32 ir;
+ u32 sar;
+ u32 pr;
+ u32 cnr;
+};
+
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASKBIT(0)
struct wdog_regs {
--
2.25.1
[PATCH v5 1/9] arch: mach-imx: imx8m: add pwm ctrl registers fields defines
Add pwm control registers fields defines into imx-regs.h:
- prescaler
- dozeen
- waiten
- dbgen
- clksrc_ipg_high
- clksrc_ipg, en field
References:
- iMX8MMRM.pdf p 3884
Signed-off-by: Tommaso Merciai
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 11389a0f4d..57a95de1b8 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -351,6 +351,14 @@ struct src {
u32 ddr2_rcr;
};
+#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN (1 << 24)
+#define PWMCR_WAITEN (1 << 23)
+#define PWMCR_DBGEN(1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define PWMCR_CLKSRC_IPG (1 << 16)
+#define PWMCR_EN (1 << 0)
+
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASKBIT(0)
struct wdog_regs {
--
2.25.1
[PATCH v5 0/9] imx8mm: add pwm-imx backlight support
Hi, This series add support for pwm/backlight on i.MX8MM evk, separe also CONFIG_DM_PWM pwm-imx implementation from non dm implementation moving pwm-imx-util into pwm-imx with driver refactoring. 1. add pwm ctrl registers fields for i.MX8MM SOC 2. add pwm_regs struct for i.MX8MM SOC 3. add pwm clocks support for i.MX8MM SOC 4. move pwm-imx-util into pwm-imx 5. get and enable per/ipg clock using dm 6. introduce pwm_dm_imx_get_parms 7. separe dm from non dm implementation into pwm-imx driver 8. add pwm1/backlight dts support for imx8mm_evk 9. add pwm backlight configs support for imx8mm_evk Tommaso Merciai (9): arch: mach-imx: imx8m: add pwm ctrl registers fields defines arch: mach-imx: imx8m: add pwm_regs struct in imx-regs clk: imx8mm: add pwm clocks support drivers: pwm: pwm-imx: move pwm-imx-util into pwm-imx driver: pwm: pwm-imx: get and enable per/ipg clock using dm driver: pwm: pwm-imx: introduce pwm_dm_imx_get_parms driver: pwm: pwm-imx: separe dm from non dm implementation arm: dts: imx8mm_evk: add pwm1/backlight support configs: imx8mm_evk: add pwm backlight support arch/arm/dts/imx8mm-evk.dtsi | 21 +++ arch/arm/include/asm/arch-imx8m/imx-regs.h | 17 +++ configs/imx8mm_evk_defconfig | 4 + drivers/clk/imx/clk-imx8mm.c | 28 drivers/pwm/Makefile | 2 +- drivers/pwm/pwm-imx-util.c | 80 --- drivers/pwm/pwm-imx-util.h | 15 -- drivers/pwm/pwm-imx.c | 155 +++-- 8 files changed, 212 insertions(+), 110 deletions(-) delete mode 100644 drivers/pwm/pwm-imx-util.c delete mode 100644 drivers/pwm/pwm-imx-util.h -- 2.25.1
Re: [PATCH v4 9/9] configs: imx8mm_evk: add pwm backlight support
On Fri, Mar 25, 2022 at 04:54:28PM -0300, Fabio Estevam wrote: > Hi Tommaso, > > On Fri, Mar 25, 2022 at 9:04 AM Tommaso Merciai > wrote: > > > > Enable support for backlight/pwm-imx driver > > > > Signed-off-by: Tommaso Merciai > > --- > > configs/imx8mm_evk_defconfig | 5 + > > 1 file changed, 5 insertions(+) > > > > diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig > > index 01395fc7eb..cfba6cc673 100644 > > --- a/configs/imx8mm_evk_defconfig > > +++ b/configs/imx8mm_evk_defconfig > > @@ -84,3 +84,8 @@ CONFIG_SYSRESET_PSCI=y > > CONFIG_SYSRESET_WATCHDOG=y > > CONFIG_DM_THERMAL=y > > CONFIG_IMX_WATCHDOG=y > > +CONFIG_DM_VIDEO=y > > There is no video driver for imx8mm yet, so you could drop this one, right? Hi Fabio, Right, I fix this in v5. Thanks, Tommaso -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
[PATCH v4 8/9] arm: dts: imx8mm_evk: add pwm1/backlight support
Add pwm1/backlight support nodes for imx8mm_evk board
Signed-off-by: Tommaso Merciai
---
arch/arm/dts/imx8mm-evk.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
index 60179e006d..e7a2bd8a64 100644
--- a/arch/arm/dts/imx8mm-evk.dtsi
+++ b/arch/arm/dts/imx8mm-evk.dtsi
@@ -41,6 +41,15 @@
enable-active-high;
};
+ backlight: backlight {
+ status = "disabled";
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 500>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <255>;
+ default-brightness-level = <250>;
+ };
+
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
@@ -350,6 +359,12 @@
status = "okay";
};
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ status = "disabled";
+};
+
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
@@ -491,4 +506,10 @@
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B0x166
>;
};
+
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT0x06
+ >;
+ };
};
--
2.25.1
[PATCH v4 9/9] configs: imx8mm_evk: add pwm backlight support
Enable support for backlight/pwm-imx driver Signed-off-by: Tommaso Merciai --- configs/imx8mm_evk_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 01395fc7eb..cfba6cc673 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -84,3 +84,8 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_DM_PWM=y +CONFIG_PWM_IMX=y \ No newline at end of file -- 2.25.1
[PATCH v4 7/9] driver: pwm: pwm-imx: separe dm from non dm implementation
Separe dm implementation from non dm implementation of pwm-imx
driver using CONFIG_DM_PWM
Signed-off-by: Tommaso Merciai
---
drivers/pwm/pwm-imx.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 1d656e726f..9b8a8c189d 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -13,17 +13,6 @@
#include
#include
#include
-
-int pwm_init(int pwm_id, int div, int invert)
-{
- struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
-
- if (!pwm)
- return -1;
-
- writel(0, &pwm->ir);
- return 0;
-}
#include
int pwm_config_internal(struct pwm_regs *pwm, unsigned long period_cycles,
@@ -44,6 +33,7 @@ int pwm_config_internal(struct pwm_regs *pwm, unsigned long
period_cycles,
return 0;
}
+#ifndef CONFIG_DM_PWM
/* pwm_id from 0..7 */
struct pwm_regs *pwm_id_to_reg(int pwm_id)
{
@@ -110,6 +100,17 @@ int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned
long *period_c,
return 0;
}
+int pwm_init(int pwm_id, int div, int invert)
+{
+ struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
+
+ if (!pwm)
+ return -1;
+
+ writel(0, &pwm->ir);
+ return 0;
+}
+
int pwm_config(int pwm_id, int duty_ns, int period_ns)
{
struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
@@ -145,7 +146,7 @@ void pwm_disable(int pwm_id)
clrbits_le32(&pwm->cr, PWMCR_EN);
}
-#if defined(CONFIG_DM_PWM)
+#else
struct imx_pwm_priv {
struct pwm_regs *regs;
bool invert;
--
2.25.1
[PATCH v4 5/9] driver: pwm: pwm-imx: get and enable per/ipg clock using dm
Get and enable ipg/per pwms clocks using dm api into imx_pwm_of_to_plat
and imx_pwm_probe driver function
Signed-off-by: Tommaso Merciai
---
Changes since v4:
- Fix ipg/per clk declaration
- Fix clk_get_by_name call
- Fix clk_enable call
drivers/pwm/pwm-imx.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 67dad21295..74b0817a05 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -24,6 +24,7 @@ int pwm_init(int pwm_id, int div, int invert)
writel(0, &pwm->ir);
return 0;
}
+#include
int pwm_config_internal(struct pwm_regs *pwm, unsigned long period_cycles,
unsigned long duty_cycles, unsigned long prescale)
@@ -148,6 +149,8 @@ void pwm_disable(int pwm_id)
struct imx_pwm_priv {
struct pwm_regs *regs;
bool invert;
+ struct clk per_clk;
+ struct clk ipg_clk;
};
static int imx_pwm_set_invert(struct udevice *dev, uint channel,
@@ -193,15 +196,43 @@ static int imx_pwm_set_enable(struct udevice *dev, uint
channel, bool enable)
static int imx_pwm_of_to_plat(struct udevice *dev)
{
+ int ret;
struct imx_pwm_priv *priv = dev_get_priv(dev);
priv->regs = dev_read_addr_ptr(dev);
+ ret = clk_get_by_name(dev, "per", &priv->per_clk);
+ if (ret) {
+ printf("Failed to get per_clk\n");
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
+ if (ret) {
+ printf("Failed to get ipg_clk\n");
+ return ret;
+ }
+
return 0;
}
static int imx_pwm_probe(struct udevice *dev)
{
+ int ret;
+ struct imx_pwm_priv *priv = dev_get_priv(dev);
+
+ ret = clk_enable(&priv->per_clk);
+ if (ret) {
+ printf("Failed to enable per_clk\n");
+ return ret;
+ }
+
+ ret = clk_enable(&priv->ipg_clk);
+ if (ret) {
+ printf("Failed to enable ipg_clk\n");
+ return ret;
+ }
+
return 0;
}
--
2.25.1
[PATCH v4 4/9] drivers: pwm: pwm-imx: move pwm-imx-util into pwm-imx
Move pwm_imx_get_parms, pwm_id_to_reg functions into pwm-imx.c
and drop off pwm-imx-util.c
Signed-off-by: Tommaso Merciai
---
drivers/pwm/Makefile | 2 +-
drivers/pwm/pwm-imx-util.c | 80 --
drivers/pwm/pwm-imx-util.h | 15 ---
drivers/pwm/pwm-imx.c | 67 ++-
4 files changed, 67 insertions(+), 97 deletions(-)
delete mode 100644 drivers/pwm/pwm-imx-util.c
delete mode 100644 drivers/pwm/pwm-imx-util.h
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 55f2bc081d..5d696ec49c 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_DM_PWM) += pwm-uclass.o
obj-$(CONFIG_PWM_AT91) += pwm-at91.o
obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o
obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
-obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
+obj-$(CONFIG_PWM_IMX) += pwm-imx.o
obj-$(CONFIG_PWM_MESON)+= pwm-meson.o
obj-$(CONFIG_PWM_MTK) += pwm-mtk.o
obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o
diff --git a/drivers/pwm/pwm-imx-util.c b/drivers/pwm/pwm-imx-util.c
deleted file mode 100644
index 823a9d2d6b..00
--- a/drivers/pwm/pwm-imx-util.c
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * (C) Copyright 2014
- * Heiko Schocher, DENX Software Engineering, h...@denx.de.
- *
- * Basic support for the pwm module on imx6.
- *
- * Based on linux:drivers/pwm/pwm-imx.c
- * from
- * Sascha Hauer
- */
-
-#include
-#include
-#include
-
-/* pwm_id from 0..7 */
-struct pwm_regs *pwm_id_to_reg(int pwm_id)
-{
- switch (pwm_id) {
- case 0:
- return (struct pwm_regs *)PWM1_BASE_ADDR;
- case 1:
- return (struct pwm_regs *)PWM2_BASE_ADDR;
-#ifdef CONFIG_MX6
- case 2:
- return (struct pwm_regs *)PWM3_BASE_ADDR;
- case 3:
- return (struct pwm_regs *)PWM4_BASE_ADDR;
-#endif
-#ifdef CONFIG_MX6SX
- case 4:
- return (struct pwm_regs *)PWM5_BASE_ADDR;
- case 5:
- return (struct pwm_regs *)PWM6_BASE_ADDR;
- case 6:
- return (struct pwm_regs *)PWM7_BASE_ADDR;
- case 7:
- return (struct pwm_regs *)PWM8_BASE_ADDR;
-#endif
- default:
- printf("unknown pwm_id: %d\n", pwm_id);
- break;
- }
- return NULL;
-}
-
-int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c,
- unsigned long *duty_c, unsigned long *prescale)
-{
- unsigned long long c;
-
- /*
-* we have not yet a clock framework for imx6, so add the clock
-* value here as a define. Replace it when we have the clock
-* framework.
-*/
- c = CONFIG_IMX6_PWM_PER_CLK;
- c = c * period_ns;
- do_div(c, 10);
- *period_c = c;
-
- *prescale = *period_c / 0x1 + 1;
-
- *period_c /= *prescale;
- c = *period_c * (unsigned long long)duty_ns;
- do_div(c, period_ns);
- *duty_c = c;
-
- /*
-* according to imx pwm RM, the real period value should be
-* PERIOD value in PWMPR plus 2.
-*/
- if (*period_c > 2)
- *period_c -= 2;
- else
- *period_c = 0;
-
- return 0;
-}
diff --git a/drivers/pwm/pwm-imx-util.h b/drivers/pwm/pwm-imx-util.h
deleted file mode 100644
index 82c61d774d..00
--- a/drivers/pwm/pwm-imx-util.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2014
- * Heiko Schocher, DENX Software Engineering, h...@denx.de.
- *
- * Basic support for the pwm module on imx6.
- */
-
-#ifndef _pwm_imx_util_h_
-#define _pwm_imx_util_h_
-
-struct pwm_regs *pwm_id_to_reg(int pwm_id);
-int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c,
- unsigned long *duty_c, unsigned long *prescale);
-#endif
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 2008c1520e..67dad21295 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -13,7 +13,6 @@
#include
#include
#include
-#include "pwm-imx-util.h"
int pwm_init(int pwm_id, int div, int invert)
{
@@ -44,6 +43,72 @@ int pwm_config_internal(struct pwm_regs *pwm, unsigned long
period_cycles,
return 0;
}
+/* pwm_id from 0..7 */
+struct pwm_regs *pwm_id_to_reg(int pwm_id)
+{
+
+ switch (pwm_id) {
+ case 0:
+ return (struct pwm_regs *)PWM1_BASE_ADDR;
+ case 1:
+ return (struct pwm_regs *)PWM2_BASE_ADDR;
+#ifdef CONFIG_MX6
+ case 2:
+ return (struct pwm_regs *)PWM3_BASE_ADDR;
+ case 3:
+ return (struct pwm_regs *)PWM4_BASE_ADDR;
+#endif
+#ifdef CONFIG_MX6SX
+ case 4:
+ return (struct pwm_regs *)PWM5_BASE_ADDR;
+ case 5:
+ return (struct pw
[PATCH v4 6/9] driver: pwm: pwm-imx: introduce pwm_dm_imx_get_parms
Introduce pwm_dm_imx_get_parms, dm version of pwm_imx_get_parms.
This function get clock rate using clk dm api
Signed-off-by: Tommaso Merciai
---
Changes since v4:
- Fix clk_get_rate call
drivers/pwm/pwm-imx.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 74b0817a05..1d656e726f 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -153,6 +153,36 @@ struct imx_pwm_priv {
struct clk ipg_clk;
};
+int pwm_dm_imx_get_parms(struct imx_pwm_priv *priv, int period_ns,
+ int duty_ns, unsigned long *period_c, unsigned long
*duty_c,
+ unsigned long *prescale)
+{
+ unsigned long long c;
+
+ c = clk_get_rate(&priv->per_clk);
+ c = c * period_ns;
+ do_div(c, 10);
+ *period_c = c;
+
+ *prescale = *period_c / 0x1 + 1;
+
+ *period_c /= *prescale;
+ c = *period_c * (unsigned long long)duty_ns;
+ do_div(c, period_ns);
+ *duty_c = c;
+
+ /*
+* according to imx pwm RM, the real period value should be
+* PERIOD value in PWMPR plus 2.
+*/
+ if (*period_c > 2)
+ *period_c -= 2;
+ else
+ *period_c = 0;
+
+ return 0;
+}
+
static int imx_pwm_set_invert(struct udevice *dev, uint channel,
bool polarity)
{
@@ -173,7 +203,7 @@ static int imx_pwm_set_config(struct udevice *dev, uint
channel,
debug("%s: Config '%s' channel: %d\n", __func__, dev->name, channel);
- pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
+ pwm_dm_imx_get_parms(priv, period_ns, duty_ns, &period_cycles,
&duty_cycles,
&prescale);
return pwm_config_internal(regs, period_cycles, duty_cycles, prescale);
--
2.25.1
[PATCH v4 3/9] clk: imx8mm: add pwm clocks support
Add clocks support for the PWM controllers. This is ported from
Linux v5.17-rc8.
Signed-off-by: Tommaso Merciai
---
drivers/clk/imx/clk-imx8mm.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 3aa8c641f9..964a778934 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -116,6 +116,18 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m",
"sys_pll1_160m", "sys_
static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m",
"sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out",
"sys_pll1_133m", };
+static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
+
static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m",
"sys_pll1_160m", "vpu_pll_out",
"sys_pll2_125m", "sys_pll3_out",
"sys_pll1_80m", "sys_pll2_166m", };
@@ -391,6 +403,14 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
clk_dm(IMX8MM_CLK_I2C4,
imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
+ clk_dm(IMX8MM_CLK_PWM1,
+ imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380));
+ clk_dm(IMX8MM_CLK_PWM2,
+ imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400));
+ clk_dm(IMX8MM_CLK_PWM3,
+ imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480));
+ clk_dm(IMX8MM_CLK_PWM4,
+ imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500));
clk_dm(IMX8MM_CLK_WDOG,
imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
clk_dm(IMX8MM_CLK_USDHC3,
@@ -425,6 +445,14 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
clk_dm(IMX8MM_CLK_OCOTP_ROOT,
imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+ clk_dm(IMX8MM_CLK_PWM1_ROOT,
+ imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
+ clk_dm(IMX8MM_CLK_PWM2_ROOT,
+ imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
+ clk_dm(IMX8MM_CLK_PWM3_ROOT,
+ imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+ clk_dm(IMX8MM_CLK_PWM4_ROOT,
+ imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
clk_dm(IMX8MM_CLK_USDHC1_ROOT,
imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
clk_dm(IMX8MM_CLK_USDHC2_ROOT,
--
2.25.1
[PATCH v4 2/9] arch: mach-imx: imx8m: add pwm_regs struct in imx-regs
Add pwm_regs struct for i.MX8MM SOC
Signed-off-by: Tommaso Merciai
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 57a95de1b8..f31f54ad0c 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -359,6 +359,15 @@ struct src {
#define PWMCR_CLKSRC_IPG (1 << 16)
#define PWMCR_EN (1 << 0)
+struct pwm_regs {
+ u32 cr;
+ u32 sr;
+ u32 ir;
+ u32 sar;
+ u32 pr;
+ u32 cnr;
+};
+
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASKBIT(0)
struct wdog_regs {
--
2.25.1
[PATCH v4 1/9] arch: mach-imx: imx8m: add pwm ctrl registers fields defines
Add pwm control registers fields defines into imx-regs.h:
- prescaler
- dozeen
- waiten
- dbgen
- clksrc_ipg_high
- clksrc_ipg, en field
References:
- iMX8MMRM.pdf p 3884
Signed-off-by: Tommaso Merciai
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 11389a0f4d..57a95de1b8 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -351,6 +351,14 @@ struct src {
u32 ddr2_rcr;
};
+#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN (1 << 24)
+#define PWMCR_WAITEN (1 << 23)
+#define PWMCR_DBGEN(1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define PWMCR_CLKSRC_IPG (1 << 16)
+#define PWMCR_EN (1 << 0)
+
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASKBIT(0)
struct wdog_regs {
--
2.25.1
[PATCH v4 0/9] imx8mm: add pwm-imx backlight support
Hi, This series add support for pwm/backlight on i.MX8MM evk, separe also CONFIG_DM_PWM pwm-imx implementation from non dm implementation moving pwm-imx-util into pwm-imx with driver refactoring. 1. add pwm ctrl registers fields for i.MX8MM SOC 2. add pwm_regs struct for i.MX8MM SOC 3. add pwm clocks support for i.MX8MM SOC 4. move pwm-imx-util into pwm-imx 5. get and enable per/ipg clock using dm 6. introduce pwm_dm_imx_get_parms 7. separe dm from non dm implementation into pwm-imx driver 8. add pwm1/backlight dts support for imx8mm_evk 9. add pwm backlight configs support for imx8mm_evk Tommaso Merciai (9): arch: mach-imx: imx8m: add pwm ctrl registers fields defines arch: mach-imx: imx8m: add pwm_regs struct in imx-regs clk: imx8mm: add pwm clocks support drivers: pwm: pwm-imx: move pwm-imx-util into pwm-imx driver: pwm: pwm-imx: get and enable per/ipg clock using dm driver: pwm: pwm-imx: introduce pwm_dm_imx_get_parms driver: pwm: pwm-imx: separe dm from non dm implementation arm: dts: imx8mm_evk: add pwm1/backlight support configs: imx8mm_evk: add pwm backlight support arch/arm/dts/imx8mm-evk.dtsi | 21 +++ arch/arm/include/asm/arch-imx8m/imx-regs.h | 17 +++ configs/imx8mm_evk_defconfig | 5 + drivers/clk/imx/clk-imx8mm.c | 28 drivers/pwm/Makefile | 2 +- drivers/pwm/pwm-imx-util.c | 80 --- drivers/pwm/pwm-imx-util.h | 15 -- drivers/pwm/pwm-imx.c | 155 +++-- 8 files changed, 213 insertions(+), 110 deletions(-) delete mode 100644 drivers/pwm/pwm-imx-util.c delete mode 100644 drivers/pwm/pwm-imx-util.h -- 2.25.1
[PATCH v3 8/9] arm: dts: imx8mm_evk: add pwm1/backlight support
Add pwm1/backlight support nodes for imx8mm_evk board
Signed-off-by: Tommaso Merciai
---
arch/arm/dts/imx8mm-evk.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
index 60179e006d..e7a2bd8a64 100644
--- a/arch/arm/dts/imx8mm-evk.dtsi
+++ b/arch/arm/dts/imx8mm-evk.dtsi
@@ -41,6 +41,15 @@
enable-active-high;
};
+ backlight: backlight {
+ status = "disabled";
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 500>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <255>;
+ default-brightness-level = <250>;
+ };
+
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
@@ -350,6 +359,12 @@
status = "okay";
};
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ status = "disabled";
+};
+
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
@@ -491,4 +506,10 @@
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B0x166
>;
};
+
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT0x06
+ >;
+ };
};
--
2.25.1
[PATCH v3 9/9] configs: imx8mm_evk: add pwm backlight support
Enable support for backlight/pwm-imx driver Signed-off-by: Tommaso Merciai --- configs/imx8mm_evk_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 01395fc7eb..cfba6cc673 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -84,3 +84,8 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_DM_PWM=y +CONFIG_PWM_IMX=y \ No newline at end of file -- 2.25.1
[PATCH v3 4/9] drivers: pwm: pwm-imx: move pwm-imx-util into pwm-imx
Move pwm_imx_get_parms, pwm_id_to_reg functions into pwm-imx.c
and drop off pwm-imx-util.c
Signed-off-by: Tommaso Merciai
---
drivers/pwm/Makefile | 2 +-
drivers/pwm/pwm-imx-util.c | 80 --
drivers/pwm/pwm-imx-util.h | 15 ---
drivers/pwm/pwm-imx.c | 67 ++-
4 files changed, 67 insertions(+), 97 deletions(-)
delete mode 100644 drivers/pwm/pwm-imx-util.c
delete mode 100644 drivers/pwm/pwm-imx-util.h
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 55f2bc081d..5d696ec49c 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_DM_PWM) += pwm-uclass.o
obj-$(CONFIG_PWM_AT91) += pwm-at91.o
obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o
obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
-obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
+obj-$(CONFIG_PWM_IMX) += pwm-imx.o
obj-$(CONFIG_PWM_MESON)+= pwm-meson.o
obj-$(CONFIG_PWM_MTK) += pwm-mtk.o
obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o
diff --git a/drivers/pwm/pwm-imx-util.c b/drivers/pwm/pwm-imx-util.c
deleted file mode 100644
index 823a9d2d6b..00
--- a/drivers/pwm/pwm-imx-util.c
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * (C) Copyright 2014
- * Heiko Schocher, DENX Software Engineering, h...@denx.de.
- *
- * Basic support for the pwm module on imx6.
- *
- * Based on linux:drivers/pwm/pwm-imx.c
- * from
- * Sascha Hauer
- */
-
-#include
-#include
-#include
-
-/* pwm_id from 0..7 */
-struct pwm_regs *pwm_id_to_reg(int pwm_id)
-{
- switch (pwm_id) {
- case 0:
- return (struct pwm_regs *)PWM1_BASE_ADDR;
- case 1:
- return (struct pwm_regs *)PWM2_BASE_ADDR;
-#ifdef CONFIG_MX6
- case 2:
- return (struct pwm_regs *)PWM3_BASE_ADDR;
- case 3:
- return (struct pwm_regs *)PWM4_BASE_ADDR;
-#endif
-#ifdef CONFIG_MX6SX
- case 4:
- return (struct pwm_regs *)PWM5_BASE_ADDR;
- case 5:
- return (struct pwm_regs *)PWM6_BASE_ADDR;
- case 6:
- return (struct pwm_regs *)PWM7_BASE_ADDR;
- case 7:
- return (struct pwm_regs *)PWM8_BASE_ADDR;
-#endif
- default:
- printf("unknown pwm_id: %d\n", pwm_id);
- break;
- }
- return NULL;
-}
-
-int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c,
- unsigned long *duty_c, unsigned long *prescale)
-{
- unsigned long long c;
-
- /*
-* we have not yet a clock framework for imx6, so add the clock
-* value here as a define. Replace it when we have the clock
-* framework.
-*/
- c = CONFIG_IMX6_PWM_PER_CLK;
- c = c * period_ns;
- do_div(c, 10);
- *period_c = c;
-
- *prescale = *period_c / 0x1 + 1;
-
- *period_c /= *prescale;
- c = *period_c * (unsigned long long)duty_ns;
- do_div(c, period_ns);
- *duty_c = c;
-
- /*
-* according to imx pwm RM, the real period value should be
-* PERIOD value in PWMPR plus 2.
-*/
- if (*period_c > 2)
- *period_c -= 2;
- else
- *period_c = 0;
-
- return 0;
-}
diff --git a/drivers/pwm/pwm-imx-util.h b/drivers/pwm/pwm-imx-util.h
deleted file mode 100644
index 82c61d774d..00
--- a/drivers/pwm/pwm-imx-util.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2014
- * Heiko Schocher, DENX Software Engineering, h...@denx.de.
- *
- * Basic support for the pwm module on imx6.
- */
-
-#ifndef _pwm_imx_util_h_
-#define _pwm_imx_util_h_
-
-struct pwm_regs *pwm_id_to_reg(int pwm_id);
-int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c,
- unsigned long *duty_c, unsigned long *prescale);
-#endif
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 2008c1520e..67dad21295 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -13,7 +13,6 @@
#include
#include
#include
-#include "pwm-imx-util.h"
int pwm_init(int pwm_id, int div, int invert)
{
@@ -44,6 +43,72 @@ int pwm_config_internal(struct pwm_regs *pwm, unsigned long
period_cycles,
return 0;
}
+/* pwm_id from 0..7 */
+struct pwm_regs *pwm_id_to_reg(int pwm_id)
+{
+
+ switch (pwm_id) {
+ case 0:
+ return (struct pwm_regs *)PWM1_BASE_ADDR;
+ case 1:
+ return (struct pwm_regs *)PWM2_BASE_ADDR;
+#ifdef CONFIG_MX6
+ case 2:
+ return (struct pwm_regs *)PWM3_BASE_ADDR;
+ case 3:
+ return (struct pwm_regs *)PWM4_BASE_ADDR;
+#endif
+#ifdef CONFIG_MX6SX
+ case 4:
+ return (struct pwm_regs *)PWM5_BASE_ADDR;
+ case 5:
+ return (struct pw
[PATCH v3 6/9] driver: pwm: pwm-imx: introduce pwm_dm_imx_get_parms
Introduce pwm_dm_imx_get_parms, dm version of pwm_imx_get_parms.
This function get clock rate using clk dm api
Signed-off-by: Tommaso Merciai
---
drivers/pwm/pwm-imx.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 429b57a423..c683909b2c 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -153,6 +153,36 @@ struct imx_pwm_priv {
struct clk *ipg_clk;
};
+int pwm_dm_imx_get_parms(struct imx_pwm_priv *priv, int period_ns,
+ int duty_ns, unsigned long *period_c, unsigned long
*duty_c,
+ unsigned long *prescale)
+{
+ unsigned long long c;
+
+ c = clk_get_rate(priv->per_clk);
+ c = c * period_ns;
+ do_div(c, 10);
+ *period_c = c;
+
+ *prescale = *period_c / 0x1 + 1;
+
+ *period_c /= *prescale;
+ c = *period_c * (unsigned long long)duty_ns;
+ do_div(c, period_ns);
+ *duty_c = c;
+
+ /*
+* according to imx pwm RM, the real period value should be
+* PERIOD value in PWMPR plus 2.
+*/
+ if (*period_c > 2)
+ *period_c -= 2;
+ else
+ *period_c = 0;
+
+ return 0;
+}
+
static int imx_pwm_set_invert(struct udevice *dev, uint channel,
bool polarity)
{
@@ -173,7 +203,7 @@ static int imx_pwm_set_config(struct udevice *dev, uint
channel,
debug("%s: Config '%s' channel: %d\n", __func__, dev->name, channel);
- pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
+ pwm_dm_imx_get_parms(priv, period_ns, duty_ns, &period_cycles,
&duty_cycles,
&prescale);
return pwm_config_internal(regs, period_cycles, duty_cycles, prescale);
--
2.25.1
[PATCH v3 7/9] driver: pwm: pwm-imx: separe dm from non dm implementation
Separe dm implementation from non dm implementation of pwm-imx
driver using CONFIG_DM_PWM
Signed-off-by: Tommaso Merciai
---
drivers/pwm/pwm-imx.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index c683909b2c..52212588ab 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -13,17 +13,6 @@
#include
#include
#include
-
-int pwm_init(int pwm_id, int div, int invert)
-{
- struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
-
- if (!pwm)
- return -1;
-
- writel(0, &pwm->ir);
- return 0;
-}
#include
int pwm_config_internal(struct pwm_regs *pwm, unsigned long period_cycles,
@@ -44,6 +33,7 @@ int pwm_config_internal(struct pwm_regs *pwm, unsigned long
period_cycles,
return 0;
}
+#ifndef CONFIG_DM_PWM
/* pwm_id from 0..7 */
struct pwm_regs *pwm_id_to_reg(int pwm_id)
{
@@ -110,6 +100,17 @@ int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned
long *period_c,
return 0;
}
+int pwm_init(int pwm_id, int div, int invert)
+{
+ struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
+
+ if (!pwm)
+ return -1;
+
+ writel(0, &pwm->ir);
+ return 0;
+}
+
int pwm_config(int pwm_id, int duty_ns, int period_ns)
{
struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
@@ -145,7 +146,7 @@ void pwm_disable(int pwm_id)
clrbits_le32(&pwm->cr, PWMCR_EN);
}
-#if defined(CONFIG_DM_PWM)
+#else
struct imx_pwm_priv {
struct pwm_regs *regs;
bool invert;
--
2.25.1
[PATCH v3 5/9] driver: pwm: pwm-imx: get and enable per/ipg clock using dm
Get and enable ipg/per pwms clocks using dm api into imx_pwm_of_to_plat
and imx_pwm_probe driver function
Signed-off-by: Tommaso Merciai
---
drivers/pwm/pwm-imx.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 67dad21295..429b57a423 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -24,6 +24,7 @@ int pwm_init(int pwm_id, int div, int invert)
writel(0, &pwm->ir);
return 0;
}
+#include
int pwm_config_internal(struct pwm_regs *pwm, unsigned long period_cycles,
unsigned long duty_cycles, unsigned long prescale)
@@ -148,6 +149,8 @@ void pwm_disable(int pwm_id)
struct imx_pwm_priv {
struct pwm_regs *regs;
bool invert;
+ struct clk *per_clk;
+ struct clk *ipg_clk;
};
static int imx_pwm_set_invert(struct udevice *dev, uint channel,
@@ -193,15 +196,43 @@ static int imx_pwm_set_enable(struct udevice *dev, uint
channel, bool enable)
static int imx_pwm_of_to_plat(struct udevice *dev)
{
+ int ret;
struct imx_pwm_priv *priv = dev_get_priv(dev);
priv->regs = dev_read_addr_ptr(dev);
+ ret = clk_get_by_name(dev, "per", priv->per_clk);
+ if (ret) {
+ printf("Failed to get per_clk\n");
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "ipg", priv->ipg_clk);
+ if (ret) {
+ printf("Failed to get ipg_clk\n");
+ return ret;
+ }
+
return 0;
}
static int imx_pwm_probe(struct udevice *dev)
{
+ int ret;
+ struct imx_pwm_priv *priv = dev_get_priv(dev);
+
+ ret = clk_enable(priv->per_clk);
+ if (ret) {
+ printf("Failed to enable per_clk\n");
+ return ret;
+ }
+
+ ret = clk_enable(priv->ipg_clk);
+ if (ret) {
+ printf("Failed to enable ipg_clk\n");
+ return ret;
+ }
+
return 0;
}
--
2.25.1
[PATCH v3 3/9] clk: imx8mm: add pwm clocks support
Add clocks support for the PWM controllers. This is ported from
Linux v5.17-rc8.
Signed-off-by: Tommaso Merciai
---
drivers/clk/imx/clk-imx8mm.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 3aa8c641f9..964a778934 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -116,6 +116,18 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m",
"sys_pll1_160m", "sys_
static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m",
"sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out",
"sys_pll1_133m", };
+static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
+
static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m",
"sys_pll1_160m", "vpu_pll_out",
"sys_pll2_125m", "sys_pll3_out",
"sys_pll1_80m", "sys_pll2_166m", };
@@ -391,6 +403,14 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
clk_dm(IMX8MM_CLK_I2C4,
imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
+ clk_dm(IMX8MM_CLK_PWM1,
+ imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380));
+ clk_dm(IMX8MM_CLK_PWM2,
+ imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400));
+ clk_dm(IMX8MM_CLK_PWM3,
+ imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480));
+ clk_dm(IMX8MM_CLK_PWM4,
+ imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500));
clk_dm(IMX8MM_CLK_WDOG,
imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
clk_dm(IMX8MM_CLK_USDHC3,
@@ -425,6 +445,14 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
clk_dm(IMX8MM_CLK_OCOTP_ROOT,
imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+ clk_dm(IMX8MM_CLK_PWM1_ROOT,
+ imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
+ clk_dm(IMX8MM_CLK_PWM2_ROOT,
+ imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
+ clk_dm(IMX8MM_CLK_PWM3_ROOT,
+ imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+ clk_dm(IMX8MM_CLK_PWM4_ROOT,
+ imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
clk_dm(IMX8MM_CLK_USDHC1_ROOT,
imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
clk_dm(IMX8MM_CLK_USDHC2_ROOT,
--
2.25.1
[PATCH v3 2/9] arch: mach-imx: imx8m: add pwm_regs struct in imx-regs
Add pwm_regs struct for i.MX8MM SOC
Signed-off-by: Tommaso Merciai
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 57a95de1b8..f31f54ad0c 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -359,6 +359,15 @@ struct src {
#define PWMCR_CLKSRC_IPG (1 << 16)
#define PWMCR_EN (1 << 0)
+struct pwm_regs {
+ u32 cr;
+ u32 sr;
+ u32 ir;
+ u32 sar;
+ u32 pr;
+ u32 cnr;
+};
+
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASKBIT(0)
struct wdog_regs {
--
2.25.1
[PATCH v3 1/9] arch: mach-imx: imx8m: add pwm ctrl registers fields defines
Add pwm control registers fields defines into imx-regs.h:
- prescaler
- dozeen
- waiten
- dbgen
- clksrc_ipg_high
- clksrc_ipg, en field
References:
- iMX8MMRM.pdf p 3884
Signed-off-by: Tommaso Merciai
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 11389a0f4d..57a95de1b8 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -351,6 +351,14 @@ struct src {
u32 ddr2_rcr;
};
+#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN (1 << 24)
+#define PWMCR_WAITEN (1 << 23)
+#define PWMCR_DBGEN(1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define PWMCR_CLKSRC_IPG (1 << 16)
+#define PWMCR_EN (1 << 0)
+
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASKBIT(0)
struct wdog_regs {
--
2.25.1
[PATCH v3 0/9] imx8mm: add pwm-imx backlight support
Hi, This series add support for pwm/backlight on i.MX8MM evk, separe also CONFIG_DM_PWM pwm-imx implementation from non dm implementation moving pwm-imx-util into pwm-imx with driver refactoring. 1. add pwm ctrl registers fields for i.MX8MM SOC 2. add pwm_regs struct for i.MX8MM SOC 3. add pwm clocks support for i.MX8MM SOC 4. move pwm-imx-util into pwm-imx 5. get and enable per/ipg clock using dm 6. introduce pwm_dm_imx_get_parms 7. separe dm from non dm implementation into pwm-imx driver 8. add pwm1/backlight dts support for imx8mm_evk 9. add pwm backlight configs support for imx8mm_evk Tommaso Merciai (9): arch: mach-imx: imx8m: add pwm ctrl registers fields defines arch: mach-imx: imx8m: add pwm_regs struct in imx-regs clk: imx8mm: add pwm clocks support drivers: pwm: pwm-imx: move pwm-imx-util into pwm-imx driver: pwm: pwm-imx: get and enable per/ipg clock using dm driver: pwm: pwm-imx: introduce pwm_dm_imx_get_parms driver: pwm: pwm-imx: separe dm from non dm implementation arm: dts: imx8mm_evk: add pwm1/backlight support configs: imx8mm_evk: add pwm backlight support arch/arm/dts/imx8mm-evk.dtsi | 21 +++ arch/arm/include/asm/arch-imx8m/imx-regs.h | 17 +++ configs/imx8mm_evk_defconfig | 5 + drivers/clk/imx/clk-imx8mm.c | 28 drivers/pwm/Makefile | 2 +- drivers/pwm/pwm-imx-util.c | 80 --- drivers/pwm/pwm-imx-util.h | 15 -- drivers/pwm/pwm-imx.c | 155 +++-- 8 files changed, 213 insertions(+), 110 deletions(-) delete mode 100644 drivers/pwm/pwm-imx-util.c delete mode 100644 drivers/pwm/pwm-imx-util.h -- 2.25.1
Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function
On Thu, Mar 17, 2022 at 04:31:15PM +0100, Marek Vasut wrote:
> On 3/17/22 16:13, Tommaso Merciai wrote:
> > On Thu, Mar 17, 2022 at 01:38:18PM +0100, Tommaso Merciai wrote:
> > > On Thu, Mar 17, 2022 at 12:58:31PM +0100, Marek Vasut wrote:
> > > > On 3/17/22 08:39, Tommaso Merciai wrote:
> > > > > On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote:
> > > > > > On 3/16/22 16:27, Tommaso Merciai wrote:
> > > > > > > Add function enable_pwm_clk into in clock_imx8mm.c. This
> > > > > > > function first configure, then enable pwm clock from clock control
> > > > > > > register. The following configuration is used:
> > > > > > >
> > > > > > > source(0) -> 24 MHz ref clock
> > > > > > > div(0)-> no division for this clock
> > > > > > >
> > > > > > > References:
> > > > > > > - iMX8MMRM.pdf p 303
> > > > > > >
> > > > > > > Signed-off-by: Tommaso Merciai
> > > > > > >
> > > > > > > ---
> > > > > > > Changes since v1:
> > > > > > > - Fix enable_pwm_clk function implementation. Now is generic
> > > > > > > for all pwm clks
> > > > > > >
> > > > > > > arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53
> > > > > > > ++
> > > > > > > 1 file changed, 53 insertions(+)
> > > > > >
> > > > > > Why is this not in drivers/clk/imx/ DM driver ?
> > > > >
> > > > > Hi Marek,
> > > > > All function that enable/configure clk from CCGR are in
> > > > > arch/arm/mach-imx/imx8m/clock_imx8mm.c.
> > > >
> > > > These seems to be CCGR:
> > > >
> > > > $ grep -C 2 '0x4[0-9a-f]\{3\}' drivers/clk/imx/clk-imx8mm.c | sed
> > > > "s@^.@@"
> > > >
> > > > clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
> > > > imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
> > > > clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
> > > > imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
> > > > clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
> > > > imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
> > > > clk_dm(IMX8MM_CLK_I2C1_ROOT,
> > > > imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
> > > > clk_dm(IMX8MM_CLK_I2C2_ROOT,
> > > > imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
> > > > clk_dm(IMX8MM_CLK_I2C3_ROOT,
> > > > imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
> > > > clk_dm(IMX8MM_CLK_I2C4_ROOT,
> > > > imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
> > > > clk_dm(IMX8MM_CLK_OCOTP_ROOT,
> > > > imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
> > > > clk_dm(IMX8MM_CLK_USDHC1_ROOT,
> > > > imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
> > > > clk_dm(IMX8MM_CLK_USDHC2_ROOT,
> > > > imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
> > > > clk_dm(IMX8MM_CLK_WDOG1_ROOT,
> > > > imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
> > > > clk_dm(IMX8MM_CLK_WDOG2_ROOT,
> > > > imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
> > > > clk_dm(IMX8MM_CLK_WDOG3_ROOT,
> > > > imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
> > > > clk_dm(IMX8MM_CLK_USDHC3_ROOT,
> > > > imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
> > > > clk_dm(IMX8MM_CLK_QSPI_ROOT,
> > > > imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
> > > > clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
> > > > imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0,
> > > > 0));
> > > >
> > > > /* clks not needed in SPL stage */
> > > > -
> > > > clk_dm(IMX8MM_C
[PATCH] clk: imx8mm: add pwm clocks support
Add clocks support for the PWM controllers. This is ported from
Linux v5.17-rc8.
Signed-off-by: Tommaso Merciai
---
drivers/clk/imx/clk-imx8mm.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 3aa8c641f9..964a778934 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -116,6 +116,18 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m",
"sys_pll1_160m", "sys_
static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m",
"sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out",
"sys_pll1_133m", };
+static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
+"sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
+
static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m",
"sys_pll1_160m", "vpu_pll_out",
"sys_pll2_125m", "sys_pll3_out",
"sys_pll1_80m", "sys_pll2_166m", };
@@ -391,6 +403,14 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
clk_dm(IMX8MM_CLK_I2C4,
imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
+ clk_dm(IMX8MM_CLK_PWM1,
+ imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380));
+ clk_dm(IMX8MM_CLK_PWM2,
+ imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400));
+ clk_dm(IMX8MM_CLK_PWM3,
+ imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480));
+ clk_dm(IMX8MM_CLK_PWM4,
+ imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500));
clk_dm(IMX8MM_CLK_WDOG,
imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
clk_dm(IMX8MM_CLK_USDHC3,
@@ -425,6 +445,14 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
clk_dm(IMX8MM_CLK_OCOTP_ROOT,
imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+ clk_dm(IMX8MM_CLK_PWM1_ROOT,
+ imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
+ clk_dm(IMX8MM_CLK_PWM2_ROOT,
+ imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
+ clk_dm(IMX8MM_CLK_PWM3_ROOT,
+ imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+ clk_dm(IMX8MM_CLK_PWM4_ROOT,
+ imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
clk_dm(IMX8MM_CLK_USDHC1_ROOT,
imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
clk_dm(IMX8MM_CLK_USDHC2_ROOT,
--
2.25.1
Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function
On Thu, Mar 17, 2022 at 01:38:18PM +0100, Tommaso Merciai wrote:
> On Thu, Mar 17, 2022 at 12:58:31PM +0100, Marek Vasut wrote:
> > On 3/17/22 08:39, Tommaso Merciai wrote:
> > > On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote:
> > > > On 3/16/22 16:27, Tommaso Merciai wrote:
> > > > > Add function enable_pwm_clk into in clock_imx8mm.c. This
> > > > > function first configure, then enable pwm clock from clock control
> > > > > register. The following configuration is used:
> > > > >
> > > > > source(0) -> 24 MHz ref clock
> > > > > div(0)-> no division for this clock
> > > > >
> > > > > References:
> > > > >- iMX8MMRM.pdf p 303
> > > > >
> > > > > Signed-off-by: Tommaso Merciai
> > > > > ---
> > > > > Changes since v1:
> > > > >- Fix enable_pwm_clk function implementation. Now is generic for
> > > > > all pwm clks
> > > > >
> > > > >arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53
> > > > > ++
> > > > >1 file changed, 53 insertions(+)
> > > >
> > > > Why is this not in drivers/clk/imx/ DM driver ?
> > >
> > > Hi Marek,
> > > All function that enable/configure clk from CCGR are in
> > > arch/arm/mach-imx/imx8m/clock_imx8mm.c.
> >
> > These seems to be CCGR:
> >
> > $ grep -C 2 '0x4[0-9a-f]\{3\}' drivers/clk/imx/clk-imx8mm.c | sed "s@^.@@"
> >
> > clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
> >imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
> > clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
> >imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
> > clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
> >imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
> > clk_dm(IMX8MM_CLK_I2C1_ROOT,
> >imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
> > clk_dm(IMX8MM_CLK_I2C2_ROOT,
> >imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
> > clk_dm(IMX8MM_CLK_I2C3_ROOT,
> >imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
> > clk_dm(IMX8MM_CLK_I2C4_ROOT,
> >imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
> > clk_dm(IMX8MM_CLK_OCOTP_ROOT,
> >imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
> > clk_dm(IMX8MM_CLK_USDHC1_ROOT,
> >imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
> > clk_dm(IMX8MM_CLK_USDHC2_ROOT,
> >imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
> > clk_dm(IMX8MM_CLK_WDOG1_ROOT,
> >imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
> > clk_dm(IMX8MM_CLK_WDOG2_ROOT,
> >imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
> > clk_dm(IMX8MM_CLK_WDOG3_ROOT,
> >imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
> > clk_dm(IMX8MM_CLK_USDHC3_ROOT,
> >imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
> > clk_dm(IMX8MM_CLK_QSPI_ROOT,
> >imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
> > clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
> > imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
> >
> > /* clks not needed in SPL stage */
> > -
> > clk_dm(IMX8MM_CLK_ENET1_ROOT,
> >imx_clk_gate4("enet1_root_clk", "enet_axi",
> >base + 0x40a0, 0));
> > endif
> >
> > > For that I continue to put here the implementation. After we can port
> > > the clk dm part to manipulate clock in drivers/clk/imx/ DM driver.
> > > What do you think about? Let me know.
> >
> > Seems like the clk_dm part is already in place and all you have to do is
> > extend it.
Hi Marek,
I test the solution using DM model, it work:
u-boot=> clk dump
2400 2| |-- pwm1
2400 3| | `-- pwm1_root_clk
2400 0| |-- pwm2
2400 0| | `-- pwm2_root_clk
2400 0| |-- pwm3
2400 0| | `-- pwm3_root_clk
2400 0| |-- pwm4
Re: [PATCH v2 7/9] imx8mm_evk: spl: enable pwm clock
On Thu, Mar 17, 2022 at 07:55:40AM -0300, Fabio Estevam wrote: > Hi Tommaso, > > On Thu, Mar 17, 2022 at 4:34 AM Tommaso Merciai > wrote: > > > Hi Fabio, > > You mean is better to move the clock enable into board_late_init function? > > Yes, you would only need PWM support in U-Boot proper, not in SPL, so better > to > turn on the PWM clock inside U-Boot proper. Hi Fabio, Ok, I move the function on board_late_init in v3. Thanks, Tommaso > > > I plan to provide support for display panel at u-boot level in particular > > I plan to use lcdif->mipi_dsi->sn65dsi84->display video pipeline. > > Ok, great. It would be great to have i.MX8MM display driver in kernel > mainline and U-Boot mainline. -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function
On Thu, Mar 17, 2022 at 12:58:31PM +0100, Marek Vasut wrote:
> On 3/17/22 08:39, Tommaso Merciai wrote:
> > On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote:
> > > On 3/16/22 16:27, Tommaso Merciai wrote:
> > > > Add function enable_pwm_clk into in clock_imx8mm.c. This
> > > > function first configure, then enable pwm clock from clock control
> > > > register. The following configuration is used:
> > > >
> > > > source(0) -> 24 MHz ref clock
> > > > div(0)-> no division for this clock
> > > >
> > > > References:
> > > >- iMX8MMRM.pdf p 303
> > > >
> > > > Signed-off-by: Tommaso Merciai
> > > > ---
> > > > Changes since v1:
> > > >- Fix enable_pwm_clk function implementation. Now is generic for all
> > > > pwm clks
> > > >
> > > >arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53
> > > > ++
> > > >1 file changed, 53 insertions(+)
> > >
> > > Why is this not in drivers/clk/imx/ DM driver ?
> >
> > Hi Marek,
> > All function that enable/configure clk from CCGR are in
> > arch/arm/mach-imx/imx8m/clock_imx8mm.c.
>
> These seems to be CCGR:
>
> $ grep -C 2 '0x4[0-9a-f]\{3\}' drivers/clk/imx/clk-imx8mm.c | sed "s@^.@@"
>
> clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
>imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
> clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
>imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
> clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
>imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
> clk_dm(IMX8MM_CLK_I2C1_ROOT,
>imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
> clk_dm(IMX8MM_CLK_I2C2_ROOT,
>imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
> clk_dm(IMX8MM_CLK_I2C3_ROOT,
>imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
> clk_dm(IMX8MM_CLK_I2C4_ROOT,
>imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
> clk_dm(IMX8MM_CLK_OCOTP_ROOT,
>imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
> clk_dm(IMX8MM_CLK_USDHC1_ROOT,
>imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
> clk_dm(IMX8MM_CLK_USDHC2_ROOT,
>imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
> clk_dm(IMX8MM_CLK_WDOG1_ROOT,
>imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
> clk_dm(IMX8MM_CLK_WDOG2_ROOT,
>imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
> clk_dm(IMX8MM_CLK_WDOG3_ROOT,
>imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
> clk_dm(IMX8MM_CLK_USDHC3_ROOT,
>imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
> clk_dm(IMX8MM_CLK_QSPI_ROOT,
> imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
> clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
> imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
>
> /* clks not needed in SPL stage */
> -
> clk_dm(IMX8MM_CLK_ENET1_ROOT,
>imx_clk_gate4("enet1_root_clk", "enet_axi",
>base + 0x40a0, 0));
> endif
>
> > For that I continue to put here the implementation. After we can port
> > the clk dm part to manipulate clock in drivers/clk/imx/ DM driver.
> > What do you think about? Let me know.
>
> Seems like the clk_dm part is already in place and all you have to do is
> extend it.
Hi Marek,
I'll try also this way and let you know.
Thanks,
Tommaso
--
Tommaso Merciai
Embedded Linux Engineer
tommaso.merc...@amarulasolutions.com
__
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function
On Wed, Mar 16, 2022 at 08:07:01PM +0100, Michael Nazzareno Trimarchi wrote:
> Hi Tommaaso
>
>
> On Wed, Mar 16, 2022 at 4:28 PM Tommaso Merciai
> wrote:
> >
> > Add function enable_pwm_clk into in clock_imx8mm.c. This
> > function first configure, then enable pwm clock from clock control
> > register. The following configuration is used:
> >
> > source(0) -> 24 MHz ref clock
> > div(0)-> no division for this clock
> >
> > References:
> > - iMX8MMRM.pdf p 303
> >
> > Signed-off-by: Tommaso Merciai
> > ---
> > Changes since v1:
> > - Fix enable_pwm_clk function implementation. Now is generic for all pwm
> > clks
> >
> > arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++
> > 1 file changed, 53 insertions(+)
> >
> > diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > index 49945faf2c..ffb9456607 100644
> > --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > @@ -313,6 +313,59 @@ void enable_usboh3_clk(unsigned int enable)
> > }
> > }
> >
> > +void enable_pwm_clk(u32 index, unsigned char enable)
> > +{
> > + switch (index) {
> > + case 0:
> > + if (enable) {
> > + clock_enable(CCGR_PWM1, false);
> > + clock_set_target_val(PWM1_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(0) |
> > +
> > CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
> > + clock_enable(CCGR_PWM1, true);
> > + } else {
> > + clock_enable(CCGR_PWM1, false);
>
> Pwm is alway before set to false and then enable. Make sense to move
> out. Then all the code is look quite the same apart
> minior change
>
> Can you clean up in order to have a more compact implementation?
Hi Michael,
Ok, I remove the else in the implementation in v3.
Thanks,
Tommaso
>
> Michael
>
> > + }
>
>
> > + return;
> > + case 1:
> > + if (enable) {
> > + clock_enable(CCGR_PWM2, false);
> > + clock_set_target_val(PWM2_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(0) |
> > +
> > CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
> > + clock_enable(CCGR_PWM2, true);
> > + } else {
> > + clock_enable(CCGR_PWM2, false);
> > + }
> > + return;
> > + case 2:
> > + if (enable) {
> > + clock_enable(CCGR_PWM3, false);
> > + clock_set_target_val(PWM3_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(0) |
> > +
> > CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
> > + clock_enable(CCGR_PWM3, true);
> > + } else {
> > + clock_enable(CCGR_PWM3, false);
> > + }
> > + return;
> > + case 3:
> > + if (enable) {
> > + clock_enable(CCGR_PWM4, false);
> > + clock_set_target_val(PWM4_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(0) |
> > +
> > CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
> > + clock_enable(CCGR_PWM4, true);
> > + } else {
> > + clock_enable(CCGR_PWM4, false);
> > + }
> > + return;
> > + default:
> > + printf("Invalid pwm index\n");
> > + return;
> > + }
> > +}
> > +
>
> Please factorize things that are always eegual
> > void init_uart_clk(u32 index)
> > {
> > /*
> > --
> > 2.25.1
> >
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> mich...@amarulasolutions.com
> __
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> i...@amarulasolutions.com
> www.amarulasolutions.com
--
Tommaso Merciai
Embedded Linux Engineer
tommaso.merc...@amarulasolutions.com
__
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function
On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote: > On 3/16/22 16:27, Tommaso Merciai wrote: > > Add function enable_pwm_clk into in clock_imx8mm.c. This > > function first configure, then enable pwm clock from clock control > > register. The following configuration is used: > > > > source(0) -> 24 MHz ref clock > > div(0)-> no division for this clock > > > > References: > > - iMX8MMRM.pdf p 303 > > > > Signed-off-by: Tommaso Merciai > > --- > > Changes since v1: > > - Fix enable_pwm_clk function implementation. Now is generic for all pwm > > clks > > > > arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++ > > 1 file changed, 53 insertions(+) > > Why is this not in drivers/clk/imx/ DM driver ? Hi Marek, All function that enable/configure clk from CCGR are in arch/arm/mach-imx/imx8m/clock_imx8mm.c. For that I continue to put here the implementation. After we can port the clk dm part to manipulate clock in drivers/clk/imx/ DM driver. What do you think about? Let me know. Thanks, Tommaso -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH v2 7/9] imx8mm_evk: spl: enable pwm clock
On Wed, Mar 16, 2022 at 09:48:57PM -0300, Fabio Estevam wrote: > On Wed, Mar 16, 2022 at 8:55 PM Fabio Estevam wrote: > > > > Hi Tommaso, > > > > On Wed, Mar 16, 2022 at 12:28 PM Tommaso Merciai > > wrote: > > > > > > Enable pwm1 clock into spl > > > > Please improve the commit log and explain why you need to enable the > > PWM clock in SPL. > > > > What is the PWM use case in PWM that you plan to use? > > I meant: "What is the PWM use case in SPL that you plan to use?" Hi Fabio, You mean is better to move the clock enable into board_late_init function? I plan to provide support for display panel at u-boot level in particular I plan to use lcdif->mipi_dsi->sn65dsi84->display video pipeline. Let me know. Thanks, Tommaso -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
[PATCH v2 9/9] configs: imx8mm_evk: add pwm backlight support
Enable support for backlight/pwm-imx driver Signed-off-by: Tommaso Merciai --- configs/imx8mm_evk_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 01395fc7eb..cfba6cc673 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -84,3 +84,8 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_DM_PWM=y +CONFIG_PWM_IMX=y \ No newline at end of file -- 2.25.1
[PATCH v2 7/9] imx8mm_evk: spl: enable pwm clock
Enable pwm1 clock into spl Signed-off-by: Tommaso Merciai --- Changes since v1: - Fix enable_pwm_clk call board/freescale/imx8mm_evk/spl.c | 4 1 file changed, 4 insertions(+) diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index 4ef7f6f180..cf173b885f 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -135,6 +135,10 @@ void board_init_f(ulong dummy) init_uart_clk(1); +#ifdef CONFIG_PWM_IMX + enable_pwm_clk(0, 1); +#endif + board_early_init_f(); timer_init(); -- 2.25.1
[PATCH v2 8/9] arm: dts: imx8mm_evk: add pwm1/backlight support
Add pwm1/backlight support nodes for imx8mm_evk board
Signed-off-by: Tommaso Merciai
---
arch/arm/dts/imx8mm-evk.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
index 60179e006d..e7a2bd8a64 100644
--- a/arch/arm/dts/imx8mm-evk.dtsi
+++ b/arch/arm/dts/imx8mm-evk.dtsi
@@ -41,6 +41,15 @@
enable-active-high;
};
+ backlight: backlight {
+ status = "disabled";
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 500>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <255>;
+ default-brightness-level = <250>;
+ };
+
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
@@ -350,6 +359,12 @@
status = "okay";
};
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ status = "disabled";
+};
+
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
@@ -491,4 +506,10 @@
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B0x166
>;
};
+
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT0x06
+ >;
+ };
};
--
2.25.1
[PATCH v2 6/9] configs: imx8mm_evk: add CONFIG_IMX6_PWM_PER_CLK config
In order to support pwm-imx-util CONFIG_IMX6_PWM_PER_CLK is needed. At the moment driver don't support clock framework Signed-off-by: Tommaso Merciai --- include/configs/imx8mm_evk.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index c7022ef0f7..3c17dd3773 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -91,4 +91,7 @@ #define IMX_FEC_BASE 0x30BE +#ifdef CONFIG_PWM_IMX + #define CONFIG_IMX6_PWM_PER_CLK 6600 +#endif #endif -- 2.25.1
[PATCH v2 5/9] imx8m: clock: add enable_pwm_clk function
Add enable_pwm_clk function in clock.h Signed-off-by: Tommaso Merciai --- Changes since v1: - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks arch/arm/include/asm/arch-imx8m/clock.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h index 50359d8e46..e320025990 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -278,3 +278,4 @@ int set_clk_enet(enum enet_freq type); int set_clk_eqos(enum enet_freq type); void hab_caam_clock_enable(unsigned char enable); void enable_usboh3_clk(unsigned int enable); +void enable_pwm_clk(u32 index, unsigned char enable); -- 2.25.1
[PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function
Add function enable_pwm_clk into in clock_imx8mm.c. This
function first configure, then enable pwm clock from clock control
register. The following configuration is used:
source(0) -> 24 MHz ref clock
div(0)-> no division for this clock
References:
- iMX8MMRM.pdf p 303
Signed-off-by: Tommaso Merciai
---
Changes since v1:
- Fix enable_pwm_clk function implementation. Now is generic for all pwm clks
arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++
1 file changed, 53 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 49945faf2c..ffb9456607 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -313,6 +313,59 @@ void enable_usboh3_clk(unsigned int enable)
}
}
+void enable_pwm_clk(u32 index, unsigned char enable)
+{
+ switch (index) {
+ case 0:
+ if (enable) {
+ clock_enable(CCGR_PWM1, false);
+ clock_set_target_val(PWM1_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0) |
+
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
+ clock_enable(CCGR_PWM1, true);
+ } else {
+ clock_enable(CCGR_PWM1, false);
+ }
+ return;
+ case 1:
+ if (enable) {
+ clock_enable(CCGR_PWM2, false);
+ clock_set_target_val(PWM2_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0) |
+
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
+ clock_enable(CCGR_PWM2, true);
+ } else {
+ clock_enable(CCGR_PWM2, false);
+ }
+ return;
+ case 2:
+ if (enable) {
+ clock_enable(CCGR_PWM3, false);
+ clock_set_target_val(PWM3_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0) |
+
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
+ clock_enable(CCGR_PWM3, true);
+ } else {
+ clock_enable(CCGR_PWM3, false);
+ }
+ return;
+ case 3:
+ if (enable) {
+ clock_enable(CCGR_PWM4, false);
+ clock_set_target_val(PWM4_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0) |
+
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
+ clock_enable(CCGR_PWM4, true);
+ } else {
+ clock_enable(CCGR_PWM4, false);
+ }
+ return;
+ default:
+ printf("Invalid pwm index\n");
+ return;
+ }
+}
+
void init_uart_clk(u32 index)
{
/*
--
2.25.1
[PATCH v2 3/9] arch: mach-imx: imx8m: add pwm_regs struct in imx-regs
Add pwm_regs struct for i.MX8MM SOC
Signed-off-by: Tommaso Merciai
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 13538ba5f6..9217f93a50 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -361,6 +361,15 @@ struct src {
#define PWMCR_CLKSRC_IPG (1 << 16)
#define PWMCR_EN (1 << 0)
+struct pwm_regs {
+ u32 cr;
+ u32 sr;
+ u32 ir;
+ u32 sar;
+ u32 pr;
+ u32 cnr;
+};
+
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASKBIT(0)
struct wdog_regs {
--
2.25.1
[PATCH v2 2/9] arch: mach-imx: imx8m: add pwm ctrl registers fields defines
Add pwm control registers fields defines into imx-regs.h:
- prescaler
- dozeen
- waiten
- dbgen
- clksrc_ipg_high
- clksrc_ipg, en field
References:
- iMX8MMRM.pdf p 3884
Signed-off-by: Tommaso Merciai
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 38f8ba41c3..13538ba5f6 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -353,6 +353,14 @@ struct src {
u32 ddr2_rcr;
};
+#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN (1 << 24)
+#define PWMCR_WAITEN (1 << 23)
+#define PWMCR_DBGEN(1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define PWMCR_CLKSRC_IPG (1 << 16)
+#define PWMCR_EN (1 << 0)
+
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASKBIT(0)
struct wdog_regs {
--
2.25.1
[PATCH v2 1/9] arch: mach-imx: imx8m: add pwm1/pwm2 base address
Add pwm1/pwm2 base address defines into imx-regs file References: - IMX8MMRM.pdf p 3882 Signed-off-by: Tommaso Merciai --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 11389a0f4d..38f8ba41c3 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -31,6 +31,8 @@ #define SRC_BASE_ADDR 0x3039 #define GPC_BASE_ADDR 0x303A +#define PWM1_BASE_ADDR 0x3066 +#define PWM2_BASE_ADDR 0x3067 #define SYSCNT_RD_BASE_ADDR0x306A #define SYSCNT_CMP_BASE_ADDR 0x306B #define SYSCNT_CTRL_BASE_ADDR 0x306C -- 2.25.1
[PATCH v2 0/9] imx8mm: add pwm-imx backlight support
Hi, This series add support for pwm/backlight on i.MX8MM evk: 1. Add pwm1/pwm2 base address registers defines 2. Add defines for pwm control register field 3. Add struct pwm_regs 4. Add enable_pwm_clk function, configure and enable pwm clock control register 5. Add enable_pwm_clk function in clock.h 6. Add CONFIG_IMX6_PWM_PER_CLK in imx8mm_evk.h 7. Add backlight/pwm1 dts nodes support for iMX8MM evk 8. Enable pwm clk into spl 9. Enable support for pwm-imx/backlight for iMX8MM evk Regards, Tommaso Tommaso Merciai (9): arch: mach-imx: imx8m: add pwm1/pwm2 base address arch: mach-imx: imx8m: add pwm ctrl registers fields defines arch: mach-imx: imx8m: add pwm_regs struct in imx-regs arm: imx: imx8mm: add enable_pwm_clk function imx8m: clock: add enable_pwm_clk function configs: imx8mm_evk: add CONFIG_IMX6_PWM_PER_CLK config imx8mm_evk: spl: enable pwm clock arm: dts: imx8mm_evk: add pwm1/backlight support configs: imx8mm_evk: add pwm backlight support arch/arm/dts/imx8mm-evk.dtsi | 21 + arch/arm/include/asm/arch-imx8m/clock.h| 1 + arch/arm/include/asm/arch-imx8m/imx-regs.h | 19 arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++ board/freescale/imx8mm_evk/spl.c | 4 ++ configs/imx8mm_evk_defconfig | 5 ++ include/configs/imx8mm_evk.h | 3 ++ 7 files changed, 106 insertions(+) -- 2.25.1
Re: [PATCH 8/9] arm: dts: imx8mm_evk: add pwm1/backlight support
On Wed, Mar 16, 2022 at 12:54:06PM +0100, Michael Walle wrote:
> Am 2022-03-16 12:51, schrieb Tommaso Merciai:
> > On Wed, Mar 16, 2022 at 12:45:22PM +0100, Michael Walle wrote:
> > > Am 2022-03-16 12:42, schrieb Tommaso Merciai:
> > > > On Wed, Mar 16, 2022 at 11:30:19AM +0100, Michael Walle wrote:
> > > > > > Add pwm1/backlight support nodes for imx8mm_evk board
> > > > > >
> > > > > > Signed-off-by: Tommaso Merciai
> > > > > >
> > > > > > ---
> > > > > > arch/arm/dts/imx8mm-evk.dtsi | 21 +
> > > > > > 1 file changed, 21 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/arm/dts/imx8mm-evk.dtsi
> > > > > > b/arch/arm/dts/imx8mm-evk.dtsi
> > > > > > index 60179e006d..e7a2bd8a64 100644
> > > > > > --- a/arch/arm/dts/imx8mm-evk.dtsi
> > > > > > +++ b/arch/arm/dts/imx8mm-evk.dtsi
> > > > > > @@ -41,6 +41,15 @@
> > > > > > enable-active-high;
> > > > > > };
> > > > > >
> > > > > > + backlight: backlight {
> > > > > > + status = "disabled";
> > > > > > + compatible = "pwm-backlight";
> > > > > > + pwms = <&pwm1 0 500>;
> > > > > > + brightness-levels = <0 255>;
> > > > > > + num-interpolated-steps = <255>;
> > > > > > + default-brightness-level = <250>;
> > > > > > + };
> > > > > > +
> > > > > > ir-receiver {
> > > > > > compatible = "gpio-ir-receiver";
> > > > > > gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
> > > > > > @@ -350,6 +359,12 @@
> > > > > > status = "okay";
> > > > > > };
> > > > > >
> > > > > > +&pwm1 {
> > > > > > + pinctrl-names = "default";
> > > > > > + pinctrl-0 = <&pinctrl_backlight>;
> > > > > > + status = "disabled";
> > > > > > +};
> > > > > > +
> > > > > > &iomuxc {
> > > > > > pinctrl_fec1: fec1grp {
> > > > > > fsl,pins = <
> > > > > > @@ -491,4 +506,10 @@
> > > > > > MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B0x166
> > > > > > >;
> > > > > > };
> > > > > > +
> > > > > > + pinctrl_backlight: backlightgrp {
> > > > > > + fsl,pins = <
> > > > > > + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT0x06
> > > > > > + >;
> > > > > > + };
> > > > >
> > > > > Will this also be submitted to upstream linux? Otherwise, the device
> > > > > trees will diverge.
> > > > >
> > > > > -michael
> > > >
> > > > Hi,
> > > > At the moment on upstream linux, backlight on pwm1 is not handle. This
> > > > will also be submitted on upstream Linux once will merged on U-Boot.
> > >
> > > Actually, it should be the other way around, because the device trees
> > > should be synced with linux once in a while. So while I don't oppose
> > > to do it this way, your changes might eventually be overwritten if
> > > this won't be merged with linux.
> > >
> > > -michael
> >
> > Hi Michael,
> > Then you suggest to submit to the Kernel also?
>
> The goal should be to have the kernel device trees in sync with
> the kernel. So yes, it should also be submitted to the kernel
> device tree.
>
> -michael
Hi Michael,
Thanks for your suggestion, then I will also send this on the Kernel :)
Tommaso
--
Tommaso Merciai
Embedded Linux Engineer
tommaso.merc...@amarulasolutions.com
__
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH 8/9] arm: dts: imx8mm_evk: add pwm1/backlight support
On Wed, Mar 16, 2022 at 12:45:22PM +0100, Michael Walle wrote:
> Am 2022-03-16 12:42, schrieb Tommaso Merciai:
> > On Wed, Mar 16, 2022 at 11:30:19AM +0100, Michael Walle wrote:
> > > > Add pwm1/backlight support nodes for imx8mm_evk board
> > > >
> > > > Signed-off-by: Tommaso Merciai
> > > > ---
> > > > arch/arm/dts/imx8mm-evk.dtsi | 21 +
> > > > 1 file changed, 21 insertions(+)
> > > >
> > > > diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
> > > > index 60179e006d..e7a2bd8a64 100644
> > > > --- a/arch/arm/dts/imx8mm-evk.dtsi
> > > > +++ b/arch/arm/dts/imx8mm-evk.dtsi
> > > > @@ -41,6 +41,15 @@
> > > > enable-active-high;
> > > > };
> > > >
> > > > + backlight: backlight {
> > > > + status = "disabled";
> > > > + compatible = "pwm-backlight";
> > > > + pwms = <&pwm1 0 500>;
> > > > + brightness-levels = <0 255>;
> > > > + num-interpolated-steps = <255>;
> > > > + default-brightness-level = <250>;
> > > > + };
> > > > +
> > > > ir-receiver {
> > > > compatible = "gpio-ir-receiver";
> > > > gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
> > > > @@ -350,6 +359,12 @@
> > > > status = "okay";
> > > > };
> > > >
> > > > +&pwm1 {
> > > > + pinctrl-names = "default";
> > > > + pinctrl-0 = <&pinctrl_backlight>;
> > > > + status = "disabled";
> > > > +};
> > > > +
> > > > &iomuxc {
> > > > pinctrl_fec1: fec1grp {
> > > > fsl,pins = <
> > > > @@ -491,4 +506,10 @@
> > > > MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B0x166
> > > > >;
> > > > };
> > > > +
> > > > + pinctrl_backlight: backlightgrp {
> > > > + fsl,pins = <
> > > > + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT0x06
> > > > + >;
> > > > + };
> > >
> > > Will this also be submitted to upstream linux? Otherwise, the device
> > > trees will diverge.
> > >
> > > -michael
> >
> > Hi,
> > At the moment on upstream linux, backlight on pwm1 is not handle. This
> > will also be submitted on upstream Linux once will merged on U-Boot.
>
> Actually, it should be the other way around, because the device trees
> should be synced with linux once in a while. So while I don't oppose
> to do it this way, your changes might eventually be overwritten if
> this won't be merged with linux.
>
> -michael
Hi Michael,
Then you suggest to submit to the Kernel also?
Thanks,
Tommaso
--
Tommaso Merciai
Embedded Linux Engineer
tommaso.merc...@amarulasolutions.com
__
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH 8/9] arm: dts: imx8mm_evk: add pwm1/backlight support
On Wed, Mar 16, 2022 at 11:30:19AM +0100, Michael Walle wrote:
> > Add pwm1/backlight support nodes for imx8mm_evk board
> >
> > Signed-off-by: Tommaso Merciai
> > ---
> > arch/arm/dts/imx8mm-evk.dtsi | 21 +
> > 1 file changed, 21 insertions(+)
> >
> > diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
> > index 60179e006d..e7a2bd8a64 100644
> > --- a/arch/arm/dts/imx8mm-evk.dtsi
> > +++ b/arch/arm/dts/imx8mm-evk.dtsi
> > @@ -41,6 +41,15 @@
> > enable-active-high;
> > };
> >
> > + backlight: backlight {
> > + status = "disabled";
> > + compatible = "pwm-backlight";
> > + pwms = <&pwm1 0 500>;
> > + brightness-levels = <0 255>;
> > + num-interpolated-steps = <255>;
> > + default-brightness-level = <250>;
> > + };
> > +
> > ir-receiver {
> > compatible = "gpio-ir-receiver";
> > gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
> > @@ -350,6 +359,12 @@
> > status = "okay";
> > };
> >
> > +&pwm1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_backlight>;
> > + status = "disabled";
> > +};
> > +
> > &iomuxc {
> > pinctrl_fec1: fec1grp {
> > fsl,pins = <
> > @@ -491,4 +506,10 @@
> > MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B0x166
> > >;
> > };
> > +
> > + pinctrl_backlight: backlightgrp {
> > + fsl,pins = <
> > + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT0x06
> > + >;
> > + };
>
> Will this also be submitted to upstream linux? Otherwise, the device
> trees will diverge.
>
> -michael
Hi,
At the moment on upstream linux, backlight on pwm1 is not handle. This
will also be submitted on upstream Linux once will merged on U-Boot.
Regards,
Tommaso
--
Tommaso Merciai
Embedded Linux Engineer
tommaso.merc...@amarulasolutions.com
__
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH 8/9] arm: dts: imx8mm_evk: add pwm1/backlight support
On Wed, Mar 16, 2022 at 11:30:19AM +0100, Michael Walle wrote:
> > Add pwm1/backlight support nodes for imx8mm_evk board
> >
> > Signed-off-by: Tommaso Merciai
> > ---
> > arch/arm/dts/imx8mm-evk.dtsi | 21 +
> > 1 file changed, 21 insertions(+)
> >
> > diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
> > index 60179e006d..e7a2bd8a64 100644
> > --- a/arch/arm/dts/imx8mm-evk.dtsi
> > +++ b/arch/arm/dts/imx8mm-evk.dtsi
> > @@ -41,6 +41,15 @@
> > enable-active-high;
> > };
> >
> > + backlight: backlight {
> > + status = "disabled";
> > + compatible = "pwm-backlight";
> > + pwms = <&pwm1 0 500>;
> > + brightness-levels = <0 255>;
> > + num-interpolated-steps = <255>;
> > + default-brightness-level = <250>;
> > + };
> > +
> > ir-receiver {
> > compatible = "gpio-ir-receiver";
> > gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
> > @@ -350,6 +359,12 @@
> > status = "okay";
> > };
> >
> > +&pwm1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_backlight>;
> > + status = "disabled";
> > +};
> > +
> > &iomuxc {
> > pinctrl_fec1: fec1grp {
> > fsl,pins = <
> > @@ -491,4 +506,10 @@
> > MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B0x166
> > >;
> > };
> > +
> > + pinctrl_backlight: backlightgrp {
> > + fsl,pins = <
> > + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT0x06
> > + >;
> > + };
>
> Will this also be submitted to upstream linux? Otherwise, the device
> trees will diverge.
>
> -michael
Hi Michael,
Thanks for review, I'll check and update in v2.
Tommaso
--
Tommaso Merciai
Embedded Linux Engineer
tommaso.merc...@amarulasolutions.com
__
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH 4/9] arm: imx: imx8mm: add enable_pwm_clk function
On Wed, Mar 16, 2022 at 10:05:47AM +0100, Michael Nazzareno Trimarchi wrote:
> Hi
>
> On Wed, Mar 16, 2022 at 10:02 AM Tommaso Merciai
> wrote:
> >
> > Add function to enable_pwm_clck function into clock_imx8mm.c. This
> > function first configure, then enable pwm1 clock from clock control
> > register. The following configuration is used:
> >
> > source(0) -> 24 MHz ref clock
> > div(0)-> no division for this clock
> >
> > References:
> > - iMX8MMRM.pdf p 303
> >
> > Signed-off-by: Tommaso Merciai
> > ---
> > arch/arm/mach-imx/imx8m/clock_imx8mm.c | 11 +++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > index 49945faf2c..5f2eddf715 100644
> > --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > @@ -313,6 +313,17 @@ void enable_usboh3_clk(unsigned int enable)
> > }
> > }
> >
> > +void enable_pwm_clk(unsigned char enable)
> > +{
> > + if (enable) {
> > + clock_enable(CCGR_PWM1, false);
> > + clock_set_target_val(PWM1_CLK_ROOT, CLK_ROOT_ON |
> > CLK_ROOT_SOURCE_SEL(0) |CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
> > + clock_enable(CCGR_PWM1, true);
> > + } else {
> > + clock_enable(CCGR_PWM1, false);
> > + }
> > +}
> > +
>
> Show not be somenthing like
> enable_pwm_clk(enum pwm_id, bool enable)
>
> ?
Hi,
Like init_clk_usdhc(u32 index) function in clock_imx8mm.c?
Ack, I'll send v2.
Thanks,
Tommaso
>
> > void init_uart_clk(u32 index)
> > {
> > /*
> > --
> > 2.25.1
> >
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> mich...@amarulasolutions.com
> __
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> i...@amarulasolutions.com
> www.amarulasolutions.com
--
Tommaso Merciai
Embedded Linux Engineer
tommaso.merc...@amarulasolutions.com
__
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
i...@amarulasolutions.com
www.amarulasolutions.com
[PATCH 7/9] imx8mm_evk: spl: enable pwm clock
Enable pwm clock into spl Signed-off-by: Tommaso Merciai --- board/freescale/imx8mm_evk/spl.c | 4 1 file changed, 4 insertions(+) diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index 4ef7f6f180..5aabdba0b0 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -135,6 +135,10 @@ void board_init_f(ulong dummy) init_uart_clk(1); +#ifdef CONFIG_PWM_IMX + enable_pwm_clk(1); +#endif + board_early_init_f(); timer_init(); -- 2.25.1
[PATCH 8/9] arm: dts: imx8mm_evk: add pwm1/backlight support
Add pwm1/backlight support nodes for imx8mm_evk board
Signed-off-by: Tommaso Merciai
---
arch/arm/dts/imx8mm-evk.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
index 60179e006d..e7a2bd8a64 100644
--- a/arch/arm/dts/imx8mm-evk.dtsi
+++ b/arch/arm/dts/imx8mm-evk.dtsi
@@ -41,6 +41,15 @@
enable-active-high;
};
+ backlight: backlight {
+ status = "disabled";
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 500>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <255>;
+ default-brightness-level = <250>;
+ };
+
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
@@ -350,6 +359,12 @@
status = "okay";
};
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ status = "disabled";
+};
+
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
@@ -491,4 +506,10 @@
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B0x166
>;
};
+
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT0x06
+ >;
+ };
};
--
2.25.1
[PATCH 9/9] configs: imx8mm_evk: add pwm backlight support
Enable support for backlight/pwm-imx driver Signed-off-by: Tommaso Merciai --- configs/imx8mm_evk_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 01395fc7eb..cfba6cc673 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -84,3 +84,8 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_DM_PWM=y +CONFIG_PWM_IMX=y \ No newline at end of file -- 2.25.1
[PATCH 6/9] configs: imx8mm_evk: add CONFIG_IMX6_PWM_PER_CLK config
In order to support pwm-imx-util CONFIG_IMX6_PWM_PER_CLK is needed. At the moment driver don't support clock framework Signed-off-by: Tommaso Merciai --- include/configs/imx8mm_evk.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index c7022ef0f7..3c17dd3773 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -91,4 +91,7 @@ #define IMX_FEC_BASE 0x30BE +#ifdef CONFIG_PWM_IMX + #define CONFIG_IMX6_PWM_PER_CLK 6600 +#endif #endif -- 2.25.1
[PATCH 5/9] imx8m: clock: add enable_pwm_clk function
Add enable_pwm_clk function in clock.h Signed-off-by: Tommaso Merciai --- arch/arm/include/asm/arch-imx8m/clock.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h index 50359d8e46..5692bafcea 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -278,3 +278,4 @@ int set_clk_enet(enum enet_freq type); int set_clk_eqos(enum enet_freq type); void hab_caam_clock_enable(unsigned char enable); void enable_usboh3_clk(unsigned int enable); +void enable_pwm_clk(unsigned char enable); -- 2.25.1
[PATCH 4/9] arm: imx: imx8mm: add enable_pwm_clk function
Add function to enable_pwm_clck function into clock_imx8mm.c. This
function first configure, then enable pwm1 clock from clock control
register. The following configuration is used:
source(0) -> 24 MHz ref clock
div(0)-> no division for this clock
References:
- iMX8MMRM.pdf p 303
Signed-off-by: Tommaso Merciai
---
arch/arm/mach-imx/imx8m/clock_imx8mm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 49945faf2c..5f2eddf715 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -313,6 +313,17 @@ void enable_usboh3_clk(unsigned int enable)
}
}
+void enable_pwm_clk(unsigned char enable)
+{
+ if (enable) {
+ clock_enable(CCGR_PWM1, false);
+ clock_set_target_val(PWM1_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0) |CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
+ clock_enable(CCGR_PWM1, true);
+ } else {
+ clock_enable(CCGR_PWM1, false);
+ }
+}
+
void init_uart_clk(u32 index)
{
/*
--
2.25.1
[PATCH 3/9] arch: mach-imx: imx8m: add pwm_regs struct in imx-regs
Add pwm_regs struct for i.MX8MM SOC
Signed-off-by: Tommaso Merciai
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 13538ba5f6..9217f93a50 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -361,6 +361,15 @@ struct src {
#define PWMCR_CLKSRC_IPG (1 << 16)
#define PWMCR_EN (1 << 0)
+struct pwm_regs {
+ u32 cr;
+ u32 sr;
+ u32 ir;
+ u32 sar;
+ u32 pr;
+ u32 cnr;
+};
+
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASKBIT(0)
struct wdog_regs {
--
2.25.1
[PATCH 2/9] arch: mach-imx: imx8m: add pwm ctrl registers fields defines
Add pwm control registers fields defines into imx-regs.h:
- prescaler
- dozeen
- waiten
- dbgen
- clksrc_ipg_high
- clksrc_ipg, en field
References:
- iMX8MMRM.pdf p 3884
Signed-off-by: Tommaso Merciai
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 38f8ba41c3..13538ba5f6 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -353,6 +353,14 @@ struct src {
u32 ddr2_rcr;
};
+#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN (1 << 24)
+#define PWMCR_WAITEN (1 << 23)
+#define PWMCR_DBGEN(1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define PWMCR_CLKSRC_IPG (1 << 16)
+#define PWMCR_EN (1 << 0)
+
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASKBIT(0)
struct wdog_regs {
--
2.25.1
[PATCH 1/9] arch: mach-imx: imx8m: add pwm1/pwm2 base address
Add pwm1/pwm2 base address defines into imx-regs file References: - IMX8MMRM.pdf p 3882 Signed-off-by: Tommaso Merciai --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 11389a0f4d..38f8ba41c3 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -31,6 +31,8 @@ #define SRC_BASE_ADDR 0x3039 #define GPC_BASE_ADDR 0x303A +#define PWM1_BASE_ADDR 0x3066 +#define PWM2_BASE_ADDR 0x3067 #define SYSCNT_RD_BASE_ADDR0x306A #define SYSCNT_CMP_BASE_ADDR 0x306B #define SYSCNT_CTRL_BASE_ADDR 0x306C -- 2.25.1
[PATCH 0/9] imx8mm: add pwm-imx backlight support
Hi, This series add support for pwm/backlight on i.MX8MM evk: 1. Add pwm1/pwm2 base address registers defines 2. Add defines for pwm control register field 3. Add struct pwm_regs 4. Add enable_pwm_clk function, configure and enable pwm clock control register 5. Add enable_pwm_clk function in clock.h 6. Add CONFIG_IMX6_PWM_PER_CLK in imx8mm_evk.h 7. Add backlight/pwm1 dts nodes support for iMX8MM evk 8. Enable pwm clk into spl 9. Enable support for pwm-imx/backlight for iMX8MM evk Regards, Tommaso Tommaso Merciai (9): arch: mach-imx: imx8m: add pwm1/pwm2 base address arch: mach-imx: imx8m: add pwm ctrl registers fields defines arch: mach-imx: imx8m: add pwm_regs struct into imx-regs.h arm: imx: imx8mm: add enable_pwm_clk function imx8m: clock: add enable_pwm_clk function configs: imx8mm_evk: add CONFIG_IMX6_PWM_PER_CLK config imx8mm_evk: spl: enable pwm clock arm: dts: imx8mm_evk: add pwm1 backlight support configs: imx8mm_evk: add pwm backlight support arch/arm/dts/imx8mm-evk.dtsi | 21 + arch/arm/include/asm/arch-imx8m/clock.h| 1 + arch/arm/include/asm/arch-imx8m/imx-regs.h | 19 +++ arch/arm/mach-imx/imx8m/clock_imx8mm.c | 11 +++ board/freescale/imx8mm_evk/spl.c | 4 configs/imx8mm_evk_defconfig | 5 + include/configs/imx8mm_evk.h | 3 +++ 7 files changed, 64 insertions(+) -- 2.25.1
Re: iMX8MM USB support?
> > > Here's what I'm seeing: > > > > > > U-Boot SPL 2020.01-00029-g6529a03-dirty (Apr 09 2020 - 13:02:21 -0700) > > > Normal Boot > > > Trying to boot from USB SDP > > > SDP: initialize... > > > SDP: handle requests... > > > Downloading file of size 584020 to 0x4020... done > > > Jumping to header at 0x4020 > > > Header Tag is not an IMX image > > > > > > Is the 'Header Tag' message normal? From adding some debugging it > > > appears to matching the dts name in my board_fit_config_name_match and > > > parsing the FIT image, loading the ATF and jumping but then I get > > > nothing. What would I expect at this point and do you have any > > > troubleshooting tips? > > > > > > > Frieder, > > > > My issue was that I forgot to set ATF_LOAD_ADDR=0x92! > > > > So I'm running now, booting imx8mm-evk via SDP using your USB patches > > and imx_usb configuration. > > > > Thank you for your help! > > > > Tim > > > Michael > > -- > Michael Nazzareno Trimarchi > Co-Founder & Chief Executive Officer > M. +39 347 913 2170 > mich...@amarulasolutions.com > __ > > Amarula Solutions BV > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > T. +31 (0)85 111 9172 > i...@amarulasolutions.com > www.amarulasolutions.com -- Tommaso Merciai Embedded Linux Developer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH] freescale: imx8mm_evk: Use IS_ENABLED instead of #ifdef
On Sat, Feb 19, 2022 at 02:08:09PM +0100, sba...@denx.de wrote: > > Use IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) to make the code > > more readable and fix checkpatch.pl warning > > Signed-off-by: Tommaso Merciai > Applied to u-boot-imx, master, thanks ! Hi Stefano, Thanks for the update. Tommaso > > Best regards, > Stefano Babic > > -- > = > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de > ========= -- Tommaso Merciai Embedded Linux Developer tommaso.merc...@amarulasolutions.com __ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH v4 4/4] phytec: phycore_imx8mp: override env_get_location
On Tue, Feb 01, 2022 at 05:22:06AM -0600, Adam Ford wrote:
> On Tue, Feb 1, 2022 at 3:09 AM Tommaso Merciai
> wrote:
> >
> > On Tue, Feb 01, 2022 at 04:16:52AM +0100, Marek Vasut wrote:
> > > On 1/31/22 23:15, Tommaso Merciai wrote:
> > > > On Mon, Jan 31, 2022 at 06:03:58PM +0100, Marek Vasut wrote:
> > > > > On 1/31/22 17:58, Tommaso Merciai wrote:
> > > > > > Override env_get_location function at board level, previously
> > > > > > dropped
> > > > > > down from arch/arm/mach-imx/imx8m/soc.c
> > > > > >
> > > > > > References:
> > > > > >- commit 98af80d3c969e69a1b8ce98bb20e5ad844022da2
> > > > > >
> > > > > > Signed-off-by: Tommaso Merciai
> > > > > >
> > > > > > ---
> > > > > >board/phytec/phycore_imx8mp/phycore-imx8mp.c | 33
> > > > > >
> > > > > >1 file changed, 33 insertions(+)
> > > > > >
> > > > > > diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
> > > > > > b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
> > > > > > index a8f0821437..05926eefa3 100644
> > > > > > --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
> > > > > > +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
> > > > > > @@ -11,9 +11,42 @@
> > > > > >#include
> > > > > >#include
> > > > > >#include
> > > > > > +#include
> > > > > >DECLARE_GLOBAL_DATA_PTR;
> > > > > > +enum env_location env_get_location(enum env_operation op, int prio)
> > > > > > +{
> > > > >
> > > > > Why don't you just turn this into default __weak function and
> > > > > override it on
> > > > > board level when it is really needed to be overridden ?
> > > >
> > > > Hi Marek,
> > > > env_get_location is already declared as __weak, check env/env.c. We
> > > > can't override it 2 times.
> > >
> > > Oh, it is this problem with missing ability to define multiple levels of
> > > symbol strength.
> > >
> > > __weak enum env_location arch_env_get_location(enum env_operation op, int
> > > prio)
> > > {
> > > if (prio >= ARRAY_SIZE(env_locations))
> > > return ENVL_UNKNOWN;
> > >
> > > return env_locations[prio];
> > > }
> > >
> > > __weak enum env_location board_env_get_location(enum env_operation op, int
> > > prio)
> > > {
> > > return arch_env_get_location(op, prio);
> > > }
> > >
> > > __weak enum env_location env_get_location(enum env_operation op, int prio)
> > > {
> > > return board_env_get_location(op, prio);
> > > }
> > >
> > > By default, the compiler will optimize it all out. If you have
> > > arch-specific
> > > default (like imx does), implement arch_env_get_location(), if you have
> > > even
> > > board-specific default (like your board likely does), implement
> > > board_env_get_location(), if you need to override both, then override
> > > env_get_location() (unlikely).
> > >
> > > This is also inline with all the other arch_*() and board_*() functions we
> > > have, and you won't have much duplication either.
> >
> > Hi Marek,
> > Thanks for the tips, then if I understand correctly, your idea is: use:
> >
> > arch_env_get_location in (soc.c)
> >
> > In this way imx8m users can override this function at board level using:
> >
> > board_env_get_location
> >
> > right?
>
> What about those of us who want to use the default option found in
> env.c?
Hi Adam,
You are right. Mmm in this way you have to duplicate the code of env.c
into your board.c. This doesn't look very functional.
I think remove it from soc.c is the right way.
> It seems like we're creating more abstraction to address the
> abstraction we don't all want. From my interpretation, the whole
> point of creating the default in env.c was to let people define the
> location of their environment, and this function in soc.c undid that.
> If people want it for their boards, put this function in their boards,
> otherwise, just use the default, or write your own.
Ack.
tommaso
>
> adam
> >
> > Thanks,
> > Tommaso
> >
> > --
> > Tommaso Merciai
> > Embedded Linux Developer
> > tommaso.merc...@amarulasolutions.com
> > __
> >
> > Amarula Solutions SRL
> > Via Le Canevare 30, 31100 Treviso, Veneto, IT
> > T. +39 042 243 5310
> > i...@amarulasolutions.com
> > www.amarulasolutions.com
--
Tommaso Merciai
Embedded Linux Developer
tommaso.merc...@amarulasolutions.com
__
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH v4 4/4] phytec: phycore_imx8mp: override env_get_location
On Tue, Feb 01, 2022 at 04:16:52AM +0100, Marek Vasut wrote:
> On 1/31/22 23:15, Tommaso Merciai wrote:
> > On Mon, Jan 31, 2022 at 06:03:58PM +0100, Marek Vasut wrote:
> > > On 1/31/22 17:58, Tommaso Merciai wrote:
> > > > Override env_get_location function at board level, previously dropped
> > > > down from arch/arm/mach-imx/imx8m/soc.c
> > > >
> > > > References:
> > > >- commit 98af80d3c969e69a1b8ce98bb20e5ad844022da2
> > > >
> > > > Signed-off-by: Tommaso Merciai
> > > > ---
> > > >board/phytec/phycore_imx8mp/phycore-imx8mp.c | 33
> > > >
> > > >1 file changed, 33 insertions(+)
> > > >
> > > > diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
> > > > b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
> > > > index a8f0821437..05926eefa3 100644
> > > > --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
> > > > +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
> > > > @@ -11,9 +11,42 @@
> > > >#include
> > > >#include
> > > >#include
> > > > +#include
> > > >DECLARE_GLOBAL_DATA_PTR;
> > > > +enum env_location env_get_location(enum env_operation op, int prio)
> > > > +{
> > >
> > > Why don't you just turn this into default __weak function and override it
> > > on
> > > board level when it is really needed to be overridden ?
> >
> > Hi Marek,
> > env_get_location is already declared as __weak, check env/env.c. We
> > can't override it 2 times.
>
> Oh, it is this problem with missing ability to define multiple levels of
> symbol strength.
>
> __weak enum env_location arch_env_get_location(enum env_operation op, int
> prio)
> {
> if (prio >= ARRAY_SIZE(env_locations))
> return ENVL_UNKNOWN;
>
> return env_locations[prio];
> }
>
> __weak enum env_location board_env_get_location(enum env_operation op, int
> prio)
> {
> return arch_env_get_location(op, prio);
> }
>
> __weak enum env_location env_get_location(enum env_operation op, int prio)
> {
> return board_env_get_location(op, prio);
> }
>
> By default, the compiler will optimize it all out. If you have arch-specific
> default (like imx does), implement arch_env_get_location(), if you have even
> board-specific default (like your board likely does), implement
> board_env_get_location(), if you need to override both, then override
> env_get_location() (unlikely).
>
> This is also inline with all the other arch_*() and board_*() functions we
> have, and you won't have much duplication either.
Hi Marek,
Thanks for the tips, then if I understand correctly, your idea is: use:
arch_env_get_location in (soc.c)
In this way imx8m users can override this function at board level using:
board_env_get_location
right?
Thanks,
Tommaso
--
Tommaso Merciai
Embedded Linux Developer
tommaso.merc...@amarulasolutions.com
__
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH v4 4/4] phytec: phycore_imx8mp: override env_get_location
On Mon, Jan 31, 2022 at 06:03:58PM +0100, Marek Vasut wrote:
> On 1/31/22 17:58, Tommaso Merciai wrote:
> > Override env_get_location function at board level, previously dropped
> > down from arch/arm/mach-imx/imx8m/soc.c
> >
> > References:
> > - commit 98af80d3c969e69a1b8ce98bb20e5ad844022da2
> >
> > Signed-off-by: Tommaso Merciai
> > ---
> > board/phytec/phycore_imx8mp/phycore-imx8mp.c | 33
> > 1 file changed, 33 insertions(+)
> >
> > diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
> > b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
> > index a8f0821437..05926eefa3 100644
> > --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
> > +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
> > @@ -11,9 +11,42 @@
> > #include
> > #include
> > #include
> > +#include
> > DECLARE_GLOBAL_DATA_PTR;
> > +enum env_location env_get_location(enum env_operation op, int prio)
> > +{
>
> Why don't you just turn this into default __weak function and override it on
> board level when it is really needed to be overridden ?
Hi Marek,
env_get_location is already declared as __weak, check env/env.c. We
can't override it 2 times.
References:
-
https://developer.arm.com/documentation/dui0491/i/Compiler-specific-Features/--weak
--
Tommaso Merciai
Embedded Linux Developer
tommaso.merc...@amarulasolutions.com
__
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
i...@amarulasolutions.com
www.amarulasolutions.com
[PATCH v4 3/4] imx: imx8mp_evk: override env_get_location
Override env_get_location function at board level, previously dropped
down from soc.c
References:
- commit 98af80d3c969e69a1b8ce98bb20e5ad844022da2
Signed-off-by: Tommaso Merciai
---
Changes since v1:
- Fix code indentation using checkpatch as suggested by MBehún
board/freescale/imx8mp_evk/imx8mp_evk.c | 34 +
1 file changed, 34 insertions(+)
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
b/board/freescale/imx8mp_evk/imx8mp_evk.c
index 62096c24fb..8548f606d2 100644
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -5,6 +5,7 @@
#include
#include
+#include
#include
#include
#include
@@ -17,6 +18,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -32,6 +34,38 @@ static iomux_v3_cfg_t const wdog_pads[] = {
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ enum boot_device dev = get_boot_device();
+ enum env_location env_loc = ENVL_UNKNOWN;
+
+ if (prio)
+ return env_loc;
+
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH) && dev == QSPI_BOOT) {
+ env_loc = ENVL_SPI_FLASH;
+ } else if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND) && dev == NAND_BOOT) {
+ env_loc = ENVL_NAND;
+ } else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) {
+ switch (dev) {
+ case SD1_BOOT:
+ case SD2_BOOT:
+ case SD3_BOOT:
+ case MMC1_BOOT:
+ case MMC2_BOOT:
+ case MMC3_BOOT:
+ env_loc = ENVL_MMC;
+ break;
+ default:
+ break;
+ }
+ } else if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) {
+ env_loc = ENVL_MMC;
+ }
+
+ return env_loc;
+}
+
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
--
2.25.1
[PATCH v4 4/4] phytec: phycore_imx8mp: override env_get_location
Override env_get_location function at board level, previously dropped
down from arch/arm/mach-imx/imx8m/soc.c
References:
- commit 98af80d3c969e69a1b8ce98bb20e5ad844022da2
Signed-off-by: Tommaso Merciai
---
board/phytec/phycore_imx8mp/phycore-imx8mp.c | 33
1 file changed, 33 insertions(+)
diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
index a8f0821437..05926eefa3 100644
--- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
+++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
@@ -11,9 +11,42 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ enum boot_device dev = get_boot_device();
+ enum env_location env_loc = ENVL_UNKNOWN;
+
+ if (prio)
+ return env_loc;
+
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH) && dev == QSPI_BOOT) {
+ env_loc = ENVL_SPI_FLASH;
+ } else if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND) && dev == NAND_BOOT) {
+ env_loc = ENVL_NAND;
+ } else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) {
+ switch (dev) {
+ case SD1_BOOT:
+ case SD2_BOOT:
+ case SD3_BOOT:
+ case MMC1_BOOT:
+ case MMC2_BOOT:
+ case MMC3_BOOT:
+ env_loc = ENVL_MMC;
+ break;
+ default:
+ break;
+ }
+ } else if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) {
+ env_loc = ENVL_MMC;
+ }
+
+ return env_loc;
+}
+
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
--
2.25.1
[PATCH v4 2/4] imx: imx8mn_evk: override env_get_location
Override env_get_location function at board level, previously dropped
down from soc.c
References:
- commit 98af80d3c969e69a1b8ce98bb20e5ad844022da2
Signed-off-by: Tommaso Merciai
---
Changes since v1:
- Fix code indentation using checkpatch as suggested by MBehún
board/freescale/imx8mn_evk/imx8mn_evk.c | 35 +
1 file changed, 35 insertions(+)
diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c
b/board/freescale/imx8mn_evk/imx8mn_evk.c
index 9a0a0488bf..ec1ab202a6 100644
--- a/board/freescale/imx8mn_evk/imx8mn_evk.c
+++ b/board/freescale/imx8mn_evk/imx8mn_evk.c
@@ -5,11 +5,46 @@
#include
#include
+#include
#include
+#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ enum boot_device dev = get_boot_device();
+ enum env_location env_loc = ENVL_UNKNOWN;
+
+ if (prio)
+ return env_loc;
+
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH) && dev == QSPI_BOOT) {
+ env_loc = ENVL_SPI_FLASH;
+ } else if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND) && dev == NAND_BOOT) {
+ env_loc = ENVL_NAND;
+ } else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) {
+ switch (dev) {
+ case SD1_BOOT:
+ case SD2_BOOT:
+ case SD3_BOOT:
+ case MMC1_BOOT:
+ case MMC2_BOOT:
+ case MMC3_BOOT:
+ env_loc = ENVL_MMC;
+ break;
+ default:
+ break;
+ }
+ } else if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) {
+ env_loc = ENVL_MMC;
+ }
+
+ return env_loc;
+}
+
int board_init(void)
{
return 0;
--
2.25.1
[PATCH v4 1/4] imx8m: drop env_get_location for imx8mn and imx8mp
This function defined for two architecture is not really generic
and can generate problem when people add a new board.
Signed-off-by: Tommaso Merciai
---
arch/arm/mach-imx/imx8m/soc.c | 39 ---
1 file changed, 39 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 863508776d..f0030a557a 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1313,45 +1313,6 @@ void do_error(struct pt_regs *pt_regs, unsigned int esr)
#endif
#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
-enum env_location env_get_location(enum env_operation op, int prio)
-{
- enum boot_device dev = get_boot_device();
- enum env_location env_loc = ENVL_UNKNOWN;
-
- if (prio)
- return env_loc;
-
- switch (dev) {
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
- case QSPI_BOOT:
- env_loc = ENVL_SPI_FLASH;
- break;
-#endif
-#ifdef CONFIG_ENV_IS_IN_NAND
- case NAND_BOOT:
- env_loc = ENVL_NAND;
- break;
-#endif
-#ifdef CONFIG_ENV_IS_IN_MMC
- case SD1_BOOT:
- case SD2_BOOT:
- case SD3_BOOT:
- case MMC1_BOOT:
- case MMC2_BOOT:
- case MMC3_BOOT:
- env_loc = ENVL_MMC;
- break;
-#endif
- default:
-#if defined(CONFIG_ENV_IS_NOWHERE)
- env_loc = ENVL_NOWHERE;
-#endif
- break;
- }
-
- return env_loc;
-}
-
#ifndef ENV_IS_EMBEDDED
long long env_get_offset(long long defautl_offset)
{
--
2.25.1
[PATCH v4 0/4] imx8m: move env_get_location for imx8mn and imx8mp at board level
This series move env_get_location from soc to board level. As suggested by Michael make no sense to define an unique way for multiple board. One board can boot from emmc and having env on spi flash etc.. Anyways, this function is kept in imx8mn_evk, imx8mp_evk, phycore-imx8mp and imx8mn_beacon boards instead of being completely dropped. Note for all imx8mp/imx8mn users: This patch move only the env_get_location function at board level in this way every users can override it depending on own needs. Test it. Tommaso Merciai (4): imx8m: drop env_get_location for imx8mn and imx8mp imx: imx8mn_evk: override env_get_location imx: imx8mp_evk: override env_get_location phytec: phycore_imx8mp: override env_get_location arch/arm/mach-imx/imx8m/soc.c| 39 board/freescale/imx8mn_evk/imx8mn_evk.c | 35 ++ board/freescale/imx8mp_evk/imx8mp_evk.c | 34 + board/phytec/phycore_imx8mp/phycore-imx8mp.c | 33 + 4 files changed, 102 insertions(+), 39 deletions(-) -- 2.25.1
Re: [RFC PATCH v3 4/5] beacon: imx8mn: override env_get_location in imx8mn_beacon.c
On Thu, Jan 27, 2022 at 10:59:51AM -0600, Adam Ford wrote:
> On Wed, Jan 26, 2022 at 2:58 PM Tommaso Merciai
> wrote:
> >
> > On Wed, Jan 26, 2022 at 12:05:22PM -0600, Adam Ford wrote:
> > > On Sat, Dec 25, 2021 at 2:26 PM Tommaso Merciai
> > > wrote:
> > > >
> > > > Override env_get_location function at board level, previously dropped
> > > > down from arch/arm/mach-imx/imx8m/soc.c
> > > >
> > > > References:
> > > > - commit 37d3e3bb95d7532e2503f115dd6c6762fd3b0262
> > > >
> > > > Signed-off-by: Tommaso Merciai
> > >
> >
> > Hi Adam,
> >
> > > I am going to re-do the patch for the beacon board, because I talked
> > > it over with my colleagues, and we'd like to force the environment to
> > > one location or another and not base it on whether or not it was the
> > > boot device.
> > >
> > > I guess my questions is what's the status of the remaining patch
> > > series, and how do I integrate my desired changes into it? I can send
> > > you what I want for my board if you're going to resubmit the series.
> >
> > It's ok for me. Send me your changes.
> > Thanks.
> >
> > > I wonder if a sub-function could be called where the existing
> > > env_get_location() is renamed to something else, but declared as weak
> > > can called from env_get_location. Anyone who wants a their own
> > > function can write their own so we don't have two functions with the
> > > same name declared as weak.
> > >
> > > What are your thoughts on that?
> >
> > Right. In this way every boards that use imx8mp/imx8mn can override this
> > function according to their own needs.
> >
>
Hi Adam,
> After trying some different options, I wonder if we can just delete
> env_get_location() completely from arch/arm/mach-imx/imx8m/soc.c.
>
> For my board, it does exactly what I want when I delete that function
> since the default from env.c is sufficient. I think it's probably
> safest to use your original approach to move them to individual board
> files with the idea that some people may not need it at all. When
> placed into their board files, they can choose what they want for
> themselves.
Ack.
>
> I would suggest sending a patch without the RFC and place the function
> into the various imx8mn and imx8mp boards, but know that you can skip
> the beacon board. I would also suggest that you add a note that
> people should test this to see if it's really what they want or if
> they can live without the code and fall back on the default.
Ok, I'll send v4 of the series (without RFC label) in these days.
Thanks,
Tommaso
>
> adam
>
> > Tommaso
> >
> > >
> > > adam
> > > > ---
> > > > board/beacon/imx8mn/imx8mn_beacon.c | 35 -
> > > > 1 file changed, 34 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/board/beacon/imx8mn/imx8mn_beacon.c
> > > > b/board/beacon/imx8mn/imx8mn_beacon.c
> > > > index 7fe252b262..05ab5613ee 100644
> > > > --- a/board/beacon/imx8mn/imx8mn_beacon.c
> > > > +++ b/board/beacon/imx8mn/imx8mn_beacon.c
> > > > @@ -6,14 +6,47 @@
> > > > #include
> > > > #include
> > > > #include
> > > > -
> > > > +#include
> > > > #include
> > > > #include
> > > > +#include
> > > > #include
> > > > #include
> > > >
> > > > DECLARE_GLOBAL_DATA_PTR;
> > > >
> > > > +enum env_location env_get_location(enum env_operation op, int prio)
> > > > +{
> > > > + enum boot_device dev = get_boot_device();
> > > > + enum env_location env_loc = ENVL_UNKNOWN;
> > > > +
> > > > + if (prio)
> > > > + return env_loc;
> > > > +
> > > > + if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH) && dev == QSPI_BOOT)
> > > > {
> > > > + env_loc = ENVL_SPI_FLASH;
> > > > + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND) && dev ==
> > > > NAND_BOOT) {
> > > > + env_loc = ENVL_NAND;
> > > > + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) {
> > > > + switch (dev) {
> > > > + case SD1_BOOT:
> > > > + case SD2_BOOT:
> > > > + case SD3_BOOT:
> > > > + case MMC1_BOOT:
> > > > + case MMC2_BOOT:
> > > > + case MMC3_BOOT:
> > > > + env_loc = ENVL_MMC;
> > > > + break;
> > > > + default:
> > > > + break;
> > > > + }
> > > > + } else if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) {
> > > > + env_loc = ENVL_MMC;
> > > > + }
> > > > +
> > > > + return env_loc;
> > > > +}
> > > > +
> > > > #if IS_ENABLED(CONFIG_FEC_MXC)
> > > > static int setup_fec(void)
> > > > {
> > > > --
> > > > 2.25.1
> > > >
Re: [RFC PATCH v3 4/5] beacon: imx8mn: override env_get_location in imx8mn_beacon.c
On Wed, Jan 26, 2022 at 12:05:22PM -0600, Adam Ford wrote:
> On Sat, Dec 25, 2021 at 2:26 PM Tommaso Merciai
> wrote:
> >
> > Override env_get_location function at board level, previously dropped
> > down from arch/arm/mach-imx/imx8m/soc.c
> >
> > References:
> > - commit 37d3e3bb95d7532e2503f115dd6c6762fd3b0262
> >
> > Signed-off-by: Tommaso Merciai
>
Hi Adam,
> I am going to re-do the patch for the beacon board, because I talked
> it over with my colleagues, and we'd like to force the environment to
> one location or another and not base it on whether or not it was the
> boot device.
>
> I guess my questions is what's the status of the remaining patch
> series, and how do I integrate my desired changes into it? I can send
> you what I want for my board if you're going to resubmit the series.
It's ok for me. Send me your changes.
Thanks.
> I wonder if a sub-function could be called where the existing
> env_get_location() is renamed to something else, but declared as weak
> can called from env_get_location. Anyone who wants a their own
> function can write their own so we don't have two functions with the
> same name declared as weak.
>
> What are your thoughts on that?
Right. In this way every boards that use imx8mp/imx8mn can override this
function according to their own needs.
Tommaso
>
> adam
> > ---
> > board/beacon/imx8mn/imx8mn_beacon.c | 35 -
> > 1 file changed, 34 insertions(+), 1 deletion(-)
> >
> > diff --git a/board/beacon/imx8mn/imx8mn_beacon.c
> > b/board/beacon/imx8mn/imx8mn_beacon.c
> > index 7fe252b262..05ab5613ee 100644
> > --- a/board/beacon/imx8mn/imx8mn_beacon.c
> > +++ b/board/beacon/imx8mn/imx8mn_beacon.c
> > @@ -6,14 +6,47 @@
> > #include
> > #include
> > #include
> > -
> > +#include
> > #include
> > #include
> > +#include
> > #include
> > #include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > +enum env_location env_get_location(enum env_operation op, int prio)
> > +{
> > + enum boot_device dev = get_boot_device();
> > + enum env_location env_loc = ENVL_UNKNOWN;
> > +
> > + if (prio)
> > + return env_loc;
> > +
> > + if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH) && dev == QSPI_BOOT) {
> > + env_loc = ENVL_SPI_FLASH;
> > + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND) && dev == NAND_BOOT) {
> > + env_loc = ENVL_NAND;
> > + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) {
> > + switch (dev) {
> > + case SD1_BOOT:
> > + case SD2_BOOT:
> > + case SD3_BOOT:
> > + case MMC1_BOOT:
> > + case MMC2_BOOT:
> > + case MMC3_BOOT:
> > + env_loc = ENVL_MMC;
> > + break;
> > + default:
> > + break;
> > + }
> > + } else if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) {
> > + env_loc = ENVL_MMC;
> > + }
> > +
> > + return env_loc;
> > +}
> > +
> > #if IS_ENABLED(CONFIG_FEC_MXC)
> > static int setup_fec(void)
> > {
> > --
> > 2.25.1
> >
Re: [RFC PATCH v3 1/5] imx8m: drop env_get_location for imx8mn and imx8mp
On Tue, Jan 11, 2022 at 09:35:54AM +, Teresa Remmet wrote:
> Hello Tommaso,
>
> Am Samstag, dem 08.01.2022 um 20:08 +0100 schrieb Tommaso Merciai:
> > On Tue, Jan 04, 2022 at 11:04:10AM +, Teresa Remmet wrote:
> > > Hello Tommaso,
> > >
> > > Am Samstag, dem 25.12.2021 um 21:25 +0100 schrieb Tommaso Merciai:
> > > > This function defined for two architecture is not really generic
> > > > and can generate problem when people add a new board.
> > > >
> > > > Signed-off-by: Tommaso Merciai
> > > > ---
> > > > arch/arm/mach-imx/imx8m/soc.c | 39 ---
> > > >
> > > >
> > > > 1 file changed, 39 deletions(-)
> > > >
> > > > diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-
> > > > imx/imx8m/soc.c
> > > > index 863508776d..f0030a557a 100644
> > > > --- a/arch/arm/mach-imx/imx8m/soc.c
> > > > +++ b/arch/arm/mach-imx/imx8m/soc.c
> > > > @@ -1313,45 +1313,6 @@ void do_error(struct pt_regs *pt_regs,
> > > > unsigned int esr)
> > > > #endif
> > > >
> > > > #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
> > > > -enum env_location env_get_location(enum env_operation op, int
> > > > prio)
> > > > -{
> > > > - enum boot_device dev = get_boot_device();
> > > > - enum env_location env_loc = ENVL_UNKNOWN;
> > > > -
> > > > - if (prio)
> > > > - return env_loc;
> > > > -
> > > > - switch (dev) {
> > > > -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
> > > > - case QSPI_BOOT:
> > > > - env_loc = ENVL_SPI_FLASH;
> > > > - break;
> > > > -#endif
> > > > -#ifdef CONFIG_ENV_IS_IN_NAND
> > > > - case NAND_BOOT:
> > > > - env_loc = ENVL_NAND;
> > > > - break;
> > > > -#endif
> > > > -#ifdef CONFIG_ENV_IS_IN_MMC
> > > > - case SD1_BOOT:
> > > > - case SD2_BOOT:
> > > > - case SD3_BOOT:
> > > > - case MMC1_BOOT:
> > > > - case MMC2_BOOT:
> > > > - case MMC3_BOOT:
> > > > - env_loc = ENVL_MMC;
> > > > - break;
> > > > -#endif
> > > > - default:
> > > > -#if defined(CONFIG_ENV_IS_NOWHERE)
> > > > - env_loc = ENVL_NOWHERE;
> > > > -#endif
> > > > - break;
> > > > - }
> > > > -
> > > > - return env_loc;
> > > > -}
> > > > -
> > > > #ifndef ENV_IS_EMBEDDED
> > > > long long env_get_offset(long long defautl_offset)
> > >
> > > would it not make sense to move also env_get_offset() to board
> > > level?
> >
> > Hi Teresa,
> > I think is better to put this function at board level. In this way
> > others boards that use i.MX8MN/i.MX8MM SOC can customize
> > env_get_location
> > function. For example: maybe one user want store U-Boot env on a
> > device
> > other than the boot device.
>
> Michael send a patch to remove the function. Which I missed. See:
> https://lore.kernel.org/u-boot/2027143456.34441-1-mich...@amarulasolutions.com/
>
> So everything is fine then.
>
> Thanks,
> Teresa
Hi Teresa,
Perfect.
Thanks,
Tommaso
>
> >
> > Tommaso
> > > Regards,
> > > Teresa
> > >
> > >
> > > > {
> > > --
> > > PHYTEC Messtechnik GmbH | Robert-Koch-Str. 39 | 55129 Mainz,
> > > Germany
> > >
> > > Geschäftsführer: Dipl.-Ing. Michael Mitezki, Dipl.-Ing. Bodo Huber
> > > |
> > > Handelsregister Mainz HRB 4656 | Finanzamt Mainz | St.Nr.
> > > 266500608, DE
> > > 149059855
> --
> PHYTEC Messtechnik GmbH | Robert-Koch-Str. 39 | 55129 Mainz, Germany
>
> Geschäftsführer: Dipl.-Ing. Michael Mitezki, Dipl.-Ing. Bodo Huber |
> Handelsregister Mainz HRB 4656 | Finanzamt Mainz | St.Nr. 266500608, DE
> 149059855
Re: [RFC PATCH v3 1/5] imx8m: drop env_get_location for imx8mn and imx8mp
On Tue, Jan 04, 2022 at 11:04:10AM +, Teresa Remmet wrote:
> Hello Tommaso,
>
> Am Samstag, dem 25.12.2021 um 21:25 +0100 schrieb Tommaso Merciai:
> > This function defined for two architecture is not really generic
> > and can generate problem when people add a new board.
> >
> > Signed-off-by: Tommaso Merciai
> > ---
> > arch/arm/mach-imx/imx8m/soc.c | 39 ---
> >
> > 1 file changed, 39 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-
> > imx/imx8m/soc.c
> > index 863508776d..f0030a557a 100644
> > --- a/arch/arm/mach-imx/imx8m/soc.c
> > +++ b/arch/arm/mach-imx/imx8m/soc.c
> > @@ -1313,45 +1313,6 @@ void do_error(struct pt_regs *pt_regs,
> > unsigned int esr)
> > #endif
> >
> > #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
> > -enum env_location env_get_location(enum env_operation op, int prio)
> > -{
> > - enum boot_device dev = get_boot_device();
> > - enum env_location env_loc = ENVL_UNKNOWN;
> > -
> > - if (prio)
> > - return env_loc;
> > -
> > - switch (dev) {
> > -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
> > - case QSPI_BOOT:
> > - env_loc = ENVL_SPI_FLASH;
> > - break;
> > -#endif
> > -#ifdef CONFIG_ENV_IS_IN_NAND
> > - case NAND_BOOT:
> > - env_loc = ENVL_NAND;
> > - break;
> > -#endif
> > -#ifdef CONFIG_ENV_IS_IN_MMC
> > - case SD1_BOOT:
> > - case SD2_BOOT:
> > - case SD3_BOOT:
> > - case MMC1_BOOT:
> > - case MMC2_BOOT:
> > - case MMC3_BOOT:
> > - env_loc = ENVL_MMC;
> > - break;
> > -#endif
> > - default:
> > -#if defined(CONFIG_ENV_IS_NOWHERE)
> > - env_loc = ENVL_NOWHERE;
> > -#endif
> > - break;
> > - }
> > -
> > - return env_loc;
> > -}
> > -
> > #ifndef ENV_IS_EMBEDDED
> > long long env_get_offset(long long defautl_offset)
>
> would it not make sense to move also env_get_offset() to board level?
Hi Teresa,
I think is better to put this function at board level. In this way
others boards that use i.MX8MN/i.MX8MM SOC can customize env_get_location
function. For example: maybe one user want store U-Boot env on a device
other than the boot device.
Tommaso
>
> Regards,
> Teresa
>
>
> > {
> --
> PHYTEC Messtechnik GmbH | Robert-Koch-Str. 39 | 55129 Mainz, Germany
>
> Geschäftsführer: Dipl.-Ing. Michael Mitezki, Dipl.-Ing. Bodo Huber |
> Handelsregister Mainz HRB 4656 | Finanzamt Mainz | St.Nr. 266500608, DE
> 149059855
Re: [PATCH 2/2] udoo: neo: Do not print the Model information
On Wed, Jan 05, 2022 at 10:10:03PM +0100, Tommaso Merciai wrote: > On Wed, Jan 05, 2022 at 05:52:23PM -0300, Fabio Estevam wrote: > > Hi Tommaso, > > > > On Wed, Jan 5, 2022 at 5:47 PM Tommaso Merciai > > wrote: > > > > > Hi Fabio, > > > Thanks, I test your patch on basic and extended model. Below some logs > > > seems all work properly. I hope I helped the cause :) > > > > Yes, thanks a lot! It's a pleasure, nice team work :) Tommaso > > > > > - BASIC log: > > > - > > > U-Boot 2022.01-rc4-00034-g19f31e718f-dirty (Jan 05 2022 - 21:38:32 +0100) > > > > > > CPU: Freescale i.MX6SX rev1.2 996 MHz (running at 792 MHz) > > > CPU: Extended Commercial temperature grade (-20C to 105C) at 32C > > > Reset cause: POR > > > Model: UDOO Neo Basic > > > > I assume you have only applied 1/2 and not 2/2. > > > > With 2/2 applied the Model line should not be printed. > > > > Thanks > > Yes, Fabio. Sorry, I forgot. Below test with 2/2. > > U-Boot 2022.01-rc4-00034-g19f31e718f-dirty (Jan 05 2022 - 22:07:22 +0100) > > CPU: Freescale i.MX6SX rev1.2 996 MHz (running at 792 MHz) > CPU: Extended Commercial temperature grade (-20C to 105C) at 45C > Reset cause: POR > Board: UDOO Neo BASIC > I2C: ready > DRAM: 512 MiB > PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 > MMC: FSL_SDHC: 1, FSL_SDHC: 2 > Loading Environment from MMC... OK > In:serial > Out: serial > Err: serial > Net: eth0: ethernet@2188000 > Hit any key to stop autoboot: 0 > > > U-Boot 2022.01-rc4-00034-g19f31e718f-dirty (Jan 05 2022 - 22:07:22 +0100) > > CPU: Freescale i.MX6SX rev1.2 996 MHz (running at 792 MHz) > CPU: Extended Commercial temperature grade (-20C to 105C) at 35C > Reset cause: POR > Board: UDOO Neo EXTENDED > I2C: ready > DRAM: 1 GiB > PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 > MMC: FSL_SDHC: 1, FSL_SDHC: 2 > Loading Environment from MMC... OK > In:serial > Out: serial > Err: serial > Net: > Error: ethernet@2188000 address not set. > No ethernet found. > > Hit any key to stop autoboot: 0 > > Thanks, > Tommaso
Re: [PATCH 2/2] udoo: neo: Do not print the Model information
On Wed, Jan 05, 2022 at 05:52:23PM -0300, Fabio Estevam wrote: > Hi Tommaso, > > On Wed, Jan 5, 2022 at 5:47 PM Tommaso Merciai wrote: > > > Hi Fabio, > > Thanks, I test your patch on basic and extended model. Below some logs > > seems all work properly. I hope I helped the cause :) > > Yes, thanks a lot! > > > - BASIC log: > > - > > U-Boot 2022.01-rc4-00034-g19f31e718f-dirty (Jan 05 2022 - 21:38:32 +0100) > > > > CPU: Freescale i.MX6SX rev1.2 996 MHz (running at 792 MHz) > > CPU: Extended Commercial temperature grade (-20C to 105C) at 32C > > Reset cause: POR > > Model: UDOO Neo Basic > > I assume you have only applied 1/2 and not 2/2. > > With 2/2 applied the Model line should not be printed. > > Thanks Yes, Fabio. Sorry, I forgot. Below test with 2/2. U-Boot 2022.01-rc4-00034-g19f31e718f-dirty (Jan 05 2022 - 22:07:22 +0100) CPU: Freescale i.MX6SX rev1.2 996 MHz (running at 792 MHz) CPU: Extended Commercial temperature grade (-20C to 105C) at 45C Reset cause: POR Board: UDOO Neo BASIC I2C: ready DRAM: 512 MiB PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In:serial Out: serial Err: serial Net: eth0: ethernet@2188000 Hit any key to stop autoboot: 0 U-Boot 2022.01-rc4-00034-g19f31e718f-dirty (Jan 05 2022 - 22:07:22 +0100) CPU: Freescale i.MX6SX rev1.2 996 MHz (running at 792 MHz) CPU: Extended Commercial temperature grade (-20C to 105C) at 35C Reset cause: POR Board: UDOO Neo EXTENDED I2C: ready DRAM: 1 GiB PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In:serial Out: serial Err: serial Net: Error: ethernet@2188000 address not set. No ethernet found. Hit any key to stop autoboot: 0 Thanks, Tommaso
Re: [PATCH 2/2] udoo: neo: Do not print the Model information
On Mon, Jan 03, 2022 at 12:15:12PM -0300, Fabio Estevam wrote:
> By default the Model information from DT is printed:
>
> CPU: Freescale i.MX6SX rev1.2 996 MHz (running at 792 MHz)
> CPU: Extended Commercial temperature grade (-20C to 105C) at 63C
> Reset cause: POR
> Model: UDOO Neo Basic
> Board: UDOO Neo FULL
> I2C: ready
>
> As the udoo basic DT is used, such output may be confusing.
>
> Improve it by only printing the Board model instead, which is
> read from the board identification GPIOs.
Hi Fabio,
Thanks, I test your patch on basic and extended model. Below some logs
seems all work properly. I hope I helped the cause :)
- BASIC log:
-
U-Boot 2022.01-rc4-00034-g19f31e718f-dirty (Jan 05 2022 - 21:38:32 +0100)
CPU: Freescale i.MX6SX rev1.2 996 MHz (running at 792 MHz)
CPU: Extended Commercial temperature grade (-20C to 105C) at 32C
Reset cause: POR
Model: UDOO Neo Basic
Board: UDOO Neo BASIC
I2C: ready
DRAM: 512 MiB
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:serial
Out: serial
Err: serial
Net: eth0: ethernet@2188000 [PRIME]
Hit
--
- EXTENDED LOG:
--
U-Boot 2022.01-rc4-00034-g19f31e718f-dirty (Jan 05 2022 - 21:38:32 +0100)
CPU: Freescale i.MX6SX rev1.2 996 MHz (running at 792 MHz)
CPU: Extended Commercial temperature grade (-20C to 105C) at 42C
Reset cause: POR
Model: UDOO Neo Basic
Board: UDOO Neo EXTENDED
I2C: ready
DRAM: 1 GiB
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:serial
Out: serial
Err: serial
Net:
Error: ethernet@2188000 address not set.
No ethernet found.
Hit any key to stop autoboot: 0
--------
Acked-by: Tommaso Merciai
Tested-by: Tommaso Merciai
Tommaso
>
> Signed-off-by: Fabio Estevam
> ---
> This applies on top of Peter's series:
> https://lore.kernel.org/all/20211221123249.455347-1-pbrobin...@gmail.com/T
>
> board/udoo/neo/neo.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
> index 0c0d3f615d18..da6a0b4e9247 100644
> --- a/board/udoo/neo/neo.c
> +++ b/board/udoo/neo/neo.c
> @@ -350,7 +350,8 @@ static char *board_string(int type)
> return "UNDEFINED";
> }
>
> -int checkboard(void)
> +/* Override the default implementation, DT model is not accurate */
> +int show_board_info(void)
> {
> int *board_type = (int *)OCRAM_START;
>
> --
> 2.25.1
>
Re: [PATCH] udoo_neo: fix udoo neo UNDEFINED
On Sun, Jan 02, 2022 at 04:28:35PM -0300, Fabio Estevam wrote: > Hi Tommaso, > > On Sun, Jan 2, 2022 at 3:27 PM Tommaso Merciai wrote: > > > > get_board_value function fails to get the right board configuration on > > second time that is call. This patch move get_board_value function at > > spl level, once is call, store the right configuration into gd static > > variable gd->board_type and fix the previous error. > > get_board_value is now call only one time. > > > > Signed-off-by: Tommaso Merciai > > I tested your patch on my udoo neo full, but it reports "BASIC" now: > > U-Boot SPL 2022.01-rc4-00031-gc5c4ced998e3-dirty (Jan 02 2022 - 16:22:05 > -0300) > Trying to boot from MMC1 > > > U-Boot 2022.01-rc4-00031-gc5c4ced998e3-dirty (Jan 02 2022 - 16:22:05 -0300) > > CPU: Freescale i.MX6SX rev1.2 996 MHz (running at 792 MHz) > CPU: Extended Commercial temperature grade (-20C to 105C) at 59C > Reset cause: WDOG > Model: UDOO Neo Basic > Board: UDOO Neo BASIC > I2C: ready > DRAM: 1 GiB > > (The size is correctly detected as 'full' though') Hi Fabio, Sent v2, I think this issue is fixed. Can you test it please. The ploblem is that after spl, gd->board_type is re-initialized. Using get_board_value inside board_early_init_f seems solve. Let me know. Thanks, Tommaso Merciai
[PATCH v2] udoo_neo: fix udoo neo UNDEFINED
get_board_value function fails to get the right board configuration on
second time that is call. This patch move get_board_value function at
spl level, once is call, store the right configuration into gd static
variable gd->board_type and fix the previous error.
get_board_value is now call only one time.
Signed-off-by: Tommaso Merciai
---
Changes since v1
- get_board_value declared as void
- fix gd->board_type, re-initialized after spl
board/udoo/neo/neo.c | 12 ++--
configs/udoo_neo_defconfig | 1 +
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
index 62f81fff68..808b727fb0 100644
--- a/board/udoo/neo/neo.c
+++ b/board/udoo/neo/neo.c
@@ -308,7 +308,7 @@ int board_init(void)
return 0;
}
-static int get_board_value(void)
+static void get_board_value(void)
{
int r184, r185;
@@ -333,12 +333,13 @@ static int get_board_value(void)
* Extended 11
*/
- return (r184 << 1) + r185;
+ gd->board_type = (r184 << 1) + r185;
}
int board_early_init_f(void)
{
setup_iomux_uart();
+ get_board_value();
return 0;
}
@@ -370,7 +371,7 @@ int board_mmc_init(struct bd_info *bis)
static char *board_string(void)
{
- switch (get_board_value()) {
+ switch (gd->board_type) {
case UDOO_NEO_TYPE_BASIC:
return "BASIC";
case UDOO_NEO_TYPE_BASIC_KS:
@@ -498,8 +499,6 @@ static void ccgr_init(void)
static void spl_dram_init(void)
{
- int board = get_board_value();
-
struct mx6_ddr_sysinfo sysinfo = {
.dsize = 1, /* width of data bus: 1 = 32 bits */
.cs_density = 24,
@@ -516,7 +515,8 @@ static void spl_dram_init(void)
};
mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
+ if (gd->board_type == UDOO_NEO_TYPE_BASIC ||
+ gd->board_type == UDOO_NEO_TYPE_BASIC_KS)
mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
&neo_basic_mem_ddr);
else
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index ca08de1bd4..eff33909d7 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig
@@ -62,3 +62,4 @@ CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
+CONFIG_BOARD_TYPES=y
\ No newline at end of file
--
2.25.1
Re: [PATCH] udoo_neo: fix udoo neo UNDEFINED
On Sun, Jan 02, 2022 at 04:28:35PM -0300, Fabio Estevam wrote: > Hi Tommaso, > > On Sun, Jan 2, 2022 at 3:27 PM Tommaso Merciai wrote: > > > > get_board_value function fails to get the right board configuration on > > second time that is call. This patch move get_board_value function at > > spl level, once is call, store the right configuration into gd static > > variable gd->board_type and fix the previous error. > > get_board_value is now call only one time. > > > > Signed-off-by: Tommaso Merciai > > I tested your patch on my udoo neo full, but it reports "BASIC" now: > > U-Boot SPL 2022.01-rc4-00031-gc5c4ced998e3-dirty (Jan 02 2022 - 16:22:05 > -0300) > Trying to boot from MMC1 > > > U-Boot 2022.01-rc4-00031-gc5c4ced998e3-dirty (Jan 02 2022 - 16:22:05 -0300) > > CPU: Freescale i.MX6SX rev1.2 996 MHz (running at 792 MHz) > CPU: Extended Commercial temperature grade (-20C to 105C) at 59C > Reset cause: WDOG > Model: UDOO Neo Basic > Board: UDOO Neo BASIC > I2C: ready > DRAM: 1 GiB > > (The size is correctly detected as 'full' though') Hi Fabio, Thanks for your test. I'll investigate on the reason and let you know. Tommaso Merciai
