Re: [PATCH v6 05/11] soc: ti: k3-navss-ringacc: Fix reconfiguration of qmode API
On 26/08/24 15:55, Chintan Vankar wrote: > Function "k3_ringacc_ring_reconfig_qmode_raw()" should reset qmode to > requested value and should not update other fields in ring configuration > register. > > Signed-off-by: Chintan Vankar > --- > Thanks for fix this up: Reviewed-by: Vignesh Raghavendra > This patch is newely added in this series. > > drivers/soc/ti/k3-navss-ringacc-u-boot.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/soc/ti/k3-navss-ringacc-u-boot.c > b/drivers/soc/ti/k3-navss-ringacc-u-boot.c > index 2799f214c77..8227d8bc3e3 100644 > --- a/drivers/soc/ti/k3-navss-ringacc-u-boot.c > +++ b/drivers/soc/ti/k3-navss-ringacc-u-boot.c > @@ -42,7 +42,7 @@ static void k3_ringacc_ring_reconfig_qmode_raw(struct > k3_nav_ring *ring, enum k3 > u32 val; > > val = readl(&ring->cfg->size); > - val &= KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK; > + val &= ~KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK; > val |= mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT; > writel(val, &ring->cfg->size); > } -- Regards Vignesh
[PATCH] mtd: nand: raw: omap_gpmc: Check return value of gpmc_nand_init
If the function is called with no NAND device attached, then this function can return error value, proceeding further ignoring the same can cause system crash. This is seen when "mtd list" is run with no NAND addon cards connected. Signed-off-by: Vignesh Raghavendra --- drivers/mtd/nand/raw/omap_gpmc.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 92a92ad63a02..a36e2a148ccc 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -1188,7 +1188,10 @@ static int gpmc_nand_probe(struct udevice *dev) return ret; base = devm_ioremap(dev, res.start, resource_size(&res)); - gpmc_nand_init(nand, base); + ret = gpmc_nand_init(nand, base); + if (ret) + return ret; + mtd->dev = dev; nand_set_flash_node(nand, dev_ofnode(dev)); -- 2.45.2
[PATCH] spl: Kconfig: ARCH_K3: Set default SPL_STACK_R_MALLOC_SIMPLE_LEN for R5 build
All ARCH_K3 platforms need about of 2MB of malloc space post reallocation. Since, this space is allocated from SDRAM, provide a generous 2MB space by default. Platforms requiring more than 2MB can override in defconfig as needed. Signed-off-by: Vignesh Raghavendra --- common/spl/Kconfig | 1 + configs/am62px_evm_r5_defconfig| 1 - configs/am62x_evm_r5_defconfig | 1 - configs/j721s2_evm_r5_defconfig| 1 - configs/j784s4_evm_r5_defconfig| 1 - configs/phycore_am62x_r5_defconfig | 1 - configs/verdin-am62_r5_defconfig | 1 - 7 files changed, 1 insertion(+), 6 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 6405374bcc12..46bacad2d81b 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -409,6 +409,7 @@ config SPL_STACK_R_MALLOC_SIMPLE_LEN depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE hex "Size of malloc_simple heap after switching to DRAM SPL stack" default 0x40 if ARCH_K3 && ARM64 + default 0x20 if ARCH_K3 && CPU_V7R default 0x10 help Specify the amount of the stack to use as memory pool for diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index b365c7ea902f..ace55696737a 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -23,7 +23,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c4b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20 CONFIG_SPL_SIZE_LIMIT=0x3C000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000 CONFIG_SPL_FS_FAT=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 648241488ed0..4b2e57b13a09 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -26,7 +26,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20 CONFIG_SPL_SIZE_LIMIT=0x3A7F0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_FS_FAT=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 5ef5247a3e00..0352f940041c 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -24,7 +24,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41c76000 CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x14 CONFIG_SPL_SIZE_LIMIT=0x8 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index f5fe7432206b..d6a702cdfe96 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -24,7 +24,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41c76000 CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x14 CONFIG_SPL_SIZE_LIMIT=0x8 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index 389672d52271..05f8ace748b7 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -26,7 +26,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20 CONFIG_SPL_SIZE_LIMIT=0x3A7F0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_FS_FAT=y diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig index 06c63fa64880..8266a7f6e8f1 100644 --- a/configs/verdin-am62_r5_defconfig +++ b/configs/verdin-am62_r5_defconfig @@ -23,7 +23,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20 CONFIG_SPL_SIZE_LIMIT=0x3A7F0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_LIBDISK_SUPPORT=y -- 2.45.1
Re: [PATCH 1/2] arm: mach-k3: am625: copy bootindex to OCRAM for main domain SPL
On 05/03/24 01:57, Bryan Brattlof wrote: > Hey Vignesh! > > On March 4, 2024 thus sayeth Vignesh Raghavendra: >> Hi Wadim, >> >> On 26/02/24 19:00, Wadim Egorov wrote: >>> Texas Instruments has begun enabling security settings on the SoCs it >>> produces to instruct ROM and TIFS to begin protecting the Security >>> Management Subsystem (SMS) from other binaries we load into the chip by >>> default. >>> >>> One way ROM and TIFS do this is by enabling firewalls to protect the >>> OCSRAM and HSM RAM regions they're using during bootup. >>> >>> The HSM RAM the wakeup SPL is in is firewalled by TIFS to protect >>> itself from the main domain applications. This means the 'bootindex' >>> value in HSM RAM, left by ROM to indicate if we're using the primary >>> or secondary boot-method, must be moved to OCSRAM (that TIFS has open >>> for us) before we make the jump to the main domain so the main domain's >>> bootloaders can keep access to this information. >>> >>> Based on commit >>> b672e8581070 ("arm: mach-k3: copy bootindex to OCRAM for main domain SPL") >>> >> >> FYI, this is mostly a problem in non SPL flow (TI prosperity SBL for >> example) where HSM RAM would be used by HSM firmware. This should be a >> issue in R5 SPL flow. Do you see any issues today? If so, whats the >> TIFS firmware being used? >> >>> Signed-off-by: Wadim Egorov >>> --- >>> arch/arm/mach-k3/Kconfig | 3 ++- >>> arch/arm/mach-k3/am625_init.c | 15 +-- >>> arch/arm/mach-k3/include/mach/am62_hardware.h | 15 +++ >>> 3 files changed, 30 insertions(+), 3 deletions(-) >>> >>> diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig >>> index 03898424c9..f5d06593f7 100644 >>> --- a/arch/arm/mach-k3/Kconfig >>> +++ b/arch/arm/mach-k3/Kconfig >>> @@ -75,7 +75,8 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX >>> default 0x41cffbfc if SOC_K3_J721E >>> default 0x41cfdbfc if SOC_K3_J721S2 >>> default 0x701bebfc if SOC_K3_AM642 >>> - default 0x43c3f290 if SOC_K3_AM625 >>> + default 0x43c3f290 if SOC_K3_AM625 && CPU_V7R >>> + default 0x7000f290 if SOC_K3_AM625 && ARM64 >>> default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R >>> default 0x7000f290 if SOC_K3_AM62A7 && ARM64 >>> help >>> diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c >>> index 6c96e88114..67cf63b103 100644 >>> --- a/arch/arm/mach-k3/am625_init.c >>> +++ b/arch/arm/mach-k3/am625_init.c >>> @@ -35,8 +35,10 @@ static struct rom_extended_boot_data bootdata >>> __section(".data"); >>> static void store_boot_info_from_rom(void) >>> { >>> bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); >>> - memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO, >>> - sizeof(struct rom_extended_boot_data)); >>> + if (IS_ENABLED(CONFIG_CPU_V7R)) { >>> + memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO, >>> + sizeof(struct rom_extended_boot_data)); >>> + } >>> } >>> >>> static void ctrl_mmr_unlock(void) >>> @@ -175,6 +177,15 @@ void board_init_f(ulong dummy) >>> k3_sysfw_loader(true, NULL, NULL); >>> } >>> >>> +#if defined(CONFIG_CPU_V7R) >>> + /* >>> +* Relocate boot information to OCRAM (after TIFS has opend this >>> +* region for us) so the next bootloader stages can keep access to >>> +* primary vs backup bootmodes. >>> +*/ >>> + writel(bootindex, K3_BOOT_PARAM_TABLE_INDEX_OCRAM); >>> +#endif >>> + >>> /* >>> * Force probe of clk_k3 driver here to ensure basic default clock >>> * configuration is always done. >>> diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h >>> b/arch/arm/mach-k3/include/mach/am62_hardware.h >>> index 54380f36e1..9f504f4642 100644 >>> --- a/arch/arm/mach-k3/include/mach/am62_hardware.h >>> +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h >>> @@ -76,8 +76,23 @@ >>> #define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + >>> 0x18170) >>> >>> #define ROM_EXTENDED_BOOT_DATA_INFO0x43c3f1e0 >>> +#define
Re: [PATCH 1/2] arm: mach-k3: am625: copy bootindex to OCRAM for main domain SPL
Hi Wadim, On 26/02/24 19:00, Wadim Egorov wrote: > Texas Instruments has begun enabling security settings on the SoCs it > produces to instruct ROM and TIFS to begin protecting the Security > Management Subsystem (SMS) from other binaries we load into the chip by > default. > > One way ROM and TIFS do this is by enabling firewalls to protect the > OCSRAM and HSM RAM regions they're using during bootup. > > The HSM RAM the wakeup SPL is in is firewalled by TIFS to protect > itself from the main domain applications. This means the 'bootindex' > value in HSM RAM, left by ROM to indicate if we're using the primary > or secondary boot-method, must be moved to OCSRAM (that TIFS has open > for us) before we make the jump to the main domain so the main domain's > bootloaders can keep access to this information. > > Based on commit > b672e8581070 ("arm: mach-k3: copy bootindex to OCRAM for main domain SPL") > FYI, this is mostly a problem in non SPL flow (TI prosperity SBL for example) where HSM RAM would be used by HSM firmware. This should be a issue in R5 SPL flow. Do you see any issues today? If so, whats the TIFS firmware being used? > Signed-off-by: Wadim Egorov > --- > arch/arm/mach-k3/Kconfig | 3 ++- > arch/arm/mach-k3/am625_init.c | 15 +-- > arch/arm/mach-k3/include/mach/am62_hardware.h | 15 +++ > 3 files changed, 30 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig > index 03898424c9..f5d06593f7 100644 > --- a/arch/arm/mach-k3/Kconfig > +++ b/arch/arm/mach-k3/Kconfig > @@ -75,7 +75,8 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX > default 0x41cffbfc if SOC_K3_J721E > default 0x41cfdbfc if SOC_K3_J721S2 > default 0x701bebfc if SOC_K3_AM642 > - default 0x43c3f290 if SOC_K3_AM625 > + default 0x43c3f290 if SOC_K3_AM625 && CPU_V7R > + default 0x7000f290 if SOC_K3_AM625 && ARM64 > default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R > default 0x7000f290 if SOC_K3_AM62A7 && ARM64 > help > diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c > index 6c96e88114..67cf63b103 100644 > --- a/arch/arm/mach-k3/am625_init.c > +++ b/arch/arm/mach-k3/am625_init.c > @@ -35,8 +35,10 @@ static struct rom_extended_boot_data bootdata > __section(".data"); > static void store_boot_info_from_rom(void) > { > bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); > - memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO, > -sizeof(struct rom_extended_boot_data)); > + if (IS_ENABLED(CONFIG_CPU_V7R)) { > + memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO, > +sizeof(struct rom_extended_boot_data)); > + } > } > > static void ctrl_mmr_unlock(void) > @@ -175,6 +177,15 @@ void board_init_f(ulong dummy) > k3_sysfw_loader(true, NULL, NULL); > } > > +#if defined(CONFIG_CPU_V7R) > + /* > + * Relocate boot information to OCRAM (after TIFS has opend this > + * region for us) so the next bootloader stages can keep access to > + * primary vs backup bootmodes. > + */ > + writel(bootindex, K3_BOOT_PARAM_TABLE_INDEX_OCRAM); > +#endif > + > /* >* Force probe of clk_k3 driver here to ensure basic default clock >* configuration is always done. > diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h > b/arch/arm/mach-k3/include/mach/am62_hardware.h > index 54380f36e1..9f504f4642 100644 > --- a/arch/arm/mach-k3/include/mach/am62_hardware.h > +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h > @@ -76,8 +76,23 @@ > #define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170) > > #define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0 > +#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290 > > +/* > + * During the boot process ROM will kill anything that writes to OCSRAM. R5 ROM is long gone when R5 SPL starts, how would it kill anything? > + * This means the wakeup SPL cannot use this region during boot. To > + * complicate things, TIFS will set a firewall between HSM RAM and the > + * main domain. > + * > + * So, during the wakeup SPL, we will need to store the EEPROM data > + * somewhere in HSM RAM, and the main domain's SPL will need to store it > + * somewhere in OCSRAM > + */ > +#ifdef CONFIG_CPU_V7R > #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c3 > +#else > + #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7001 Why not 0x7000 ? > +#endif /* CONFIG_CPU_V7R */ > Can't we store directly in OCRAM in both stages? This RAM should be accessible post TIFS is up (ie post k3_sysfw_loader() call) > static inline int k3_get_core_nr(void) > { -- Regards Vignesh
Re: [PATCH] arm: dts: k3-am625-verdin-r5: Change CPU frequency to 1000MHz
On 19/02/24 18:04, Vitor Soares wrote: > From: Vitor Soares > > The same U-Boot binary is compatible with multiple Verdin AM62 board > variants. However, some of the SoC models can only operate at a maximum > speed of 1 GHz. > > Previously, the boards with lower-speed grades were running at > overclocked speeds, leading to kernel complaints about unsupported > configurations. > > To resolve this issue, the operating speed has been decreased to the > maximum allowable value across all Verdin AM62 board variants. As a > result, there is a regression in overall boot time, increasing by around > 200 milliseconds for the faster SoC variant. > Patch as such is fine. But one way to avoid boot regression is to fixup the clock freq using based on speed grade identified by k3_get_speed_grade() and freq mapping table for each letter as show in datasheet [0] This may need VDD_CORE voltage information via PMIC driver. Even w/o that could at least bump to 1.25Ghz safely. [0] https://www.ti.com/lit/ds/symlink/am625.pdf Table 7-1. Device Speed Grades > Signed-off-by: Vitor Soares > --- > arch/arm/dts/k3-am625-verdin-r5.dts | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts > b/arch/arm/dts/k3-am625-verdin-r5.dts > index 305d199678..6b03e7405a 100644 > --- a/arch/arm/dts/k3-am625-verdin-r5.dts > +++ b/arch/arm/dts/k3-am625-verdin-r5.dts > @@ -23,7 +23,7 @@ >*/ > assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks > 157 20>; > assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 > 22>; > - assigned-clock-rates = <2>, <12>, <2500>; > + assigned-clock-rates = <2>, <10>, <2500>; > clocks = <&k3_clks 61 0>; > power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, > <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, -- Regards Vignesh
Re: [PATCH 1/3] board: ti: common: add rtc setup to common folder
On 08/11/23 04:51, Bryan Brattlof wrote: > All of the starter kit boards for the am62xxx extended family utilize > the same 32k crystal oscillator for a more accurate clock for the RTC > instance. Add the setup the clock mux and debounce configuration to the > common board directory so the entire am62xxx extended family can utilize > it. > > Signed-off-by: Bryan Brattlof > --- > board/ti/common/Kconfig | 8 +++ > board/ti/common/rtc.c | 47 + > 2 files changed, 55 insertions(+) > create mode 100644 board/ti/common/rtc.c > > diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig > index 49edd98014ab7..56a65c0a402bb 100644 > --- a/board/ti/common/Kconfig > +++ b/board/ti/common/Kconfig > @@ -1,3 +1,11 @@ > +config BOARD_HAS_32K_RTC_CRYSTAL > + bool "Enable the 32k crystial for RTC" > + help > +Some of Texas Instrument's Starter-Kit boards have > +an onboard 32k crystal. Select this option if you wish Uboot > +to enable this crystal for Linux > + default n > + > config TI_I2C_BOARD_DETECT > bool "Support for Board detection for TI platforms" > help > diff --git a/board/ti/common/rtc.c b/board/ti/common/rtc.c > new file mode 100644 > index 0..e117a927765c5 > --- /dev/null > +++ b/board/ti/common/rtc.c > @@ -0,0 +1,47 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * RTC setup for TI Platforms > + * > + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ > + */ > +#include > +#include > +#include > + > +#define WKUP_CTRLMMR_DBOUNCE_CFG1 0x04504084 > +#define WKUP_CTRLMMR_DBOUNCE_CFG2 0x04504088 > +#define WKUP_CTRLMMR_DBOUNCE_CFG3 0x0450408c > +#define WKUP_CTRLMMR_DBOUNCE_CFG4 0x04504090 > +#define WKUP_CTRLMMR_DBOUNCE_CFG5 0x04504094 > +#define WKUP_CTRLMMR_DBOUNCE_CFG6 0x04504098 > + > +void board_rtc_init(void) > +{ > + u32 val; > + > + /* We have 32k crystal, so lets enable it */ > + val = readl(MCU_CTRL_LFXOSC_CTRL); > + val &= ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL); > + writel(val, MCU_CTRL_LFXOSC_CTRL); > + > + /* Add any TRIM needed for the crystal here.. */ > + /* Make sure to mux up to take the SoC 32k from the crystal */ > + writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, > +MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); > + > + /* Setup debounce conf registers - arbitrary values. > + * Times are approx > + */ > + /* 1.9ms debounce @ 32k */ > + writel(WKUP_CTRLMMR_DBOUNCE_CFG1, 0x1); > + /* 5ms debounce @ 32k */ > + writel(WKUP_CTRLMMR_DBOUNCE_CFG2, 0x5); > + /* 20ms debounce @ 32k */ > + writel(WKUP_CTRLMMR_DBOUNCE_CFG3, 0x14); > + /* 46ms debounce @ 32k */ > + writel(WKUP_CTRLMMR_DBOUNCE_CFG4, 0x18); > + /* 100ms debounce @ 32k */ > + writel(WKUP_CTRLMMR_DBOUNCE_CFG5, 0x1c); > + /* 156ms debounce @ 32k */ > + writel(WKUP_CTRLMMR_DBOUNCE_CFG6, 0x1f); > +} Pad Debounce settings has nothing to do with RTC. This doesn't belong to board_rtc_init() -- Regards Vignesh
Re: Question about boot failure of AM64-SK
Hi, On 21/09/23 21:52, Masahiro Yamada wrote: > On Fri, Sep 22, 2023 at 12:03 AM Masahiro Yamada wrote: >> >> Hi. >> >> I am seeing a boot failure on AM64-SK. >> >> >> I got the following error in SPL of the main core. >> Do you have any clue? > > > > As a side-topic, I downloaded a prebuilt image > from https://www.ti.com/tool/SK-AM64 > > It failed too (but in a different way). > > I flashed tisdk-debian-bookworm-am64xx-evm.wic > to a SD card by using the 'dd' command, then I got this: > Prebuilt images are targeted for High Secure (HS FS) devices. Looks like the board has a non HS Silicon (GP). Please overwrite the tiboot3.bin in boot partition with that of GP cp tiboot3-am64x-gp-evm.bin tiboot3.bin > > > U-Boot SPL 2023.04 (Jul 14 2023 - 08:10:06 +) > EEPROM not available at 0x50, trying to read at 0x51 > k3_system_controller sysctrler: k3_sysctrler_start: Boot Notification > response failed. ret = -110 > Firmware init failed on rproc (-110) > > resetting ... > ti_sci system-controller@44043000: ti_sci_get_response: Message > receive failed. ret = -110 > ti_sci system-controller@44043000: ti_sci_get_response: Message > receive failed. ret = -110 > ti_sci system-controller@44043000: ti_sci_get_response: Message > receive failed. ret = -110 > no sysreset > ### ERROR ### Please RESET the board ### > > > > > Am I doing something wrong? > > > > > > -- Regards Vignesh
Re: Question about boot failure of AM64-SK
Hi Masahiro, On 21/09/23 20:33, Masahiro Yamada wrote: > Hi. [...] > spl: mmc boot mode: fs > Found FIT > Error reading cluster > fit read sector 0, sectors=985528, dst=, count=18446744073709551615, > size=0xf09b8 > SPL: failed to boot from all boot devices > ### ERROR ### Please RESET the board ### > Looks like SD card incompatibility to me. Could you try couple of things: a) Different brand SD card b) Degrade speeds to non UHS mode: diff --git a/arch/arm/dts/k3-am642-sk.dts b/arch/arm/dts/k3-am642-sk.dts index 2e2d40da360a..35da121de872 100644 --- a/arch/arm/dts/k3-am642-sk.dts +++ b/arch/arm/dts/k3-am642-sk.dts @@ -408,6 +408,7 @@ pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; disable-wp; + no-1-8-v; }; > > > > > My build sequence is something like this: > > > > # for wakeup > make -j "$(nproc)" O=build-wakeup CROSS_COMPILE=arm-linux-gnueabihf- \ > BINMAN_INDIRS="${SNAPCRAFT_STAGE}/ti-linux-firmware" \ > am64x_evm_r5_defconfig all > cp build-wakeup/tiboot3-am64x-gp-evm.bin "${STAGE}/tiboot3.bin" > > # for main > make -j "$(nproc)" O=build-main am64x_evm_a53_defconfig > make -j "$(nproc)" O=build-main CROSS_COMPILE=aarch64-linux-gnu- \ > BINMAN_INDIRS="${STAGE}/ti-linux-firmware" \ > BL31="${STAGE}/bl31.bin" \ > TEE="${STAGE}/tee-raw.bin" \ > all > cp build-main/tispl.bin build-main/u-boot.img "${STAGE}" > > Seems alright to me. > > > > > Strangely, AM62-SK booted successfully, > but AM64-SK failed. > I do not know why. > > -- Regards Vignesh
[PATCH] arm: mach-k3: am62a7_init: Open up FSS_DAT_REG3 firewall
On security enforced (HS-SE) devices ROM firewalls OSPI data region3 that is present in above 64bit region. Open this up in bootloader to allow Linux to access OSPI flashes in mmap mode. Without this kernel will crash when accessing this region due to firewall violations on HS-SE devices. Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/am62a7_init.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c index 1f51b0408969..8ac834cffdf9 100644 --- a/arch/arm/mach-k3/am62a7_init.c +++ b/arch/arm/mach-k3/am62a7_init.c @@ -14,6 +14,10 @@ #include #include +struct fwl_data cbass_main_fwls[] = { + { "FSS_DAT_REG3", 7, 8 }, +}; + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -166,6 +170,9 @@ void board_init_f(ulong dummy) /* Output System Firmware version info */ k3_sysfw_print_ver(); + /* Disable ROM configured firewalls right after loading sysfw */ + remove_fwl_configs(cbass_main_fwls, ARRAY_SIZE(cbass_main_fwls)); + #if defined(CONFIG_K3_AM62A_DDRSS) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) -- 2.40.1
[PATCH] common: spl: Warn about overflow of SRAM stack
If early stack usage is exactly same as SIZE_LIMIT_PROVIDE_STACK, then its most likely to have overflowed beyond this limit and corrupted any regions beyond stack. Warn about this to the user. Signed-off-by: Vignesh Raghavendra --- I found this useful when debugging slient corruption of code/data leading to random failures post relocation. common/spl/spl.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/common/spl/spl.c b/common/spl/spl.c index 72078a8ebc8e..9a9c8fad7673 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -950,6 +950,13 @@ __weak void spl_relocate_stack_check(void) } printf("SPL initial stack usage: %lu bytes\n", CONFIG_VAL(SIZE_LIMIT_PROVIDE_STACK) - i); + + /* +* If we used up all of the SIZE_LIMIT_PROVIDE_STACK, then here is high +* possibility of stack overflow, warn the user accordingly +*/ + if (!i) + printf("SPL possible initial stack overflow detected!!\n"); #endif } -- 2.40.1
[PATCH] configs: am64x_evm_*_defconfig: Enable High Secure device support
Enable CONFIG_TI_SECURE_DEVICE to support booting High Secure(HS) variants of AM64x SoC. Signed-off-by: Vignesh Raghavendra --- configs/am64x_evm_a53_defconfig | 1 + configs/am64x_evm_r5_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 4589624e96..09037ecd0f 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_LEN=0x200 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 023ee638a0..d824298773 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_LEN=0x200 CONFIG_SYS_MALLOC_F_LEN=0x8 CONFIG_SPL_GPIO=y -- 2.40.1
Re: [PATCH v2 03/10] arm: K3: Add basic support for J784S4 SoC definition
[...] On 21/03/23 19:40, Hari Nagalla wrote: > default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R > @@ -172,7 +175,7 @@ config K3_ATF_LOAD_ADDR > > config K3_DM_FW > bool "Separate DM firmware image" > - depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || > SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN > + depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || > SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_J784S4) && !CLK_TI_SCI && > !TI_SCI_POWER_DOMAIN > default y > help > Enabling this will indicate that the system has separate DM > @@ -194,4 +197,5 @@ source "board/ti/am62ax/Kconfig" > source "board/ti/j721e/Kconfig" > source "board/siemens/iot2050/Kconfig" > source "board/ti/j721s2/Kconfig" > +source "board/ti/j784s4/Kconfig" You are adding file to Kconfig here, but the actual file itself is introduced only in 9/10. This breaks git bisect. Please make sure each individual each compile patch fine when applied in the order of posting. > endif [...] -- Regards Vignesh
Re: [PATCH v2 08/10] soc: ti: k3-socinfo: Add entry for J784S4 SoC
On 21/03/23 19:40, Hari Nagalla wrote: > Add support for J784S4 SoC Identification. > > Signed-off-by: Hari Nagalla > --- > drivers/soc/soc_ti_k3.c | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c > index 8af0ac7051..caf8db9574 100644 > --- a/drivers/soc/soc_ti_k3.c > +++ b/drivers/soc/soc_ti_k3.c > @@ -17,6 +17,7 @@ > #define J721S2 0xbb75 > #define AM62X0xbb7e > #define AM62AX 0xbb8d > +#define J784S4 0xbb80 > > #define JTAG_ID_VARIANT_SHIFT28 > #define JTAG_ID_VARIANT_MASK (0xf << 28) > @@ -54,9 +55,14 @@ static const char *get_family_string(u32 idreg) > case AM62X: > family = "AM62X"; > break; > + > case AM62AX: > family = "AM62AX"; > + You are missing a break here. This will render AM62Ax unbootable as we end up returning family as J784S4 > + case J784S4: > + family = "J784S4"; > break; > + > default: > family = "Unknown Silicon"; > }; -- Regards Vignesh
Re: [PATCH v2 2/3] Kconfig: j721s2: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region
On 08/05/23 10:21, Manorit Chawdhry wrote: > Hi Nishanth, > > On 08:45-20230505, Nishanth Menon wrote: >> Manorit, >> >> On 20:59-20230504, Tom Rini wrote: >>> On Thu, May 04, 2023 at 11:07:07AM +0530, Manorit Chawdhry wrote: >>> On K3 HS-SE devices all the firewalls are locked by default until sysfw comes up. Rom configures some of the firewall for its usage along with the SRAM for R5 but the PSRAM region is still locked. The K3 MCU Scratchpad for j721s2 was set to a PSRAM region triggering the firewall exception before sysfw came up. The exception started happening after adding multi dtb support that accesses the scratchpad for reading EEPROM contents. Old map: ┌─┐ 0x41c0 │ SPL │ ├─┤ 0x41c61f20 (approx) │STACK│ ├─┤ 0x41c65f20 │ Global data │ │ sizeof(struct global_data) = 0xd8 │ ├─┤ gd->malloc_base = 0x41c66000 │HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x1 │ ├─┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x41c76000) │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ ├─┤ (0x41c8) │ DM DATA │ ├─┤ (0x41c84130) (approx) │EMPTY│ └─┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX (0x41cffbfc) New map: ┌─┐ 0x41c0 │ SPL │ ├─┤ 0x41c61f20 (approx) │STACK│ ├─┤ 0x41c65f20 │ Global data │ │ sizeof(struct global_data) = 0xd8 │ ├─┤ gd->malloc_base = 0x41c66000 │HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x1 │ ├─┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x41c76000) │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ ├─┤ (0x41c8) │ DM DATA │ ├─┤ (0x41c84130) (approx) │EMPTY│ ├─┤ SYS_K3_MCU_SCRATCHPAD_BASE │ SCRATCHPAD │ (0x41cff9fc) │ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │ └─┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX (0x41cffbfc) Reviewed-by: Kamlesh Gurudasani Signed-off-by: Manorit Chawdhry >>> Applied to u-boot/master, thanks! >> >> I just finally caught up with this patch, Sorry for the late >> response-> Thank you for clearly elaborating this in commit message, >> BUT: >> >> Can we start documenting this in rst after we have incorporated the >> binman changes? The memory map on the SRAM is a black magic(at least >> for me) that needs explanation in a single doc without needing to dig >> through commit messages and variables and defconfigs.. >> >> Documentation should clearly indicate what parameters from: >> * binman configuration. >> * various config header files >> * defconfig >> >> We should explain the rationale, variations (HS-SE for example: if any >> or if not any) - including risks such as stack-heap collisions. Any >> interplay with firmware components in the heterogenous system that folks >> need to be careful about needs to be called out as well. >> > Thanks for the insights! Queueing this up when binman get merged. > Would be good to let me know a place also to document all this as I > couldn't find any j721s2 specific documentation, I believe these things > can become device specific also based on the requirements as j721s2 and > j721e have a different map of SPL for them. doc/board/ti/ is the right place IMO. We need an equivalent for j721e_evm.rst which explains combined image boot flow and SRAM layout for J721s2 / j784s4 (and possibly same for J7200)? Regards Vignesh -- Regards Vignesh
[PATCH] configs: am62ax_evm_a53_defconfig: Enable YMODEM support at A53 SPL
This is required for UART boot flow where u-boot.img needs to be downloaded via YMODEM. Signed-off-by: Vignesh Raghavendra --- configs/am62ax_evm_a53_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index 41fa6f38aa72..76ec5ed40463 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -35,6 +35,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_MMC=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -- 2.40.1
Re: [PATCH v1 2/6] video: bridge: add Solomon SSD2825 DSI/LVDS driver
On 20/04/23 22:02, Svyatoslav Ryhel wrote: ..] > +static int ssd2825_spi_write(struct udevice *dev, int reg, > +const void *buf, int flags) > +{ > + struct spi_slave *slave = dev_get_parent_priv(dev); > + u8 command[2]; > + > + if (flags & SSD2825_CMD_SEND) { > + command[0] = SSD2825_CMD_MASK; > + command[1] = reg; > + spi_xfer(slave, 9, &command, > +NULL, SPI_XFER_ONCE); Please can you use dm_spi_xfer() instead, thoughout? >>> I will replace it, but isn't spi_xfer preferable over dm_spi_xfer? >>> I remember that I had doubts about which to use. >> No, we should use the dm variants where available, since then we can >> drop the old ones. >> > I have switched to the dm version and it seems to fit even better, everything > works perfectly fine. > Yes, please switch to dm_spi_xfer() for DM compatible clients. -- Regards Vignesh
[PATCH] arm: mach-k3: common: Default to non fitImage boot on HS-FS
Allow non fitImage bootflow on Field Securable (HS-FS) devices in addition to GP, force fitImage boot only on Security enforced (HS-SE) devices where signed images are necessary to maintain chain of trust. Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index a2adb791f6c0..1efeae4bc677 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -606,8 +606,8 @@ int misc_init_r(void) printf("Failed to probe am65_cpsw_nuss driver\n"); } - /* Default FIT boot on non-GP devices */ - if (get_device_type() != K3_DEVICE_TYPE_GP) + /* Default FIT boot on HS-SE devices */ + if (get_device_type() == K3_DEVICE_TYPE_HS_SE) env_set("boot_fit", "1"); return 0; -- 2.40.0
[PATCH] arm: mach-k3: Workaround errata ID i2331
From: Nitin Yadav Errata doc: https://www.ti.com/lit/pdf/sprz457 Errata ID i2331 CPSW: Device lockup when reading CPSW registers Details: A device lockup can occur during the second read of any CPSW subsystem register after any MAIN domain power on reset (POR). A MAIN domain POR occurs using the hardware MCU_PORz signal, or via software using CTRLMMR_RST_CTRL.SW_MAIN_POR or CTRLMMR_MCU_RST_CTRL.SW_MAIN_POR. After these resets, the processor and internal bus structures may get into a state which is only recoverable with full device reset using MCU_PORz. Due to this errata, Ethernet boot should not be used on this device. Workaround(s): To avoid the lockup, a warm reset should be issued after a MAIN domain POR and before any access to the CPSW registers. The warm reset realigns internal clocks and prevents the lockup from happening. Workaround above errata by calling do_reset() in case of cold boot in order to trigger warm reset. This needs enabling SYSRESET driver in R5 SPL to enable TI SCI reset driver. Signed-off-by: Nitin Yadav Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/am642_init.c | 33 + configs/am64x_evm_r5_defconfig | 3 +++ 2 files changed, 36 insertions(+) diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 1bf7e163cc46..093a68b63077 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -22,9 +22,15 @@ #include #include #include +#include #define CTRLMMR_MCU_RST_CTRL 0x04518170 +#define CTRLMMR_MCU_RST_SRC(MCU_CTRL_MMR0_BASE + 0x18178) +#define COLD_BOOT 0 +#define SW_POR_MCU BIT(24) +#define SW_POR_MAINBIT(25) + static void ctrl_mmr_unlock(void) { /* Unlock all PADCFG_MMR1 module registers */ @@ -166,6 +172,7 @@ void board_init_f(ulong dummy) #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM64_DDRSS) || defined(CONFIG_ESM_K3) struct udevice *dev; int ret; + int rst_src; #endif #if defined(CONFIG_CPU_V7R) @@ -210,6 +217,32 @@ void board_init_f(ulong dummy) k3_mmc_restart_clock); #endif +#if defined(CONFIG_CPU_V7R) + /* +* Errata ID i2331 CPSW: A device lockup can occur during the second +* read of any CPSW subsystem register after any MAIN domain power on +* reset (POR). A MAIN domain POR occurs using the hardware MCU_PORz +* signal, or via software using CTRLMMR_RST_CTRL.SW_MAIN_POR or +* CTRLMMR_MCU_RST_CTRL.SW_MAIN_POR. After these resets, the processor +* and internal bus structures may get into a state which is only +* recoverable with full device reset using MCU_PORz. +* Workaround(s): To avoid the lockup, a warm reset should be issued +* after a MAIN domain POR and before any access to the CPSW registers. +* The warm reset realigns internal clocks and prevents the lockup from +* happening. +*/ + ret = uclass_first_device_err(UCLASS_SYSRESET, &dev); + if (ret) + printf("\n%s:uclass device error [%d]\n",__func__,ret); + + rst_src = readl(CTRLMMR_MCU_RST_SRC); + if (rst_src == COLD_BOOT || rst_src & (SW_POR_MCU | SW_POR_MAIN)) { + printf("Resetting on cold boot to workaround ErrataID:i2331\n"); + printf("Please resend tiboot3.bin in case of UART/DFU boot\n"); + do_reset(NULL, 0, 0, NULL); + } +#endif + /* Output System Firmware version info */ k3_sysfw_print_ver(); diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index b75cae6d803e..bb705a1c3ce2 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -169,3 +169,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y -- 2.40.0
Re: [PATCH V6 08/13] cmd: bmp: Split bmp commands and functions
Hi Nikhil, On 06/04/23 11:57, Nikhil M Jain wrote: >>> +struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp, >>> + void **alloc_addr) >>> +{ >>> + void *dst; >>> + unsigned long len; >>> + struct bmp_image *bmp; >>> + >> >> if (!IS_ENABLED(CONFIG_VIDEO_BMP_GZIP)) >> return NULL; >> > > I preferred to use #if to avoid compilation of code when not required. > > For example, if someone doesn't want to display a gzip bmp image they > wouldn't want the code to be compiled, so that binary size doesn't > increase. Both are equivalent. Compiler will optimize out the function if CONFIG_VIDEO_BMP_GZIP is not defined. #ifdefs are complicated to read compared to inline if()s (at least for me). > >>> + /* >>> + * Decompress bmp image >>> + */ >>> + len = CONFIG_VIDEO_LOGO_MAX_SIZE; >>> + /* allocate extra 3 bytes for 32-bit-aligned-address + 2 >>> alignment */ >>> + dst = malloc(CONFIG_VIDEO_LOGO_MAX_SIZE + 3); >>> + if (!dst) { >>> + puts("Error: malloc in gunzip failed!\n"); >>> + return NULL; >>> + } >>> + >>> + /* align to 32-bit-aligned-address + 2 */ >>> + bmp = dst + 2; >>> + >>> + if (gunzip(bmp, CONFIG_VIDEO_LOGO_MAX_SIZE, map_sysmem(addr, 0), >>> + &len)) { >>> + free(dst); >>> + return NULL; >>> + } >>> + if (len == CONFIG_VIDEO_LOGO_MAX_SIZE) >>> + puts("Image could be truncated (increase >>> CONFIG_VIDEO_LOGO_MAX_SIZE)!\n"); >>> + >>> + /* >>> + * Check for bmp mark 'BM' >>> + */ >>> + if (!((bmp->header.signature[0] == 'B') && >>> + (bmp->header.signature[1] == 'M'))) { >>> + free(dst); >>> + return NULL; >>> + } >>> + >>> + debug("Gzipped BMP image detected!\n"); >>> + >>> + *alloc_addr = dst; >>> + return bmp; >>> +} >>> +#else >>> +struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp, >>> + void **alloc_addr) >>> +{ >>> + return NULL; >>> +} >>> +#endif >>> + [...] -- Regards Vignesh
[PATCH] board: ti: am64x: Add support for AM64B SK
From: Judith Mendez The AM64x SR2.0 SK board uses "AM64B-SKEVM" as the EEPROM identifier. This board is similar to the AM64x SKEVM except that it has a new PMIC that will be enabled in the future and consequently could use a different device tree file in the future. For now we treat the board same as an AM64x SK. Signed-off-by: Judith Mendez Acked-by: Andrew Davis Signed-off-by: Vignesh Raghavendra --- board/ti/am64x/evm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index c88139ac7acc..9aead2bc3345 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -20,7 +20,9 @@ #include "../common/board_detect.h" #define board_is_am64x_gpevm() board_ti_k3_is("AM64-GPEVM") -#define board_is_am64x_skevm() board_ti_k3_is("AM64-SKEVM") + +#define board_is_am64x_skevm() (board_ti_k3_is("AM64-SKEVM") || \ + board_ti_k3_is("AM64B-SKEVM")) DECLARE_GLOBAL_DATA_PTR; -- 2.40.0
[PATCH] dma: ti: k3-udma: Fix channel hang on teardown
Setting RX flow error handling will stall the channel until descriptors are available to move RX data. Setting this bit causes issues when tearing down ethernet DMA channel at the end of TFTP transfer as unrelated network packets can cause teardown to stall indefinitely waiting for driver to queue add more desc leading to channel hang with error logs: udma_stop_dev2mem TIMEOUT ! udma_stop_dev2mem: peer not stopped TIMEOUT ! udma_stop_dev2mem TIMEOUT ! Fix this by clearing rx_error_handling similar to how its done for UDMA as part of udma_alloc_rchan_sci_req() This fixes occasional TFTP Failures seen when downloading multiple files one after the other on AM64/AM62 SoCs. Fixes: 9a92851c33e8 ("dma: ti: k3-udma: Add BCDMA and PKTDMA support") Reported-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra --- drivers/dma/ti/k3-udma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index d92b96443694..05c3a4311ced 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -2150,7 +2150,7 @@ static int pktdma_tisci_rx_channel_config(struct udma_chan *uc) flow_req.rx_psinfo_present = 1; else flow_req.rx_psinfo_present = 0; - flow_req.rx_error_handling = 1; + flow_req.rx_error_handling = 0; ret = tisci_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req); -- 2.39.2
Re: [EXTERNAL] Re: [PATCH 3/9] arm: dts: k3-am62-main: Add device tree node for TIDSS
Hi Nikhil, On 17/01/23 18:49, Tom Rini wrote: > On Tue, Jan 17, 2023 at 10:09:00AM +0530, Nikhl M Jain wrote: >> Hi, Tom >> >> On 13/01/23 20:13, Tom Rini wrote: >>> On Fri, Jan 13, 2023 at 01:59:21PM +0530, Nikhil M Jain wrote: >>> Add device tree node which includes the register regions to write properties of planes (vidl1 and vid1), overlays (ovr1 and ovr2),and video ports(vp1 and vp2). TIDSS uses 3 clocks, fck- for its internal logic and clk vp1 and vp2 for oldi and HDMI ports. To control the oldi panel its register region is added in dss_oldi_io_ctrl. Signed-off-by: Nikhil M Jain --- arch/arm/dts/k3-am62-main.dtsi | 41 ++ 1 file changed, 41 insertions(+) >>> >>> Can we not get this with a re-sync of the dts upstream? We should do >>> that instead. >>> >> On linux side pathces have been sent upstream, waiting for patches to be >> accepted. >> >> link: >> https://lore.kernel.org/linux-arm-kernel/20220505134303.23208-2-a-bhat...@ti.com/T/ >> >> Is it possible to accept these patches now and resync the dts when the >> patches on the linux side gets accepted. > > Based on the link you give here, they haven't been accepted, they've had > changes requested: > https://lore.kernel.org/linux-arm-kernel/20220505134303.23208-2-a-bhat...@ti.com/T/#mcf7eb2921982735440f2b0959feb3831530a2f05 > Please wait for the kernel bindings to settle down. Else we will end up with different sets of bindings for kernel and u-boot. I don't see why DSS should be exempted from the rule that kernel bindings and DT being accepted. -- Regards Vignesh
Re: [PATCH] configs: Increase malloc size after relocation
On 11/01/23 11:34, Neha Malcom Francis wrote: > Current default size of 0x10 is not capable of getting the FIT > buffer during boot when transitioning to using binman generated boot > images for certain K3 devices, so increase it to 0x40. Since A72 SPL > is coming after relocation to DDR this should not be an issue for any K3 > device, so make it default for all. > > Signed-off-by: Neha Malcom Francis > --- > common/spl/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/common/spl/Kconfig b/common/spl/Kconfig > index a25d8fd2e0..d8c78ddb76 100644 > --- a/common/spl/Kconfig > +++ b/common/spl/Kconfig > @@ -385,6 +385,7 @@ config SPL_STACK_R_ADDR > config SPL_STACK_R_MALLOC_SIMPLE_LEN > depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE > hex "Size of malloc_simple heap after switching to DRAM SPL stack" > + default 0x40 if ARCH_K3 Wont this take affect for both R5 SPL and A72 SPL as ARCH_K3 = y in both cases? > default 0x10 > help > Specify the amount of the stack to use as memory pool for -- Regards Vignesh
Re: [PATCH 04/12] drivers: dma: Add support for J784S4
On 20/11/22 00:29, Hari Nagalla wrote: > diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile > index 6807eb8e8b..bd4ce68d9c 100644 > --- a/drivers/dma/ti/Makefile > +++ b/drivers/dma/ti/Makefile > @@ -8,3 +8,4 @@ k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o > k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o > k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o > k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o > +k3-psil-data-$(CONFIG_SOC_K3_J784S4) += k3-psil-j784s4.o > diff --git a/drivers/dma/ti/k3-psil-j784s4.c b/drivers/dma/ti/k3-psil-j784s4.c > new file mode 100644 > index 00..e73ea1d030 > --- /dev/null > +++ b/drivers/dma/ti/k3-psil-j784s4.c > @@ -0,0 +1,167 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com > + */ > +/* TODO : check again for j784s4 */ Could you address the TODO or drop it if already done? -- Regards Vignesh
Re: [PATCH 016/347] FogBugz #516535: Fix QSPI write issues
Hi, On 30/08/22 11:50 am, Jit Loon Lim wrote: > From: Chee Hong Ang > > QSPI driver perform chip select on every flash read/write > access. The driver need to disable/enable the QSPI controller > while performing chip select. This may cause some data lost > especially the QSPI controller is configured to run at slower > speed as it may take longer time to access the flash device. > This patch prevent the driver from disable/enable the QSPI > controller too soon and inadvertently halting any ongoing flash > read/write access by ensuring the QSPI controller is always in > idle mode after each read/write access. > > Signed-off-by: Chee Hong Ang > --- > drivers/spi/cadence_qspi_apb.c | 15 --- > 1 file changed, 8 insertions(+), 7 deletions(-) > > diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c > index 2cdf4c9c9f..5e03495f45 100644 > --- a/drivers/spi/cadence_qspi_apb.c > +++ b/drivers/spi/cadence_qspi_apb.c > @@ -858,13 +858,9 @@ cadence_qspi_apb_indirect_read_execute(struct > cadence_spi_plat *plat, > writel(CQSPI_REG_INDIRECTRD_DONE, > plat->regbase + CQSPI_REG_INDIRECTRD); > > - /* Check indirect done status */ > - ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD, > - CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0); > - if (ret) { > - printf("Indirect read clear completion error (%i)\n", ret); > - goto failrd; > - } Why would you drop looking at CQSPI_REG_INDIRECTRD_DONE status bit? This gives out a much granular error wrt what operation actually failed. > + /* Wait til QSPI is idle */ > + if (!cadence_qspi_wait_idle(plat->regbase)) > + return -EIO; > > return 0; > > @@ -1031,6 +1027,11 @@ cadence_qspi_apb_indirect_write_execute(struct > cadence_spi_plat *plat, > > if (bounce_buf) > free(bounce_buf); > + > + /* Wait til QSPI is idle */ > + if (!cadence_qspi_wait_idle(plat->regbase)) > + return -EIO; > + > return 0; > > failwr:
[PATCH] firmware: ti_sci_static_data: Make file board agnostic
Static DMA channel data for R5 SPL is mostly board agnostic so use SOC configs instead of EVM specific config to ease adding new board support. Drop J7200 EVM specific settings as its same as J721e Signed-off-by: Vignesh Raghavendra --- drivers/firmware/ti_sci_static_data.h | 42 +++ 1 file changed, 4 insertions(+), 38 deletions(-) diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h index 8529ef2900..5ae0556a9a 100644 --- a/drivers/firmware/ti_sci_static_data.h +++ b/drivers/firmware/ti_sci_static_data.h @@ -16,7 +16,7 @@ struct ti_sci_resource_static_data { #if IS_ENABLED(CONFIG_K3_DM_FW) -#if IS_ENABLED(CONFIG_TARGET_J721E_R5_EVM) +#if IS_ENABLED(CONFIG_SOC_K3_J721E) static struct ti_sci_resource_static_data rm_static_data[] = { /* Free rings */ { @@ -48,43 +48,9 @@ static struct ti_sci_resource_static_data rm_static_data[] = { }, { }, }; -#endif /* CONFIG_TARGET_J721E_R5_EVM */ +#endif /* CONFIG_SOC_K3_J721E */ -#if IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM) -static struct ti_sci_resource_static_data rm_static_data[] = { - /* Free rings */ - { - .dev_id = 235, - .subtype = 1, - .range_start = 124, - .range_num = 32, - }, - /* TX channels */ - { - .dev_id = 236, - .subtype = 13, - .range_start = 6, - .range_num = 2, - }, - /* RX channels */ - { - .dev_id = 236, - .subtype = 10, - .range_start = 6, - .range_num = 2, - }, - /* RX Free flows */ - { - .dev_id = 236, - .subtype = 0, - .range_start = 60, - .range_num = 8, - }, - { }, -}; -#endif /* CONFIG_TARGET_J7200_R5_EVM */ - -#if IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM) +#if IS_ENABLED(CONFIG_SOC_K3_J721S2) static struct ti_sci_resource_static_data rm_static_data[] = { /* Free rings */ { @@ -116,7 +82,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = { }, { }, }; -#endif /* CONFIG_TARGET_J721S2_R5_EVM */ +#endif /* CONFIG_SOC_K3_J721S2 */ #if IS_ENABLED(CONFIG_SOC_K3_AM625) static struct ti_sci_resource_static_data rm_static_data[] = { -- 2.36.1
[PATCH v2 09/12] board: ti: Introduce the basic files to support AM62 SK board
From: Suman Anna Add basic support for AM62 SK. This has 2GB DDR. Note that stack for R5 SPL is in OCRAM @ 0x7000 so that is away from BSS and does not step on BSS section Add only the bare minimum required to support UART and SD. Signed-off-by: Suman Anna Signed-off-by: Aswath Govindraju Signed-off-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/Kconfig | 1 + board/ti/am62x/Kconfig | 59 board/ti/am62x/Makefile | 8 ++ board/ti/am62x/evm.c | 39 ++ 4 files changed, 107 insertions(+) create mode 100644 board/ti/am62x/Kconfig create mode 100644 board/ti/am62x/Makefile create mode 100644 board/ti/am62x/evm.c diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 0dc4f44fdd..57f693e9a1 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -178,6 +178,7 @@ config K3_DM_FW source "board/ti/am65x/Kconfig" source "board/ti/am64x/Kconfig" +source "board/ti/am62x/Kconfig" source "board/ti/j721e/Kconfig" source "board/siemens/iot2050/Kconfig" source "board/ti/j721s2/Kconfig" diff --git a/board/ti/am62x/Kconfig b/board/ti/am62x/Kconfig new file mode 100644 index 00..87fed44df1 --- /dev/null +++ b/board/ti/am62x/Kconfig @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ +# Suman Anna + +choice + prompt "TI K3 AM62x based boards" + optional + +config TARGET_AM625_A53_EVM + bool "TI K3 based AM625 EVM running on A53" + select ARM64 + select SOC_K3_AM625 + +config TARGET_AM625_R5_EVM + bool "TI K3 based AM625 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select SOC_K3_AM625 + select RAM + select SPL_RAM + select K3_DDRSS + imply SYS_K3_SPL_ATF + +endchoice + +if TARGET_AM625_A53_EVM + +config SYS_BOARD + default "am62x" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "am62x_evm" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_AM625_R5_EVM + +config SYS_BOARD + default "am62x" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "am62x_evm" + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +source "board/ti/common/Kconfig" + +endif diff --git a/board/ti/am62x/Makefile b/board/ti/am62x/Makefile new file mode 100644 index 00..f4c35edffa --- /dev/null +++ b/board/ti/am62x/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ +# Suman Anna +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evm.o diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c new file mode 100644 index 00..4dd5e64299 --- /dev/null +++ b/board/ti/am62x/evm.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board specific initialization for AM62x platforms + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Suman Anna + * + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x8000; + + return 0; +} + +int dram_init_banksize(void) +{ + /* Bank 0 declares the memory available in the DDR low region */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x8000; + gd->ram_size = 0x8000; + + return 0; +} -- 2.36.1
[PATCH v2 10/12] arm: dts: Add support for AM62-SK
From: Nishanth Menon AM62 StarterKit (SK) board is a low cost, small form factor board designed for TI’s AM625 SoC. It supports the following interfaces: * 2 GB DDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode * x1 HDMI Port with audio + x1 OLDI/LVDS Display interface for Dual Display * x1 Headphone Jack * x1 USB2.0 Hub with two Type A host and x1 USB Type-C DRP Port * x1 UHS-1 capable µSD card slot * 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837 * 512 Mbit OSPI flash * x4 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin User Expansion Connector * 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO) * 20-pin header for Programmable Realtime Unit (PRU) IO pins * 15-pin CSI header Add basic support for AM62-SK. To keep the changes to minimum. Only UART And SD are supported at the moment. This should serve as good example for adding new board support based on AM62x SoC Schematics: https://www.ti.com/lit/zip/sprr448 Signed-off-by: Nishanth Menon Signed-off-by: Aswath Govindraju Signed-off-by: Nishanth Menon Signed-off-by: Dave Gerlach Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/Makefile |3 + arch/arm/dts/k3-am625-r5-sk.dts| 140 ++ arch/arm/dts/k3-am625-sk-u-boot.dtsi | 100 + arch/arm/dts/k3-am625-sk.dts | 150 ++ arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi | 2189 5 files changed, 2582 insertions(+) create mode 100644 arch/arm/dts/k3-am625-r5-sk.dts create mode 100644 arch/arm/dts/k3-am625-sk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am625-sk.dts create mode 100644 arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3ca980aae0..d1df5ae196 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1177,6 +1177,9 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \ k3-am642-sk.dtb \ k3-am642-r5-sk.dtb +dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ + k3-am625-r5-sk.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts new file mode 100644 index 00..2691af40a1 --- /dev/null +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM625 SK dts file for R5 SPL + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am625-sk.dts" +#include "k3-am62x-sk-ddr4-1600MTs.dtsi" +#include "k3-am62-ddr.dtsi" + +#include "k3-am625-sk-u-boot.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + serial0 = &wkup_uart0; + serial3 = &main_uart1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &timer1; + }; + + memory@8000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x 0x8000 0x 0x8000>; + + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e80 { + reg = <0x00 0x9e80 0x00 0x0180>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a9 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <2>, <12>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + u-boot,dm-spl; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 22>, + <&secure_proxy_main 23>; + u-boot,dm-spl; + }; +}; + +&dmsc { + mboxes=
[PATCH v2 08/12] arm: dts: Introduce base AM62 SoC dtsi files
From: Suman Anna Introduce the basic AM62 SoC description dtsi files describing most peripherals as per kernel dts. Signed-off-by: Gowtham Tammana Signed-off-by: Suman Anna Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-am62-ddr.dtsi| 11 + arch/arm/dts/k3-am62-main.dtsi | 533 +++ arch/arm/dts/k3-am62-mcu.dtsi| 56 arch/arm/dts/k3-am62-wakeup.dtsi | 41 +++ arch/arm/dts/k3-am62.dtsi| 105 ++ arch/arm/dts/k3-am625.dtsi | 103 ++ 6 files changed, 849 insertions(+) create mode 100644 arch/arm/dts/k3-am62-ddr.dtsi create mode 100644 arch/arm/dts/k3-am62-main.dtsi create mode 100644 arch/arm/dts/k3-am62-mcu.dtsi create mode 100644 arch/arm/dts/k3-am62-wakeup.dtsi create mode 100644 arch/arm/dts/k3-am62.dtsi create mode 100644 arch/arm/dts/k3-am625.dtsi diff --git a/arch/arm/dts/k3-am62-ddr.dtsi b/arch/arm/dts/k3-am62-ddr.dtsi new file mode 100644 index 00..0a8ced8f38 --- /dev/null +++ b/arch/arm/dts/k3-am62-ddr.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am64-ddr.dtsi" +&memorycontroller { + power-domains = <&k3_pds 170 TI_SCI_PD_SHARED>, + <&k3_pds 55 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 170 0>, <&k3_clks 16 4>; +}; diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi new file mode 100644 index 00..4b6ba98dd0 --- /dev/null +++ b/arch/arm/dts/k3-am62-main.dtsi @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family Main Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + oc_sram: sram@7000 { + compatible = "mmio-sram"; + reg = <0x00 0x7000 0x00 0x1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x7000 0x1>; + }; + + gic500: interrupt-controller@180 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x0180 0x00 0x1>, /* GICD */ + <0x00 0x0188 0x00 0xc>, /* GICR */ + <0x00 0x0188 0x00 0xc>, /* GICR */ + <0x01 0x 0x00 0x2000>,/* GICC */ + <0x01 0x0001 0x00 0x1000>,/* GICH */ + <0x01 0x0002 0x00 0x2000>;/* GICV */ + /* +* vcpumntirq: +* virtual CPU interface maintenance interrupt +*/ + interrupts = ; + + gic_its: msi-controller@182 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x0182 0x00 0x1>; + socionext,synquacer-pre-its = <0x100 0x40>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_conf: syscon@10 { + compatible = "syscon", "simple-mfd"; + reg = <0x00 0x0010 0x00 0x2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x0010 0x2>; + + phy_gmii_sel: phy@4044 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4044 0x8>; + #phy-cells = <1>; + }; + }; + + dmss: bus@4800 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x4800 0x00 0x4800 0x00 0x0640>; + + ti,sci-dev-id = <25>; + + secure_proxy_main: mailbox@4d00 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x4d00 0x00 0x8>, + <0x00 0x4a60 0x00 0x8>, + <0x00 0x4a40 0x00 0x8>; + interrupt-names = "rx_012"; + interrupts = ; + }; + + inta_main_dmss: interrupt-contro
[PATCH v2 12/12] doc: ti: Add readme for AM62x SK
Add info of boot flow and build steps for AM62x SK. Signed-off-by: Vignesh Raghavendra --- doc/board/ti/am62x_sk.rst | 231 ++ doc/board/ti/index.rst| 1 + 2 files changed, 232 insertions(+) create mode 100644 doc/board/ti/am62x_sk.rst diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst new file mode 100644 index 00..4e68c2018a --- /dev/null +++ b/doc/board/ti/am62x_sk.rst @@ -0,0 +1,231 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Vignesh Raghavendra + +Texas Instruments AM62 Platforms + + +Introduction: +- +The AM62 SoC family is the follow on AM335x built on the K3 Multicore +SoC architecture platform, providing ultra-low-power modes, dual +display, multi-sensor edge compute, security and other BOM-saving +integrations. The AM62 SoC targets a broad market to enable +applications such as Industrial HMI, PLC/CNC/Robot control, Medical +Equipment, Building Automation, Appliances and more. + +Some highlights of this SoC are: + +* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. + Pin-to-pin compatible options for single and quad core are available. +* Cortex-M4F for general-purpose or safety usage. +* Dual display support, providing 24-bit RBG parallel interface and + OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display + resolution. +* Selectable GPU support, up to 8GFLOPS, providing better user experience + in 3D graphic display case and Android. +* PRU(Programmable Realtime Unit) support for customized programmable + interfaces/IOs. +* Integrated Giga-bit Ethernet switch supporting up to a total of two + external ports (TSN capable). +* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for + NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, + 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. +* Dedicated Centralized System Controller for Security, Power, and + Resource Management. +* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, + enabling battery powered system design. + +More details can be found in the Technical Reference Manual: +https://www.ti.com/lit/pdf/spruiv7 + +Boot Flow: +-- +Below is the pictorial representation of boot flow: + +.. code-block:: text + + ++ + |TIFS| Main R5 |A53| + ++ + |++ | | | + || Reset | | | | + |++ | | | + | : | | | + |++ | +---+ | | + || *ROM* |--|-->| Reset rls | | | + |++ | +---+ | | + ||| | : | | + || ROM | | : | | + ||services| | : | | + ||| | +-+ | | + ||| | | *R5 ROM* | | | + ||| | +-+ | | + |||<-|---|Load and auth| | | + ||| | | tiboot3.bin | | | + |++ | +-+ | | + |||<-|---| Load sysfw | | | + ||| | | part to TIFS| | | + ||| | | core| | | + ||| | +-+ | | + ||| | : | | + ||| | : | | + ||| | : | | + ||| | +-+ | | + ||| | | *R5 SPL* | | | + ||| | +-+ | | + ||| | |DDR | | | + ||| | | config| | | + ||| | +-+ | | + ||| | |Load | | | + ||| | |
[PATCH v2 11/12] configs: Add configs for AM62x SK
Add am62x_evm_r5_defconfig for R5 SPL and am62x_evm_a53_defconfig for A53 SPL and U-Boot support. To keep the changes to minimum. Only UART And SD boot related configs are included. This should serve as good starting point for new board bringup with AM62x. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra --- board/ti/am62x/MAINTAINERS | 8 +++ configs/am62x_evm_a53_defconfig | 71 + configs/am62x_evm_r5_defconfig | 91 +++ include/configs/am62x_evm.h | 106 4 files changed, 276 insertions(+) create mode 100644 board/ti/am62x/MAINTAINERS create mode 100644 configs/am62x_evm_a53_defconfig create mode 100644 configs/am62x_evm_r5_defconfig create mode 100644 include/configs/am62x_evm.h diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS new file mode 100644 index 00..105e741995 --- /dev/null +++ b/board/ti/am62x/MAINTAINERS @@ -0,0 +1,8 @@ +AM62x BOARD +M: Dave Gerlach +M: Tom Rini +S: Maintained +F: board/ti/am62x/ +F: include/configs/am62x_evm.h +F: configs/am62x_evm_r5_defconfig +F: configs/am62x_evm_a53_defconfig diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig new file mode 100644 index 00..fd18fbd890 --- /dev/null +++ b/configs/am62x_evm_a53_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM625=y +CONFIG_K3_ATF_LOAD_ADDR=0x9e78 +CONFIG_TARGET_AM625_A53_EVM=y +CONFIG_SPL_TEXT_BASE=0x8008 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk" +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100 +CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_CMD_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig new file mode 100644 index 00..0e1b2ef13e --- /dev/null +++ b/configs/am62x_evm_r5_defconfig @@ -0,0 +1,91 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_SOC_K3_AM625=y +CONFIG_TARGET_AM625_R5_EVM=y +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_TEXT_BASE=0x43c0 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_SPL_SIZE_LIMIT=0x4 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-sk" +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8008 +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
[PATCH v2 07/12] firmware: ti_sci_static_data: add static DMA chan data
Add range of DMA channels available for R5 SPL usage before DM firmware is loaded. Signed-off-by: Vignesh Raghavendra --- drivers/firmware/ti_sci_static_data.h | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h index e6a3b66c03..8529ef2900 100644 --- a/drivers/firmware/ti_sci_static_data.h +++ b/drivers/firmware/ti_sci_static_data.h @@ -118,6 +118,19 @@ static struct ti_sci_resource_static_data rm_static_data[] = { }; #endif /* CONFIG_TARGET_J721S2_R5_EVM */ +#if IS_ENABLED(CONFIG_SOC_K3_AM625) +static struct ti_sci_resource_static_data rm_static_data[] = { + /* BC channels */ + { + .dev_id = 26, + .subtype = 32, + .range_start = 18, + .range_num = 2, + }, + { }, +}; +#endif /* CONFIG_SOC_K3_AM625 */ + #else static struct ti_sci_resource_static_data rm_static_data[] = { { }, -- 2.36.1
[PATCH v2 04/12] arm: mach-k3: Introduce the basic files to support AM62
From: Suman Anna The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC architecture platform, providing ultra-low-power modes, dual display, multi-sensor edge compute, security and other BOM-saving integration. The AM62 SoC targets broad market to enable applications such as Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building Automation, Appliances and more. Some highlights of this SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Pin-to-pin compatible options for single and quad core are available. * Cortex-M4F for general-purpose or safety usage. * Dual display support, providing 24-bit RBG parallel interface and OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display resolution. * Selectable GPUsupport, up to 8GFLOPS, providing better user experience in 3D graphic display case and Android. * PRU(Programmable Realtime Unit) support for customized programmable interfaces/IOs. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized System Controller for Security, Power, and Resource Management. * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only, enabling battery powered system design. AM625 is the first device of the family. Add DT bindings for the same. More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Suman Anna Signed-off-by: Gowtham Tammana Signed-off-by: Aswath Govindraju Signed-off-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/Kconfig | 9 +- arch/arm/mach-k3/Makefile | 1 + arch/arm/mach-k3/am625_init.c | 271 ++ arch/arm/mach-k3/arm64-mmu.c | 4 +- arch/arm/mach-k3/include/mach/am62_hardware.h | 75 + arch/arm/mach-k3/include/mach/am62_spl.h | 48 arch/arm/mach-k3/include/mach/hardware.h | 4 + arch/arm/mach-k3/include/mach/spl.h | 5 + drivers/ram/Kconfig | 1 + 9 files changed, 415 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-k3/am625_init.c create mode 100644 arch/arm/mach-k3/include/mach/am62_hardware.h create mode 100644 arch/arm/mach-k3/include/mach/am62_spl.h diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index a01bf23514..0dc4f44fdd 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -16,6 +16,9 @@ config SOC_K3_J721S2 config SOC_K3_AM642 bool "TI's K3 based AM642 SoC Family Support" +config SOC_K3_AM625 + bool "TI's K3 based AM625 SoC Family Support" + endchoice config SYS_SOC @@ -26,6 +29,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE default 0x8 if SOC_K3_AM6 default 0x10 if SOC_K3_J721E || SOC_K3_J721S2 default 0x1c if SOC_K3_AM642 + default 0x3c000 if SOC_K3_AM625 help Describes the total size of the MCU or OCMC MSRAM present on the SoC in use. This doesn't specify the total size of SPL as @@ -37,6 +41,7 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE default 0x58000 if SOC_K3_AM6 default 0xc if SOC_K3_J721E || SOC_K3_J721S2 default 0x18 if SOC_K3_AM642 + default 0x38000 if SOC_K3_AM625 help Describes the maximum size of the image that ROM can download from any boot media. @@ -61,6 +66,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX default 0x41cffbfc if SOC_K3_J721E default 0x41cfdbfc if SOC_K3_J721S2 default 0x701bebfc if SOC_K3_AM642 + default 0x43c3f290 if SOC_K3_AM625 help Address at which ROM stores the value which determines if SPL is booted up by primary boot media or secondary boot media. @@ -129,6 +135,7 @@ config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART config K3_SYSFW_IMAGE_SIZE_MAX int "Amount of memory dynamically allocated for loading SYSFW blob" depends on K3_LOAD_SYSFW + default 163840 if SOC_K3_AM625 default 278000 help Amount of memory (in bytes) reserved through dynamic allocation at @@ -160,7 +167,7 @@ config K3_ATF_LOAD_ADDR config K3_DM_FW bool "Separate DM firmware image" - depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN default y help Enabling this will indicate that the system has separate DM diff --git a/ar
[PATCH v2 05/12] arm: mach-k3: am62: Introduce autogenerated SoC data
From: Suman Anna Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach Signed-off-by: Suman Anna Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/am62x/Makefile| 6 + arch/arm/mach-k3/am62x/clk-data.c | 366 + arch/arm/mach-k3/am62x/dev-data.c | 78 ++ drivers/clk/ti/clk-k3.c| 6 + drivers/power/domain/ti-power-domain.c | 6 + include/k3-clk.h | 1 + include/k3-dev.h | 1 + 7 files changed, 464 insertions(+) create mode 100644 arch/arm/mach-k3/am62x/Makefile create mode 100644 arch/arm/mach-k3/am62x/clk-data.c create mode 100644 arch/arm/mach-k3/am62x/dev-data.c diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile new file mode 100644 index 00..d6c876df66 --- /dev/null +++ b/arch/arm/mach-k3/am62x/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/am62x/clk-data.c b/arch/arm/mach-k3/am62x/clk-data.c new file mode 100644 index 00..c0881778fe --- /dev/null +++ b/arch/arm/mach-k3/am62x/clk-data.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62X specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + NULL, + NULL, + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + NULL, +}; + +static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = { + "board_0_mmc0_clklb_out", + "board_0_mmc0_clk_out", +}; + +static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = { + "board_0_mmc1_clklb_out", + "board_0_mmc1_clk_out", +}; + +static const char * const main_ospi_loopback_clk_sel_out0_parents[] = { + "board_0_ospi0_dqs_out", + "board_0_ospi0_lbclko_out", +}; + +static const char * const main_usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const main_usb1_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const clkout0_ctrl_out0_parents[] = { + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", +}; + +static const char * const clk_32k_rc_sel_out0_parents[] = { + "gluelogic_rcosc_clk_1p0v_97p65k", + "hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", + "clk_32k_rc_sel_div_clkout", + "gluelogic_lfosc0_clkout", +}; + +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_gtcclk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_ospi_ref_clk_sel_out0_parents[] = { +
[PATCH v2 06/12] dma: ti: Add PSIL data for AM62x DMASS
Add PSIL data for AM62x SoC. Signed-off-by: Vignesh Raghavendra --- drivers/dma/ti/Makefile | 1 + drivers/dma/ti/k3-psil-am62.c | 50 +++ drivers/dma/ti/k3-psil-priv.h | 1 + drivers/dma/ti/k3-psil.c | 2 ++ 4 files changed, 54 insertions(+) create mode 100644 drivers/dma/ti/k3-psil-am62.c diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index 6a4f4f1365..56f348700d 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile @@ -7,3 +7,4 @@ k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o +k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o diff --git a/drivers/dma/ti/k3-psil-am62.c b/drivers/dma/ti/k3-psil-am62.c new file mode 100644 index 00..9527da4cac --- /dev/null +++ b/drivers/dma/ti/k3-psil-am62.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com + */ + +#include + +#include "k3-psil-priv.h" + +#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1,\ + .psd_size = 16, \ + .mapped_channel_id = ch,\ + .flow_start = flow_base,\ + .flow_num = flow_cnt, \ + .default_flow_id = flow_base, \ + }, \ + } + +/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ +static struct psil_ep am62_src_ep_map[] = { + /* CPSW3G */ + PSIL_ETHERNET(0x4600, 19, 19, 16), +}; + +/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ +static struct psil_ep am62_dst_ep_map[] = { + /* CPSW3G */ + PSIL_ETHERNET(0xc600, 19, 19, 8), + PSIL_ETHERNET(0xc601, 20, 27, 8), + PSIL_ETHERNET(0xc602, 21, 35, 8), + PSIL_ETHERNET(0xc603, 22, 43, 8), + PSIL_ETHERNET(0xc604, 23, 51, 8), + PSIL_ETHERNET(0xc605, 24, 59, 8), + PSIL_ETHERNET(0xc606, 25, 67, 8), + PSIL_ETHERNET(0xc607, 26, 75, 8), +}; + +struct psil_ep_map am62_ep_map = { + .name = "am62", + .src = am62_src_ep_map, + .src_count = ARRAY_SIZE(am62_src_ep_map), + .dst = am62_dst_ep_map, + .dst_count = ARRAY_SIZE(am62_dst_ep_map), +}; diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h index 77acaf2139..28078c6bd8 100644 --- a/drivers/dma/ti/k3-psil-priv.h +++ b/drivers/dma/ti/k3-psil-priv.h @@ -41,5 +41,6 @@ extern struct psil_ep_map am654_ep_map; extern struct psil_ep_map j721e_ep_map; extern struct psil_ep_map j721s2_ep_map; extern struct psil_ep_map am64_ep_map; +extern struct psil_ep_map am62_ep_map; #endif /* K3_PSIL_PRIV_H_ */ diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c index 8b2129d4f5..f1330bf4b0 100644 --- a/drivers/dma/ti/k3-psil.c +++ b/drivers/dma/ti/k3-psil.c @@ -24,6 +24,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id) soc_ep_map = &j721s2_ep_map; else if (IS_ENABLED(CONFIG_SOC_K3_AM642)) soc_ep_map = &am64_ep_map; + else if (IS_ENABLED(CONFIG_SOC_K3_AM625)) + soc_ep_map = &am62_ep_map; } if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) { -- 2.36.1
[PATCH v2 03/12] soc: ti: k3-socinfo: Add entry for AM62X SoC family
From: Suman Anna Add support for AM62x SoC identification. Signed-off-by: Suman Anna Signed-off-by: Vignesh Raghavendra --- drivers/soc/soc_ti_k3.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 965728e818..42344145f9 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -15,6 +15,7 @@ #define J7200 0xbb6d #define AM64X 0xbb38 #define J721S2 0xbb75 +#define AM62X 0xbb7e #define JTAG_ID_VARIANT_SHIFT 28 #define JTAG_ID_VARIANT_MASK (0xf << 28) @@ -49,6 +50,9 @@ static const char *get_family_string(u32 idreg) case J721S2: family = "J721S2"; break; + case AM62X: + family = "AM62X"; + break; default: family = "Unknown Silicon"; }; -- 2.36.1
[PATCH v2 02/12] dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62
From: Suman Anna Add pinctrl macros for AM62x SoCs. These macro definitions are similar to that of previous platforms, but adding new definitions to avoid any naming confusions in the SoC dts files. checkpatch insists the following error exists: ERROR: Macros with complex values should be enclosed in parentheses However, we do not need parentheses enclosing the values for this macro as we do intend it to generate two separate values as has been done for other similar platforms. Signed-off-by: Suman Anna Signed-off-by: Vignesh Raghavendra --- include/dt-bindings/pinctrl/k3.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index 63e038e36c..a5204ab91d 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -41,4 +41,7 @@ #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J721S2_WKUP_IOPAD(pa, val, muxmode)(((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #endif -- 2.36.1
[PATCH v2 00/12] TI: Add support for AM62 SoC
This adds basic support for TI's new AM62 family of SoCs and AM625 Starter Kit EVM with SD boot and UART boot. Board support, dts and configs are intentionally kept small to serve as example for future board bringups based on this SoC. Additional peripheral support will be posted separately All bindings and DT patches are in linux-next I have dropped review tags from previous version due to quite a few changes as mentioned below v2: * Patch 9,10,11 are trimmed down to bare minimum * Introduce patch to setup DMA static data for R5 SPL TISCI (patch 7) * Sync with kernel dts. * Drop unnecessary header inclusions () v1: lore.kernel.org/r/20220415140931.490047-1-vigne...@ti.com Aswath Govindraju (1): drivers: mmc: am654_sdhci: Add new compatible for AM62 SoC Nishanth Menon (1): arm: dts: Add support for AM62-SK Suman Anna (6): dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62 soc: ti: k3-socinfo: Add entry for AM62X SoC family arm: mach-k3: Introduce the basic files to support AM62 arm: mach-k3: am62: Introduce autogenerated SoC data arm: dts: Introduce base AM62 SoC dtsi files board: ti: Introduce the basic files to support AM62 SK board Vignesh Raghavendra (4): dma: ti: Add PSIL data for AM62x DMASS firmware: ti_sci_static_data: add static DMA chan data configs: Add configs for AM62x SK doc: ti: Add readme for AM62x SK arch/arm/dts/Makefile |3 + arch/arm/dts/k3-am62-ddr.dtsi | 11 + arch/arm/dts/k3-am62-main.dtsi| 533 arch/arm/dts/k3-am62-mcu.dtsi | 56 + arch/arm/dts/k3-am62-wakeup.dtsi | 41 + arch/arm/dts/k3-am62.dtsi | 105 + arch/arm/dts/k3-am625-r5-sk.dts | 140 ++ arch/arm/dts/k3-am625-sk-u-boot.dtsi | 100 + arch/arm/dts/k3-am625-sk.dts | 150 ++ arch/arm/dts/k3-am625.dtsi| 103 + arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi| 2189 + arch/arm/mach-k3/Kconfig | 10 +- arch/arm/mach-k3/Makefile |1 + arch/arm/mach-k3/am625_init.c | 271 ++ arch/arm/mach-k3/am62x/Makefile |6 + arch/arm/mach-k3/am62x/clk-data.c | 366 +++ arch/arm/mach-k3/am62x/dev-data.c | 78 + arch/arm/mach-k3/arm64-mmu.c |4 +- arch/arm/mach-k3/include/mach/am62_hardware.h | 75 + arch/arm/mach-k3/include/mach/am62_spl.h | 48 + arch/arm/mach-k3/include/mach/hardware.h |4 + arch/arm/mach-k3/include/mach/spl.h |5 + board/ti/am62x/Kconfig| 59 + board/ti/am62x/MAINTAINERS|8 + board/ti/am62x/Makefile |8 + board/ti/am62x/evm.c | 39 + configs/am62x_evm_a53_defconfig | 71 + configs/am62x_evm_r5_defconfig| 91 + doc/board/ti/am62x_sk.rst | 231 ++ doc/board/ti/index.rst|1 + drivers/clk/ti/clk-k3.c |6 + drivers/dma/ti/Makefile |1 + drivers/dma/ti/k3-psil-am62.c | 50 + drivers/dma/ti/k3-psil-priv.h |1 + drivers/dma/ti/k3-psil.c |2 + drivers/firmware/ti_sci_static_data.h | 13 + drivers/mmc/am654_sdhci.c |4 + drivers/power/domain/ti-power-domain.c|6 + drivers/ram/Kconfig |1 + drivers/soc/soc_ti_k3.c |4 + include/configs/am62x_evm.h | 106 + include/dt-bindings/pinctrl/k3.h |3 + include/k3-clk.h |1 + include/k3-dev.h |1 + 44 files changed, 5003 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/k3-am62-ddr.dtsi create mode 100644 arch/arm/dts/k3-am62-main.dtsi create mode 100644 arch/arm/dts/k3-am62-mcu.dtsi create mode 100644 arch/arm/dts/k3-am62-wakeup.dtsi create mode 100644 arch/arm/dts/k3-am62.dtsi create mode 100644 arch/arm/dts/k3-am625-r5-sk.dts create mode 100644 arch/arm/dts/k3-am625-sk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am625-sk.dts create mode 100644 arch/arm/dts/k3-am625.dtsi create mode 100644 arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi create mode 100644 arch/arm/mach-k3/am625_init.c create mode 100644 arch/arm/mach-k3/am62x/Makefile create mode 100644 arch/arm/mach-k3/am62x/clk-data.c create mode 100644 arch/arm/mach-k3/am62x/dev-data.c create mode 100644 arch/arm/mach-k3/include/mach/am62_hardware.h create mode 100644 arch/arm/mach-k3/include/mach/am62_spl.h create mode 100644 board/ti/am62x/Kconfig create mode 100644 board/ti/am62x/MAINTAINERS create mode 100644 board/ti/am62x/Makefile create mode 100644 board/ti/am62x/evm.c create mode 100644 co
[PATCH v2 01/12] drivers: mmc: am654_sdhci: Add new compatible for AM62 SoC
From: Aswath Govindraju The phy used in the 8 bit instance has been changed to the phy used in 4 bit instance on AM62 SoC. This implies the phy configuration required for both the instances of mmc are similar. Therefore, add a new compatible for AM62 SoC using the driver data of am64 4 bit instance. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra --- drivers/mmc/am654_sdhci.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 4305967d78..42a6134364 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -670,6 +670,10 @@ static const struct udevice_id am654_sdhci_ids[] = { .compatible = "ti,am64-sdhci-4bit", .data = (ulong)&sdhci_am64_4bit_drvdata, }, + { + .compatible = "ti,am62-sdhci", + .data = (ulong)&sdhci_am64_4bit_drvdata, + }, { } }; -- 2.36.1
Re: [PATCH 11/11] doc: ti: Add readme for AM62x SK
On 18/04/22 8:26 pm, Andrew Davis wrote: > On 4/15/22 9:09 AM, Vignesh Raghavendra wrote: >> Add info of boot flow and build steps for AM62x SK. >> >> Signed-off-by: Vignesh Raghavendra >> --- >> doc/board/ti/am62x_sk.rst | 231 ++ > > > This isn't specific to the SK, more the AM62x in general, suggest name > am62x.rst. > Agreed > [...] > > >> +Build procedure: >> + >> +1. ATF: >> + >> +.. code-block:: text >> + >> + $ make CROSS_COMPILE=aarch64-none-linux-gnu- ARCH=aarch64 PLAT=k3 >> TARGET_BOARD=lite SPD=opteed >> + > > > These compiler names might not be the same as installed by some current > package managers (-none), > maybe we start by setting up two env vars to point to the two compilers > we use: > > export CROSS_COMPILE32=arm-none-linux-gnueabihf- > export CROSS_COMPILE64=aarch64-none-linux-gnu- > > Then just use those below, that way we only have to switch these first > two commands if we > have a different compiler. > > CROSS_COMPILE=$CROSS_COMPILE32 > Good idea, thanks! > etc.. > > >> +2. OPTEE: >> + >> +.. code-block:: text >> + >> + $ make PLATFORM=k3 CFG_ARM64_core=y >> CROSS_COMPILE=arm-none-linux-gnueabihf- >> CROSS_COMPILE64=aarch64-none-linux-gnu- >> + >> +3. U-Boot: >> + >> +* 3.1 R5: >> + >> +.. code-block:: text >> + >> + $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- >> am62x_evm_r5_defconfig O=/tmp/r5 > > > Lets not pollute directories outside of the current one, suggest > `O=build/r5` > and the same below. Sure, will fix! Regards Vignesh
Re: [PATCH 04/11] arm: mach-k3: Introduce the basic files to support AM62
Hi, On 15/04/22 11:11 pm, Tom Rini wrote: > On Fri, Apr 15, 2022 at 10:08:32PM +0530, Vignesh Raghavendra wrote: >> >> >> On 15/04/22 9:57 pm, Tom Rini wrote: >>> On Fri, Apr 15, 2022 at 07:39:24PM +0530, Vignesh Raghavendra wrote: >>> >>> [snip] >>>> diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c >>>> new file mode 100644 >>>> index 00..ee902a774e >>>> --- /dev/null >>>> +++ b/arch/arm/mach-k3/am625_init.c >>>> @@ -0,0 +1,254 @@ >>>> +// SPDX-License-Identifier: GPL-2.0 >>>> +/* >>>> + * AM625: SoC specific initialization >>>> + * >>>> + * Copyright (C) 2020-2022 Texas Instruments Incorporated - >>>> https://www.ti.com/ >>>> + *Suman Anna >>>> + */ >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include "common.h" >>>> +#include >>>> +#include >>>> +#include >>> >>> Er, common.h twice? >> >> Second one refers to arch/arm/mach-k3/common.h > > OK, lets rename that, and see what info there we can put elsewhere. arch/arm/mach-k3/common.c which contains set of helper functions that are used across the K3 family of devices and this header exports those helpers (and is local to arch/arm/mach-k3/). We may have split into multiple files according to functions in a separate series. > >>> Please re-check this, and then also drop common.h >>> (here and elsewhere) as it only includes other headers and we should >>> avoid it when possible. >> >> Sure, will do. >> >>> In fact, checkpatch.pl complains about both >>> dm.h and common.h so please address series-wide, thanks. >>> >> >> Unfortunately, it doesn't ;( > > Ah, right. It only checks for inside of headers. But still should be > avoided. > Yes, I will drop including in next version. Regards Vignesh
Re: [PATCH 07/11] arm: dts: Introduce base AM62 SoC dtsi files
On 15/04/22 9:58 pm, Tom Rini wrote: > On Fri, Apr 15, 2022 at 07:39:27PM +0530, Vignesh Raghavendra wrote: >> From: Suman Anna >> >> Introduce the basic AM62 SoC description dtsi files. While doing this, >> lets reuse the DDR controller definition from AM64 as the instance is >> the same >> >> Signed-off-by: Gowtham Tammana >> Signed-off-by: Suman Anna >> Signed-off-by: Vignesh Raghavendra >> --- >> arch/arm/dts/k3-am62-ddr.dtsi| 11 + >> arch/arm/dts/k3-am62-main.dtsi | 503 +++ >> arch/arm/dts/k3-am62-mcu.dtsi| 36 +++ >> arch/arm/dts/k3-am62-wakeup.dtsi | 41 +++ >> arch/arm/dts/k3-am62.dtsi| 105 +++ >> arch/arm/dts/k3-am625.dtsi | 103 +++ >> 6 files changed, 799 insertions(+) > > Since the commit doesn't say, what is the status of this with upstream > Linux kernel? Thanks. > Base dts with UART support is upstream[1]. Rest of peripherals are under review [2] [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/ti/k3-am625-sk.dts [2] https://lore.kernel.org/linux-arm-kernel/20220415131917.431137-1-vigne...@ti.com/T/#t
Re: [PATCH 04/11] arm: mach-k3: Introduce the basic files to support AM62
On 15/04/22 9:57 pm, Tom Rini wrote: > On Fri, Apr 15, 2022 at 07:39:24PM +0530, Vignesh Raghavendra wrote: > > [snip] >> diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c >> new file mode 100644 >> index 00..ee902a774e >> --- /dev/null >> +++ b/arch/arm/mach-k3/am625_init.c >> @@ -0,0 +1,254 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * AM625: SoC specific initialization >> + * >> + * Copyright (C) 2020-2022 Texas Instruments Incorporated - >> https://www.ti.com/ >> + * Suman Anna >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include "common.h" >> +#include >> +#include >> +#include > > Er, common.h twice? Second one refers to arch/arm/mach-k3/common.h > Please re-check this, and then also drop common.h > (here and elsewhere) as it only includes other headers and we should > avoid it when possible. Sure, will do. > In fact, checkpatch.pl complains about both > dm.h and common.h so please address series-wide, thanks. > Unfortunately, it doesn't ;( Regards Vignesh
Re: [PATCH 02/11] dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62
On 15/04/22 9:57 pm, Tom Rini wrote: > On Fri, Apr 15, 2022 at 07:39:22PM +0530, Vignesh Raghavendra wrote: >> From: Suman Anna >> >> Add pinctrl macros for AM62x SoCs. These macro definitions are similar >> to that of previous platforms, but adding new definitions to avoid any >> naming confusions in the SoC dts files. >> >> checkpatch insists the following error exists: >> ERROR: Macros with complex values should be enclosed in parentheses >> >> However, we do not need parentheses enclosing the values for this >> macro as we do intend it to generate two separate values as has been >> done for other similar platforms. >> >> Signed-off-by: Suman Anna >> Signed-off-by: Vignesh Raghavendra >> --- >> include/dt-bindings/pinctrl/k3.h | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/include/dt-bindings/pinctrl/k3.h >> b/include/dt-bindings/pinctrl/k3.h >> index 63e038e36c..a5204ab91d 100644 >> --- a/include/dt-bindings/pinctrl/k3.h >> +++ b/include/dt-bindings/pinctrl/k3.h >> @@ -41,4 +41,7 @@ >> #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) >> ((val) | (muxmode)) >> #define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | >> (muxmode)) >> >> +#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) >> ((val) | (muxmode)) >> +#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | >> (muxmode)) >> + >> #endif > > I assume this is being submitted to upstream linux as well? > Sorry, forgot to include upstream ref.: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/pinctrl/k3.h#n44
[PATCH 09/11] arm: dts: Add support for AM62-SK
From: Nishanth Menon AM62 StarterKit (SK) board is a low cost, small form factor board designed for TI’s AM625 SoC. It supports the following interfaces: * 2 GB DDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode * x1 HDMI Port with audio + x1 OLDI/LVDS Display interface for Dual Display * x1 Headphone Jack * x1 USB2.0 Hub with two Type A host and x1 USB Type-C DRP Port * x1 UHS-1 capable µSD card slot * 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837 * 512 Mbit OSPI flash * x4 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin User Expansion Connector * 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO) * 20-pin header for Programmable Realtime Unit (PRU) IO pins * 15-pin CSI header Add basic support for AM62-SK. Schematics: https://www.ti.com/lit/zip/sprr448 Signed-off-by: Nishanth Menon Signed-off-by: Aswath Govindraju Signed-off-by: Nishanth Menon Signed-off-by: Dave Gerlach Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/Makefile |3 + arch/arm/dts/k3-am62-main.dtsi | 44 +- arch/arm/dts/k3-am62-mcu.dtsi | 20 + arch/arm/dts/k3-am625-r5-sk.dts| 130 ++ arch/arm/dts/k3-am625-sk-u-boot.dtsi | 124 ++ arch/arm/dts/k3-am625-sk.dts | 469 + arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi | 2189 7 files changed, 2972 insertions(+), 7 deletions(-) create mode 100644 arch/arm/dts/k3-am625-r5-sk.dts create mode 100644 arch/arm/dts/k3-am625-sk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am625-sk.dts create mode 100644 arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index df7b4addf9..fdfdefc5e4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1162,6 +1162,9 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \ k3-am642-sk.dtb \ k3-am642-r5-sk.dtb +dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ + k3-am625-r5-sk.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi index 8516393d1e..4b6ba98dd0 100644 --- a/arch/arm/dts/k3-am62-main.dtsi +++ b/arch/arm/dts/k3-am62-main.dtsi @@ -280,6 +280,36 @@ clock-names = "fck"; }; + main_spi0: spi@2010 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x2010 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 172 0>; + }; + + main_spi1: spi@2011 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x2011 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 173 0>; + }; + + main_spi2: spi@2012 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x2012 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 174 0>; + }; + main_gpio_intr: interrupt-controller@a0 { compatible = "ti,sci-intr"; reg = <0x00 0x00a0 0x00 0x800>; @@ -328,7 +358,7 @@ sdhci0: mmc@fa1 { compatible = "ti,am62-sdhci"; - reg = <0x00 0xfa1 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; + reg = <0x00 0x0fa1 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; interrupts = ; power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; @@ -348,7 +378,7 @@ sdhci1: mmc@fa0 { compatible = "ti,am62-sdhci"; - reg = <0x00 0xfa0 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; + reg = <0x00 0x0fa0 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; interrupts = ; power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; @@ -371,7 +401,7 @@
[PATCH 11/11] doc: ti: Add readme for AM62x SK
Add info of boot flow and build steps for AM62x SK. Signed-off-by: Vignesh Raghavendra --- doc/board/ti/am62x_sk.rst | 231 ++ doc/board/ti/index.rst| 1 + 2 files changed, 232 insertions(+) create mode 100644 doc/board/ti/am62x_sk.rst diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst new file mode 100644 index 00..4e68c2018a --- /dev/null +++ b/doc/board/ti/am62x_sk.rst @@ -0,0 +1,231 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Vignesh Raghavendra + +Texas Instruments AM62 Platforms + + +Introduction: +- +The AM62 SoC family is the follow on AM335x built on the K3 Multicore +SoC architecture platform, providing ultra-low-power modes, dual +display, multi-sensor edge compute, security and other BOM-saving +integrations. The AM62 SoC targets a broad market to enable +applications such as Industrial HMI, PLC/CNC/Robot control, Medical +Equipment, Building Automation, Appliances and more. + +Some highlights of this SoC are: + +* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. + Pin-to-pin compatible options for single and quad core are available. +* Cortex-M4F for general-purpose or safety usage. +* Dual display support, providing 24-bit RBG parallel interface and + OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display + resolution. +* Selectable GPU support, up to 8GFLOPS, providing better user experience + in 3D graphic display case and Android. +* PRU(Programmable Realtime Unit) support for customized programmable + interfaces/IOs. +* Integrated Giga-bit Ethernet switch supporting up to a total of two + external ports (TSN capable). +* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for + NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, + 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. +* Dedicated Centralized System Controller for Security, Power, and + Resource Management. +* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, + enabling battery powered system design. + +More details can be found in the Technical Reference Manual: +https://www.ti.com/lit/pdf/spruiv7 + +Boot Flow: +-- +Below is the pictorial representation of boot flow: + +.. code-block:: text + + ++ + |TIFS| Main R5 |A53| + ++ + |++ | | | + || Reset | | | | + |++ | | | + | : | | | + |++ | +---+ | | + || *ROM* |--|-->| Reset rls | | | + |++ | +---+ | | + ||| | : | | + || ROM | | : | | + ||services| | : | | + ||| | +-+ | | + ||| | | *R5 ROM* | | | + ||| | +-+ | | + |||<-|---|Load and auth| | | + ||| | | tiboot3.bin | | | + |++ | +-+ | | + |||<-|---| Load sysfw | | | + ||| | | part to TIFS| | | + ||| | | core| | | + ||| | +-+ | | + ||| | : | | + ||| | : | | + ||| | : | | + ||| | +-+ | | + ||| | | *R5 SPL* | | | + ||| | +-+ | | + ||| | |DDR | | | + ||| | | config| | | + ||| | +-+ | | + ||| | |Load | | | + ||| | |
[PATCH 10/11] configs: Add configs for AM62x SK
Add am62x_evm_r5_defconfig for R5 SPL and am62x_evm_a53_defconfig for A53 SPL and U-Boot support. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra --- board/ti/am62x/MAINTAINERS | 8 +++ configs/am62x_evm_a53_defconfig | 110 ++ configs/am62x_evm_r5_defconfig | 114 include/configs/am62x_evm.h | 106 + 4 files changed, 338 insertions(+) create mode 100644 board/ti/am62x/MAINTAINERS create mode 100644 configs/am62x_evm_a53_defconfig create mode 100644 configs/am62x_evm_r5_defconfig create mode 100644 include/configs/am62x_evm.h diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS new file mode 100644 index 00..8942876cba --- /dev/null +++ b/board/ti/am62x/MAINTAINERS @@ -0,0 +1,8 @@ +AM64x BOARD +M: Dave Gerlach +M: Tom Rini +S: Maintained +F: board/ti/am62x/ +F: include/configs/am62x_evm.h +F: configs/am62x_evm_r5_defconfig +F: configs/am62x_evm_a53_defconfig diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig new file mode 100644 index 00..d06083442c --- /dev/null +++ b/configs/am62x_evm_a53_defconfig @@ -0,0 +1,110 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM625=y +CONFIG_K3_ATF_LOAD_ADDR=0x9e78 +CONFIG_TARGET_AM625_A53_EVM=y +CONFIG_ENV_SIZE=0x2 +CONFIG_ENV_OFFSET=0x68 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x28 +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_TEXT_BASE=0x8008 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk" +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100 +CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern" +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_TIME=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig new file mode 100644 index 00..c8323f6bed --- /dev/null +++ b/configs/am62x_evm_r5_defconfig @@ -0,0 +1,114 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_SOC_K3_AM625=y +CONFIG_TARGET_AM625_R5_EVM=y +CONFIG_ENV_SIZE=0x2 +CONFIG_ENV_OFFSET=0x68 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_TEXT_BASE=0x43c0 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_SPL_SIZE_LIMIT=0x4 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 +CONFIG_SPL_FS_FAT=y +CONFIG_S
[PATCH 08/11] board: ti: Introduce the basic files to support AM62 SK board
From: Suman Anna Add basic support for AM64 SK. This has 2GB DDR. Note that stack for R5 SPL is in OCRAM @ 0x7000 so that is away from BSS and does not step on BSS section Signed-off-by: Suman Anna Signed-off-by: Aswath Govindraju Signed-off-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/Kconfig | 1 + board/ti/am62x/Kconfig| 63 +++ board/ti/am62x/Makefile | 8 ++ board/ti/am62x/evm.c | 149 ++ drivers/firmware/ti_sci_static_data.h | 7 ++ 5 files changed, 228 insertions(+) create mode 100644 board/ti/am62x/Kconfig create mode 100644 board/ti/am62x/Makefile create mode 100644 board/ti/am62x/evm.c diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 0dc4f44fdd..57f693e9a1 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -178,6 +178,7 @@ config K3_DM_FW source "board/ti/am65x/Kconfig" source "board/ti/am64x/Kconfig" +source "board/ti/am62x/Kconfig" source "board/ti/j721e/Kconfig" source "board/siemens/iot2050/Kconfig" source "board/ti/j721s2/Kconfig" diff --git a/board/ti/am62x/Kconfig b/board/ti/am62x/Kconfig new file mode 100644 index 00..95eec27170 --- /dev/null +++ b/board/ti/am62x/Kconfig @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ +# Suman Anna + +choice + prompt "TI K3 AM62x based boards" + optional + +config TARGET_AM625_A53_EVM + bool "TI K3 based AM625 EVM running on A53" + select ARM64 + select SOC_K3_AM625 + imply BOARD + imply SPL_BOARD + imply TI_I2C_BOARD_DETECT + +config TARGET_AM625_R5_EVM + bool "TI K3 based AM625 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select SOC_K3_AM625 + select RAM + select SPL_RAM + select K3_DDRSS + imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT + +endchoice + +if TARGET_AM625_A53_EVM + +config SYS_BOARD + default "am62x" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "am62x_evm" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_AM625_R5_EVM + +config SYS_BOARD + default "am62x" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "am62x_evm" + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +source "board/ti/common/Kconfig" + +endif diff --git a/board/ti/am62x/Makefile b/board/ti/am62x/Makefile new file mode 100644 index 00..f4c35edffa --- /dev/null +++ b/board/ti/am62x/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ +# Suman Anna +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evm.o diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c new file mode 100644 index 00..cf25f0acd9 --- /dev/null +++ b/board/ti/am62x/evm.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board specific initialization for AM62x platforms + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Suman Anna + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../common/board_detect.h" + +#define board_is_am62x_skevm() board_ti_k3_is("AM62-SKEVM") + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x8000; + + return 0; +} + +int dram_init_banksize(void) +{ + /* Bank 0 declares the memory available in the DDR low region */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x8000; + gd->ram_size = 0x8000; + + return 0; +} + +#if defined(CONFIG_SPL_LOAD_FIT) +int board_fit_config_name_match(const char *name) +{ + bool eeprom_read = board_ti_was_eeprom_read(); + + if (!eeprom_read || board_is_am62x_skevm()) { + if (!strcmp(name, "k3-am625-r5-sk") || !strcmp(name, "k3-am625-sk")) + return 0; + } + + return -1; +} +#endif + +#ifdef CONFIG_TI_I2C_BOARD_DETECT +int do_board_detect(void) +{ + int ret; + + ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS, +CONFIG_EEPROM_CHIP_ADDRESS); + if (ret) { + printf("EEPROM not available at 0x%02x, trying to read at 0x%02x\n", + CONFIG_EEPROM_CHIP_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS + 1); +
[PATCH 07/11] arm: dts: Introduce base AM62 SoC dtsi files
From: Suman Anna Introduce the basic AM62 SoC description dtsi files. While doing this, lets reuse the DDR controller definition from AM64 as the instance is the same Signed-off-by: Gowtham Tammana Signed-off-by: Suman Anna Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-am62-ddr.dtsi| 11 + arch/arm/dts/k3-am62-main.dtsi | 503 +++ arch/arm/dts/k3-am62-mcu.dtsi| 36 +++ arch/arm/dts/k3-am62-wakeup.dtsi | 41 +++ arch/arm/dts/k3-am62.dtsi| 105 +++ arch/arm/dts/k3-am625.dtsi | 103 +++ 6 files changed, 799 insertions(+) create mode 100644 arch/arm/dts/k3-am62-ddr.dtsi create mode 100644 arch/arm/dts/k3-am62-main.dtsi create mode 100644 arch/arm/dts/k3-am62-mcu.dtsi create mode 100644 arch/arm/dts/k3-am62-wakeup.dtsi create mode 100644 arch/arm/dts/k3-am62.dtsi create mode 100644 arch/arm/dts/k3-am625.dtsi diff --git a/arch/arm/dts/k3-am62-ddr.dtsi b/arch/arm/dts/k3-am62-ddr.dtsi new file mode 100644 index 00..0a8ced8f38 --- /dev/null +++ b/arch/arm/dts/k3-am62-ddr.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am64-ddr.dtsi" +&memorycontroller { + power-domains = <&k3_pds 170 TI_SCI_PD_SHARED>, + <&k3_pds 55 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 170 0>, <&k3_clks 16 4>; +}; diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi new file mode 100644 index 00..8516393d1e --- /dev/null +++ b/arch/arm/dts/k3-am62-main.dtsi @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family Main Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + oc_sram: sram@7000 { + compatible = "mmio-sram"; + reg = <0x00 0x7000 0x00 0x1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x7000 0x1>; + }; + + gic500: interrupt-controller@180 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x0180 0x00 0x1>, /* GICD */ + <0x00 0x0188 0x00 0xc>, /* GICR */ + <0x00 0x0188 0x00 0xc>, /* GICR */ + <0x01 0x 0x00 0x2000>,/* GICC */ + <0x01 0x0001 0x00 0x1000>,/* GICH */ + <0x01 0x0002 0x00 0x2000>;/* GICV */ + /* +* vcpumntirq: +* virtual CPU interface maintenance interrupt +*/ + interrupts = ; + + gic_its: msi-controller@182 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x0182 0x00 0x1>; + socionext,synquacer-pre-its = <0x100 0x40>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_conf: syscon@10 { + compatible = "syscon", "simple-mfd"; + reg = <0x00 0x0010 0x00 0x2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x0010 0x2>; + + phy_gmii_sel: phy@4044 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4044 0x8>; + #phy-cells = <1>; + }; + }; + + dmss: bus@4800 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x4800 0x00 0x4800 0x00 0x0640>; + + ti,sci-dev-id = <25>; + + secure_proxy_main: mailbox@4d00 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x4d00 0x00 0x8>, + <0x00 0x4a60 0x00 0x8>, + <0x00 0x4a40 0x00 0x8>; + interrupt-names = "rx_012"; + interrupts = ; + }; + +
[PATCH 06/11] dma: ti: Add PSIL data for AM62x DMASS
Add PSIL data for AM62x SoC Signed-off-by: Vignesh Raghavendra --- drivers/dma/ti/Makefile | 1 + drivers/dma/ti/k3-psil-am62.c | 50 +++ drivers/dma/ti/k3-psil-priv.h | 1 + drivers/dma/ti/k3-psil.c | 2 ++ 4 files changed, 54 insertions(+) create mode 100644 drivers/dma/ti/k3-psil-am62.c diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index 6a4f4f1365..56f348700d 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile @@ -7,3 +7,4 @@ k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o +k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o diff --git a/drivers/dma/ti/k3-psil-am62.c b/drivers/dma/ti/k3-psil-am62.c new file mode 100644 index 00..9527da4cac --- /dev/null +++ b/drivers/dma/ti/k3-psil-am62.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com + */ + +#include + +#include "k3-psil-priv.h" + +#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1,\ + .psd_size = 16, \ + .mapped_channel_id = ch,\ + .flow_start = flow_base,\ + .flow_num = flow_cnt, \ + .default_flow_id = flow_base, \ + }, \ + } + +/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ +static struct psil_ep am62_src_ep_map[] = { + /* CPSW3G */ + PSIL_ETHERNET(0x4600, 19, 19, 16), +}; + +/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ +static struct psil_ep am62_dst_ep_map[] = { + /* CPSW3G */ + PSIL_ETHERNET(0xc600, 19, 19, 8), + PSIL_ETHERNET(0xc601, 20, 27, 8), + PSIL_ETHERNET(0xc602, 21, 35, 8), + PSIL_ETHERNET(0xc603, 22, 43, 8), + PSIL_ETHERNET(0xc604, 23, 51, 8), + PSIL_ETHERNET(0xc605, 24, 59, 8), + PSIL_ETHERNET(0xc606, 25, 67, 8), + PSIL_ETHERNET(0xc607, 26, 75, 8), +}; + +struct psil_ep_map am62_ep_map = { + .name = "am62", + .src = am62_src_ep_map, + .src_count = ARRAY_SIZE(am62_src_ep_map), + .dst = am62_dst_ep_map, + .dst_count = ARRAY_SIZE(am62_dst_ep_map), +}; diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h index 77acaf2139..28078c6bd8 100644 --- a/drivers/dma/ti/k3-psil-priv.h +++ b/drivers/dma/ti/k3-psil-priv.h @@ -41,5 +41,6 @@ extern struct psil_ep_map am654_ep_map; extern struct psil_ep_map j721e_ep_map; extern struct psil_ep_map j721s2_ep_map; extern struct psil_ep_map am64_ep_map; +extern struct psil_ep_map am62_ep_map; #endif /* K3_PSIL_PRIV_H_ */ diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c index 8b2129d4f5..f1330bf4b0 100644 --- a/drivers/dma/ti/k3-psil.c +++ b/drivers/dma/ti/k3-psil.c @@ -24,6 +24,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id) soc_ep_map = &j721s2_ep_map; else if (IS_ENABLED(CONFIG_SOC_K3_AM642)) soc_ep_map = &am64_ep_map; + else if (IS_ENABLED(CONFIG_SOC_K3_AM625)) + soc_ep_map = &am62_ep_map; } if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) { -- 2.35.3
[PATCH 05/11] arm: mach-k3: am62: Introduce autogenerated SoC data
From: Suman Anna Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach Signed-off-by: Suman Anna Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/am62x/Makefile| 6 + arch/arm/mach-k3/am62x/clk-data.c | 366 + arch/arm/mach-k3/am62x/dev-data.c | 78 ++ drivers/clk/ti/clk-k3.c| 6 + drivers/power/domain/ti-power-domain.c | 6 + include/k3-clk.h | 1 + include/k3-dev.h | 1 + 7 files changed, 464 insertions(+) create mode 100644 arch/arm/mach-k3/am62x/Makefile create mode 100644 arch/arm/mach-k3/am62x/clk-data.c create mode 100644 arch/arm/mach-k3/am62x/dev-data.c diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile new file mode 100644 index 00..d6c876df66 --- /dev/null +++ b/arch/arm/mach-k3/am62x/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/am62x/clk-data.c b/arch/arm/mach-k3/am62x/clk-data.c new file mode 100644 index 00..c0881778fe --- /dev/null +++ b/arch/arm/mach-k3/am62x/clk-data.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62X specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + NULL, + NULL, + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + NULL, +}; + +static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = { + "board_0_mmc0_clklb_out", + "board_0_mmc0_clk_out", +}; + +static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = { + "board_0_mmc1_clklb_out", + "board_0_mmc1_clk_out", +}; + +static const char * const main_ospi_loopback_clk_sel_out0_parents[] = { + "board_0_ospi0_dqs_out", + "board_0_ospi0_lbclko_out", +}; + +static const char * const main_usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const main_usb1_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const clkout0_ctrl_out0_parents[] = { + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", +}; + +static const char * const clk_32k_rc_sel_out0_parents[] = { + "gluelogic_rcosc_clk_1p0v_97p65k", + "hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", + "clk_32k_rc_sel_div_clkout", + "gluelogic_lfosc0_clkout", +}; + +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_gtcclk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_ospi_ref_clk_sel_out0_parents[] = { +
[PATCH 04/11] arm: mach-k3: Introduce the basic files to support AM62
From: Suman Anna The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC architecture platform, providing ultra-low-power modes, dual display, multi-sensor edge compute, security and other BOM-saving integration. The AM62 SoC targets broad market to enable applications such as Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building Automation, Appliances and more. Some highlights of this SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Pin-to-pin compatible options for single and quad core are available. * Cortex-M4F for general-purpose or safety usage. * Dual display support, providing 24-bit RBG parallel interface and OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display resolution. * Selectable GPUsupport, up to 8GFLOPS, providing better user experience in 3D graphic display case and Android. * PRU(Programmable Realtime Unit) support for customized programmable interfaces/IOs. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized System Controller for Security, Power, and Resource Management. * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only, enabling battery powered system design. AM625 is the first device of the family. Add DT bindings for the same. More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Suman Anna Signed-off-by: Gowtham Tammana Signed-off-by: Aswath Govindraju Signed-off-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/Kconfig | 9 +- arch/arm/mach-k3/Makefile | 1 + arch/arm/mach-k3/am625_init.c | 254 ++ arch/arm/mach-k3/arm64-mmu.c | 4 +- arch/arm/mach-k3/include/mach/am62_hardware.h | 66 + arch/arm/mach-k3/include/mach/am62_spl.h | 44 +++ arch/arm/mach-k3/include/mach/hardware.h | 4 + arch/arm/mach-k3/include/mach/spl.h | 5 + drivers/ram/Kconfig | 1 + 9 files changed, 385 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-k3/am625_init.c create mode 100644 arch/arm/mach-k3/include/mach/am62_hardware.h create mode 100644 arch/arm/mach-k3/include/mach/am62_spl.h diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index a01bf23514..0dc4f44fdd 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -16,6 +16,9 @@ config SOC_K3_J721S2 config SOC_K3_AM642 bool "TI's K3 based AM642 SoC Family Support" +config SOC_K3_AM625 + bool "TI's K3 based AM625 SoC Family Support" + endchoice config SYS_SOC @@ -26,6 +29,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE default 0x8 if SOC_K3_AM6 default 0x10 if SOC_K3_J721E || SOC_K3_J721S2 default 0x1c if SOC_K3_AM642 + default 0x3c000 if SOC_K3_AM625 help Describes the total size of the MCU or OCMC MSRAM present on the SoC in use. This doesn't specify the total size of SPL as @@ -37,6 +41,7 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE default 0x58000 if SOC_K3_AM6 default 0xc if SOC_K3_J721E || SOC_K3_J721S2 default 0x18 if SOC_K3_AM642 + default 0x38000 if SOC_K3_AM625 help Describes the maximum size of the image that ROM can download from any boot media. @@ -61,6 +66,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX default 0x41cffbfc if SOC_K3_J721E default 0x41cfdbfc if SOC_K3_J721S2 default 0x701bebfc if SOC_K3_AM642 + default 0x43c3f290 if SOC_K3_AM625 help Address at which ROM stores the value which determines if SPL is booted up by primary boot media or secondary boot media. @@ -129,6 +135,7 @@ config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART config K3_SYSFW_IMAGE_SIZE_MAX int "Amount of memory dynamically allocated for loading SYSFW blob" depends on K3_LOAD_SYSFW + default 163840 if SOC_K3_AM625 default 278000 help Amount of memory (in bytes) reserved through dynamic allocation at @@ -160,7 +167,7 @@ config K3_ATF_LOAD_ADDR config K3_DM_FW bool "Separate DM firmware image" - depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN default y help Enabling this will indicate that the system has separate DM diff --git a/ar
[PATCH 03/11] soc: ti: k3-socinfo: Add entry for AM62X SoC family
From: Suman Anna Add support for AM62x SoC identification. Signed-off-by: Suman Anna Signed-off-by: Vignesh Raghavendra --- drivers/soc/soc_ti_k3.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 965728e818..42344145f9 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -15,6 +15,7 @@ #define J7200 0xbb6d #define AM64X 0xbb38 #define J721S2 0xbb75 +#define AM62X 0xbb7e #define JTAG_ID_VARIANT_SHIFT 28 #define JTAG_ID_VARIANT_MASK (0xf << 28) @@ -49,6 +50,9 @@ static const char *get_family_string(u32 idreg) case J721S2: family = "J721S2"; break; + case AM62X: + family = "AM62X"; + break; default: family = "Unknown Silicon"; }; -- 2.35.3
[PATCH 02/11] dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62
From: Suman Anna Add pinctrl macros for AM62x SoCs. These macro definitions are similar to that of previous platforms, but adding new definitions to avoid any naming confusions in the SoC dts files. checkpatch insists the following error exists: ERROR: Macros with complex values should be enclosed in parentheses However, we do not need parentheses enclosing the values for this macro as we do intend it to generate two separate values as has been done for other similar platforms. Signed-off-by: Suman Anna Signed-off-by: Vignesh Raghavendra --- include/dt-bindings/pinctrl/k3.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index 63e038e36c..a5204ab91d 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -41,4 +41,7 @@ #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J721S2_WKUP_IOPAD(pa, val, muxmode)(((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #endif -- 2.35.3
[PATCH 01/11] drivers: mmc: am654_sdhci: Add new compatible for AM62 SoC
From: Aswath Govindraju The phy used in the 8 bit instance has been changed to the phy used in 4 bit instance on AM62 SoC. This implies the phy configuration required for both the instances of mmc are similar. Therefore, add a new compatible for AM62 SoC using the driver data of am64 4 bit instance. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra --- drivers/mmc/am654_sdhci.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 4305967d78..42a6134364 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -670,6 +670,10 @@ static const struct udevice_id am654_sdhci_ids[] = { .compatible = "ti,am64-sdhci-4bit", .data = (ulong)&sdhci_am64_4bit_drvdata, }, + { + .compatible = "ti,am62-sdhci", + .data = (ulong)&sdhci_am64_4bit_drvdata, + }, { } }; -- 2.35.3
[PATCH 00/11] TI: Add support for AM62 SoC
This adds basic support for TI's new AM62 family of SoCs and AM625 Starter Kit EVM with SD boot and networking support at U-Boot prompt Aswath Govindraju (1): drivers: mmc: am654_sdhci: Add new compatible for AM62 SoC Nishanth Menon (1): arm: dts: Add support for AM62-SK Suman Anna (6): dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62 soc: ti: k3-socinfo: Add entry for AM62X SoC family arm: mach-k3: Introduce the basic files to support AM62 arm: mach-k3: am62: Introduce autogenerated SoC data arm: dts: Introduce base AM62 SoC dtsi files board: ti: Introduce the basic files to support AM62 SK board Vignesh Raghavendra (3): dma: ti: Add PSIL data for AM62x DMASS configs: Add configs for AM62x SK doc: ti: Add readme for AM62x SK arch/arm/dts/Makefile |3 + arch/arm/dts/k3-am62-ddr.dtsi | 11 + arch/arm/dts/k3-am62-main.dtsi| 533 arch/arm/dts/k3-am62-mcu.dtsi | 56 + arch/arm/dts/k3-am62-wakeup.dtsi | 41 + arch/arm/dts/k3-am62.dtsi | 105 + arch/arm/dts/k3-am625-r5-sk.dts | 130 + arch/arm/dts/k3-am625-sk-u-boot.dtsi | 124 + arch/arm/dts/k3-am625-sk.dts | 469 arch/arm/dts/k3-am625.dtsi| 103 + arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi| 2189 + arch/arm/mach-k3/Kconfig | 10 +- arch/arm/mach-k3/Makefile |1 + arch/arm/mach-k3/am625_init.c | 254 ++ arch/arm/mach-k3/am62x/Makefile |6 + arch/arm/mach-k3/am62x/clk-data.c | 366 +++ arch/arm/mach-k3/am62x/dev-data.c | 78 + arch/arm/mach-k3/arm64-mmu.c |4 +- arch/arm/mach-k3/include/mach/am62_hardware.h | 66 + arch/arm/mach-k3/include/mach/am62_spl.h | 44 + arch/arm/mach-k3/include/mach/hardware.h |4 + arch/arm/mach-k3/include/mach/spl.h |5 + board/ti/am62x/Kconfig| 63 + board/ti/am62x/MAINTAINERS|8 + board/ti/am62x/Makefile |8 + board/ti/am62x/evm.c | 149 ++ configs/am62x_evm_a53_defconfig | 110 + configs/am62x_evm_r5_defconfig| 114 + doc/board/ti/am62x_sk.rst | 231 ++ doc/board/ti/index.rst|1 + drivers/clk/ti/clk-k3.c |6 + drivers/dma/ti/Makefile |1 + drivers/dma/ti/k3-psil-am62.c | 50 + drivers/dma/ti/k3-psil-priv.h |1 + drivers/dma/ti/k3-psil.c |2 + drivers/firmware/ti_sci_static_data.h |7 + drivers/mmc/am654_sdhci.c |4 + drivers/power/domain/ti-power-domain.c|6 + drivers/ram/Kconfig |1 + drivers/soc/soc_ti_k3.c |4 + include/configs/am62x_evm.h | 106 + include/dt-bindings/pinctrl/k3.h |3 + include/k3-clk.h |1 + include/k3-dev.h |1 + 44 files changed, 5476 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/k3-am62-ddr.dtsi create mode 100644 arch/arm/dts/k3-am62-main.dtsi create mode 100644 arch/arm/dts/k3-am62-mcu.dtsi create mode 100644 arch/arm/dts/k3-am62-wakeup.dtsi create mode 100644 arch/arm/dts/k3-am62.dtsi create mode 100644 arch/arm/dts/k3-am625-r5-sk.dts create mode 100644 arch/arm/dts/k3-am625-sk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am625-sk.dts create mode 100644 arch/arm/dts/k3-am625.dtsi create mode 100644 arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi create mode 100644 arch/arm/mach-k3/am625_init.c create mode 100644 arch/arm/mach-k3/am62x/Makefile create mode 100644 arch/arm/mach-k3/am62x/clk-data.c create mode 100644 arch/arm/mach-k3/am62x/dev-data.c create mode 100644 arch/arm/mach-k3/include/mach/am62_hardware.h create mode 100644 arch/arm/mach-k3/include/mach/am62_spl.h create mode 100644 board/ti/am62x/Kconfig create mode 100644 board/ti/am62x/MAINTAINERS create mode 100644 board/ti/am62x/Makefile create mode 100644 board/ti/am62x/evm.c create mode 100644 configs/am62x_evm_a53_defconfig create mode 100644 configs/am62x_evm_r5_defconfig create mode 100644 doc/board/ti/am62x_sk.rst create mode 100644 drivers/dma/ti/k3-psil-am62.c create mode 100644 include/configs/am62x_evm.h -- 2.35.3
Re: [PATCH] ARM: dts: k3-j721s2: Correct timer frequency
On 07/03/22 2:55 pm, Vignesh Raghavendra wrote: > MCU Timer0 runs at 250MHz, and the clock-frequency defined in DT appears > incorrect. > > Without this delays in R5 SPL are 10x off. > > Signed-off-by: Vignesh Raghavendra > --- > arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi > b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi > index 749bc717f3..a17e61eccf 100644 > --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi > +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi > @@ -40,7 +40,7 @@ > compatible = "ti,omap5430-timer"; > reg = <0x0 0x4040 0x0 0x80>; > ti,timer-alwon; > - clock-frequency = <2500>; > + clock-frequency = <25000>; > u-boot,dm-spl; > }; > Gentle ping...
[PATCH v2 2/2] ARM: dts: k3-am642: Correct timer frequency
Timer0 runs at 200MHz,and the clock-frequency defined in DT is incorrect. Fix it. Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-am642-evm-u-boot.dtsi | 2 +- arch/arm/dts/k3-am642-sk-u-boot.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi index 03688a51a3..0c2d973409 100644 --- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi @@ -16,7 +16,7 @@ compatible = "ti,omap5430-timer"; reg = <0x0 0x240 0x0 0x80>; ti,timer-alwon; - clock-frequency = <25000>; + clock-frequency = <2>; u-boot,dm-spl; }; }; diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi index e5c26b8326..afe5baba8c 100644 --- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi @@ -20,7 +20,7 @@ compatible = "ti,omap5430-timer"; reg = <0x0 0x240 0x0 0x80>; ti,timer-alwon; - clock-frequency = <25000>; + clock-frequency = <2>; u-boot,dm-spl; }; }; -- 2.35.1
[PATCH v2 1/2] configs: am64x_evm_a53_defconfig: Switch to per-cpu timer as tick provider
On arm64 systems, recommendation is to use per-cpu timer for time keeping. Currently AM64 ends up using DM timer as tick timer as driver is enabled in the config. Drop OMAP DM Timer related configs, this will switch to using armv8 per-cpu timer as tick timer for A53 SPL/U-Boot. Signed-off-by: Vignesh Raghavendra --- configs/am64x_evm_a53_defconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 7397436def..bceb35f5ec 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -135,9 +135,6 @@ CONFIG_CADENCE_QSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y -CONFIG_TIMER=y -CONFIG_SPL_TIMER=y -CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y -- 2.35.1
[PATCH v2 0/2] AM64: Tick timer fixes
Patch 1 switches AM64 to use armv8 per-cpu timer at A53 SPL/U-Boot stage as done in other TI K3 platforms Patch 2 corrects DM timer freq to be 200MHz (used at R5 SPL stage) v2: Update commit message 1/2 as per Nishanth's suggestion Reword commit msg in 2/2 to be more readable. v1: lore.kernel.org/r/20220307092059.669376-1-vigne...@ti.com Vignesh Raghavendra (2): configs: am64x_evm_a53_defconfig: Switch to per-cpu timer as tick provider ARM: dts: k3-am642: Correct timer frequency arch/arm/dts/k3-am642-evm-u-boot.dtsi | 2 +- arch/arm/dts/k3-am642-sk-u-boot.dtsi | 2 +- configs/am64x_evm_a53_defconfig | 3 --- 3 files changed, 2 insertions(+), 5 deletions(-) -- 2.35.1
[PATCH] ARM: dts: k3-j721s2: Correct timer frequency
MCU Timer0 runs at 250MHz, and the clock-frequency defined in DT appears incorrect. Without this delays in R5 SPL are 10x off. Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index 749bc717f3..a17e61eccf 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -40,7 +40,7 @@ compatible = "ti,omap5430-timer"; reg = <0x0 0x4040 0x0 0x80>; ti,timer-alwon; - clock-frequency = <2500>; + clock-frequency = <25000>; u-boot,dm-spl; }; -- 2.35.1
[PATCH 2/2] ARM: dts: k3-am642: Fix correct timer frequency
Timer0 runs at 200MHz,and the clock-frequency defined in DT appears is incorrect. Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-am642-evm-u-boot.dtsi | 2 +- arch/arm/dts/k3-am642-sk-u-boot.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi index 03688a51a3..0c2d973409 100644 --- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi @@ -16,7 +16,7 @@ compatible = "ti,omap5430-timer"; reg = <0x0 0x240 0x0 0x80>; ti,timer-alwon; - clock-frequency = <25000>; + clock-frequency = <2>; u-boot,dm-spl; }; }; diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi index e5c26b8326..afe5baba8c 100644 --- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi @@ -20,7 +20,7 @@ compatible = "ti,omap5430-timer"; reg = <0x0 0x240 0x0 0x80>; ti,timer-alwon; - clock-frequency = <25000>; + clock-frequency = <2>; u-boot,dm-spl; }; }; -- 2.35.1
[PATCH 0/2] AM64: Tick timer fixes
Patch 1 switches AM64 to use GTC as system timer at A53 SPL/U-boot stage as done in other TI K3 platforms Patch 2 corrects DM timer freq to be 200MHz (used at R5 SPL stage) Vignesh Raghavendra (2): configs: am64x_evm_a53_defconfig: Switch to GTC as tick timer ARM: dts: k3-am642: Fix correct timer frequency arch/arm/dts/k3-am642-evm-u-boot.dtsi | 2 +- arch/arm/dts/k3-am642-sk-u-boot.dtsi | 2 +- configs/am64x_evm_a53_defconfig | 3 --- 3 files changed, 2 insertions(+), 5 deletions(-) -- 2.35.1
[PATCH 1/2] configs: am64x_evm_a53_defconfig: Switch to GTC as tick timer
GTC is to be used as tick timer for A53 SPL/U-Boot, but currently AM64 ends up using DM timer as driver is enabled in the config, drop OMAP DM Timer related configs so that GTC is used by default. Signed-off-by: Vignesh Raghavendra --- configs/am64x_evm_a53_defconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 7397436def..bceb35f5ec 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -135,9 +135,6 @@ CONFIG_CADENCE_QSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y -CONFIG_TIMER=y -CONFIG_SPL_TIMER=y -CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y -- 2.35.1
[PATCH] spl: ymodem: Fix buffer overflow during Image copy
ymodem_read_fit() driver will end copying up to BUF_SIZE boundary even when requested size of copy operation is less than that. For example, if offset = 0, size = 1440B, ymodem_read_fit() ends up copying 2KB from offset = 0, to destination buffer addr This causes data corruption when malloc'd buffer is passed during UART boot since commit 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d buffer for loading images") With this, UART boot works again on K3 (AM654, J7, AM64) family of devices. Fixes: 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d buffer for loading images") Signed-off-by: Vignesh Raghavendra --- common/spl/spl_ymodem.c | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c index 047df74856..fdd5261042 100644 --- a/common/spl/spl_ymodem.c +++ b/common/spl/spl_ymodem.c @@ -42,6 +42,7 @@ static ulong ymodem_read_fit(struct spl_load_info *load, ulong offset, int res, err, buf_offset; struct ymodem_fit_info *info = load->priv; char *buf = info->buf; + ulong copy_size = size; while (info->image_read < offset) { res = xyzModem_stream_read(buf, BUF_SIZE, &err); @@ -57,8 +58,14 @@ static ulong ymodem_read_fit(struct spl_load_info *load, ulong offset, buf_offset = (info->image_read % BUF_SIZE); else buf_offset = BUF_SIZE; + + if (res > copy_size) { + memcpy(addr, &buf[buf_offset - res], copy_size); + goto done; + } memcpy(addr, &buf[buf_offset - res], res); addr = addr + res; + copy_size -= res; } while (info->image_read < offset + size) { @@ -66,11 +73,17 @@ static ulong ymodem_read_fit(struct spl_load_info *load, ulong offset, if (res <= 0) break; - memcpy(addr, buf, res); info->image_read += res; + if (res > copy_size) { + memcpy(addr, buf, copy_size); + goto done; + } + memcpy(addr, buf, res); addr += res; + copy_size -= res; } +done: return size; } -- 2.35.0
[PATCH] net: ti: am65-cpsw: Cleanup resources before jump to kernel
In case fastboot over Ethernet, am65_cpsw_stop() is not called unless DM_FLAG_OS_PREPARE is set. Without call to am65_cpsw_stop(), DMA resources are not released thus leading to failures in kernel. Fix this by adding DM_FLAG_OS_PREPARE flag to am65_cpsw_nuss_port driver. Reported-by: Christian Gmeiner Signed-off-by: Vignesh Raghavendra --- drivers/net/ti/am65-cpsw-nuss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 454986ff15..87f51b3b99 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -817,5 +817,5 @@ U_BOOT_DRIVER(am65_cpsw_nuss_port) = { .ops= &am65_cpsw_ops, .priv_auto = sizeof(struct am65_cpsw_priv), .plat_auto = sizeof(struct eth_pdata), - .flags = DM_FLAG_ALLOC_PRIV_DMA, + .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE, }; -- 2.35.0
Re: [PATCH 8/8] configs: am64x_evm_r5/a53_defconfig: Enable configs required for Ethboot
On 21/01/22 8:27 pm, Tom Rini wrote: > On Fri, Jan 21, 2022 at 09:59:21AM +0530, Vignesh Raghavendra wrote: >> >> >> On 17/01/22 8:47 am, Tom Rini wrote: >>> On Fri, Dec 24, 2021 at 12:55:36PM +0530, Vignesh Raghavendra wrote: >>> >>>> Enable config options needed to support Ethernet boot on AM64x SK. >>>> >>>> Signed-off-by: Vignesh Raghavendra >>> >>> This leads to size overflow on r5. >>> >> >> Hmm, I don't see size limitations locally. >> >> $ size spl/u-boot-spl >>text data bss dec hex filename >> 23047010401 12992 253863 3dfa7 spl/u-boot-spl >> >> vs limit declared in configs/am64x_evm_r5_defconfig: >> >> CONFIG_SPL_SIZE_LIMIT=0x19 >> >> I don't expect size overflow? > > What toolchain are you using? I'm seeing this with gcc-11.1. > I am using 10.3.1. Will try 11.1. But what's is overflow error being reported? Also, could you try if [1] compiles fine on top of latest master? [1] https://lore.kernel.org/u-boot/20220121071754.197577-1-vigne...@ti.com/T/#t Regards Vignesh
[PATCH 4/4] configs: am64x_evm_r5/a53_defconfig: Enable configs required for Ethboot
Enable config options needed to support Ethernet boot on AM64x SK. Signed-off-by: Vignesh Raghavendra --- configs/am64x_evm_a53_defconfig | 4 configs/am64x_evm_r5_defconfig | 12 2 files changed, 16 insertions(+) diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 3ce2129e49..77010a3ef1 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y @@ -38,8 +39,11 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y +CONFIG_SPL_ETH=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot A53 SPL" CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 2b609ad9ac..e51a2511d0 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -38,10 +38,14 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y +CONFIG_SPL_ETH=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot R5 SPL" CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y @@ -63,6 +67,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y @@ -90,12 +95,15 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_SPL_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -108,6 +116,9 @@ CONFIG_SPL_PHY=y CONFIG_PHY_CADENCE_SIERRA=y CONFIG_PHY_CADENCE_TORRENT=y CONFIG_PHY_J721E_WIZ=y +CONFIG_PHY_TI_DP83867=y +CONFIG_DM_ETH=y +CONFIG_TI_AM65_CPSW_NUSS=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y @@ -125,6 +136,7 @@ CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y +CONFIG_SOC_TI=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y -- 2.34.1
[PATCH 3/4] configs: am64xx_evm: Increase BSS max size to 16K
With Ethboot support in SPL, network stack requires more BSS area, so increase BSS max size to 16K Signed-off-by: Vignesh Raghavendra --- include/configs/am64x_evm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 99624081c3..135cb3c2ee 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -33,7 +33,7 @@ * our memory footprint. The less we use for BSS the more we have available * for everything else. */ -#define CONFIG_SPL_BSS_MAX_SIZE0x1000 +#define CONFIG_SPL_BSS_MAX_SIZE0x4000 /* * Link BSS to be within SPL in a dedicated region located near the top of * the MCU SRAM, this way making it available also before relocation. Note -- 2.34.1
[PATCH 2/4] ARM: dts: k3-am642-sk: Disable cpsw_port1 in SPL
ROM supports cpsw_port2 for Ethernet boot and SPL stages continue to download images on the same port, therefore there is no need to enable cpsw_port1. Disable the same. Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-am642-r5-sk.dts | 11 --- arch/arm/dts/k3-am642-sk-u-boot.dtsi | 8 2 files changed, 19 deletions(-) diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index 3a17448ca0..7d1cb85615 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -231,23 +231,12 @@ &rgmii2_pins_default>; }; -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy0>; -}; - &cpsw_port2 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy1>; }; &cpsw3g_mdio { - cpsw3g_phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - }; - cpsw3g_phy1: ethernet-phy@1 { reg = <1>; ti,rx-internal-delay = ; diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi index 2f5cfaa04f..e5c26b8326 100644 --- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi @@ -117,10 +117,6 @@ u-boot,dm-spl; }; -&cpsw_port1 { - u-boot,dm-spl; -}; - &main_bcdma { u-boot,dm-spl; }; @@ -141,10 +137,6 @@ u-boot,dm-spl; }; -&cpsw3g_phy0 { - u-boot,dm-spl; -}; - &cpsw3g_phy1 { u-boot,dm-spl; }; -- 2.34.1
[PATCH 1/4] net: ti: am65-cpsw-nuss: Fix err msg for port bind failures
Replace error case print with meaning full message. Signed-off-by: Vignesh Raghavendra --- drivers/net/ti/am65-cpsw-nuss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 6ae69b51c7..454986ff15 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -752,7 +752,7 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", ofnode_get_name(node), node, &port_dev); if (ret) - printf("SCREEEM\n"); + dev_err(dev, "Failed to bind to %s node\n", ofnode_get_name(node)); } for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) { -- 2.34.1
[PATCH 0/4] ARM: ti: AM64x: Clean up Ethernet boot support on AM64x SK
This series is follow up to [1] First patch cleans up err msg in CPSW-NUSS driver Second patch disable cpsw_port1 at SPL stage Third patch increases SPL BSS size in anticipation of enabling network stack Last patch enables all configs needed to support ethboot [1] https://lore.kernel.org/u-boot/20211224072536.270251-1-vigne...@ti.com/T/#t Vignesh Raghavendra (4): net: ti: am65-cpsw-nuss: Fix err msg for port bind failures ARM: dts: k3-am642-sk: Disable cpsw_port1 in SPL configs: am64xx_evm: Increase BSS max size to 16K configs: am64x_evm_r5/a53_defconfig: Enable configs required for Ethboot arch/arm/dts/k3-am642-r5-sk.dts | 11 --- arch/arm/dts/k3-am642-sk-u-boot.dtsi | 8 configs/am64x_evm_a53_defconfig | 4 configs/am64x_evm_r5_defconfig | 12 drivers/net/ti/am65-cpsw-nuss.c | 2 +- include/configs/am64x_evm.h | 2 +- 6 files changed, 18 insertions(+), 21 deletions(-) -- 2.34.1
Re: [PATCH 6/8] configs: am64x_evm: set eth1 as boot interface
On 17/01/22 8:16 pm, Tom Rini wrote: > On Fri, Dec 24, 2021 at 12:55:34PM +0530, Vignesh Raghavendra wrote: > >> ROM supports boot from CPSW second port, therefore set eth1 boot >> interface >> >> Signed-off-by: Vignesh Raghavendra >> --- >> include/configs/am64x_evm.h | 5 - >> 1 file changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h >> index 99624081c3..cd4b658e5f 100644 >> --- a/include/configs/am64x_evm.h >> +++ b/include/configs/am64x_evm.h >> @@ -33,7 +33,7 @@ >> * our memory footprint. The less we use for BSS the more we have available >> * for everything else. >> */ >> -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 >> +#define CONFIG_SPL_BSS_MAX_SIZE 0xa000 >> /* >> * Link BSS to be within SPL in a dedicated region located near the top of >> * the MCU SRAM, this way making it available also before relocation. Note >> @@ -64,6 +64,7 @@ >> "if test $fdtfile = undefined; then " \ >> "echo WARNING: Could not determine device tree to use; >> fi; \0" \ >> "name_kern=Image\0" \ >> +"ethact=eth0\0" \ This is redundant, will drop. >> "console=ttyS2,115200n8\0" \ >> "args_all=setenv optargs earlycon=ns16550a,mmio32,0x0280 " \ >> "${mtdparts}\0" \ >> @@ -140,4 +141,6 @@ >> >> #define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 >> >> +#define CONFIG_SPL_ETH_DEVICE "eth1" >> + >> #endif /* __CONFIG_AM642_EVM_H */ > > What's going on exactly here? First, CONFIG_SPL_ETH_DEVICE needs to be > migrated to Kconfig now, if we're going to use it. But, it's used to > set "ethact", which wouldd normally be eth0, but you're setting it to > eth1 here and eth0 for U-Boot itself? Can you please explain the setup > here? Thanks! > ROM supports boot from cpsw_port2 (eth1) and not cpsw_port1 (eth0), hence I had to set CONFIG_SPL_ETH_DEVICE to eth1. Thinking a bit more, it does not make sense to enable both ports in SPL as only eth1 is used during ethboot. So CONFIG_SPL_ETH_DEVICE need not be touched if eth0 is disabled for SPL. Will update DT files accordingly. Regards Vignesh
Re: [PATCH 2/8] net: ti: am65-cpsw: Add support for multi port independent MAC mode
On 21/01/22 4:49 am, Tom Rini wrote: > On Fri, Jan 21, 2022 at 01:13:54AM +0200, Ramon Fried wrote: >> On Mon, Jan 17, 2022 at 8:37 PM Tom Rini wrote: >>> >>> On Fri, Dec 24, 2021 at 12:55:30PM +0530, Vignesh Raghavendra wrote: >>> >>>> On certain TI SoC, like AM64x there is a CPSW3G which supports 2 >>>> external independent MAC ports for single CPSW instance. >>>> It is not possible for Ethernet driver to register more than one port >>>> for given instance. >>>> >>>> This patch modifies top level CPSW NUSS as UCLASS_MISC and binds >>>> UCLASS_ETH to individual ports so as to support bring up more than one >>>> Ethernet interface in U-Boot. >>>> >>>> Note that there is no isolation in the since, CPSW NUSS is in promisc >>>> mode and forwards all packets to host. >>>> >>>> Since top level driver is now UCLASS_MISC, board files would need to >>>> instantiate this driver explicitly. >>>> >>>> Signed-off-by: Vignesh Raghavendra >>> >>> Applied to u-boot/master, thanks! >> why ? comments were not addressed. > > I missed that you had comments, sorry. Shall I revert this one for now? > Could you please hold off revert? Will send follow up patch fixing stray printf() pointed out by Ramon Apologies for not noticing comment beforehand! Regards Vignesh
Re: [PATCH 8/8] configs: am64x_evm_r5/a53_defconfig: Enable configs required for Ethboot
On 17/01/22 8:47 am, Tom Rini wrote: > On Fri, Dec 24, 2021 at 12:55:36PM +0530, Vignesh Raghavendra wrote: > >> Enable config options needed to support Ethernet boot on AM64x SK. >> >> Signed-off-by: Vignesh Raghavendra > > This leads to size overflow on r5. > Hmm, I don't see size limitations locally. $ size spl/u-boot-spl textdata bss dec hex filename 230470 10401 12992 253863 3dfa7 spl/u-boot-spl vs limit declared in configs/am64x_evm_r5_defconfig: CONFIG_SPL_SIZE_LIMIT=0x19 I don't expect size overflow? Regards Vignesh
Re: [PATCH 2/8] net: ti: am65-cpsw: Add support for multi port independent MAC mode
On 30/12/21 1:01 am, Ramon Fried wrote: > On Fri, Dec 24, 2021 at 9:25 AM Vignesh Raghavendra wrote: >> >> On certain TI SoC, like AM64x there is a CPSW3G which supports 2 >> external independent MAC ports for single CPSW instance. >> It is not possible for Ethernet driver to register more than one port >> for given instance. >> >> This patch modifies top level CPSW NUSS as UCLASS_MISC and binds >> UCLASS_ETH to individual ports so as to support bring up more than one >> Ethernet interface in U-Boot. >> >> Note that there is no isolation in the since, CPSW NUSS is in promisc >> mode and forwards all packets to host. > So both ports are working in parallel, how do I choose from which port to > exit ? One would have to chose active port with ethact. Packet from non active port is dropped by the driver. >> >> Since top level driver is now UCLASS_MISC, board files would need to >> instantiate this driver explicitly. >> >> Signed-off-by: Vignesh Raghavendra >> --- [...] >> -static int am65_cpsw_probe_cpsw(struct udevice *dev) >> +static int am65_cpsw_port_probe(struct udevice *dev) >> { >> struct am65_cpsw_priv *priv = dev_get_priv(dev); >> struct eth_pdata *pdata = dev_get_plat(dev); >> struct am65_cpsw_common *cpsw_common; >> - ofnode ports_np, node; >> - int ret, i; >> + char portname[15]; >> + int ret; >> >> priv->dev = dev; >> >> - cpsw_common = calloc(1, sizeof(*priv->cpsw_common)); >> - if (!cpsw_common) >> - return -ENOMEM; >> + cpsw_common = dev_get_priv(dev->parent); >> priv->cpsw_common = cpsw_common; >> >> + sprintf(portname, "%s%s", dev->parent->name, dev->name); >> + device_set_name(dev, portname); >> + >> + ret = am65_cpsw_ofdata_parse_phy(dev); >> + if (ret) >> + goto out; >> + >> + am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id); >> + >> + ret = am65_cpsw_mdio_init(dev); >> + if (ret) >> + goto out; >> + >> + ret = am65_cpsw_phy_init(dev); >> + if (ret) >> + goto out; >> +out: >> + return ret; >> +} >> + >> +static int am65_cpsw_probe_nuss(struct udevice *dev) >> +{ >> + struct am65_cpsw_common *cpsw_common = dev_get_priv(dev); >> + ofnode ports_np, node; >> + int ret, i; >> + struct udevice *port_dev; >> + >> cpsw_common->dev = dev; >> cpsw_common->ss_base = dev_read_addr(dev); >> if (cpsw_common->ss_base == FDT_ADDR_T_NONE) >> @@ -723,10 +750,9 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev) >> if (disabled) >> continue; >> >> - priv->port_id = port_id; >> - ret = am65_cpsw_ofdata_parse_phy(dev, node); >> + ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", >> ofnode_get_name(node), node, &port_dev); >> if (ret) >> - goto out; >> + printf("SCREEEM\n"); > Please handle reasonably. Oops, sorry, I missed to clean this up before posting... Since the patch is merged, will send a followup patch addressing the same. [...] Regards Vignesh
[PATCH 8/8] configs: am64x_evm_r5/a53_defconfig: Enable configs required for Ethboot
Enable config options needed to support Ethernet boot on AM64x SK. Signed-off-by: Vignesh Raghavendra --- configs/am64x_evm_a53_defconfig | 4 configs/am64x_evm_r5_defconfig | 12 2 files changed, 16 insertions(+) diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index aafbb410b6..b8add31a30 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y @@ -36,8 +37,11 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y +CONFIG_SPL_ETH=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot A53 SPL" CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index f564fa064e..01c1bc02ae 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -36,10 +36,14 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y +CONFIG_SPL_ETH=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot R5 SPL" CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y @@ -61,6 +65,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y @@ -84,12 +89,15 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_SPL_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -97,6 +105,9 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_TI_DP83867=y +CONFIG_DM_ETH=y +CONFIG_TI_AM65_CPSW_NUSS=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y @@ -114,6 +125,7 @@ CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y +CONFIG_SOC_TI=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y -- 2.34.1
[PATCH 7/8] ARM: dts: K3-am642-r5-sk: Enable Second CPSW port in R5/A53 SPL
Enable Second Ethernet port on which ROM support Ethboot. Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-am642-r5-sk.dts | 74 arch/arm/dts/k3-am642-sk-u-boot.dtsi | 40 ++- 2 files changed, 113 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index 79eff8259f..b4a0438449 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include +#include #include "k3-am642.dtsi" #include "k3-am64-sk-lp4-1333MTs.dtsi" #include "k3-am64-ddr.dtsi" @@ -107,6 +109,47 @@ AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0)/* (C20) MMC1_SDWP */ >; }; + + mdio1_pins_default: mdio1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ + AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ + >; + }; + + rgmii1_pins_default: rgmii1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ + AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ + AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */ + AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */ + AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */ + AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */ + AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ + AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ + AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ + AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ + AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ + AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ + >; + }; + + rgmii2_pins_default: rgmii2-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; }; &dmsc { @@ -142,4 +185,35 @@ pinctrl-0 = <&main_mmc1_pins_default>; }; +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default +&rgmii1_pins_default +&rgmii2_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + #include "k3-am642-sk-u-boot.dtsi" diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi index efbcfb36e9..ade040e601 100644 --- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi @@ -100,13 +100,51 @@ <0x0 0x43000200 0x0 0x8>; reg-names = "cpsw_nuss&
[PATCH 6/8] configs: am64x_evm: set eth1 as boot interface
ROM supports boot from CPSW second port, therefore set eth1 boot interface Signed-off-by: Vignesh Raghavendra --- include/configs/am64x_evm.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 99624081c3..cd4b658e5f 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -33,7 +33,7 @@ * our memory footprint. The less we use for BSS the more we have available * for everything else. */ -#define CONFIG_SPL_BSS_MAX_SIZE0x1000 +#define CONFIG_SPL_BSS_MAX_SIZE0xa000 /* * Link BSS to be within SPL in a dedicated region located near the top of * the MCU SRAM, this way making it available also before relocation. Note @@ -64,6 +64,7 @@ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "name_kern=Image\0" \ + "ethact=eth0\0" \ "console=ttyS2,115200n8\0" \ "args_all=setenv optargs earlycon=ns16550a,mmio32,0x0280 " \ "${mtdparts}\0" \ @@ -140,4 +141,6 @@ #define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_ETH_DEVICE "eth1" + #endif /* __CONFIG_AM642_EVM_H */ -- 2.34.1
[PATCH 5/8] mach-k3: am64_spl: Alias Ethernet RGMII boot to CPGMAC
This is required to enables spl_net boot on AM64x Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/include/mach/am64_spl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-k3/include/mach/am64_spl.h b/arch/arm/mach-k3/include/mach/am64_spl.h index 607b09c2e5..b4f396b2c0 100644 --- a/arch/arm/mach-k3/include/mach/am64_spl.h +++ b/arch/arm/mach-k3/include/mach/am64_spl.h @@ -12,6 +12,7 @@ #define BOOT_DEVICE_QSPI 0x02 #define BOOT_DEVICE_SPI0x03 #define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_CPGMAC 0x04 #define BOOT_DEVICE_ETHERNET_RGMII 0x04 #define BOOT_DEVICE_ETHERNET_RMII 0x05 #define BOOT_DEVICE_I2C0x06 -- 2.34.1
[PATCH 4/8] mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL
In order to support Ethernet boot on AM64x, probe AM65 CPSW NUSS. Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/am642_init.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 533905daeb..184f1a2761 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -196,6 +196,13 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif + if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) && + spl_boot_device() == BOOT_DEVICE_ETHERNET) { + struct udevice *cpswdev; + + if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), &cpswdev)) + printf("Failed to probe am65_cpsw_nuss driver\n"); + } } u32 spl_mmc_boot_mode(const u32 boot_device) -- 2.34.1
[PATCH 3/8] board: ti: am64x: Init DRAM size in R5/A53 SPL
Call dram_init_banksize() from spl_board_init() otherwise TFTP download fails due to lmb_get_free_size() not able to find unreserved region due to lack of DRAM size info. Required to support Ethernet boot on AM64x. Signed-off-by: Vignesh Raghavendra --- board/ti/am64x/evm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index 1a9f69c6cf..8373c768f1 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -196,5 +196,8 @@ void spl_board_init(void) val = readl(CTRLMMR_USB0_PHY_CTRL); val &= ~(CORE_VOLTAGE); writel(val, CTRLMMR_USB0_PHY_CTRL); + + /* Init DRAM size for R5/A53 SPL */ + dram_init_banksize(); } #endif -- 2.34.1
[PATCH 2/8] net: ti: am65-cpsw: Add support for multi port independent MAC mode
On certain TI SoC, like AM64x there is a CPSW3G which supports 2 external independent MAC ports for single CPSW instance. It is not possible for Ethernet driver to register more than one port for given instance. This patch modifies top level CPSW NUSS as UCLASS_MISC and binds UCLASS_ETH to individual ports so as to support bring up more than one Ethernet interface in U-Boot. Note that there is no isolation in the since, CPSW NUSS is in promisc mode and forwards all packets to host. Since top level driver is now UCLASS_MISC, board files would need to instantiate this driver explicitly. Signed-off-by: Vignesh Raghavendra --- drivers/net/ti/Kconfig | 2 + drivers/net/ti/am65-cpsw-nuss.c | 77 + 2 files changed, 52 insertions(+), 27 deletions(-) diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index f2dbbd0128..59c96d862d 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -28,6 +28,8 @@ config DRIVER_TI_KEYSTONE_NET config TI_AM65_CPSW_NUSS bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver" depends on ARCH_K3 + imply MISC_INIT_R + imply MISC select PHYLIB help This driver supports TI K3 MCU CPSW Nuss Ethernet controller diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 3ab6a30828..6ae69b51c7 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -597,7 +597,7 @@ static int am65_cpsw_phy_init(struct udevice *dev) return ret; } -static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np) +static int am65_cpsw_ofdata_parse_phy(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct am65_cpsw_priv *priv = dev_get_priv(dev); @@ -605,7 +605,9 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np) const char *phy_mode; int ret = 0; - phy_mode = ofnode_read_string(port_np, "phy-mode"); + dev_read_u32(dev, "reg", &priv->port_id); + + phy_mode = dev_read_string(dev, "phy-mode"); if (phy_mode) { pdata->phy_interface = phy_get_interface_by_name(phy_mode); @@ -617,13 +619,13 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np) } } - ofnode_read_u32(port_np, "max-speed", (u32 *)&pdata->max_speed); + dev_read_u32(dev, "max-speed", (u32 *)&pdata->max_speed); if (pdata->max_speed) dev_err(dev, "Port %u speed froced to %uMbit\n", priv->port_id, pdata->max_speed); priv->has_phy = true; - ret = ofnode_parse_phandle_with_args(port_np, "phy-handle", + ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle", NULL, 0, 0, &out_args); if (ret) { dev_err(dev, "can't parse phy-handle port %u (%d)\n", @@ -646,21 +648,46 @@ out: return ret; } -static int am65_cpsw_probe_cpsw(struct udevice *dev) +static int am65_cpsw_port_probe(struct udevice *dev) { struct am65_cpsw_priv *priv = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); struct am65_cpsw_common *cpsw_common; - ofnode ports_np, node; - int ret, i; + char portname[15]; + int ret; priv->dev = dev; - cpsw_common = calloc(1, sizeof(*priv->cpsw_common)); - if (!cpsw_common) - return -ENOMEM; + cpsw_common = dev_get_priv(dev->parent); priv->cpsw_common = cpsw_common; + sprintf(portname, "%s%s", dev->parent->name, dev->name); + device_set_name(dev, portname); + + ret = am65_cpsw_ofdata_parse_phy(dev); + if (ret) + goto out; + + am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id); + + ret = am65_cpsw_mdio_init(dev); + if (ret) + goto out; + + ret = am65_cpsw_phy_init(dev); + if (ret) + goto out; +out: + return ret; +} + +static int am65_cpsw_probe_nuss(struct udevice *dev) +{ + struct am65_cpsw_common *cpsw_common = dev_get_priv(dev); + ofnode ports_np, node; + int ret, i; + struct udevice *port_dev; + cpsw_common->dev = dev; cpsw_common->ss_base = dev_read_addr(dev); if (cpsw_common->ss_base == FDT_ADDR_T_NONE) @@ -723,10 +750,9 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev) if (disabled) continue; - priv->port_id = port_id; - ret = am65_cpsw_ofdata_parse_phy(dev, node); + ret = device_bind_driver_to_node(dev, "am
[PATCH 1/8] mach-k3: common: Instantiate AM65 CPSW NUSS wrapper
Probe toplevel AM65 CPSW NUSS driver from misc_init_r() when driver is enabled. Since driver is modeled as UCLASS_MISC, we need to explicitly probe the driver. Use common misc_init_r() that entire K3 family of SoCs. Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/common.c | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 2666cd2d7b..39d00270b7 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -549,3 +549,19 @@ void spl_board_prepare_for_linux(void) dcache_disable(); } #endif + +int misc_init_r(void) +{ + if (IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(am65_cpsw_nuss), + &dev); + if (ret) + printf("Failed to probe am65_cpsw_nuss driver\n"); + } + + return 0; +} -- 2.34.1
[PATCH 0/8] ARM: ti: AM64x: Add Ethernet boot support on AM64x SK
This series enables ethernet boot support on AM64x SK. AM64x SoC has CPSW3g IP that supports 2 ext Eth port. ROM supports booting from 2nd port. But currently am65-cpsw-nuss only supports single port (1st port). So the first two patches modify driver to support more than 1 ext port. This is done by breaking up am65-cpsw-nuss into UCLASS_MISC for toplevel NUSS driver and UCLASS_ETH for each of individual ports. Next 4 patches add mach-k3 and board level changes to enable Ethernet and TFTP to work at SPL. Last two patches add dts and config changes need to for Ethernet boot. Tested on AM64x SK with RGMII 1G bootmode at 1G. https://controlc.com/90d555ee Sanity tested TFTP at U-Boot prompt on AM65x and J721e. Vignesh Raghavendra (8): mach-k3: common: Instantiate AM65 CPSW NUSS wrapper net: ti: am65-cpsw: Add support for multi port independent MAC mode board: ti: am64x: Init DRAM size in R5/A53 SPL mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL mach-k3: am64_spl: Alias Ethernet RGMII boot to CPGMAC configs: am64x_evm: set eth1 as boot interface ARM: dts: K3-am642-r5-sk: Enable Second CPSW port in R5/A53 SPL configs: am64x_evm_r5/a53_defconfig: Enable configs required for Ethboot arch/arm/dts/k3-am642-r5-sk.dts | 74 +++ arch/arm/dts/k3-am642-sk-u-boot.dtsi | 40 +++- arch/arm/mach-k3/am642_init.c| 7 +++ arch/arm/mach-k3/common.c| 16 + arch/arm/mach-k3/include/mach/am64_spl.h | 1 + board/ti/am64x/evm.c | 3 + configs/am64x_evm_a53_defconfig | 4 ++ configs/am64x_evm_r5_defconfig | 12 drivers/net/ti/Kconfig | 2 + drivers/net/ti/am65-cpsw-nuss.c | 77 +++- include/configs/am64x_evm.h | 5 +- 11 files changed, 212 insertions(+), 29 deletions(-) -- 2.34.1
[PATCH] dma: ti: k3-udma: Fix rflow reservation for PKTDMA
Driver has a bug in that it uses rflow_in_use bitmap when setting up free rflow range from TISCI but use rflow_map for reservation in __udma_reserve_rflow() Fix this by dropping rflow_in_use bitmap array and use rflow_map for PKTDMA. BCDMA does not need rflow_in_use either. This fixes CPSW3g not able to get DMA channels at R5 SPL on AM64x Signed-off-by: Vignesh Raghavendra --- drivers/dma/ti/k3-udma.c | 21 - 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 411edef3a7..86603d43f1 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -165,7 +165,6 @@ struct udma_dev { unsigned long *rchan_map; unsigned long *rflow_map; unsigned long *rflow_map_reserved; - unsigned long *rflow_in_use; unsigned long *tflow_map; struct udma_bchan *bchans; @@ -1448,15 +1447,11 @@ static int bcdma_setup_resources(struct udma_dev *ud) sizeof(unsigned long), GFP_KERNEL); ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), GFP_KERNEL); - /* BCDMA do not really have flows, but the driver expect it */ - ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt), - sizeof(unsigned long), - GFP_KERNEL); ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows), GFP_KERNEL); if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map || - !ud->rflow_in_use || !ud->bchans || !ud->tchans || !ud->rchans || + !ud->bchans || !ud->tchans || !ud->rchans || !ud->rflows) return -ENOMEM; @@ -1535,16 +1530,16 @@ static int pktdma_setup_resources(struct udma_dev *ud) sizeof(unsigned long), GFP_KERNEL); ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), GFP_KERNEL); - ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), - sizeof(unsigned long), - GFP_KERNEL); + ud->rflow_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), +sizeof(unsigned long), +GFP_KERNEL); ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), GFP_KERNEL); ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt), sizeof(unsigned long), GFP_KERNEL); if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans || - !ud->rchans || !ud->rflows || !ud->rflow_in_use) + !ud->rchans || !ud->rflows || !ud->rflow_map) return -ENOMEM; /* Get resource ranges from tisci */ @@ -1592,12 +1587,12 @@ static int pktdma_setup_resources(struct udma_dev *ud) rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; if (IS_ERR(rm_res)) { /* all rflows are assigned exclusively to Linux */ - bitmap_zero(ud->rflow_in_use, ud->rflow_cnt); + bitmap_zero(ud->rflow_map, ud->rflow_cnt); } else { - bitmap_fill(ud->rflow_in_use, ud->rflow_cnt); + bitmap_fill(ud->rflow_map, ud->rflow_cnt); for (i = 0; i < rm_res->sets; i++) { rm_desc = &rm_res->desc[i]; - bitmap_clear(ud->rflow_in_use, rm_desc->start, + bitmap_clear(ud->rflow_map, rm_desc->start, rm_desc->num); dev_dbg(dev, "ti-sci-res: rflow: %d:%d\n", rm_desc->start, rm_desc->num); -- 2.34.1
[PATCH] ARM: mach-k3: sysfw-loader: Copy sysfw.itb to OCRAM in OSPI/SPI bootmode
In case of xSPI bootmode OSPI flash is in DDR mode and needs to be accessed in multiple of 16bit accesses Hence we cannot parse sysfw.itb FIT image directly on OSPI flash via MMIO window. So, copy the image to internal on-chip RAM before parsing the image. Moreover, board cfg data maybe modified by ROM/TIFS in case of HS platform and thus cannot reside in OSPI/xSPI and needs to be copied over to internal OCRAM. This unblocks OSPI/xSPI boot on HS platforms Signed-off-by: Vignesh Raghavendra Reviewed-by: Dave Gerlach Tested-by: Keerthy --- arch/arm/mach-k3/sysfw-loader.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index 9ce576186c..5e48c36ccd 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -22,6 +22,7 @@ #include #include +#include #include #include "common.h" @@ -335,6 +336,14 @@ static void *k3_sysfw_get_spi_addr(void) return (void *)(addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS); } + +static void k3_sysfw_spi_copy(u32 *dst, u32 *src, size_t len) +{ + size_t i; + + for (i = 0; i < len / sizeof(*dst); i++) + *dst++ = *src++; +} #endif void k3_sysfw_loader(bool rom_loaded_sysfw, @@ -344,6 +353,9 @@ void k3_sysfw_loader(bool rom_loaded_sysfw, struct spl_image_info spl_image = { 0 }; struct spl_boot_device bootdev = { 0 }; struct ti_sci_handle *ti_sci; +#if CONFIG_IS_ENABLED(SPI_LOAD) + void *sysfw_spi_base; +#endif int ret = 0; if (rom_loaded_sysfw) { @@ -394,9 +406,11 @@ void k3_sysfw_loader(bool rom_loaded_sysfw, #endif #if CONFIG_IS_ENABLED(SPI_LOAD) case BOOT_DEVICE_SPI: - sysfw_load_address = k3_sysfw_get_spi_addr(); - if (!sysfw_load_address) + sysfw_spi_base = k3_sysfw_get_spi_addr(); + if (!sysfw_spi_base) ret = -ENODEV; + k3_sysfw_spi_copy(sysfw_load_address, sysfw_spi_base, + CONFIG_K3_SYSFW_IMAGE_SIZE_MAX); break; #endif #if CONFIG_IS_ENABLED(YMODEM_SUPPORT) -- 2.34.1
[PATCH -next] ARM: dts: k3-j7200-common-proc-board-u-boot.dtsi: Fix dtc warnings
Fix following dtc warning by explicitly setting up #size-cells and #address-cells when overriding node in -u-boot.dtsi arch/arm/dts/k3-j7200-common-proc-board.dtb: Warning (reg_format): /bus@10/bus@2838/mcu-navss/ringacc@2b80:reg: property has invalid length (80 bytes) (#address-cells == 2, #size-cells == 1) Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 41ce9fcb59..786cc48050 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -43,6 +43,8 @@ mcu-navss{ u-boot,dm-spl; + #address-cells = <2>; + #size-cells = <2>; ringacc@2b80 { reg = <0x0 0x2b80 0x0 0x40>, -- 2.32.0
Re: [GIT PULL v2] TI changes for v2021.10 next
On 6/14/21 1:35 PM, Tero Kristo wrote: > On 13/06/2021 19:49, Tom Rini wrote: >> On Fri, Jun 11, 2021 at 09:40:14PM +0530, Lokesh Vutla wrote: >> >>> Hi Tom, >>> Please find the PR for master branch targeted for v2021.10-next >>> branch >>> with checkpatch warnings fixed. Details about the PR are updated in >>> the tag message. >>> >>> Gitlab CI report: >>> https://source.denx.de/u-boot/custodians/u-boot-ti/-/pipelines/7817 >>> >>> The following changes since commit >>> e8f720ee1707b43a0e14ade87b40a1f84baeb2f3: >>> >>> Merge branch '2021-06-08-kconfig-migrations' into next (2021-06-09 >>> 08:19:13 -0400) >>> >>> are available in the Git repository at: >>> >>> https://source.denx.de/u-boot/custodians/u-boot-ti.git >>> tags/ti-v2021.10-next-v2 >>> >>> for you to fetch changes up to 5abb694d6016eaf497c3d9a3ec79382e217e7508: >>> >>> dma: ti: k3-udma: Add support for native configuration of >>> chan/flow (2021-06-11 19:18:52 +0530) >>> >> >> I've applied this to u-boot/next now. But please follow up to fix: >> w+(j7200_evm_a72 j721e_evm_a72 j721e_hs_evm_a72 j7200_evm_r5 >> j721e_evm_r5 j721e_hs_evm_r5) >> arch/arm/dts/k3-j7200-common-proc-board.dtb: Warning (reg_format): >> /bus@10/bus@2838/mcu-navss/ringacc@2b80:reg: property has >> invalid length (80 bytes) (#address-cells == 2, #size-cells == 1) >> >> and all of the other dtc warnings. Thanks! >> > > Thanks a lot Tom! > > I think those DTC warnings are coming out of the DMA support series from > Vignesh. Vignesh, any comments? > I had provided a diff to squash at [1]. Looks like that was not picked up. Will send a follow up patch. [1] https://lore.kernel.org/u-boot/c8a8bad1-cd13-344e-5701-02748bb00...@ti.com/
Re: [PATCH v2 0/7] J72xx: R5 SPL DMA support post HSM Rearch
On 6/8/21 12:35 PM, Lokesh Vutla wrote: > > > On 07/06/21 7:47 pm, Vignesh Raghavendra wrote: >> This series add DMA support for R5 SPL on J721e/J7200 SoCs post HSM >> Rearch. >> >> Depends on Tero's base HSM rearch support series. >> >> v2: >> Use IS_ENABLED() consistentially instead of #ifdef >> Reword commit msg for 5/7 as suggested by Lokesh >> Rebase on Tero's latest HSM base series. > > I see the folloiwing build warnings with this series: > > arch/arm/dts/k3-j7200-common-proc-board.dtb: Warning (reg_format): > /bus@10/bus@2838/mcu-navss/ringacc@2b80:reg: property has invalid > length (80 bytes) (#address-cells == 2, #size-cells == 1) > arch/arm/dts/k3-j7200-common-proc-board.dtb: Warning > (avoid_default_addr_size): > /bus@10/bus@2838/mcu-navss/ringacc@2b80: Relying on default > #address-cells value > arch/arm/dts/k3-j7200-common-proc-board.dtb: Warning > (avoid_default_addr_size): > /bus@10/bus@2838/mcu-navss/ringacc@2b80: Relying on default > #size-cells value > arch/arm/dts/k3-j7200-common-proc-board.dtb: Warning > (avoid_default_addr_size): > /bus@10/bus@2838/mcu-navss/dma-controller@285c: Relying on default > #address-cells value > arch/arm/dts/k3-j7200-common-proc-board.dtb: Warning > (avoid_default_addr_size): > /bus@10/bus@2838/mcu-navss/dma-controller@285c: Relying on default > #size-cells value > arch/arm/dts/k3-j7200-r5-common-proc-board.dtb: Warning (reg_format): > /bus@10/bus@2838/mcu-navss/ringacc@2b80:reg: property has invalid > length (80 bytes) (#address-cells == 2, #size-cells == 1) > arch/arm/dts/k3-j7200-r5-common-proc-board.dtb: Warning > (avoid_default_addr_size): > /bus@10/bus@2838/mcu-navss/ringacc@2b80: > Relying on default #address-cells value > arch/arm/dts/k3-j7200-r5-common-proc-board.dtb: Warning > (avoid_default_addr_size): > /bus@10/bus@2838/mcu-navss/ringacc@2b80: > Relying on default #size-cells value > arch/arm/dts/k3-j7200-r5-common-proc-board.dtb: Warning > (avoid_default_addr_size): > /bus@10/bus@2838/mcu-navss/dma-controller@285c: Relying on default > #address-cells value > arch/arm/dts/k3-j7200-r5-common-proc-board.dtb: Warning > (avoid_default_addr_size): > /bus@10/bus@2838/mcu-navss/dma-controller@285c: Relying on default > #size-cells value > > Can you fix it or send me fix, Ill can squash? Hmm, weird. I had to fix #address-cells and #size-cells in k3-j7200-common-proc-board-u-boot.dtsi but they same does not seem to be needed for j721e. Anyway below diff fixes the warning Could you squash to 5/7? diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 41ce9fcb59..786cc48050 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -43,6 +43,8 @@ mcu-navss{ u-boot,dm-spl; + #address-cells = <2>; + #size-cells = <2>; ringacc@2b80 { reg = <0x0 0x2b80 0x0 0x40>, Regards Vignesh
[PATCH v2 7/7] dma: ti: k3-udma: Add support for native configuration of chan/flow
In absence of Device Manager (DM) services such as at R5 SPL stage, driver will have to natively setup TCHAN/RCHAN/RFLOW cfg registers. Add support for the same. Note that we still need to send chan/flow cfg message to TIFS via TISCI client driver in order to open up firewalls around chan/flow but setting up of cfg registers is handled locally. U-Boot specific code is in a separate file included in main driver so as to maintain similarity with kernel driver in order to ease porting of code in future. Signed-off-by: Vignesh Raghavendra --- drivers/dma/ti/k3-udma-u-boot.c | 177 drivers/dma/ti/k3-udma.c| 42 +++- 2 files changed, 215 insertions(+), 4 deletions(-) create mode 100644 drivers/dma/ti/k3-udma-u-boot.c diff --git a/drivers/dma/ti/k3-udma-u-boot.c b/drivers/dma/ti/k3-udma-u-boot.c new file mode 100644 index 00..3e04f551e2 --- /dev/null +++ b/drivers/dma/ti/k3-udma-u-boot.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com + */ + +#define UDMA_RCHAN_RFLOW_RNG_FLOWID_CNT_SHIFT (16) + +/* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */ +#define UDMA_RFLOW_SRCTAG_NONE 0 +#define UDMA_RFLOW_SRCTAG_CFG_TAG 1 +#define UDMA_RFLOW_SRCTAG_FLOW_ID 2 +#define UDMA_RFLOW_SRCTAG_SRC_TAG 4 + +#define UDMA_RFLOW_DSTTAG_NONE 0 +#define UDMA_RFLOW_DSTTAG_CFG_TAG 1 +#define UDMA_RFLOW_DSTTAG_FLOW_ID 2 +#define UDMA_RFLOW_DSTTAG_DST_TAG_LO 4 +#define UDMA_RFLOW_DSTTAG_DST_TAG_HI 5 + +#define UDMA_RFLOW_RFC_DEFAULT \ + ((UDMA_RFLOW_SRCTAG_NONE << UDMA_RFLOW_RFC_SRC_TAG_HI_SEL_SHIFT) | \ +(UDMA_RFLOW_SRCTAG_SRC_TAG << UDMA_RFLOW_RFC_SRC_TAG_LO_SEL_SHIFT) | \ +(UDMA_RFLOW_DSTTAG_DST_TAG_HI << UDMA_RFLOW_RFC_DST_TAG_HI_SEL_SHIFT) | \ +(UDMA_RFLOW_DSTTAG_DST_TAG_LO << UDMA_RFLOW_RFC_DST_TAG_LO_SE_SHIFT)) + +#define UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT (16) + +/* TCHAN */ +static inline u32 udma_tchan_read(struct udma_tchan *tchan, int reg) +{ + if (!tchan) + return 0; + return udma_read(tchan->reg_chan, reg); +} + +static inline void udma_tchan_write(struct udma_tchan *tchan, int reg, u32 val) +{ + if (!tchan) + return; + udma_write(tchan->reg_chan, reg, val); +} + +static inline void udma_tchan_update_bits(struct udma_tchan *tchan, int reg, + u32 mask, u32 val) +{ + if (!tchan) + return; + udma_update_bits(tchan->reg_chan, reg, mask, val); +} + +/* RCHAN */ +static inline u32 udma_rchan_read(struct udma_rchan *rchan, int reg) +{ + if (!rchan) + return 0; + return udma_read(rchan->reg_chan, reg); +} + +static inline void udma_rchan_write(struct udma_rchan *rchan, int reg, u32 val) +{ + if (!rchan) + return; + udma_write(rchan->reg_chan, reg, val); +} + +static inline void udma_rchan_update_bits(struct udma_rchan *rchan, int reg, + u32 mask, u32 val) +{ + if (!rchan) + return; + udma_update_bits(rchan->reg_chan, reg, mask, val); +} + +/* RFLOW */ +static inline u32 udma_rflow_read(struct udma_rflow *rflow, int reg) +{ + if (!rflow) + return 0; + return udma_read(rflow->reg_rflow, reg); +} + +static inline void udma_rflow_write(struct udma_rflow *rflow, int reg, u32 val) +{ + if (!rflow) + return; + udma_write(rflow->reg_rflow, reg, val); +} + +static inline void udma_rflow_update_bits(struct udma_rflow *rflow, int reg, + u32 mask, u32 val) +{ + if (!rflow) + return; + udma_update_bits(rflow->reg_rflow, reg, mask, val); +} + +static void udma_alloc_tchan_raw(struct udma_chan *uc) +{ + u32 mode, fetch_size; + + if (uc->config.pkt_mode) + mode = UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR; + else + mode = UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR; + + udma_tchan_update_bits(uc->tchan, UDMA_TCHAN_TCFG_REG, + UDMA_CHAN_CFG_CHAN_TYPE_MASK, mode); + + if (uc->config.dir == DMA_MEM_TO_MEM) + fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2; + else + fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib, + uc->config.psd_size, 0) >> 2; + + udma_tchan_update_bits(uc->tchan, UDMA_TCHAN_TCFG_REG, + UDMA_CHAN_CFG_FETCH_SIZE_MASK, fetch_size); + udma_tchan_write(uc->tchan, UDMA_TCHAN_TCQ_REG, +k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring)); +} + +static void udma_alloc_rchan_raw(struct udma_chan *uc) +{ + struct udma_dev
[PATCH v2 6/7] soc: ti: k3-navss-ringacc: Add support for native configuration of rings
In absence of Device Manager (DM) services such as at R5 SPL stage, driver will have to natively setup Ring Cfg registers. Add support for the same. Note that we still need to send RING_CFG message to TIFS via TISCI client driver in order to open up firewalls around Rings. U-Boot specific code is in a separate file included in main driver so as to maintain similarity with kernel driver in order to ease porting of code in future. Signed-off-by: Vignesh Raghavendra --- drivers/soc/ti/k3-navss-ringacc-u-boot.c | 61 drivers/soc/ti/k3-navss-ringacc.c| 36 -- 2 files changed, 94 insertions(+), 3 deletions(-) create mode 100644 drivers/soc/ti/k3-navss-ringacc-u-boot.c diff --git a/drivers/soc/ti/k3-navss-ringacc-u-boot.c b/drivers/soc/ti/k3-navss-ringacc-u-boot.c new file mode 100644 index 00..f958239c2a --- /dev/null +++ b/drivers/soc/ti/k3-navss-ringacc-u-boot.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot specific helpers for TI K3 AM65x NAVSS Ring accelerator + * Manager (RA) subsystem driver + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com + */ + +struct k3_nav_ring_cfg_regs { + u32 resv_64[16]; + u32 ba_lo; /* Ring Base Address Lo Register */ + u32 ba_hi; /* Ring Base Address Hi Register */ + u32 size; /* Ring Size Register */ + u32 event; /* Ring Event Register */ + u32 orderid;/* Ring OrderID Register */ +}; + +#define KNAV_RINGACC_CFG_REGS_STEP 0x100 + +#define KNAV_RINGACC_CFG_RING_BA_HI_ADDR_HI_MASK GENMASK(15, 0) + +#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK GENMASK(31, 30) +#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT (30) + +#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_MASK GENMASK(26, 24) +#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT(24) + +static void k3_ringacc_ring_reset_raw(struct k3_nav_ring *ring) +{ + writel(0, &ring->cfg->size); +} + +static void k3_ringacc_ring_reconfig_qmode_raw(struct k3_nav_ring *ring, enum k3_nav_ring_mode mode) +{ + u32 val; + + val = readl(&ring->cfg->size); + val &= KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK; + val |= mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT; + writel(val, &ring->cfg->size); +} + +static void k3_ringacc_ring_free_raw(struct k3_nav_ring *ring) +{ + writel(0, &ring->cfg->ba_hi); + writel(0, &ring->cfg->ba_lo); + writel(0, &ring->cfg->size); +} + +static void k3_nav_ringacc_ring_cfg_raw(struct k3_nav_ring *ring) +{ + u32 val; + + writel(lower_32_bits(ring->ring_mem_dma), &ring->cfg->ba_lo); + writel(upper_32_bits(ring->ring_mem_dma), &ring->cfg->ba_hi); + + val = ring->mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT | + ring->elm_size << KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT | + ring->size; + writel(val, &ring->cfg->size); +} diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c index b5a5c9da98..f110d78ce1 100644 --- a/drivers/soc/ti/k3-navss-ringacc.c +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -124,6 +124,7 @@ struct k3_nav_ring_state { /** * struct k3_nav_ring - RA Ring descriptor * + * @cfg - Ring configuration registers * @rt - Ring control/status registers * @fifos - Ring queues registers * @ring_mem_dma - Ring buffer dma address @@ -138,6 +139,7 @@ struct k3_nav_ring_state { * @use_count - Use count for shared rings */ struct k3_nav_ring { + struct k3_nav_ring_cfg_regs __iomem *cfg; struct k3_nav_ring_rt_regs __iomem *rt; struct k3_nav_ring_fifo_regs __iomem *fifos; dma_addr_t ring_mem_dma; @@ -195,6 +197,8 @@ struct k3_nav_ringacc { bool dual_ring; }; +#include "k3-navss-ringacc-u-boot.c" + static int k3_nav_ringacc_ring_read_occ(struct k3_nav_ring *ring) { return readl(&ring->rt->occ) & KNAV_RINGACC_RT_OCC_MASK; @@ -330,6 +334,9 @@ static void k3_ringacc_ring_reset_sci(struct k3_nav_ring *ring) struct k3_nav_ringacc *ringacc = ring->parent; int ret; + if (IS_ENABLED(CONFIG_K3_DM_FW)) + return k3_ringacc_ring_reset_raw(ring); + ret = ringacc->tisci_ring_ops->config( ringacc->tisci, TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID, @@ -362,6 +369,9 @@ static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_nav_ring *ring, struct k3_nav_ringacc *ringacc = ring->parent; int ret; + if (IS_ENABLED(CONFIG_K3_DM_FW)) + return k3_ringacc_ring_reconfig_qmode_raw(ring, mode); + ret = ringacc->tisci_ring_ops->config( ringacc->tisci,
[PATCH v2 5/7] ARM: dts: k3: Add cfg register space for ringacc and udmap
R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING CFG, TCHAN CFG and RCHAN CFG address ranges. Note that these registers are present within respective IPs but are not populated in Linux DT nodes (as they are configured via TISCI APIs) and hence are added to -u-boot.dtsi for now. Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++ .../k3-j7200-common-proc-board-u-boot.dtsi| 26 +++ .../k3-j721e-common-proc-board-u-boot.dtsi| 14 ++ 3 files changed, 54 insertions(+) diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index b0602d1dad..2840258518 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -35,11 +35,25 @@ u-boot,dm-spl; ringacc@2b80 { + reg = <0x0 0x2b80 0x0 0x40>, + <0x0 0x2b00 0x0 0x40>, + <0x0 0x2859 0x0 0x100>, + <0x0 0x2a50 0x0 0x4>, + <0x0 0x2844 0x0 0x4>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; u-boot,dm-spl; ti,dma-ring-reset-quirk; }; dma-controller@285c { + reg = <0x0 0x285c 0x0 0x100>, + <0x0 0x284c 0x0 0x4000>, + <0x0 0x2a80 0x0 0x4>, + <0x0 0x284a 0x0 0x4000>, + <0x0 0x2aa0 0x0 0x4>, + <0x0 0x2840 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; u-boot,dm-spl; }; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index c3aae65b39..41ce9fcb59 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -40,6 +40,32 @@ chipid@4314 { u-boot,dm-spl; }; + + mcu-navss{ + u-boot,dm-spl; + + ringacc@2b80 { + reg = <0x0 0x2b80 0x0 0x40>, + <0x0 0x2b00 0x0 0x40>, + <0x0 0x2859 0x0 0x100>, + <0x0 0x2a50 0x0 0x4>, + <0x0 0x2844 0x0 0x4>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + u-boot,dm-spl; + }; + + dma-controller@285c { + reg = <0x0 0x285c 0x0 0x100>, + <0x0 0x284c 0x0 0x4000>, + <0x0 0x2a80 0x0 0x4>, + <0x0 0x284a 0x0 0x4000>, + <0x0 0x2aa0 0x0 0x4>, + <0x0 0x2840 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; + u-boot,dm-spl; + }; + }; }; &secure_proxy_main { diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 951331831e..974dae8416 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -54,10 +54,24 @@ u-boot,dm-spl; ringacc@2b80 { + reg = <0x0 0x2b80 0x0 0x40>, + <0x0 0x2b00 0x0 0x40>, + <0x0 0x2859 0x0 0x100>, + <0x0 0x2a50 0x0 0x4>, + <0x0 0x2844 0x0 0x4>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; u-boot,dm-spl; }; dma-controller@285c { + reg = <0x0 0x285c 0x0 0x100>, + <0x0
[PATCH v2 4/7] ARM: dts: j72xx-r5-common-proc-board: Add DM firmware node
Add DM firmware node which will provide DM services during R5 SPL stage. Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 17 + arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 18 ++ 2 files changed, 35 insertions(+) diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 0491432060..9963746c1d 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -79,6 +79,16 @@ mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>; mbox-names = "tx", "rx"; }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&mcu_secproxy 21>, + <&mcu_secproxy 23>; + u-boot,dm-spl; + }; }; &dmsc { @@ -276,4 +286,11 @@ }; }; +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; #include "k3-j7200-common-proc-board-u-boot.dtsi" diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 4e8422e662..0542b2f8b8 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -76,6 +76,16 @@ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&mcu_secproxy 21>, + <&mcu_secproxy 23>; + u-boot,dm-spl; + }; }; &cbass_main { @@ -345,3 +355,11 @@ u-boot,dm-spl; }; }; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; -- 2.31.1
[PATCH v2 3/7] firmware: ti_sci: Add support for Resoure Management at R5 SPL stage.
On J721e and J7200, MCU R5 core (boot master) itself would run Device Manager (DM) Firmware and interact with TI Foundational Security (TIFS) firmware to enable DMA and such other Resource Management (RM) services. So, during R5 SPL stage there is no such RM service available and ti_sci driver will have to directly interact with TIFS using DM to DMSC channels to request RM resources. Therefore add DT binding and driver for the same. This driver will handle Resource Management services at R5 SPL stage. Signed-off-by: Vignesh Raghavendra --- .../firmware/ti,j721e-dm-sci.txt | 32 +++ drivers/firmware/ti_sci.c | 91 +-- 2 files changed, 113 insertions(+), 10 deletions(-) create mode 100644 doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt diff --git a/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt b/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt new file mode 100644 index 00..0217341f0c --- /dev/null +++ b/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt @@ -0,0 +1,32 @@ +Bindings for Texas Instruments System Control Interface (TI-SCI) Message +Protocol for Device Manager(DM) to TI Foundational Security(TIFS) +Firmware communication + +Required properties: + +- compatible: should be "ti,j721e-dm-sci" +- mbox-names: + "rx" - Mailbox corresponding to receive path + "tx" - Mailbox corresponding to transmit path + +- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes + property should contain a phandle to the mailbox controller device + node and an args specifier that will be the phandle to the intended + sub-mailbox child node to be used for communication. + +- ti,host-id: Host ID to use for communication. + +Optional Properties: + +- ti,secure-host: If the host is defined as secure. + +Example: + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&mcu_secproxy 21>, + <&mcu_secproxy 23>; + }; diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 0318da208e..0b6ba35b59 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -1670,8 +1670,9 @@ fail: } static int __maybe_unused -ti_sci_get_resource_range_static(u32 dev_id, u8 subtype, u16 *range_start, -u16 *range_num) +ti_sci_cmd_get_resource_range_static(const struct ti_sci_handle *handle, +u32 dev_id, u8 subtype, +u16 *range_start, u16 *range_num) { struct ti_sci_resource_static_data *data; int i = 0; @@ -1712,11 +1713,6 @@ static int ti_sci_cmd_get_resource_range(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u16 *range_start, u16 *range_num) { - if (CONFIG_IS_ENABLED(TI_K3_RAW_RM)) - return ti_sci_get_resource_range_static(dev_id, subtype, - range_start, - range_num); - return ti_sci_get_resource_range(handle, dev_id, subtype, TI_SCI_IRQ_SECONDARY_HOST_INVALID, range_start, range_num); @@ -1740,9 +1736,6 @@ int ti_sci_cmd_get_resource_range_from_shost(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u8 s_host, u16 *range_start, u16 *range_num) { - if (CONFIG_IS_ENABLED(TI_K3_RAW_RM)) - return -EINVAL; - return ti_sci_get_resource_range(handle, dev_id, subtype, s_host, range_start, range_num); } @@ -3052,6 +3045,58 @@ static int ti_sci_probe(struct udevice *dev) return ret; } +/** + * ti_sci_dm_probe() - Basic probe for DM to TIFS SCI + * @dev: corresponding system controller interface device + * + * Return: 0 if all goes good, else appropriate error message. + */ +static __maybe_unused int ti_sci_dm_probe(struct udevice *dev) +{ + struct ti_sci_rm_core_ops *rm_core_ops; + struct ti_sci_rm_udmap_ops *udmap_ops; + struct ti_sci_rm_ringacc_ops *rops; + struct ti_sci_rm_psil_ops *psilops; + struct ti_sci_ops *ops; + struct ti_sci_info *info; + int ret; + + debug("%s(dev=%p)\n", __func__, dev); + + info = dev_get_priv(dev); + info->desc = (void *)dev_get_driver_data(dev); + + ret = ti_sci_of_to_info(dev, info); + if (ret) { + dev_err(dev, "%s:
[PATCH v2 1/7] mailbox: k3-sec-proxy: Add DM to DMSC communication thread
R5 SPL would need to talk to DMSC using DM to DMSC sec-proxy threads. Mark these as valid threads in the driver. Signed-off-by: Vignesh Raghavendra --- drivers/mailbox/k3-sec-proxy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c index 88f320515a..20fdb09f31 100644 --- a/drivers/mailbox/k3-sec-proxy.c +++ b/drivers/mailbox/k3-sec-proxy.c @@ -409,7 +409,7 @@ static int k3_sec_proxy_remove(struct udevice *dev) return 0; } -static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13 }; +static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13, 20, 21, 22, 23 }; static const struct k3_sec_proxy_desc am654_desc = { .thread_count = 90, -- 2.31.1
[PATCH v2 2/7] firmware: ti_sci: Implement GET_RANGE with static data
In case of R5 SPL, GET_RANGE API service is not available (as DM services are not yet up), therefore service such calls locally using per SoC static data. Signed-off-by: Vignesh Raghavendra --- drivers/firmware/ti_sci.c | 36 +++ drivers/firmware/ti_sci_static_data.h | 92 +++ 2 files changed, 128 insertions(+) create mode 100644 drivers/firmware/ti_sci_static_data.h diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 4671a5e3a8..0318da208e 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -23,6 +23,7 @@ #include #include "ti_sci.h" +#include "ti_sci_static_data.h" /* List of all TI SCI devices active in system */ static LIST_HEAD(ti_sci_list); @@ -1668,6 +1669,33 @@ fail: return ret; } +static int __maybe_unused +ti_sci_get_resource_range_static(u32 dev_id, u8 subtype, u16 *range_start, +u16 *range_num) +{ + struct ti_sci_resource_static_data *data; + int i = 0; + + while (1) { + data = &rm_static_data[i]; + + if (!data->dev_id) + return -EINVAL; + + if (data->dev_id != dev_id || data->subtype != subtype) { + i++; + continue; + } + + *range_start = data->range_start; + *range_num = data->range_num; + + return 0; + } + + return -EINVAL; +} + /** * ti_sci_cmd_get_resource_range - Get a range of resources assigned to host *that is same as ti sci interface host. @@ -1684,6 +1712,11 @@ static int ti_sci_cmd_get_resource_range(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u16 *range_start, u16 *range_num) { + if (CONFIG_IS_ENABLED(TI_K3_RAW_RM)) + return ti_sci_get_resource_range_static(dev_id, subtype, + range_start, + range_num); + return ti_sci_get_resource_range(handle, dev_id, subtype, TI_SCI_IRQ_SECONDARY_HOST_INVALID, range_start, range_num); @@ -1707,6 +1740,9 @@ int ti_sci_cmd_get_resource_range_from_shost(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u8 s_host, u16 *range_start, u16 *range_num) { + if (CONFIG_IS_ENABLED(TI_K3_RAW_RM)) + return -EINVAL; + return ti_sci_get_resource_range(handle, dev_id, subtype, s_host, range_start, range_num); } diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h new file mode 100644 index 00..3c506e667a --- /dev/null +++ b/drivers/firmware/ti_sci_static_data.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + * + */ + +#ifndef __TI_SCI_STATIC_DATA_H +#define __TI_SCI_STATIC_DATA_H + +struct ti_sci_resource_static_data { + u32 dev_id; + u16 range_start; + u16 range_num; + u8 subtype; +}; + +#if IS_ENABLED(CONFIG_K3_DM_FW) + +#if IS_ENABLED(CONFIG_TARGET_J721E_R5_EVM) +static struct ti_sci_resource_static_data rm_static_data[] = { + /* Free rings */ + { + .dev_id = 235, + .subtype = 1, + .range_start = 124, + .range_num = 32, + }, + /* TX channels */ + { + .dev_id = 236, + .subtype = 13, + .range_start = 6, + .range_num = 2, + }, + /* RX channels */ + { + .dev_id = 236, + .subtype = 10, + .range_start = 6, + .range_num = 2, + }, + /* RX Free flows */ + { + .dev_id = 236, + .subtype = 0, + .range_start = 60, + .range_num = 8, + }, + { }, +}; +#endif /* CONFIG_TARGET_J721E_R5_EVM */ + +#if IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM) +static struct ti_sci_resource_static_data rm_static_data[] = { + /* Free rings */ + { + .dev_id = 235, + .subtype = 1, + .range_start = 144, + .range_num = 32, + }, + /* TX channels */ + { + .dev_id = 236, + .subtype = 13, + .range_start = 7, + .range_num = 2, + }, + /* RX channels */ + { + .dev_id = 236, + .subtype = 10, + .range_start = 7, + .range_num =
[PATCH v2 0/7] J72xx: R5 SPL DMA support post HSM Rearch
This series add DMA support for R5 SPL on J721e/J7200 SoCs post HSM Rearch. Depends on Tero's base HSM rearch support series. v2: Use IS_ENABLED() consistentially instead of #ifdef Reword commit msg for 5/7 as suggested by Lokesh Rebase on Tero's latest HSM base series. Vignesh Raghavendra (7): mailbox: k3-sec-proxy: Add DM to DMSC communication thread firmware: ti_sci: Implement GET_RANGE with static data firmware: ti_sci: Add support for Resoure Management at R5 SPL stage. ARM: dts: j72xx-r5-common-proc-board: Add DM firmware node ARM: dts: k3: Add cfg register space for ringacc and udmap soc: ti: k3-navss-ringacc: Add support for native configuration of rings dma: ti: k3-udma: Add support for native configuration of chan/flow arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++ .../k3-j7200-common-proc-board-u-boot.dtsi| 26 +++ .../arm/dts/k3-j7200-r5-common-proc-board.dts | 17 ++ .../k3-j721e-common-proc-board-u-boot.dtsi| 14 ++ .../arm/dts/k3-j721e-r5-common-proc-board.dts | 18 ++ .../firmware/ti,j721e-dm-sci.txt | 32 drivers/dma/ti/k3-udma-u-boot.c | 177 ++ drivers/dma/ti/k3-udma.c | 42 - drivers/firmware/ti_sci.c | 107 +++ drivers/firmware/ti_sci_static_data.h | 92 + drivers/mailbox/k3-sec-proxy.c| 2 +- drivers/soc/ti/k3-navss-ringacc-u-boot.c | 61 ++ drivers/soc/ti/k3-navss-ringacc.c | 36 +++- 13 files changed, 630 insertions(+), 8 deletions(-) create mode 100644 doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt create mode 100644 drivers/dma/ti/k3-udma-u-boot.c create mode 100644 drivers/firmware/ti_sci_static_data.h create mode 100644 drivers/soc/ti/k3-navss-ringacc-u-boot.c -- 2.31.1
[PATCH] configs: am64x_evm_a53_defconfig: Enable DP83867 PHY driver
AM64x GP and SK EVM have DP83867 PHY connected to CPSW external port0. Enable the driver in order to use ethernet at U-Boot prompt. CONFIG_PHY_TI is selected by CONFIG_PHY_TI_DP83867 and thus can be dropped. Signed-off-by: Vignesh Raghavendra --- Based on top of https://source.denx.de/u-boot/custodians/u-boot-ti.git tags/ti-v2021.07-rc3 configs/am64x_evm_a53_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 0e942e36b4..e1e1c375cf 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -76,6 +76,7 @@ CONFIG_SF_DEFAULT_MODE=0 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_TI=y +CONFIG_PHY_TI_DP83867=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_TI_AM65_CPSW_NUSS=y -- 2.31.1