Re: [U-Boot] [PATCH v7] qi_lb60: add nand spl support
Hi Daniel Thanks for reply. patches coming soon. Xiangfu On 01/07/2013 03:54 AM, Daniel Schwierzeck wrote: > 2013/1/4 Xiangfu Liu : >> Hi >> >> Any chance merge this commit to upstream. make it a new year gift for me. :) >> Thanks >> >> Xiangfu >> > > hm, somehow I missed that patch. Please prepend your patch subject > with "MIPS:" and CC me next time to avoid this. > Also send a new patch which is rebased to current master and move the > cosmetic changes not related to SPL into a > separate patch. > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7] qi_lb60: add nand spl support
Hi Any chance merge this commit to upstream. make it a new year gift for me. :) Thanks Xiangfu On 10/30/2012 08:41 AM, Scott Wood wrote: > On 10/26/2012 08:07:47 PM, xian...@openmobilefree.net wrote: >> From: Xiangfu >> >> The JZ4740 CPU can load 8KB from two different addresses: >>1. the normal area up to 8KB starting from NAND flash address 0x >>2. the backup area up to 8KB starting from NAND flash address 0x2000 >> >> Signed-off-by: Xiangfu >> --- >> Makefile | 12 +++ >> arch/mips/cpu/xburst/Makefile |7 +- >> arch/mips/cpu/xburst/cpu.c|4 + >> arch/mips/cpu/xburst/jz4740.c | 82 +++-- >> arch/mips/cpu/xburst/spl/Makefile | 47 ++ >> arch/mips/cpu/xburst/spl/start.S | 63 + >> board/qi/qi_lb60/Makefile |4 + >> board/qi/qi_lb60/qi_lb60-spl.c| 30 +++ >> board/qi/qi_lb60/qi_lb60.c|8 +- >> board/qi/qi_lb60/u-boot-spl.lds | 61 + >> drivers/mtd/nand/jz4740_nand.c| 39 - >> include/configs/qi_lb60.h | 175 >> ++--- >> 12 files changed, 386 insertions(+), 146 deletions(-) >> create mode 100644 arch/mips/cpu/xburst/spl/Makefile >> create mode 100644 arch/mips/cpu/xburst/spl/start.S >> create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c >> create mode 100644 board/qi/qi_lb60/u-boot-spl.lds > > For the drivers/mtd/nand part: > Acked-by: Scott Wood > > -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v7] qi_lb60: add nand spl support
From: Xiangfu
The JZ4740 CPU can load 8KB from two different addresses:
1. the normal area up to 8KB starting from NAND flash address 0x
2. the backup area up to 8KB starting from NAND flash address 0x2000
Signed-off-by: Xiangfu
---
Makefile | 12 +++
arch/mips/cpu/xburst/Makefile |7 +-
arch/mips/cpu/xburst/cpu.c|4 +
arch/mips/cpu/xburst/jz4740.c | 82 +++--
arch/mips/cpu/xburst/spl/Makefile | 47 ++
arch/mips/cpu/xburst/spl/start.S | 63 +
board/qi/qi_lb60/Makefile |4 +
board/qi/qi_lb60/qi_lb60-spl.c| 30 +++
board/qi/qi_lb60/qi_lb60.c|8 +-
board/qi/qi_lb60/u-boot-spl.lds | 61 +
drivers/mtd/nand/jz4740_nand.c| 39 -
include/configs/qi_lb60.h | 175 ++---
12 files changed, 386 insertions(+), 146 deletions(-)
create mode 100644 arch/mips/cpu/xburst/spl/Makefile
create mode 100644 arch/mips/cpu/xburst/spl/start.S
create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c
create mode 100644 board/qi/qi_lb60/u-boot-spl.lds
diff --git a/Makefile b/Makefile
index 34d9075..a22778e 100644
--- a/Makefile
+++ b/Makefile
@@ -393,6 +393,10 @@ ALL-y += $(obj)u-boot-nodtb-tegra.bin
endif
endif
+ifeq ($(CPU),xburst)
+ALL-y += $(obj)u-boot-xburst.bin
+endif
+
all: $(ALL-y) $(SUBDIR_EXAMPLES)
$(obj)u-boot.dtb: $(obj)u-boot
@@ -506,6 +510,14 @@ $(obj)u-boot-nodtb-tegra.bin:
$(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
endif
endif
+ifeq ($(CPU),xburst)
+$(obj)u-boot-xburst.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ dd if=$(obj)spl/u-boot-spl.bin of=$(obj)spl/u-boot-pad.bin
conv=sync bs=8192 count=1
+ dd if=$(obj)spl/u-boot-spl.bin of=$(obj)spl/u-boot-pad.bin
conv=sync,notrunc oflag=append bs=8192 count=1
+ tr '\0' '\377' < /dev/zero | dd of=$(obj)spl/u-boot-pad.bin
conv=sync,notrunc oflag=append bs=16384 count=1
+ cat $(obj)spl/u-boot-pad.bin u-boot.bin > $@
+endif
+
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile
index b1f2ae4..ec35e55 100644
--- a/arch/mips/cpu/xburst/Makefile
+++ b/arch/mips/cpu/xburst/Makefile
@@ -24,9 +24,12 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
+COBJS-y= cpu.o jz_serial.o
+
+ifneq ($(CONFIG_SPL_BUILD),y)
START = start.o
-SOBJS-y=
-COBJS-y= cpu.o timer.o jz_serial.o
+COBJS-y += timer.o
+endif
COBJS-$(CONFIG_JZ4740) += jz4740.o
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa..1432838 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -42,6 +42,8 @@
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
+#ifndef CONFIG_SPL_BUILD
+
void __attribute__((weak)) _machine_restart(void)
{
struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
cache_op(Hit_Invalidate_D, addr);
}
+#endif
+
void flush_icache_all(void)
{
u32 addr, t = 0;
diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c
index c0b9817..8816aa3 100644
--- a/arch/mips/cpu/xburst/jz4740.c
+++ b/arch/mips/cpu/xburst/jz4740.c
@@ -32,31 +32,19 @@ int disable_interrupts(void)
return 0;
}
-/*
- * PLL output clock = EXTAL * NF / (NR * NO)
- * NF = FD + 2, NR = RD + 2
- * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
- */
void pll_init(void)
{
struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
- register unsigned int cfcr, plcr1;
- int n2FR[33] = {
- 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
- 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
- 9
- };
- int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
- int nf, pllout2;
+ register unsigned int cfcr, plcr;
+ unsigned int nf, pllout2;
cfcr = CPM_CPCCR_CLKOEN |
- CPM_CPCCR_PCS |
- (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
- (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
- (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
- (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
- (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
+ (0 << CPM_CPCCR_CDIV_BIT) |
+ (2 << CPM_CPCCR_HDIV_BIT) |
+ (2 << CPM_CPCCR_PDIV_BIT) |
+ (2 << CPM_CPCCR_MDIV_BIT) |
+ (2 << CPM_CPCCR_LDIV_BIT);
pllout2 = (cfcr & CPM_CPCCR_PCS) ?
CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_
[U-Boot] [PATCH v7] qi_lb60: add nand spl support
From: Xiangfu Big thanks to Tom Rini, Daniel Schwierzeck and Marek Vasut for feedback. For the usbboot code. I can not fast re-write them to u-boot USB sub-system. but I don't want wait. so let's finish the nand spl code first. :) V7: * fix typo V6: * remove usbboot code * add u-boot-xburst.bin rule to main Makefile V5: * use puts instread of serial_puts (enable CONFIG_SPL_LIBCOMMON_SUPPORT) * update my email address * fix compiles warnings V4: * split to 2 patches (nand spl/usbbot) * remove use define string.c using CONFIG_SPL_LIBGENERIC_SUPPORT * fix checkputch.pl warnings V3: * add simpile string.c to mips/lib * some cleanup on jz4740.c * move to new spl/ structure * support software usbboot mode Xiangfu (1): qi_lb60: add nand spl support Makefile | 12 +++ arch/mips/cpu/xburst/Makefile |7 +- arch/mips/cpu/xburst/cpu.c|4 + arch/mips/cpu/xburst/jz4740.c | 82 +++-- arch/mips/cpu/xburst/spl/Makefile | 47 ++ arch/mips/cpu/xburst/spl/start.S | 63 + board/qi/qi_lb60/Makefile |4 + board/qi/qi_lb60/qi_lb60-spl.c| 30 +++ board/qi/qi_lb60/qi_lb60.c|8 +- board/qi/qi_lb60/u-boot-spl.lds | 61 + drivers/mtd/nand/jz4740_nand.c| 39 - include/configs/qi_lb60.h | 175 ++--- 12 files changed, 386 insertions(+), 146 deletions(-) create mode 100644 arch/mips/cpu/xburst/spl/Makefile create mode 100644 arch/mips/cpu/xburst/spl/start.S create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c create mode 100644 board/qi/qi_lb60/u-boot-spl.lds -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6] qi_lb60: add nand spl support
From: Xiangfu
The JZ4740 CPU can load 8KB from two different addresses:
1. the normal area up to 8KB starting from NAND flash address 0x
2. the backup area up to 8KB starting from NAND flash address 0x2000
Signed-off-by: Xiangfu
---
Makefile | 12 +++
arch/mips/cpu/xburst/Makefile |7 +-
arch/mips/cpu/xburst/cpu.c|4 +
arch/mips/cpu/xburst/jz4740.c | 84 +++---
arch/mips/cpu/xburst/spl/Makefile | 47 ++
arch/mips/cpu/xburst/spl/start.S | 63 +
board/qi/qi_lb60/Makefile |4 +
board/qi/qi_lb60/qi_lb60-spl.c| 30 +++
board/qi/qi_lb60/qi_lb60.c|8 +-
board/qi/qi_lb60/u-boot-spl.lds | 61 +
drivers/mtd/nand/jz4740_nand.c| 39 -
include/configs/qi_lb60.h | 175 ++---
12 files changed, 387 insertions(+), 147 deletions(-)
create mode 100644 arch/mips/cpu/xburst/spl/Makefile
create mode 100644 arch/mips/cpu/xburst/spl/start.S
create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c
create mode 100644 board/qi/qi_lb60/u-boot-spl.lds
diff --git a/Makefile b/Makefile
index 34d9075..a22778e 100644
--- a/Makefile
+++ b/Makefile
@@ -393,6 +393,10 @@ ALL-y += $(obj)u-boot-nodtb-tegra.bin
endif
endif
+ifeq ($(CPU),xburst)
+ALL-y += $(obj)u-boot-xburst.bin
+endif
+
all: $(ALL-y) $(SUBDIR_EXAMPLES)
$(obj)u-boot.dtb: $(obj)u-boot
@@ -506,6 +510,14 @@ $(obj)u-boot-nodtb-tegra.bin:
$(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
endif
endif
+ifeq ($(CPU),xburst)
+$(obj)u-boot-xburst.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ dd if=$(obj)spl/u-boot-spl.bin of=$(obj)spl/u-boot-pad.bin
conv=sync bs=8192 count=1
+ dd if=$(obj)spl/u-boot-spl.bin of=$(obj)spl/u-boot-pad.bin
conv=sync,notrunc oflag=append bs=8192 count=1
+ tr '\0' '\377' < /dev/zero | dd of=$(obj)spl/u-boot-pad.bin
conv=sync,notrunc oflag=append bs=16384 count=1
+ cat $(obj)spl/u-boot-pad.bin u-boot.bin > $@
+endif
+
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile
index b1f2ae4..ec35e55 100644
--- a/arch/mips/cpu/xburst/Makefile
+++ b/arch/mips/cpu/xburst/Makefile
@@ -24,9 +24,12 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
+COBJS-y= cpu.o jz_serial.o
+
+ifneq ($(CONFIG_SPL_BUILD),y)
START = start.o
-SOBJS-y=
-COBJS-y= cpu.o timer.o jz_serial.o
+COBJS-y += timer.o
+endif
COBJS-$(CONFIG_JZ4740) += jz4740.o
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa..1432838 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -42,6 +42,8 @@
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
+#ifndef CONFIG_SPL_BUILD
+
void __attribute__((weak)) _machine_restart(void)
{
struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
cache_op(Hit_Invalidate_D, addr);
}
+#endif
+
void flush_icache_all(void)
{
u32 addr, t = 0;
diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c
index c0b9817..1e874ee 100644
--- a/arch/mips/cpu/xburst/jz4740.c
+++ b/arch/mips/cpu/xburst/jz4740.c
@@ -32,31 +32,19 @@ int disable_interrupts(void)
return 0;
}
-/*
- * PLL output clock = EXTAL * NF / (NR * NO)
- * NF = FD + 2, NR = RD + 2
- * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
- */
void pll_init(void)
{
struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
- register unsigned int cfcr, plcr1;
- int n2FR[33] = {
- 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
- 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
- 9
- };
- int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
- int nf, pllout2;
+ register unsigned int cfcr, plcr;
+ unsigned int nf, pllout2;
cfcr = CPM_CPCCR_CLKOEN |
- CPM_CPCCR_PCS |
- (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
- (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
- (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
- (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
- (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
+ (0 << CPM_CPCCR_CDIV_BIT) |
+ (2 << CPM_CPCCR_HDIV_BIT) |
+ (2 << CPM_CPCCR_PDIV_BIT) |
+ (2 << CPM_CPCCR_MDIV_BIT) |
+ (2 << CPM_CPCCR_LDIV_BIT);
pllout2 = (cfcr & CPM_CPCCR_PCS) ?
CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_
[U-Boot] [PATCH v6] qi_lb60(Ben NanoNote): add nand spl and usbboot support
From: Xiangfu Big thanks to Tom Rini, Daniel Schwierzeck and Marek Vasut for feedback. For the usbboot code. I can not fast re-write them to u-boot USB sub-system. but I don't want wait. so let's finish the nand spl code first. :) V6: * remove usbboot code. * add u-boot-xburst.bin rule to main Makefile V5: * use puts instread of serial_puts (enable CONFIG_SPL_LIBCOMMON_SUPPORT) * update my email address * fix compiles warnings V4: * split to 2 patches (nand spl/usbbot) * remove use define string.c using CONFIG_SPL_LIBGENERIC_SUPPORT * fix checkputch.pl warnings V3: * add simpile string.c to mips/lib * some cleanup on jz4740.c * move to new spl/ structure * support software usbboot mode Xiangfu (1): qi_lb60: add nand spl support Makefile | 12 +++ arch/mips/cpu/xburst/Makefile |7 +- arch/mips/cpu/xburst/cpu.c|4 + arch/mips/cpu/xburst/jz4740.c | 84 +++--- arch/mips/cpu/xburst/spl/Makefile | 47 ++ arch/mips/cpu/xburst/spl/start.S | 63 + board/qi/qi_lb60/Makefile |4 + board/qi/qi_lb60/qi_lb60-spl.c| 30 +++ board/qi/qi_lb60/qi_lb60.c|8 +- board/qi/qi_lb60/u-boot-spl.lds | 61 + drivers/mtd/nand/jz4740_nand.c| 39 - include/configs/qi_lb60.h | 175 ++--- 12 files changed, 387 insertions(+), 147 deletions(-) create mode 100644 arch/mips/cpu/xburst/spl/Makefile create mode 100644 arch/mips/cpu/xburst/spl/start.S create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c create mode 100644 board/qi/qi_lb60/u-boot-spl.lds -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/2] qi_lb60: add nand spl support
Hi Marek I will look into CPU-specific. come out with new patches. Xiangfu On 10/13/2012 08:50 PM, Marek Vasut wrote: > This is CPU-specific , right? So it should be some kind of CPU-specific > override > in CPU-specific directory, not polute the main Makefile. > > Best regards, > Marek Vasut > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 2/2] qi_lb60: add software usbboot support
On 10/13/2012 08:52 PM, Marek Vasut wrote: > Dear xiangfu liu, > >> > Hi Marek >> > >> > On Sat, Oct 13, 2012 at 8:23 PM, Marek Vasut wrote: >>> > > Dear xiangfu liu, >>> > > >>>> > > > Hi Marek >>>> > > > >>>> > > > This file was wrote by Ingenic people. I don't have time to convert >>>> > > > it >>>> > > > to C(I am not very good in mips assembler). the .S file implement >>>> > > > basic USB stack. >>> > > >>> > > We already do have an USB stack. >> > >> > This usbboot.S implement a very base usb-client protocol and it implement a >> > jz4740 hardware feature. > We have that too -- see drivers/usb/gadget/ Hi Marek I will look into this issue later, try to integrate this jz4740 feature with u-boot usb structure. but I am not sure that if I can finish this fast. wait my patches on jz4740 software usb boot. :) > >> > (jz4740 have a hard-code rom inside cpu. that have >> > the same feature, they named it 'boot from usb'). so this usbboot.S is for >> > implement the same feature in a software way. > Won't DFU work then? > I know this DFU. but it will different with the hardware-feature. Thanks again for feedback. Xiangfu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 2/2] qi_lb60: add software usbboot support
Hi Marek On Sat, Oct 13, 2012 at 8:23 PM, Marek Vasut wrote: > Dear xiangfu liu, > > > Hi Marek > > > > This file was wrote by Ingenic people. I don't have time to convert it to > > C(I am not very good in mips assembler). the .S file implement basic USB > > stack. > > We already do have an USB stack. > This usbboot.S implement a very base usb-client protocol and it implement a jz4740 hardware feature. (jz4740 have a hard-code rom inside cpu. that have the same feature, they named it 'boot from usb'). so this usbboot.S is for implement the same feature in a software way. and I think this usbboot.S can move to 'arch/mips/cpu/xburst/spl/jz4740_usbboot.s' in future. and I don't think it will impact with other usb code in u-boot. > > > this C code ( > > > http://projects.qi-hardware.com/index.php/p/xburst-tools/source/tree/master > > /xbboot) implement the host app. the host app source code even clear then > > the original Ingenic document. so feel free to send patch. > > Sorry, but it is my duty as a USB custodian to NAK patches which try to > circumvent the constant effort to keep the code clean. Obviously, > implementing > yet another USB stack is violation of this. > Yes. I understand your duty. and keep a project code clean is not easy. thanks for feedback. (I never look into u-boot usb code. don't have much experience on u-boot usb structure. :) All the best Xiangfu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/2] qi_lb60: add nand spl support
On 10/13/2012 10:59 AM, Marek Vasut wrote: >> From: Xiangfu >> > >> > The JZ4740 CPU can load 8KB from two different addresses: >> >1. the normal area up to 8KB starting from NAND flash address 0x >> >2. the backup area up to 8KB starting from NAND flash address 0x2000 >> > >> > After create u-boot-spl.bin. it needs those 4 commands create final image >> > for jz4740 cpu. >> > dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync bs=8192 count=1 >> > dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync,notrunc >> > oflag=append bs=8192 count=1 tr '\0' '\377' < /dev/zero | dd >> > of=u-boot-nand.bin conv=sync,notrunc oflag=append bs=16384 count=1 cat >> > u-boot-nand.bin u-boot.bin > u-boot-nand-final.bin >> > > Can you not do this in the linker script? Or implement CPU-specific build > target > that does this? Hi Marex Thanks for reply, I don't know how to do this in linker script. but I have plan to send out a patch on Makefile. Attachment is the patch. do you think it is ok for upstream? if it's ok. I will send out this patch in another email. Xiangfu diff --git a/Makefile b/Makefile index 34d9075..55fc72d 100644 --- a/Makefile +++ b/Makefile @@ -554,8 +554,16 @@ $(obj)u-boot.lds: $(LDSCRIPT) nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend $(MAKE) -C nand_spl/board/$(BOARDDIR) all +ifdef CONFIG_JZ4740 +$(obj)u-boot-nand.bin: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin + dd if=$(obj)spl/u-boot-spl.bin of=$(obj)spl/u-boot-nand.bin conv=sync bs=8192 count=1 + dd if=$(obj)spl/u-boot-spl.bin of=$(obj)spl/u-boot-nand.bin conv=sync,notrunc oflag=append bs=8192 count=1 + tr '\0' '\377' < /dev/zero | dd of=$(obj)spl/u-boot-nand.bin conv=sync,notrunc oflag=append bs=16384 count=1 + cat $(obj)spl/u-boot-nand.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin +else $(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin +endif $(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend $(MAKE) -C spl all ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 2/2] qi_lb60: add software usbboot support
Hi Marek This file was wrote by Ingenic people. I don't have time to convert it to C(I am not very good in mips assembler). the .S file implement basic USB stack. this C code ( http://projects.qi-hardware.com/index.php/p/xburst-tools/source/tree/master/xbboot) implement the host app. the host app source code even clear then the original Ingenic document. so feel free to send patch. Xiangfu On Sat, Oct 13, 2012 at 11:01 AM, Marek Vasut wrote: > Dear xian...@openmobilefree.net, > > > From: Xiangfu > > > > JZ4740 CPU have a internal ROM have such kind of code, that make > > JZ4740 can boot from USB > > > > usbboot.S can downloads user program from the USB port to internal > > SRAM and branches to the internal SRAM to execute the program > > > > Signed-off-by: Xiangfu > > --- > > board/qi/qi_lb60/qi_lb60-spl.c | 20 + > > board/qi/qi_lb60/usbboot.S | 838 > > 2 files changed, 858 > > insertions(+) > > create mode 100644 board/qi/qi_lb60/usbboot.S > > > [...] > > UGH. Simply ... UGH. > > Can that assembler blob not be rewritten into C ? > > Best regards, > Marek Vasut > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 1/2] qi_lb60: add nand spl support
From: Xiangfu
The JZ4740 CPU can load 8KB from two different addresses:
1. the normal area up to 8KB starting from NAND flash address 0x
2. the backup area up to 8KB starting from NAND flash address 0x2000
After create u-boot-spl.bin. it needs those 4 commands create final image for
jz4740 cpu.
dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync bs=8192 count=1
dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync,notrunc oflag=append
bs=8192 count=1
tr '\0' '\377' < /dev/zero | dd of=u-boot-nand.bin conv=sync,notrunc
oflag=append bs=16384 count=1
cat u-boot-nand.bin u-boot.bin > u-boot-nand-final.bin
~~~~
Signed-off-by: Xiangfu
---
arch/mips/cpu/xburst/Makefile |7 +-
arch/mips/cpu/xburst/cpu.c|4 +
arch/mips/cpu/xburst/jz4740.c | 84 +++---
arch/mips/cpu/xburst/spl/Makefile | 47 ++
arch/mips/cpu/xburst/spl/start.S | 63 +
board/qi/qi_lb60/Makefile |5 ++
board/qi/qi_lb60/qi_lb60-spl.c| 30 +++
board/qi/qi_lb60/qi_lb60.c|8 +-
board/qi/qi_lb60/u-boot-spl.lds | 62 +
drivers/mtd/nand/jz4740_nand.c| 39 -
include/configs/qi_lb60.h | 175 ++---
11 files changed, 377 insertions(+), 147 deletions(-)
create mode 100644 arch/mips/cpu/xburst/spl/Makefile
create mode 100644 arch/mips/cpu/xburst/spl/start.S
create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c
create mode 100644 board/qi/qi_lb60/u-boot-spl.lds
diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile
index b1f2ae4..ec35e55 100644
--- a/arch/mips/cpu/xburst/Makefile
+++ b/arch/mips/cpu/xburst/Makefile
@@ -24,9 +24,12 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
+COBJS-y= cpu.o jz_serial.o
+
+ifneq ($(CONFIG_SPL_BUILD),y)
START = start.o
-SOBJS-y=
-COBJS-y= cpu.o timer.o jz_serial.o
+COBJS-y += timer.o
+endif
COBJS-$(CONFIG_JZ4740) += jz4740.o
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa..1432838 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -42,6 +42,8 @@
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
+#ifndef CONFIG_SPL_BUILD
+
void __attribute__((weak)) _machine_restart(void)
{
struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
cache_op(Hit_Invalidate_D, addr);
}
+#endif
+
void flush_icache_all(void)
{
u32 addr, t = 0;
diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c
index c0b9817..1e874ee 100644
--- a/arch/mips/cpu/xburst/jz4740.c
+++ b/arch/mips/cpu/xburst/jz4740.c
@@ -32,31 +32,19 @@ int disable_interrupts(void)
return 0;
}
-/*
- * PLL output clock = EXTAL * NF / (NR * NO)
- * NF = FD + 2, NR = RD + 2
- * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
- */
void pll_init(void)
{
struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
- register unsigned int cfcr, plcr1;
- int n2FR[33] = {
- 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
- 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
- 9
- };
- int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
- int nf, pllout2;
+ register unsigned int cfcr, plcr;
+ unsigned int nf, pllout2;
cfcr = CPM_CPCCR_CLKOEN |
- CPM_CPCCR_PCS |
- (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
- (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
- (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
- (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
- (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
+ (0 << CPM_CPCCR_CDIV_BIT) |
+ (2 << CPM_CPCCR_HDIV_BIT) |
+ (2 << CPM_CPCCR_PDIV_BIT) |
+ (2 << CPM_CPCCR_MDIV_BIT) |
+ (2 << CPM_CPCCR_LDIV_BIT);
pllout2 = (cfcr & CPM_CPCCR_PCS) ?
CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
@@ -65,15 +53,18 @@ void pll_init(void)
writel(pllout2 / 4800 - 1, &cpm->uhccdr);
nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
- plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
+ plcr = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
(0 << CPM_CPPCR_PLLOD_BIT) |/* OD=0, NO=1 */
- (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
+ (0x32 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
CPM_CPPCR_PLLEN;/* enable PLL */
[U-Boot] [PATCH v5 2/2] qi_lb60: add software usbboot support
From: Xiangfu
JZ4740 CPU have a internal ROM have such kind of code, that make
JZ4740 can boot from USB
usbboot.S can downloads user program from the USB port to internal
SRAM and branches to the internal SRAM to execute the program
Signed-off-by: Xiangfu
---
board/qi/qi_lb60/qi_lb60-spl.c | 20 +
board/qi/qi_lb60/usbboot.S | 838
2 files changed, 858 insertions(+)
create mode 100644 board/qi/qi_lb60/usbboot.S
diff --git a/board/qi/qi_lb60/qi_lb60-spl.c b/board/qi/qi_lb60/qi_lb60-spl.c
index 3fe3fa3..aea459c 100644
--- a/board/qi/qi_lb60/qi_lb60-spl.c
+++ b/board/qi/qi_lb60/qi_lb60-spl.c
@@ -12,6 +12,24 @@
#include
#include
+#define KEY_U_OUT (32 * 2 + 16)
+#define KEY_U_IN(32 * 3 + 19)
+
+extern void usb_boot(void);
+
+static void check_usb_boot(void)
+{
+ __gpio_as_input(KEY_U_IN);
+ __gpio_enable_pull(KEY_U_IN);
+ __gpio_as_output(KEY_U_OUT);
+ __gpio_clear_pin(KEY_U_OUT);
+
+ if (!__gpio_get_pin(KEY_U_IN)) {
+ puts("[U] pressed, goto USBBOOT mode\n");
+ usb_boot();
+ }
+}
+
void nand_spl_boot(void)
{
__gpio_as_sdram_16bit_4720();
@@ -23,6 +41,8 @@ void nand_spl_boot(void)
pll_init();
sdram_init();
+ check_usb_boot();
+
nand_init();
puts("\nQi LB60 SPL: Starting U-Boot ...\n");
diff --git a/board/qi/qi_lb60/usbboot.S b/board/qi/qi_lb60/usbboot.S
new file mode 100644
index 000..c872266
--- /dev/null
+++ b/board/qi/qi_lb60/usbboot.S
@@ -0,0 +1,838 @@
+/*
+ * for jz4740 usb boot
+ *
+ * Copyright (c) 2009 Author:
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+.set noreorder
+.globl usb_boot
+.text
+
+/*
+ * Both NAND and USB boot load data to D-Cache first, then transfer
+ * data from D-Cache to I-Cache, and jump to execute the code in I-Cache.
+ * So init caches first and then dispatch to a proper boot routine.
+ */
+
+.macro load_addr reg addr
+ li \reg, 0x8000
+ addiu \reg, \reg, \addr
+ la $2, usbboot_begin
+ subu \reg, \reg, $2
+.endm
+
+usb_boot:
+ /* Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz. */
+ la $9, 0xB000 /* CPCCR: Clock Control Register */
+ la $8, 0x42041110 /* I:S:M:P=1:2:2:2 */
+ sw $8, 0($9)
+
+ la $9, 0xB010 /* CPPCR: PLL Control Register */
+ la $8, 0x06000120 /* M=12 N=0 D=0 CLK=12*(M+2)/(N+2) */
+ sw $8, 0($9)
+
+ mtc0$0, $26 /* CP0_ERRCTL, restore WST reset state */
+ nop
+
+ mtc0$0, $16 /* CP0_CONFIG */
+ nop
+
+ /* Relocate code to beginning of the ram */
+
+ la $2, usbboot_begin
+ la $3, usbboot_end
+ li $4, 0x8000
+
+1:
+ lw $5, 0($2)
+ sw $5, 0($4)
+ addiu $2, $2, 4
+ bne $2, $3, 1b
+ addiu $4, $4, 4
+
+ li $2, 0x8000
+ ori $3, $2, 0
+ addiu $3, $3, usbboot_end
+ la $4, usbboot_begin
+ subu $3, $3, $4
+
+
+2:
+ cache 0x0, 0($2) /* Index_Invalidate_I */
+ cache 0x1, 0($2) /* Index_Writeback_Inv_D */
+ addiu $2, $2, 32
+ subu $4, $3, $2
+ bgtz$4, 2b
+ nop
+
+ load_addr $3, usb_boot_return
+
+ jr $3
+
+usbboot_begin:
+
+init_caches:
+ li $2, 3 /* cacheable for kseg0 access */
+ mtc0$2, $16 /* CP0_CONFIG */
+ nop
+
+ li $2, 0x2000 /* enable idx-store-data cache insn */
+ mtc0$2, $26 /* CP0_ERRCTL */
+
+ ori $2, $28, 0 /* start address */
+ ori $3, $2, 0x3fe0 /* end address, total 16KB */
+ mtc0$0, $28, 0 /* CP0_TAGLO */
+ mtc0$0, $28, 1 /* CP0_DATALO */
+cache_clear_a_line:
+ cache 0x8, 0($2) /* Index_Store_Tag_I */
+ cache 0x9, 0($2) /* Index_Store_Tag_D */
+ bne $2, $3, cache_clear_a_line
+ addiu $2, $2, 32 /* increment CACHE_LINE_SIZE */
[U-Boot] [PATCH v5 0/2] qi_lb60(Ben NanoNote): add nand spl and usbboot support
From: Xiangfu Big thanks to Tom Rini and Daniel Schwierzeck for feedback. V5: * use puts instread of serial_puts (enable CONFIG_SPL_LIBCOMMON_SUPPORT) * update my email address * fix compiles warnings V4: * split to 2 patches (nand spl/usbbot) * remove use define string.c using CONFIG_SPL_LIBGENERIC_SUPPORT * fix checkputch.pl warnings V3: * add simpile string.c to mips/lib * some cleanup on jz4740.c * move to new spl/ structure * support software usbboot mode Xiangfu (2): qi_lb60: add nand spl support qi_lb60: add software usbboot support arch/mips/cpu/xburst/Makefile |7 +- arch/mips/cpu/xburst/cpu.c|4 + arch/mips/cpu/xburst/jz4740.c | 84 ++-- arch/mips/cpu/xburst/spl/Makefile | 47 +++ arch/mips/cpu/xburst/spl/start.S | 63 +++ board/qi/qi_lb60/Makefile |5 + board/qi/qi_lb60/qi_lb60-spl.c| 50 +++ board/qi/qi_lb60/qi_lb60.c|8 +- board/qi/qi_lb60/u-boot-spl.lds | 62 +++ board/qi/qi_lb60/usbboot.S| 838 + drivers/mtd/nand/jz4740_nand.c| 39 +- include/configs/qi_lb60.h | 175 12 files changed, 1235 insertions(+), 147 deletions(-) create mode 100644 arch/mips/cpu/xburst/spl/Makefile create mode 100644 arch/mips/cpu/xburst/spl/start.S create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c create mode 100644 board/qi/qi_lb60/u-boot-spl.lds create mode 100644 board/qi/qi_lb60/usbboot.S -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] add nand spl boot for qi_lb60 board
Hi Tom Rini I cannot easy find a way to use 'puts' instead 'serial_puts' in my code. any advise will be great. Thanks Xiangfu On 10/10/2012 05:27 AM, Daniel Schwierzeck wrote: >> I'm happy you've moved to the new SPL infrastructure. A few comments: >> >> In general, please check for checkpatch.pl issues, I spotted a few. >> Also, don't use // comments in asm, everything else in MIPS uses '#' or >> '/* ... */'. Please use 'puts' rather than 'serial_puts' directly. >> ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] add nand spl boot for qi_lb60 board
Hi
Thanks for feedback. PATVH v4 will coming soon. about 'CONFIG_SPL_FRAMEWORK'
I don't know this when I working on ben nanonote spl. I think I will stick
with this spl for awhile.
is there a plan remove drivers/mtd/nand/nand_spl_*.c?
Xiangfu
On 10/10/2012 05:27 AM, Daniel Schwierzeck wrote:
> 2012/10/9 Tom Rini :
>> On Tue, Oct 09, 2012 at 04:28:05PM +0800, xian...@openmobilefree.net wrote:
>>
>>> From: Xiangfu Liu
>>>
>>> * After create u-boot-spl.bin. it needs those 4 commands create final
>>> image for jz4740 cpu.
>>>
>>> dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync bs=8192 count=1
>>> dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync,notrunc
>>> oflag=append bs=8192 count=1
>>> tr '\0' '\377' < /dev/zero | dd of=u-boot-nand.bin conv=sync,notrunc
>>> oflag=append bs=16384 count=1
>>> cat u-boot-nand.bin u-boot.bin > u-boot-nand-final.bin
>>>
>>> The JZ4740 CPU can load 8KB from two different addresses:
>>>1. the normal area up to 8KB starting from NAND flash address 0x
>>>2. the backup area up to 8KB starting from NAND flash address 0x2000
>>>
>>>
>>> * Add software usbboot mode
>>>Downloads user program from the USB port to internal
>>>SRAM and branches to the internal SRAM to execute the program.
>>>(JZ4740 CPU have a internal ROM have such kind of code, that make
>>> JZ4740 can boot from USB)
>>> ---
>>> v3:
>>> * add simpile string.c to mips/lib
>>> * some cleanup on jz4740.c
>>> * move to new spl/ structure
>>> * support software usbboot mode
>>
>> I'm happy you've moved to the new SPL infrastructure. A few comments:
>>
>> In general, please check for checkpatch.pl issues, I spotted a few.
>> Also, don't use // comments in asm, everything else in MIPS uses '#' or
>> '/* ... */'. Please use 'puts' rather than 'serial_puts' directly.
>>
>> [snip]
>>> diff --git a/arch/mips/lib/string.c b/arch/mips/lib/string.c
>>> new file mode 100644
>>> index 000..d59f44a
>>> --- /dev/null
>>> +++ b/arch/mips/lib/string.c
>>> @@ -0,0 +1,32 @@
>>
>> Can you try just enabling CONFIG_SPL_LIBGENERIC_SUPPORT ? You should
>> have the unused functions garbage collected automatically.
>>
>>> diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
>>> index 3ec34f3..4ab2229 100644
>>> --- a/drivers/mtd/nand/jz4740_nand.c
>>> +++ b/drivers/mtd/nand/jz4740_nand.c
>>> @@ -15,6 +15,9 @@
>>> #include
>>> #include
>>>
>>> +#ifdef CONFIG_SPL_BUILD
>>> +#define printf(arg...) do {} while (0)
>>> +#endif
>>
>> In this case you should just switch to puts.
>>
>> And a non-blocking question, have you looked at the CONFIG_SPL_FRAMEWORK
>> code in common/spl/ now?
>>
>
> in addition to Tom's comments:
> please split coding style cleanups, code reordering, NAND SPL and USB
> boot into separate patches
>
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 1/2] qi_lb60: add nand spl support
From: Xiangfu
The JZ4740 CPU can load 8KB from two different addresses:
1. the normal area up to 8KB starting from NAND flash address 0x
2. the backup area up to 8KB starting from NAND flash address 0x2000
After create u-boot-spl.bin. it needs those 4 commands create final image for
jz4740 cpu.
dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync bs=8192 count=1
dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync,notrunc oflag=append
bs=8192 count=1
tr '\0' '\377' < /dev/zero | dd of=u-boot-nand.bin conv=sync,notrunc
oflag=append bs=16384 count=1
cat u-boot-nand.bin u-boot.bin > u-boot-nand-final.bin
~~~~
Signed-off-by: Xiangfu
---
arch/mips/cpu/xburst/Makefile |7 +-
arch/mips/cpu/xburst/cpu.c|4 +
arch/mips/cpu/xburst/jz4740.c | 84 --
arch/mips/cpu/xburst/spl/Makefile | 47 ++
arch/mips/cpu/xburst/spl/start.S | 65 ++
board/qi/qi_lb60/Makefile |4 +
board/qi/qi_lb60/qi_lb60-spl.c| 33 +++
board/qi/qi_lb60/qi_lb60.c|6 +-
board/qi/qi_lb60/u-boot-spl.lds | 62 +
drivers/mtd/nand/jz4740_nand.c| 39 -
include/configs/qi_lb60.h | 174 ++---
11 files changed, 380 insertions(+), 145 deletions(-)
create mode 100644 arch/mips/cpu/xburst/spl/Makefile
create mode 100644 arch/mips/cpu/xburst/spl/start.S
create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c
create mode 100644 board/qi/qi_lb60/u-boot-spl.lds
diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile
index b1f2ae4..ec35e55 100644
--- a/arch/mips/cpu/xburst/Makefile
+++ b/arch/mips/cpu/xburst/Makefile
@@ -24,9 +24,12 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
+COBJS-y= cpu.o jz_serial.o
+
+ifneq ($(CONFIG_SPL_BUILD),y)
START = start.o
-SOBJS-y=
-COBJS-y= cpu.o timer.o jz_serial.o
+COBJS-y += timer.o
+endif
COBJS-$(CONFIG_JZ4740) += jz4740.o
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa..1432838 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -42,6 +42,8 @@
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
+#ifndef CONFIG_SPL_BUILD
+
void __attribute__((weak)) _machine_restart(void)
{
struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
cache_op(Hit_Invalidate_D, addr);
}
+#endif
+
void flush_icache_all(void)
{
u32 addr, t = 0;
diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c
index c0b9817..40ef411 100644
--- a/arch/mips/cpu/xburst/jz4740.c
+++ b/arch/mips/cpu/xburst/jz4740.c
@@ -32,31 +32,19 @@ int disable_interrupts(void)
return 0;
}
-/*
- * PLL output clock = EXTAL * NF / (NR * NO)
- * NF = FD + 2, NR = RD + 2
- * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
- */
void pll_init(void)
{
struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
- register unsigned int cfcr, plcr1;
- int n2FR[33] = {
- 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
- 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
- 9
- };
- int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
- int nf, pllout2;
+ register unsigned int cfcr, plcr;
+ unsigned int nf, pllout2;
cfcr = CPM_CPCCR_CLKOEN |
- CPM_CPCCR_PCS |
- (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
- (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
- (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
- (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
- (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
+ (0 << CPM_CPCCR_CDIV_BIT) |
+ (2 << CPM_CPCCR_HDIV_BIT) |
+ (2 << CPM_CPCCR_PDIV_BIT) |
+ (2 << CPM_CPCCR_MDIV_BIT) |
+ (2 << CPM_CPCCR_LDIV_BIT);
pllout2 = (cfcr & CPM_CPCCR_PCS) ?
CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
@@ -65,15 +53,18 @@ void pll_init(void)
writel(pllout2 / 4800 - 1, &cpm->uhccdr);
nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
- plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
+ plcr = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
(0 << CPM_CPPCR_PLLOD_BIT) |/* OD=0, NO=1 */
- (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
+ (0x32 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
CPM_CPPCR_PLLEN;/* enable PLL */
[U-Boot] [PATCH v4 2/2] qi_lb60: add software usbboot support
From: Xiangfu
JZ4740 CPU have a internal ROM have such kind of code, that make
JZ4740 can boot from USB
usbboot.S can downloads user program from the USB port to internal
SRAM and branches to the internal SRAM to execute the program
Signed-off-by: Xiangfu
---
board/qi/qi_lb60/Makefile |1 +
board/qi/qi_lb60/qi_lb60-spl.c | 21 +
board/qi/qi_lb60/usbboot.S | 838
3 files changed, 860 insertions(+)
create mode 100644 board/qi/qi_lb60/usbboot.S
diff --git a/board/qi/qi_lb60/Makefile b/board/qi/qi_lb60/Makefile
index e399246..6dd8c6f 100644
--- a/board/qi/qi_lb60/Makefile
+++ b/board/qi/qi_lb60/Makefile
@@ -23,6 +23,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).o
ifeq ($(CONFIG_SPL_BUILD),y)
+SOBJS := usbboot.o
COBJS := $(BOARD)-spl.o
else
COBJS := $(BOARD).o
diff --git a/board/qi/qi_lb60/qi_lb60-spl.c b/board/qi/qi_lb60/qi_lb60-spl.c
index 739cd37..44d5dd6 100644
--- a/board/qi/qi_lb60/qi_lb60-spl.c
+++ b/board/qi/qi_lb60/qi_lb60-spl.c
@@ -12,6 +12,22 @@
#include
#include
+#define KEY_U_OUT (32 * 2 + 16)
+#define KEY_U_IN(32 * 3 + 19)
+
+static int is_usb_boot()
+{
+ __gpio_as_input(KEY_U_IN);
+ __gpio_enable_pull(KEY_U_IN);
+ __gpio_as_output(KEY_U_OUT);
+ __gpio_clear_pin(KEY_U_OUT);
+
+ if (__gpio_get_pin(KEY_U_IN) == 0)
+ return 1;
+
+ return 0;
+}
+
void nand_spl_boot(void)
{
uint32_t reg;
@@ -26,6 +42,11 @@ void nand_spl_boot(void)
pll_init();
sdram_init();
+ if (is_usb_boot()) {
+ serial_puts("[U] pressed, goto USBBOOT mode\n");
+ usb_boot();
+ }
+
nand_init();
serial_puts("\nStarting U-Boot ...\n");
diff --git a/board/qi/qi_lb60/usbboot.S b/board/qi/qi_lb60/usbboot.S
new file mode 100644
index 000..c872266
--- /dev/null
+++ b/board/qi/qi_lb60/usbboot.S
@@ -0,0 +1,838 @@
+/*
+ * for jz4740 usb boot
+ *
+ * Copyright (c) 2009 Author:
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+.set noreorder
+.globl usb_boot
+.text
+
+/*
+ * Both NAND and USB boot load data to D-Cache first, then transfer
+ * data from D-Cache to I-Cache, and jump to execute the code in I-Cache.
+ * So init caches first and then dispatch to a proper boot routine.
+ */
+
+.macro load_addr reg addr
+ li \reg, 0x8000
+ addiu \reg, \reg, \addr
+ la $2, usbboot_begin
+ subu \reg, \reg, $2
+.endm
+
+usb_boot:
+ /* Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz. */
+ la $9, 0xB000 /* CPCCR: Clock Control Register */
+ la $8, 0x42041110 /* I:S:M:P=1:2:2:2 */
+ sw $8, 0($9)
+
+ la $9, 0xB010 /* CPPCR: PLL Control Register */
+ la $8, 0x06000120 /* M=12 N=0 D=0 CLK=12*(M+2)/(N+2) */
+ sw $8, 0($9)
+
+ mtc0$0, $26 /* CP0_ERRCTL, restore WST reset state */
+ nop
+
+ mtc0$0, $16 /* CP0_CONFIG */
+ nop
+
+ /* Relocate code to beginning of the ram */
+
+ la $2, usbboot_begin
+ la $3, usbboot_end
+ li $4, 0x8000
+
+1:
+ lw $5, 0($2)
+ sw $5, 0($4)
+ addiu $2, $2, 4
+ bne $2, $3, 1b
+ addiu $4, $4, 4
+
+ li $2, 0x8000
+ ori $3, $2, 0
+ addiu $3, $3, usbboot_end
+ la $4, usbboot_begin
+ subu $3, $3, $4
+
+
+2:
+ cache 0x0, 0($2) /* Index_Invalidate_I */
+ cache 0x1, 0($2) /* Index_Writeback_Inv_D */
+ addiu $2, $2, 32
+ subu $4, $3, $2
+ bgtz$4, 2b
+ nop
+
+ load_addr $3, usb_boot_return
+
+ jr $3
+
+usbboot_begin:
+
+init_caches:
+ li $2, 3 /* cacheable for kseg0 access */
+ mtc0$2, $16 /* CP0_CONFIG */
+ nop
+
+ li $2, 0x2000 /* enable idx-store-data cache insn */
+ mtc0$2, $26 /* CP0_ERRCTL */
+
+ ori $2, $28, 0 /* start address */
+ ori $3, $2, 0x3fe0 /* end address, total 16KB *
[U-Boot] [PATCH v4 0/2] qi_lb60 add nand spl and usbboot support
From: Xiangfu V4: * split to 2 patches (nand spl/usbbot) * remove use define string.c using CONFIG_SPL_LIBGENERIC_SUPPORT * fix checkputch.pl warnings V3: * add simpile string.c to mips/lib * some cleanup on jz4740.c * move to new spl/ structure * support software usbboot mode Xiangfu (2): qi_lb60: add nand spl support qi_lb60: add software usbboot support arch/mips/cpu/xburst/Makefile |7 +- arch/mips/cpu/xburst/cpu.c|4 + arch/mips/cpu/xburst/jz4740.c | 84 ++-- arch/mips/cpu/xburst/spl/Makefile | 47 +++ arch/mips/cpu/xburst/spl/start.S | 65 +++ board/qi/qi_lb60/Makefile |5 + board/qi/qi_lb60/qi_lb60-spl.c| 54 +++ board/qi/qi_lb60/qi_lb60.c|6 +- board/qi/qi_lb60/u-boot-spl.lds | 62 +++ board/qi/qi_lb60/usbboot.S| 838 + drivers/mtd/nand/jz4740_nand.c| 39 +- include/configs/qi_lb60.h | 174 12 files changed, 1240 insertions(+), 145 deletions(-) create mode 100644 arch/mips/cpu/xburst/spl/Makefile create mode 100644 arch/mips/cpu/xburst/spl/start.S create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c create mode 100644 board/qi/qi_lb60/u-boot-spl.lds create mode 100644 board/qi/qi_lb60/usbboot.S -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] add nand spl boot for qi_lb60 board
From: Xiangfu Liu
* After create u-boot-spl.bin. it needs those 4 commands create final image
for jz4740 cpu.
dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync bs=8192 count=1
dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync,notrunc oflag=append
bs=8192 count=1
tr '\0' '\377' < /dev/zero | dd of=u-boot-nand.bin conv=sync,notrunc
oflag=append bs=16384 count=1
cat u-boot-nand.bin u-boot.bin > u-boot-nand-final.bin
The JZ4740 CPU can load 8KB from two different addresses:
1. the normal area up to 8KB starting from NAND flash address 0x
2. the backup area up to 8KB starting from NAND flash address 0x2000
* Add software usbboot mode
Downloads user program from the USB port to internal
SRAM and branches to the internal SRAM to execute the program.
(JZ4740 CPU have a internal ROM have such kind of code, that make
JZ4740 can boot from USB)
---
v3:
* add simpile string.c to mips/lib
* some cleanup on jz4740.c
* move to new spl/ structure
* support software usbboot mode
arch/mips/cpu/xburst/Makefile |7 +-
arch/mips/cpu/xburst/cpu.c|4 +
arch/mips/cpu/xburst/jz4740.c | 84 ++--
arch/mips/cpu/xburst/spl/Makefile | 47 ++
arch/mips/cpu/xburst/spl/start.S | 65 +++
arch/mips/lib/Makefile|4 +
arch/mips/lib/string.c| 32 ++
board/qi/qi_lb60/Makefile |5 +
board/qi/qi_lb60/qi_lb60-spl.c| 56 +++
board/qi/qi_lb60/qi_lb60.c|6 +-
board/qi/qi_lb60/u-boot-spl.lds | 62 +++
board/qi/qi_lb60/usbboot.S| 880 +
drivers/mtd/nand/jz4740_nand.c| 39 +-
include/configs/qi_lb60.h | 173
14 files changed, 1319 insertions(+), 145 deletions(-)
create mode 100644 arch/mips/cpu/xburst/spl/Makefile
create mode 100644 arch/mips/cpu/xburst/spl/start.S
create mode 100644 arch/mips/lib/string.c
create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c
create mode 100644 board/qi/qi_lb60/u-boot-spl.lds
create mode 100644 board/qi/qi_lb60/usbboot.S
diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile
index b1f2ae4..ec35e55 100644
--- a/arch/mips/cpu/xburst/Makefile
+++ b/arch/mips/cpu/xburst/Makefile
@@ -24,9 +24,12 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
+COBJS-y= cpu.o jz_serial.o
+
+ifneq ($(CONFIG_SPL_BUILD),y)
START = start.o
-SOBJS-y=
-COBJS-y= cpu.o timer.o jz_serial.o
+COBJS-y += timer.o
+endif
COBJS-$(CONFIG_JZ4740) += jz4740.o
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa..1432838 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -42,6 +42,8 @@
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
+#ifndef CONFIG_SPL_BUILD
+
void __attribute__((weak)) _machine_restart(void)
{
struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
cache_op(Hit_Invalidate_D, addr);
}
+#endif
+
void flush_icache_all(void)
{
u32 addr, t = 0;
diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c
index c0b9817..40ef411 100644
--- a/arch/mips/cpu/xburst/jz4740.c
+++ b/arch/mips/cpu/xburst/jz4740.c
@@ -32,31 +32,19 @@ int disable_interrupts(void)
return 0;
}
-/*
- * PLL output clock = EXTAL * NF / (NR * NO)
- * NF = FD + 2, NR = RD + 2
- * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
- */
void pll_init(void)
{
struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
- register unsigned int cfcr, plcr1;
- int n2FR[33] = {
- 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
- 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
- 9
- };
- int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
- int nf, pllout2;
+ register unsigned int cfcr, plcr;
+ unsigned int nf, pllout2;
cfcr = CPM_CPCCR_CLKOEN |
- CPM_CPCCR_PCS |
- (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
- (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
- (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
- (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
- (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
+ (0 << CPM_CPCCR_CDIV_BIT) |
+ (2 << CPM_CPCCR_HDIV_BIT) |
+ (2 << CPM_CPCCR_PDIV_BIT) |
+ (2 << CPM_CPCCR_MDIV_BIT) |
+ (2 << CPM_CPCCR_LDIV_BIT);
pllout2 = (cfcr & CPM_CPCCR_PCS) ?
CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
@@ -65,15 +53,18 @@ void pll_init(void)
writel(pllout2 / 4800 - 1, &cpm->uhccdr);
nf =
Re: [U-Boot] [U-Boot-DM] [PATCH 3/3] dm: mips: Fix warnings in lb60 board
Thanks Marek Vasu, Daniel Schwierzeck, Xiangfu On 08/20/2012 02:19 AM, Daniel Schwierzeck wrote: 2012/7/27 Marek Vasut : The lb60 board accesses the clkgr register, which is 32bit via 16bit IO ops. This causes malfunction. Fix this. qi_lb60.c: In function ‘cpm_init’: qi_lb60.c:72:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] qi_lb60.c:84:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut Cc: Daniel Cc: Shinya Kuribayashi Cc: Xiangfu Liu --- board/qi/qi_lb60/qi_lb60.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) applied to u-boot-mips/master, thanks ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] add nand spl boot for qi_lb60 board
Hi Scott thanks for your comments. PATCH v3 have sent out for you to review. On 01/07/2012 06:36 AM, Scott Wood wrote: We are transitioning from nand_spl/ to spl/. Please try to work within the new infrastructure. You may run into problems with size in spl/, due to gc-sections not removing strings on components you don't need -- I plan to fix those issues (for NAND), hopefully this merge window, by requiring all files to be explicitly asked for. Feel free to fix them first if you'd like. :-) I'd like to move the new spl/. I have one question about the new spl/ I didn't see the new spl/ link to nand_spl/nand_boot.c. so how the new spl/ using nand_boot()? can we add a new define 'CONFIG_SPL_START_S_NAME', since qi_lb60 using start_spl.S for SPL, not start.S. I think better I make the nand_spl/ working. then move to the new spl/ :) +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS= -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_NAND_SPL_TEXT_BASE) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL -O2 Why -O2 and not the -Os that you should already be inheriting from config.mk? when I remove the -O2. it give me error: jz4740.c:(.text.sdram_init+0x14): undefined reference to `memcpy' so I keep the -O2 there. please anyone give me some advice on how to fix this. that will be great. thanks again xiangfu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] add nand spl boot for qi_lb60 board
Signed-off-by: Xiangfu Liu
---
Changes for v2:
-Add CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-Cleanup jz4740_nand.c a little
Changes for v3:
-Remove CONFIG_NAND_SPL_TEXT_BASE, fix the wrong TEXT base under SPL u-boot.lds
-Remove overcomplicated 'dd', pad to 32KB SPL instead of 256. comments added
in Makefile
-Cleanup the qi_lb60.h
arch/mips/cpu/xburst/cpu.c |4 +
arch/mips/cpu/xburst/start_spl.S | 65 +
drivers/mtd/nand/jz4740_nand.c | 40 -
include/configs/qi_lb60.h| 166 --
nand_spl/board/qi/qi_lb60/Makefile | 124 +
nand_spl/board/qi/qi_lb60/nand_spl.c | 37
nand_spl/board/qi/qi_lb60/u-boot.lds | 62 +
7 files changed, 407 insertions(+), 91 deletions(-)
create mode 100644 arch/mips/cpu/xburst/start_spl.S
create mode 100644 nand_spl/board/qi/qi_lb60/Makefile
create mode 100644 nand_spl/board/qi/qi_lb60/nand_spl.c
create mode 100644 nand_spl/board/qi/qi_lb60/u-boot.lds
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index e976341..afd166c 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -42,6 +42,8 @@
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
+#ifndef CONFIG_NAND_SPL
+
void __attribute__((weak)) _machine_restart(void)
{
struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
cache_op(Hit_Invalidate_D, addr);
}
+#endif
+
void flush_icache_all(void)
{
u32 addr, t = 0;
diff --git a/arch/mips/cpu/xburst/start_spl.S b/arch/mips/cpu/xburst/start_spl.S
new file mode 100644
index 000..f137ccd
--- /dev/null
+++ b/arch/mips/cpu/xburst/start_spl.S
@@ -0,0 +1,65 @@
+/*
+ * Startup Code for MIPS32 XBURST CPU-core
+ *
+ * Copyright (c) 2010 Xiangfu Liu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+ .set noreorder
+
+ .globl _start
+ .text
+_start:
+ .word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
+reset:
+ /*
+* STATUS register
+* CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
+*/
+ li t0, 0x0040FC04
+ mtc0t0, CP0_STATUS
+ /*
+* CAUSE register
+* IV=1, use the specical interrupt vector (0x200)
+*/
+ li t1, 0x0080
+ mtc0t1, CP0_CAUSE
+
+ bal 1f
+nop
+ .word _GLOBAL_OFFSET_TABLE_
+1:
+ movegp, ra
+ lw t1, 0(ra)
+ movegp, t1
+
+ la sp, 0x80004000
+ la t9, nand_spl_boot
+ j t9
+nop
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index 3ec34f3..7ef07a5 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -15,6 +15,10 @@
#include
#include
+#ifdef CONFIG_NAND_SPL
+ #define printf(arg...) do {} while (0)
+#endif
+
#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB800)
#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x1)
@@ -176,7 +180,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd,
u_char *dat,
for (k = 0; k < 9; k++)
writeb(read_ecc[k], &emc->nfpar[k]);
}
- /* Set PRDY */
+
writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
/* Wait for completion */
@@ -184,7 +188,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd,
u_char *dat,
status = readl(&emc->nfints);
} while (!(status & EMC_NFINTS_DECF));
- /* disable ecc */
+ /* Disable ECC */
writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
/* Check decoding */
@@ -192,7 +196,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd,
u_char *dat,
return 0;
if (status & EMC_NFINTS_UNCOR) {
-
Re: [U-Boot] add nand spl boot for qi_lb60 board
On 01/07/2012 03:05 AM, Scott Wood wrote: > forget add CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST to board configure head > file. That still doesn't explain how a few duplicate externs changed the resulting binary... yes. strange. have no idea about this. when I have time I will compare the binary more. try to understand this. xiangfu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] add nand spl boot for qi_lb60 board
On 01/06/2012 02:44 AM, Scott Wood wrote: Use "mips-whatever-objdump -dlrsh" on the good and bad u-boot binaries (or on any .o files you suspect may be relevant), to see more specifically what's different. You may also want to try compiling suspect files to assembly and comparing the differences there. -Scott thanks Scott. a working patch is coming soon. forget add CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST to board configure head file. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] add nand spl boot for qi_lb60 board
Signed-off-by: Xiangfu Liu
---
arch/mips/cpu/xburst/cpu.c |4 +
arch/mips/cpu/xburst/start_spl.S | 65
drivers/mtd/nand/jz4740_nand.c | 40 +++-
include/configs/qi_lb60.h|3 +
nand_spl/board/qi/qi_lb60/Makefile | 112 ++
nand_spl/board/qi/qi_lb60/nand_spl.c | 37 +++
nand_spl/board/qi/qi_lb60/u-boot.lds | 63 +++
7 files changed, 321 insertions(+), 3 deletions(-)
create mode 100644 arch/mips/cpu/xburst/start_spl.S
create mode 100644 nand_spl/board/qi/qi_lb60/Makefile
create mode 100644 nand_spl/board/qi/qi_lb60/nand_spl.c
create mode 100644 nand_spl/board/qi/qi_lb60/u-boot.lds
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index e976341..afd166c 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -42,6 +42,8 @@
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
+#ifndef CONFIG_NAND_SPL
+
void __attribute__((weak)) _machine_restart(void)
{
struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
cache_op(Hit_Invalidate_D, addr);
}
+#endif
+
void flush_icache_all(void)
{
u32 addr, t = 0;
diff --git a/arch/mips/cpu/xburst/start_spl.S b/arch/mips/cpu/xburst/start_spl.S
new file mode 100644
index 000..f137ccd
--- /dev/null
+++ b/arch/mips/cpu/xburst/start_spl.S
@@ -0,0 +1,65 @@
+/*
+ * Startup Code for MIPS32 XBURST CPU-core
+ *
+ * Copyright (c) 2010 Xiangfu Liu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+ .set noreorder
+
+ .globl _start
+ .text
+_start:
+ .word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
+reset:
+ /*
+* STATUS register
+* CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
+*/
+ li t0, 0x0040FC04
+ mtc0t0, CP0_STATUS
+ /*
+* CAUSE register
+* IV=1, use the specical interrupt vector (0x200)
+*/
+ li t1, 0x0080
+ mtc0t1, CP0_CAUSE
+
+ bal 1f
+nop
+ .word _GLOBAL_OFFSET_TABLE_
+1:
+ movegp, ra
+ lw t1, 0(ra)
+ movegp, t1
+
+ la sp, 0x80004000
+ la t9, nand_spl_boot
+ j t9
+nop
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index 3ec34f3..7ef07a5 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -15,6 +15,10 @@
#include
#include
+#ifdef CONFIG_NAND_SPL
+ #define printf(arg...) do {} while (0)
+#endif
+
#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB800)
#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x1)
@@ -176,7 +180,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd,
u_char *dat,
for (k = 0; k < 9; k++)
writeb(read_ecc[k], &emc->nfpar[k]);
}
- /* Set PRDY */
+
writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
/* Wait for completion */
@@ -184,7 +188,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd,
u_char *dat,
status = readl(&emc->nfints);
} while (!(status & EMC_NFINTS_DECF));
- /* disable ecc */
+ /* Disable ECC */
writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
/* Check decoding */
@@ -192,7 +196,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd,
u_char *dat,
return 0;
if (status & EMC_NFINTS_UNCOR) {
- printf("uncorrectable ecc\n");
+ printf("JZ4740 uncorrectable ECC\n");
return -1;
}
@@ -230,6 +234,32 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd,
u_char *dat,
return errcnt;
}
+#ifdef CONFIG_NAND_SPL
+void nand_read_buf(struct mtd_info
Re: [U-Boot] add nand spl boot for qi_lb60 board
Hi yes. I have cpmpared this. but I can't find where is the problem. attachment is the u-boot.map diff. after remove those 'extern' the u-boot-nand-spl is exact same. binary file. map file both same. but the u-boot.bin/map changed. Please help me take a look. thanks Scott. xiangfu On 01/05/2012 06:12 AM, Scott Wood wrote: Or compare the resulting binaries, see what's actually changed. -Scott --- YES/u-boot.map 2012-01-01 20:41:57.020058001 +0800 +++ NO/u-boot.map 2012-01-01 20:41:13.068058002 +0800 @@ -1058,7 +1058,7 @@ 0x80118b20__ashrdi3 0x80118b60. = ALIGN (0x4) -.rodata 0x80118b60 0x5550 +.rodata 0x80118b60 0x5558 *(SORT(.rodata*)) .rodata0x80118b60 0xd0 common/libcommon.o .rodata0x80118c30 0x20 lib/libgeneric.o @@ -1157,102 +1157,102 @@ .rodata.tab_seq 0x8011e04c0xc common/libcommon.o .rodata.version_string -0x8011e058 0x38 common/libcommon.o +0x8011e058 0x40 common/libcommon.o 0x8011e058version_string .rodata.xyzModem_error -0x8011e090 0x20 common/libcommon.o +0x8011e098 0x20 common/libcommon.o -.rel.dyn0x8011e0b00x0 +.rel.dyn0x8011e0b80x0 .rel.dyn 0x0x0 arch/mips/cpu/xburst/start.o -0x8011e0b0. = ALIGN (0x4) +0x8011e0b8. = ALIGN (0x4) -.data 0x8011e0b0 0x1978 +.data 0x8011e0b8 0x1978 *(.data*) - .data.uart 0x8011e0b00x4 arch/mips/cpu/xburst/libxburst.o -0x8011e0b0uart + .data.uart 0x8011e0b80x4 arch/mips/cpu/xburst/libxburst.o +0x8011e0b8uart .data.rel.init_sequence -0x8011e0b4 0x28 arch/mips/lib/libmips.o -0x8011e0b4init_sequence +0x8011e0bc 0x28 arch/mips/lib/libmips.o +0x8011e0bcinit_sequence .data.rel.boot_os -0x8011e0dc 0x4c common/libcommon.o +0x8011e0e4 0x4c common/libcommon.o .data.rel.local.cmd_bootm_sub -0x8011e128 0x90 common/libcommon.o - .data.do_echo 0x8011e1b80x4 common/libcommon.o +0x8011e130 0x90 common/libcommon.o + .data.do_echo 0x8011e1c00x4 common/libcommon.o .data.dp_last_length -0x8011e1bc0x4 common/libcommon.o +0x8011e1c40x4 common/libcommon.o .data.load_addr -0x8011e1c00x4 common/libcommon.o -0x8011e1c0load_addr +0x8011e1c80x4 common/libcommon.o +0x8011e1c8load_addr .data.rel.cmd_env_sub -0x8011e1c4 0xc0 common/libcommon.o - .data.env_id 0x8011e2840x4 common/libcommon.o +0x8011e1cc 0xc0 common/libcommon.o + .data.env_id 0x8011e28c0x4 common/libcommon.o .data.trim_threshold -0x8011e2880x4 common/libcommon.o +0x8011e2900x4 common/libcommon.o .data.rel.local.av_ -0x8011e28c 0x408 common/libcommon.o +0x8011e294 0x408 common/libcommon.o .data.sbrk_base -0x8011e6940x4 common/libcommon.o +0x8011e69c0x4 common/libcommon.o .data.rel.local.env_name_spec -0x8011e6980x4 common/libcommon.o -0x8011e698env_name_spec +0x8011e6a00x4 common/libcommon.o +0x8011e6a0env_name_spec .data.rel.ro.local.uimage_comp -0x8011e69c 0x48 common/libcommon.o +0x8011e6a4 0x48 common/libcommon.o .data.rel.ro.local.uimage_type -0x8011e6e4 0xc0 common/libcommon.o +0x8011e6ec 0xc0 common/libcommon.o .data.rel.ro.local.uimage_arch -0x8011e7a4 0xf0 common/libcommon.o +0x8011e7ac 0xf0 common/libcommon.o .data.rel.ro.local.uimage_os -0x8011e894 0x54 common/libcommon.o +0x8011e89c 0x54 common/libcommon.o .data.r
[U-Boot] add nand spl boot for qi_lb60 board
Hi Scott Wood
this is the patch I try to add nand spl boot for qi_lb60 board
this patch works fine under qi_lb60(ben nanonote) but there are three
'extern' lines under: nand_spl/board/qi/qi_lb60/nand_spl.c
those 'extern' lines already in jz4740.h, my question is when I remove
those three lines under nand_spl/board/qi/qi_lb60/nand_spl.c, it will
make u-boot-nand.bin break. can't boot the device anymore.
Please give me some advice how to debug the error.
thanks
xiangfu
Signed-off-by: Xiangfu Liu
---
arch/mips/cpu/xburst/cpu.c |4 +
arch/mips/cpu/xburst/start_spl.S | 65
drivers/mtd/nand/jz4740_nand.c | 40 +++-
include/configs/qi_lb60.h|1 +
nand_spl/board/qi/qi_lb60/Makefile | 112 ++
nand_spl/board/qi/qi_lb60/nand_spl.c | 41
nand_spl/board/qi/qi_lb60/u-boot.lds | 63 +++
7 files changed, 323 insertions(+), 3 deletions(-)
create mode 100644 arch/mips/cpu/xburst/start_spl.S
create mode 100644 nand_spl/board/qi/qi_lb60/Makefile
create mode 100644 nand_spl/board/qi/qi_lb60/nand_spl.c
create mode 100644 nand_spl/board/qi/qi_lb60/u-boot.lds
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index e976341..afd166c 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -42,6 +42,8 @@
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
+#ifndef CONFIG_NAND_SPL
+
void __attribute__((weak)) _machine_restart(void)
{
struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
cache_op(Hit_Invalidate_D, addr);
}
+#endif
+
void flush_icache_all(void)
{
u32 addr, t = 0;
diff --git a/arch/mips/cpu/xburst/start_spl.S b/arch/mips/cpu/xburst/start_spl.S
new file mode 100644
index 000..f137ccd
--- /dev/null
+++ b/arch/mips/cpu/xburst/start_spl.S
@@ -0,0 +1,65 @@
+/*
+ * Startup Code for MIPS32 XBURST CPU-core
+ *
+ * Copyright (c) 2010 Xiangfu Liu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+ .set noreorder
+
+ .globl _start
+ .text
+_start:
+ .word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
+reset:
+ /*
+* STATUS register
+* CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
+*/
+ li t0, 0x0040FC04
+ mtc0t0, CP0_STATUS
+ /*
+* CAUSE register
+* IV=1, use the specical interrupt vector (0x200)
+*/
+ li t1, 0x0080
+ mtc0t1, CP0_CAUSE
+
+ bal 1f
+nop
+ .word _GLOBAL_OFFSET_TABLE_
+1:
+ movegp, ra
+ lw t1, 0(ra)
+ movegp, t1
+
+ la sp, 0x80004000
+ la t9, nand_spl_boot
+ j t9
+nop
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index 3ec34f3..7ef07a5 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -15,6 +15,10 @@
#include
#include
+#ifdef CONFIG_NAND_SPL
+ #define printf(arg...) do {} while (0)
+#endif
+
#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB800)
#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x1)
@@ -176,7 +180,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd,
u_char *dat,
for (k = 0; k < 9; k++)
writeb(read_ecc[k], &emc->nfpar[k]);
}
- /* Set PRDY */
+
writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
/* Wait for completion */
@@ -184,7 +188,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd,
u_char *dat,
status = readl(&emc->nfints);
} while (!(status & EMC_NFINTS_DECF));
- /* disable ecc */
+ /* Disable ECC */
writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
/* Check decoding */
@@ -192,7 +196,7
Re: [U-Boot] [PATCH] tools: checkpatch.pl from Linux added to tools
On 10/12/2011 09:41 AM, Joe Hershberger wrote: > Added from Linux - commit 30ecad51849ae132dc6ef6ddb62d499c7257515b > > Include config file to ignore common false-positives great thanks Joe. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7 0/3] those series patches for add ben nanonote board
On 10/02/2011 09:52 PM, Shinya Kuribayashi wrote: > Hi, > > Here's seventh patchset for Ben NanoNote initial support. I've been > working with Xiangfu past six months to polish v6 patches. We have > addressed all comments from Wolfgang and Scott so far, drop nand_spl > and USB_boot functions to make the initial bring-up minimum and simple. > > I think the patchset is now in good shape, so will merge and make a > pull-request during this merge window. Please give it a final review > and if something to fix, please let us know. > thanks Shinya. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 4/7] jz4740 nand driver
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/26/2011 12:04 AM, Scott Wood wrote: >> hmm... some question. a little confuse. >> > >> > 1. I using all rest of nand as rootfs partition. >> >do I have keep some space in nand for BBT? > The last block or so is marked reserved for the BBT. > >> > 2. do I have to tell u-boot where is the BBT? > No, it's marked with a special OOB marker. If it isn't present, it will > create it at the end of the chip. > >> > 3. do I need some configure in linux kernel for BBT? > Set the nand->options flag, same as in U-Boot. > thanks for the info. will enable the BBT in next series patches - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk222o4ACgkQRRAEFRxkgLQOmgCfSfL0iN6BY0TlDcg9jbUiSnen VukAnA1pE4d3YnZwA5nLRQbPUv2tecXR =d/2S -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 4/7] jz4740 nand driver
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/23/2011 12:10 AM, Scott Wood wrote: >> I have tried to move those 'usb_boot' to board files. the only problem is >> > I have to run this 'usb_boot' very early. after CPU load the real u-boot >> > to memory >> > the usb_boot will not working. I will try to found more info about this. >> > then explain more in next email. > OK, so you need to run it during the SPL phase -- but there should be > some board/cpu-specific file for the SPL (if not, create one). > > Current examples of this > include nand_spl/board/freescale/p1_p2_rdb/nand_boot.c and > arch/powerpc/cpu/mpc83xx/nand_init.c. > Hi Scott Wood thanks for the info. for speed up I think I will remove the usbboot and nandboot SPL in those patches series. I am NOT SOTP working on that. I will try to implement them in next series patches and will include the mmc/lcd/nandSPL source code in next serial patches. thanks again. - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk222lMACgkQRRAEFRxkgLSMaACgrOofX/zJNpNp1e1WvhTVyAl3 64kAoIvIx38HasmCmqer2FXzoKPKlagH =Qmft -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 4/7] jz4740 nand driver
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/08/2011 07:44 AM, Scott Wood wrote: > You don't set nand->options... > > Don't you want a bad block table? > hmm... some question. a little confuse. 1. I using all rest of nand as rootfs partition. do I have keep some space in nand for BBT? 2. do I have to tell u-boot where is the BBT? 3. do I need some configure in linux kernel for BBT? - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk2MXZ0ACgkQRRAEFRxkgLTxoACePzD7G02iYng9GEHkbEWw4Ndk 6tgAn26gxUBbZK+hVJQSqnpL15GafZcA =bIOO -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 7/7] modify files for ben nanonote board
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/15/2011 11:16 AM, Shinya Kuribayashi wrote: > You added targets with the same name to two places. In this case, > boards.cfg will be used to configure qi_lb60. All MIPS targets can > be configured through boards.cfg now, so please 1) remove $(TOPDIR)/ > Makefile part, and 2) get 'qi_lb60' entry work as expected, instead. thanks for the info. fixed. send the patches later today - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk2MWxQACgkQRRAEFRxkgLTE8ACgw1I/fOPkebQqzknd7uLqRzRn WlMAn277HMxQbepuRM2uArCns7hVodD8 =iibd -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 4/7] jz4740 nand driver
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/08/2011 07:44 AM, Scott Wood wrote: >> +#if defined(CONFIG_QI_LB60) >> > +#define KEY_U_OUT (32 * 2 + 16) >> > +#define KEY_U_IN(32 * 3 + 19) >> > + __gpio_as_input(KEY_U_IN); >> > + __gpio_enable_pull(KEY_U_IN); >> > + __gpio_as_output(KEY_U_OUT); >> > + __gpio_clear_pin(KEY_U_OUT); >> > + >> > + if (__gpio_get_pin(KEY_U_IN) == 0) >> > + usb_boot(); >> > +#endif >> > +#endif > This stuff does not belong in the NAND driver; it belongs under your board > or cpu directory. > I have tried to move those 'usb_boot' to board files. the only problem is I have to run this 'usb_boot' very early. after CPU load the real u-boot to memory the usb_boot will not working. I will try to found more info about this. then explain more in next email. thanks Scott Wood for your feedback. I will keeping working. until the code is good enough :) - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk2IWZcACgkQRRAEFRxkgLTVvwCfaw7jKe7ZVzycMS+gN2lFdV2t mEYAoIFahfXxtoiXs565cuN4vAuDdlIR =tdrU -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 2/7] this is jz4740 head file
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/15/2011 10:27 AM, Shinya Kuribayashi wrote: > This is used by files in PATCH v6 1/7. Please fold > this patch into the v6 1/7. That should be ok. ok. will do that in next patches. thanks again - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk2IWJEACgkQRRAEFRxkgLRP0wCeIQOwWuYAiODMuN5mlVtSMXt7 YYwAnjs6C7ljE5Rl1RZAe6u2AYG4T8sL =gAnu -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 1/7] those files are jz4740 base files
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/15/2011 10:26 AM, Shinya Kuribayashi wrote: >> +++ b/arch/mips/cpu/xburst/jz_serial.c > [...] >> > +/* >> > + * serial_init - initialize a channel >> > + * >> > + * This routine initializes the number of data bits, parity >> > + * and set the selected baud rate. Interrupts are disabled. >> > + * Set the modem control signals if the option is selected. >> > + * >> > + * RETURNS: N/A >> > + */ >> > +struct jz4740_uart *uart = (struct jz4740_uart *) CONFIG_SYS_UART_BASE; >> > + > Can we make this static? yes. sure. thanks for point out - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk2IWHcACgkQRRAEFRxkgLRs5wCfftxO5qxhizl9V//tIKZu7qZz F68AnjWK9zwRCKcH1jtGlMF5bblGNZDJ =CxrY -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 1/7] those files are jz4740 base files
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/15/2011 10:38 AM, Shinya Kuribayashi wrote: > Please pay more attention to coding style issues. > - Comments with multiple lines > - Trailing whitespaces > - Inconsistent tab and space usages > - Follow the basic Linux CodingStyle guide > > and so on. thanks for your patch. I will fix the others. by the way is there a tools can check those things? - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk2IWFYACgkQRRAEFRxkgLRD6gCdHkGTEkkR3yRPDwUBIr6xzGnq 7sgAmQFtIiOHuXlJ5iIkZLM7tIOL6H62 =OrTO -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 7/7] modify files for ben nanonote board
modify files for ben nanonote board
Signed-off-by: Xiangfu Liu
Acked-by: Daniel
---
Changes for v6
- add some static data needed by timer.c
MAKEALL |4 +++-
Makefile| 13 +
arch/mips/include/asm/global_data.h | 15 +++
arch/mips/lib/board.c |8
arch/mips/lib/time.c|2 ++
5 files changed, 41 insertions(+), 1 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index a732e6a..7297367 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -530,7 +530,9 @@ LIST_mips=" \
## MIPS Systems(little endian)
#
-LIST_mips4kc_el=""
+LIST_mips4kc_el=" \
+ qi_lb60
+"
LIST_mips5kc_el=""
diff --git a/Makefile b/Makefile
index dc2e3d8..758daf2 100644
--- a/Makefile
+++ b/Makefile
@@ -1093,6 +1093,19 @@ smdk6400_config : unconfig
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
#
+# MIPS
+#
+#
+## MIPS32 XBurst jz4740
+#
+qi_lb60_config : unconfig
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+ @echo "Compile NAND boot image for QI LB60"
+ @$(MKCONFIG) -a qi_lb60 mips xburst nanonote xburst
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
+#
# Nios
#
diff --git a/arch/mips/include/asm/global_data.h
b/arch/mips/include/asm/global_data.h
index 271a290..c65a6d5 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -39,6 +39,21 @@
typedefstruct global_data {
bd_t*bd;
unsigned long flags;
+#if defined(CONFIG_JZSOC)
+/* There are other clocks in the jz4740 */
+unsigned long cpu_clk;/* CPU core clock */
+unsigned long sys_clk;/* System bus clock */
+unsigned long per_clk;/* Peripheral bus clock */
+unsigned long mem_clk;/* Memory bus clock */
+unsigned long dev_clk;/* Device clock */
+unsigned long fb_base;/* base address of framebuffer */
+ /* "static data" needed by most of timer.c */
+ unsigned long timer_rate_hz;
+ unsigned long tbl;
+ unsigned long tbu;
+ unsigned long long timer_reset_value;
+ unsigned long lastinc;
+#endif
unsigned long baudrate;
unsigned long have_console; /* serial_init() was called */
phys_size_t ram_size; /* RAM size */
diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
index f317124..9115055 100644
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
@@ -136,10 +136,18 @@ static int init_baudrate (void)
* argument, and returns an integer return code, where 0 means
* "continue" and != 0 means "fatal error, hang the system".
*/
+
+#if defined(CONFIG_JZSOC)
+extern int jzsoc_init(void);
+#endif
+
typedef int (init_fnc_t) (void);
init_fnc_t *init_sequence[] = {
board_early_init_f,
+#if defined(CONFIG_JZSOC)
+ jzsoc_init, /* init gpio/clocks/dram etc. */
+#endif
timer_init,
env_init, /* initialize environment */
#ifdef CONFIG_INCA_IP
diff --git a/arch/mips/lib/time.c b/arch/mips/lib/time.c
index 0e66441..653be6c 100644
--- a/arch/mips/lib/time.c
+++ b/arch/mips/lib/time.c
@@ -24,6 +24,7 @@
#include
#include
+#ifndef CONFIG_JZSOC
static unsigned long timestamp;
/* how many counter cycles in a jiffy */
@@ -96,3 +97,4 @@ ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}
+#endif
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 6/7] add entry to MAINTAINERS and boards.cfg
add entry to MAINTAINERS and boards.cfg Signed-off-by: Xiangfu Liu Acked-by: Daniel --- Changes for v4: - add Entry to MAINTAINERS and boards.cfg - add ben nanonote(qi_lb60) to Makefile - tested with CROSS_COMPILE=mips_4KCle- ./MAKEALL mips_el MAINTAINERS |4 boards.cfg |1 + 2 files changed, 5 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4756f14..e6d571b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -932,6 +932,10 @@ Stefan Roese vct_xxx MIPS32 4Kc +Xiangfu Liu + + qi_lb60 MIPS32 jz4740 + # # Nios-II Systems: # # # diff --git a/boards.cfg b/boards.cfg index 45c3102..cb8c6a0 100644 --- a/boards.cfg +++ b/boards.cfg @@ -243,6 +243,7 @@ vct_platinumavc mipsmipsvct microna vct_platinumavc_smallmipsmipsvct micronas - vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE vct_platinumavc_onenand mipsmipsvct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND vct_platinumavc_onenand_small mips mipsvct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE +qi_lb60 mipsmips PCI5441 nios2 nios2 pci5441 psyent PK1C20 nios2 nios2 pk1c20 psyent EVB64260 powerpc 74xx_7xxevb64260- - EVB64260 -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 5/7] add Ben NanoNote board
add ben nanonote board files
Signed-off-by: Xiangfu Liu
Acked-by: Daniel
---
Changes for v6
- clean up config files a little
board/xburst/nanonote/Makefile| 45 +++
board/xburst/nanonote/config.mk | 31 +
board/xburst/nanonote/nanonote.c | 95 +++
board/xburst/nanonote/u-boot-nand.lds | 63 ++
include/configs/nanonote.h| 205 +
include/configs/qi_lb60.h | 34 ++
6 files changed, 473 insertions(+), 0 deletions(-)
create mode 100644 board/xburst/nanonote/Makefile
create mode 100644 board/xburst/nanonote/config.mk
create mode 100644 board/xburst/nanonote/nanonote.c
create mode 100644 board/xburst/nanonote/u-boot-nand.lds
create mode 100644 include/configs/nanonote.h
create mode 100644 include/configs/qi_lb60.h
diff --git a/board/xburst/nanonote/Makefile b/board/xburst/nanonote/Makefile
new file mode 100644
index 000..2f5b4be
--- /dev/null
+++ b/board/xburst/nanonote/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor,
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/xburst/nanonote/config.mk b/board/xburst/nanonote/config.mk
new file mode 100644
index 000..858e6a2
--- /dev/null
+++ b/board/xburst/nanonote/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2006 Qi Hardware, Inc.
+# Author: Xiangfu Liu
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
+#
+
+ifndef TEXT_BASE
+# ROM version
+# TEXT_BASE = 0x8800
+
+# RAM version
+TEXT_BASE = 0x8010
+endif
diff --git a/board/xburst/nanonote/nanonote.c b/board/xburst/nanonote/nanonote.c
new file mode 100644
index 000..9cbe5e0
--- /dev/null
+++ b/board/xburst/nanonote/nanonote.c
@@ -0,0 +1,95 @@
+/*
+ * Authors: Xiangfu Liu
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_init(void)
+{
+ /* Initialize NAND Flash Pins */
+ __gpio_as_nand();
+
+ /* Initialize SDRAM pins */
+ __gpio_as_sdram_16bit_4720();
+
+ /* Initialize LCD pins */
+ __gpio_as_lcd_18bit();
+
+ /* Initialize MSC pins */
+ __gpio_as_msc();
+
+ /* Initialize Other pins */
+ unsigned int i;
+ for (i = 0; i < 7; i++){
+ __gpio_as_input(GPIO_KEYIN_BASE + i);
+ __gpio_enable_pull(GPIO_KEYIN_BASE + i);
+ }
+
+ for (i = 0; i < 8; i++) {
+ __gpio_as_output(GPIO_KEYOUT_BASE + i);
+ __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
+ }
+
+ __gpio_as_input(GPIO_KEYIN_8);
+ __gpio_enable_pull(GPIO_KEYIN_8);
+
+ /* enable the TP4, TP5 as UART0 */
+ __gpio_jtag_to_uart0();
+
+ __gpio_as_
[U-Boot] [PATCH v6 4/7] jz4740 nand driver
jz4740 nand driver
Signed-off-by: Xiangfu Liu
Acked-by: Daniel
---
Changes for v3
- use proper I/O accessors to access registers.
- don't breaks the 80-charcter-wide rule
- remove C++ comments, cleanup code style.
Changes for v6
- delete all base + offset. using C struct and proper I/O accressors
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/jz4740_nand.c | 329
2 files changed, 330 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/jz4740_nand.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 8b598f6..bf2a8f9 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -50,6 +50,7 @@ COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
+COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
endif
COBJS := $(COBJS-y)
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
new file mode 100644
index 000..a7d16e3
--- /dev/null
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -0,0 +1,329 @@
+/*
+ * Platform independend driver for JZ4740.
+ *
+ * Copyright (c) 2007 Ingenic Semiconductor Inc.
+ * Author:
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+#include
+
+#include
+#include
+#include
+
+#ifdef CONFIG_NAND_SPL
+#define printf(arg...) do {} while (0)
+#endif
+
+#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB800)
+#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
+#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x1)
+
+#define BIT(x) (1 << (x))
+#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
+#define JZ_NAND_ECC_CTRL_RSBIT(2)
+#define JZ_NAND_ECC_CTRL_RESET BIT(1)
+#define JZ_NAND_ECC_CTRL_ENABLEBIT(0)
+
+#define EMC_SMCR1_OPT_NAND 0x094c4400
+/* Optimize the timing of nand */
+
+static struct jz4740_emc * emc = (struct jz4740_emc *) JZ4740_EMC_BASE;
+
+static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
+ .eccbytes = 72,
+ .eccpos = {
+ 12, 13, 14, 15, 16, 17, 18, 19,
+ 20, 21, 22, 23, 24, 25, 26, 27,
+ 28, 29, 30, 31, 32, 33, 34, 35,
+ 36, 37, 38, 39, 40, 41, 42, 43,
+ 44, 45, 46, 47, 48, 49, 50, 51,
+ 52, 53, 54, 55, 56, 57, 58, 59,
+ 60, 61, 62, 63, 64, 65, 66, 67,
+ 68, 69, 70, 71, 72, 73, 74, 75,
+ 76, 77, 78, 79, 80, 81, 82, 83},
+ .oobfree = {
+ {.offset = 2,
+.length = 10},
+ {.offset = 84,
+.length = 44}}
+};
+
+#ifdef CONFIG_NAND_SPL
+#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3)
+ #define NAND_BUS_WIDTH 8
+ #define NAND_ROW_CYCLE 3
+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2)
+ #define NAND_BUS_WIDTH 8
+ #define NAND_ROW_CYCLE 2
+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3)
+ #define NAND_BUS_WIDTH 16
+ #define NAND_ROW_CYCLE 3
+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2)
+ #define NAND_BUS_WIDTH 16
+ #define NAND_ROW_CYCLE 2
+#endif
+
+static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ int i;
+ struct nand_chip *this = mtd->priv;
+#if NAND_BUS_WIDTH == 16
+ for (i = 0; i < len; i += 2)
+ buf[i] = readw(this->IO_ADDR_R);
+#elif NAND_BUS_WIDTH == 8
+ for (i = 0; i < len; i++)
+ buf[i] = readb(this->IO_ADDR_R);
+#endif
+}
+
+static u_char nand_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *this = mtd->priv;
+ return readb(this->IO_ADDR_R);
+}
+#endif
+
+static int is_reading;
+
+static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if (ctrl & NAND_ALE)
+ this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
+ else if (ctrl & NAND_CLE)
+ this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
+ else
+ this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
+
+ if (ctrl & NAND_NCE)
+ writel(readl(&emc->nfcsr) | EMC_NFCSR_NFCE1,
&emc->nfcsr);
+ else
+ writel(readl(&emc->nfcsr) & ~EMC_NFCSR_NFCE1,
&emc->nfcsr);
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+static int jz_nand_device_ready(struct mtd_info *mtd)
+{
+ return (readl(GPIO_PXPIN(2)) & 0x4000) ? 1 : 0;
+}
+
+void board_nand_select_device(str
[U-Boot] [PATCH v6 2/7] this is jz4740 head file
this is jz4740 base head file Signed-off-by: Xiangfu Liu Acked-by: Daniel --- Changes for v2: - remove useless code, prepare for using io.h - delete all base + offset. using C struct arch/mips/include/asm/jz4740.h | 1102 1 files changed, 1102 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/jz4740.h diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h new file mode 100644 index 000..e9209f6 --- /dev/null +++ b/arch/mips/include/asm/jz4740.h @@ -0,0 +1,1102 @@ +/* + * head file for Ingenic Semiconductor's JZ4740 CPU. + */ +#ifndef __JZ4740_H__ +#define __JZ4740_H__ + +#include +#include + +/* Boot ROM Specification */ +/* NOR Boot config */ +#define JZ4740_NORBOOT_8BIT0x /* 8-bit data bus flash */ +#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ +#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ +/* NAND Boot config */ +#define JZ4740_NANDBOOT_B8R3 0x /* 8-bit bus & 3 row cycles */ +#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ +#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ +#define JZ4740_NANDBOOT_B16R2 0x /* 16-bit bus & 2 row cycles */ + +/* 1st-level interrupts */ +#define JZ4740_IRQ_I2C 1 +#define JZ4740_IRQ_UHC 3 +#define JZ4740_IRQ_UART0 9 +#define JZ4740_IRQ_SADC12 +#define JZ4740_IRQ_MSC 14 +#define JZ4740_IRQ_RTC 15 +#define JZ4740_IRQ_SSI 16 +#define JZ4740_IRQ_CIM 17 +#define JZ4740_IRQ_AIC 18 +#define JZ4740_IRQ_ETH 19 +#define JZ4740_IRQ_DMAC20 +#define JZ4740_IRQ_TCU221 +#define JZ4740_IRQ_TCU122 +#define JZ4740_IRQ_TCU023 +#define JZ4740_IRQ_UDC 24 +#define JZ4740_IRQ_GPIO3 25 +#define JZ4740_IRQ_GPIO2 26 +#define JZ4740_IRQ_GPIO1 27 +#define JZ4740_IRQ_GPIO0 28 +#define JZ4740_IRQ_IPU 29 +#define JZ4740_IRQ_LCD 30 +/* 2nd-level interrupts */ +#define JZ4740_IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ +#define JZ4740_IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ + +/* Register Definitions */ +#defineJZ4740_CPM_BASE 0x1000 +#defineJZ4740_INTC_BASE0x10001000 +#defineJZ4740_TCU_BASE 0x10002000 +#defineJZ4740_WDT_BASE 0x10002000 +#defineJZ4740_RTC_BASE 0x10003000 +#defineJZ4740_GPIO_BASE0x1001 +#defineJZ4740_AIC_BASE 0x1002 +#defineJZ4740_ICDC_BASE0x1002 +#defineJZ4740_MSC_BASE 0x10021000 +#defineJZ4740_UART0_BASE 0x1003 +#defineJZ4740_I2C_BASE 0x10042000 +#defineJZ4740_SSI_BASE 0x10043000 +#defineJZ4740_SADC_BASE0x1007 +#defineJZ4740_EMC_BASE 0x1301 +#defineJZ4740_DMAC_BASE0x1302 +#defineJZ4740_UHC_BASE 0x1303 +#defineJZ4740_UDC_BASE 0x1304 +#defineJZ4740_LCD_BASE 0x1305 +#defineJZ4740_SLCD_BASE0x1305 +#defineJZ4740_CIM_BASE 0x1306 +#defineJZ4740_ETH_BASE 0x1310 + +/* 8bit Mode Register of SDRAM bank 0 */ +#define JZ4740_EMC_SDMR0 (JZ4740_EMC_BASE + 0xa000) + +/* GPIO (General-Purpose I/O Ports) */ +/* = 0,1,2,3 */ +#define GPIO_PXPIN(n) (JZ4740_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */ +#define GPIO_PXDAT(n) (JZ4740_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */ +#define GPIO_PXDATS(n) (JZ4740_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */ +#define GPIO_PXDATC(n) (JZ4740_GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */ +#define GPIO_PXIM(n) (JZ4740_GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */ +#define GPIO_PXIMS(n) (JZ4740_GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */ +#define GPIO_PXIMC(n) (JZ4740_GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */ +#define GPIO_PXPE(n) (JZ4740_GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */ +#define GPIO_PXPES(n) (JZ4740_GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */ +#define GPIO_PXPEC(n) (JZ4740_GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */ +#define GPIO_PXFUN(n) (JZ4740_GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */ +#define GPIO_PXFUNS(n) (JZ4740_GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */ +#define GPIO_PXFUNC(n) (JZ4740_GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */ +#define GPIO_PXSEL(n) (JZ4740_GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */ +#define GPIO_PXSELS(n) (JZ4740_GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */ +
[U-Boot] [PATCH v6 3/7] jz4740 nand spl files
ben nanonote nand spl files
Signed-off-by: Xiangfu Liu
Acked-by: Daniel
---
Changes for v3
- use proper I/O accessors to access registers.
Changes for v5
- remove nand_spl/nand_boot_jz4740.c
- some cleanup
Changes for v6
- delete all base + offset. using C struct
nand_spl/board/xburst/nanonote/Makefile | 106 +
nand_spl/board/xburst/nanonote/u-boot.lds | 63 +
2 files changed, 169 insertions(+), 0 deletions(-)
create mode 100644 nand_spl/board/xburst/nanonote/Makefile
create mode 100644 nand_spl/board/xburst/nanonote/u-boot.lds
diff --git a/nand_spl/board/xburst/nanonote/Makefile
b/nand_spl/board/xburst/nanonote/Makefile
new file mode 100644
index 000..9775d14
--- /dev/null
+++ b/nand_spl/board/xburst/nanonote/Makefile
@@ -0,0 +1,106 @@
+#
+# (C) Copyright 2006
+# Stefan Roese, DENX Software Engineering, s...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS= -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_NAND_SPL_TEXT_BASE)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL -O2
+
+SOBJS = start.o usbboot.o
+COBJS = nand_boot.o cpu.o jz4740.o jz_serial.o jz4740_nand.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj:= $(OBJTREE)/nand_spl/
+
+ALL= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin
$(nandobj)u-boot-spl-16k.bin
+all: $(obj).depend $(ALL)
+
+#The boot program can load two areas of data from NAND flash to internal SRAM,
one is the normal
+#area up to 8KB starting from NAND flash address 0, the other is the backup
area up to 8KB starting
+#from NAND flash address 0x2000. After reset, the boot program will first read
the normal area data
+#from NAND flash using hardware Reed-Solomon ECC. If no ECC error is detected
or ECC error is
+#correctable, the boot program then branches to internal SRAM at 4 bytes
offset. If it detects an
+#uncorrectable ECC error, it will continue to read the backup area of data
from NAND flash using
+#hardware Reed-Solomon ECC.
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
+ dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
+ cat $< $(nandobj)junk1 > $(nandobj)junk2
+ dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
+ cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
+ dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
+ cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
+ dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
+ rm -f $(nandobj)junk*
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+$(obj)start.S:
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $@
+
+$(obj)usbboot.S:
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/usbboot.S $@
+
+$(obj)cpu.c:
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/cpu.c $@
+
+$(obj)jz4740.c:
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz4740.c $@
+
+$(obj)jz_serial.c:
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $@
+
+$(obj)nand_boot.c:
+ @rm -f $@
+ ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
+
+$(obj)jz4740_nand.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/drivers/mtd/nand/jz4740_nand.c $@
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/nand_spl/board/xburst/nanonote/u-boot.lds
b/nand_spl/board/xburst/nanonote/u-boot.lds
new file mode 100644
index 000..7042388
--- /dev/null
+++ b/nand_spl/board/xburst/nanonote/u-boot.lds
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2005
+ * Ingenic Semiconduc
[U-Boot] [PATCH v6 1/7] those files are jz4740 base files
those files are jz4740 base files this xburst jz4740 cpu have one feature is Boot From USB, there is a small rom in jz4740, the cpu can boot to this small rom, then init cpu and USB module, then we can send 8KB bin file to the cpu cache by using 'xbboot' or 'usbboot', Debian package named xburst-tools. for more info about Ingenic Xburst JZ4740 http://www.ingenic.cn/eng/default.aspx http://www.linux-mips.org/wiki/Ingenic http://en.qi-hardware.com Signed-off-by: Xiangfu Liu Acked-by: Daniel --- Changes for v2: - add jz4740 soc description Changes for v3: - remove the ENDIANNESS in config.mk - don't breaks the 80-charcter-wide rule - get rid of #if 0 - use proper I/O accessors to access registers. - remove C++ comments, cleanup code style. Changes for v6: - delete all base + offset. using C struct and proper I/O accressors arch/mips/cpu/xburst/Makefile| 50 +++ arch/mips/cpu/xburst/config.mk | 33 ++ arch/mips/cpu/xburst/cpu.c | 160 arch/mips/cpu/xburst/jz4740.c| 264 arch/mips/cpu/xburst/jz_serial.c | 114 + arch/mips/cpu/xburst/start.S | 160 arch/mips/cpu/xburst/start_spl.S | 63 +++ arch/mips/cpu/xburst/timer.c | 167 arch/mips/cpu/xburst/usbboot.S | 841 ++ 9 files changed, 1852 insertions(+), 0 deletions(-) create mode 100644 arch/mips/cpu/xburst/Makefile create mode 100644 arch/mips/cpu/xburst/config.mk create mode 100644 arch/mips/cpu/xburst/cpu.c create mode 100644 arch/mips/cpu/xburst/jz4740.c create mode 100644 arch/mips/cpu/xburst/jz_serial.c create mode 100644 arch/mips/cpu/xburst/start.S create mode 100644 arch/mips/cpu/xburst/start_spl.S create mode 100644 arch/mips/cpu/xburst/timer.c create mode 100644 arch/mips/cpu/xburst/usbboot.S diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile new file mode 100644 index 000..a9a6e77 --- /dev/null +++ b/arch/mips/cpu/xburst/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).o + +START = start.o +SOBJS-y= +COBJS-y = cpu.o timer.o jz_serial.o + +COBJS-$(CONFIG_JZ4740) += jz4740.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk new file mode 100644 index 000..fc9b255 --- /dev/null +++ b/arch/mips/cpu/xburst/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2) +MIPSFLAGS:=$(shell \ +if [ "$v" -lt "14" ]; then \ + echo "-mcpu=4kc"; \ +else \ + echo "-march=4kc -mtune=4kc"; \ +fi) + +MIPSFLAGS += -mab
[U-Boot] [PATCH v6 0/7] those series patches for add ben nanonote board
Hi Wolfgang those patches are for add xburst jz4740 base file and Ben NanoNote (codename qi_lb60) to U-Boot some info about xburst jz4740: the xburst jz4740 is recently added to linux 2.6.36 and it's support the device Ben NanoNote out of box, this xburst jz4740 cpu have one feature is Boot From USB, there is a small rom in jz4740, but LOW some PIN, the cpu will boot to this small rom, then init cpu and USB module, then we can send 8KB bin file to the cpu by USB(by using 'xbboot' or 'usbboot'[1]). which means if your bootloader is borken,(the first few KBs in NAND) you can always boot the device from usb, then reflash the nand. in OpenMoko FreeRunner, there are NOR and NAND. when people broken the nand bootloader, it's must boot from NOR, reflash the bootloader back when people broken the NAND and NOR, he(she) must reflash by using JTAG but in Ben NanoNote, we just need boot from usb. flash the nand again :) BTW:there are a lot of PMP, Audio device in China use the Xburst cpu, but I think they are all base on u-boot 1.1.6. by working on Ben NanoNote (http://en.qi-hardware.com) one year, we try to update the u-boot to last version and send it to upstream. :) for more info about Ingenic Xburst JZ4740 http://www.ingenic.cn/eng/default.aspx http://www.linux-mips.org/wiki/Ingenic Xiangfu Liu (7): those files are jz4740 base files this is jz4740 head file jz4740 nand spl files jz4740 nand driver add Ben NanoNote board add entry to MAINTAINERS and boards.cfg modify files for ben nanonote board MAINTAINERS |4 + MAKEALL |4 +- Makefile | 13 + arch/mips/cpu/xburst/Makefile | 50 ++ arch/mips/cpu/xburst/config.mk| 33 + arch/mips/cpu/xburst/cpu.c| 160 + arch/mips/cpu/xburst/jz4740.c | 264 +++ arch/mips/cpu/xburst/jz_serial.c | 114 +++ arch/mips/cpu/xburst/start.S | 160 + arch/mips/cpu/xburst/start_spl.S | 63 ++ arch/mips/cpu/xburst/timer.c | 167 + arch/mips/cpu/xburst/usbboot.S| 841 ++ arch/mips/include/asm/global_data.h | 15 + arch/mips/include/asm/jz4740.h| 1102 + arch/mips/lib/board.c |8 + arch/mips/lib/time.c |2 + board/xburst/nanonote/Makefile| 45 ++ board/xburst/nanonote/config.mk | 31 + board/xburst/nanonote/nanonote.c | 95 +++ board/xburst/nanonote/u-boot-nand.lds | 63 ++ boards.cfg|1 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/jz4740_nand.c| 329 + include/configs/nanonote.h| 205 ++ include/configs/qi_lb60.h | 34 + nand_spl/board/xburst/nanonote/Makefile | 106 +++ nand_spl/board/xburst/nanonote/u-boot.lds | 63 ++ 27 files changed, 3972 insertions(+), 1 deletions(-) create mode 100644 arch/mips/cpu/xburst/Makefile create mode 100644 arch/mips/cpu/xburst/config.mk create mode 100644 arch/mips/cpu/xburst/cpu.c create mode 100644 arch/mips/cpu/xburst/jz4740.c create mode 100644 arch/mips/cpu/xburst/jz_serial.c create mode 100644 arch/mips/cpu/xburst/start.S create mode 100644 arch/mips/cpu/xburst/start_spl.S create mode 100644 arch/mips/cpu/xburst/timer.c create mode 100644 arch/mips/cpu/xburst/usbboot.S create mode 100644 arch/mips/include/asm/jz4740.h create mode 100644 board/xburst/nanonote/Makefile create mode 100644 board/xburst/nanonote/config.mk create mode 100644 board/xburst/nanonote/nanonote.c create mode 100644 board/xburst/nanonote/u-boot-nand.lds create mode 100644 drivers/mtd/nand/jz4740_nand.c create mode 100644 include/configs/nanonote.h create mode 100644 include/configs/qi_lb60.h create mode 100644 nand_spl/board/xburst/nanonote/Makefile create mode 100644 nand_spl/board/xburst/nanonote/u-boot.lds ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/8] those files are jz4740 base files
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi find out. using global_data. On 02/28/2011 12:54 PM, Xiangfu Liu wrote: >>>> +static ulong timestamp; >>>> >> > +static ulong lastdec; >> > As already has been pointed out several times before: this will not >> > work because BSS cannot be accessed before relocation. >> > >> > > can you give me some tips how to fix this? > > thanks > - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk1rQlQACgkQRRAEFRxkgLTzBgCdH/ijv6fHispAkQxoppfX5qSO 9IMAnR2nW6nZVz7OFjPZ7aZ38SlZsb/d =rg9P -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/8] those files are jz4740 base files
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Wolfgang Denk On 01/18/2011 05:35 AM, Wolfgang Denk wrote: > Please do not use base + offset notation. Declare a proper C struct > instead. Please fix globally. > >> > + /* Disable port interrupts while changing hardware */ >> > + *uart_ier = 0; > And use proper I/O accessors to access device registers. Please fix > globally. I have delete all base + offset. using C struct now. and using proper I/O accressors > > ... >> > +static ulong timestamp; >> > +static ulong lastdec; > As already has been pointed out several times before: this will not > work because BSS cannot be accessed before relocation. > > can you give me some tips how to fix this? thanks - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk1rKpAACgkQRRAEFRxkgLTsFwCbBXgBNGik7HRZpdqEaUGQWni4 F4oAnjCE/5HzHaTt8Rn1lSziHKhpGQyv =ILT1 -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 8/8] add software usbboot
Signed-off-by: Xiangfu Liu Acked-by: Daniel Acked-by: ChangWei Jia --- drivers/mtd/nand/jz4740_nand.c | 12 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c index 32b41ef..b15c4ea 100644 --- a/drivers/mtd/nand/jz4740_nand.c +++ b/drivers/mtd/nand/jz4740_nand.c @@ -285,6 +285,18 @@ extern int serial_init(void); pll_init(); serial_init(); sdram_init(); + +#if defined(CONFIG_NANONOTE) +#define KEY_U_OUT (32 * 2 + 16) +#define KEY_U_IN(32 * 3 + 19) + __gpio_as_input(KEY_U_IN); + __gpio_enable_pull(KEY_U_IN); + __gpio_as_output(KEY_U_OUT); + __gpio_clear_pin(KEY_U_OUT); + + if (__gpio_get_pin(KEY_U_IN) == 0) + usb_boot(); +#endif #endif uint32_t reg; -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 7/8] modify files for ben nanonote board
Signed-off-by: Xiangfu Liu
Acked-by: Daniel
Acked-by: ChangWei Jia
---
MAKEALL |4 +++-
Makefile| 10 ++
arch/mips/include/asm/global_data.h |9 +
arch/mips/lib/board.c |8
arch/mips/lib/time.c|2 ++
5 files changed, 32 insertions(+), 1 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index a732e6a..7297367 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -530,7 +530,9 @@ LIST_mips=" \
## MIPS Systems(little endian)
#
-LIST_mips4kc_el=""
+LIST_mips4kc_el=" \
+ qi_lb60
+"
LIST_mips5kc_el=""
diff --git a/Makefile b/Makefile
index 9055028..838bd23 100644
--- a/Makefile
+++ b/Makefile
@@ -1176,6 +1176,16 @@ qemu_mips_config : unconfig
@echo "#define CONFIG_QEMU_MIPS 1" >$(obj)include/config.h
@$(MKCONFIG) -a qemu-mips mips mips qemu-mips
+#
+## MIPS32 XBurst jz4740
+#
+qi_lb60_config : unconfig
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+ @echo "Compile NAND boot image for QI LB60"
+ @$(MKCONFIG) -a qi_lb60 mips xburst nanonote xburst
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
#
# Nios
#
diff --git a/arch/mips/include/asm/global_data.h
b/arch/mips/include/asm/global_data.h
index 271a290..256f242 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -39,6 +39,15 @@
typedefstruct global_data {
bd_t*bd;
unsigned long flags;
+#if defined(CONFIG_JZSOC)
+/* There are other clocks in the jz4740 */
+unsigned long cpu_clk;/* CPU core clock */
+unsigned long sys_clk;/* System bus clock */
+unsigned long per_clk;/* Peripheral bus clock */
+unsigned long mem_clk;/* Memory bus clock */
+unsigned long dev_clk;/* Device clock */
+unsigned long fb_base;/* base address of framebuffer */
+#endif
unsigned long baudrate;
unsigned long have_console; /* serial_init() was called */
phys_size_t ram_size; /* RAM size */
diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
index f317124..9115055 100644
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
@@ -136,10 +136,18 @@ static int init_baudrate (void)
* argument, and returns an integer return code, where 0 means
* "continue" and != 0 means "fatal error, hang the system".
*/
+
+#if defined(CONFIG_JZSOC)
+extern int jzsoc_init(void);
+#endif
+
typedef int (init_fnc_t) (void);
init_fnc_t *init_sequence[] = {
board_early_init_f,
+#if defined(CONFIG_JZSOC)
+ jzsoc_init, /* init gpio/clocks/dram etc. */
+#endif
timer_init,
env_init, /* initialize environment */
#ifdef CONFIG_INCA_IP
diff --git a/arch/mips/lib/time.c b/arch/mips/lib/time.c
index 0e66441..653be6c 100644
--- a/arch/mips/lib/time.c
+++ b/arch/mips/lib/time.c
@@ -24,6 +24,7 @@
#include
#include
+#ifndef CONFIG_JZSOC
static unsigned long timestamp;
/* how many counter cycles in a jiffy */
@@ -96,3 +97,4 @@ ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}
+#endif
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 6/8] add entry to MAINTAINERS and boards.cfg
Signed-off-by: Xiangfu Liu Acked-by: Daniel Acked-by: ChangWei Jia --- MAINTAINERS |4 boards.cfg |1 + 2 files changed, 5 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index ba83f71..0482a5f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -906,6 +906,10 @@ Stefan Roese vct_xxx MIPS32 4Kc +Xiangfu Liu + + qi_lb60 MIPS32 jz4740 + # # Nios-II Systems: # # # diff --git a/boards.cfg b/boards.cfg index 94b8745..2802a5c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -210,6 +210,7 @@ EP2500 m68kmcf52x2 ep2500 Mercury microblaze-generic microblaze microblaze microblaze-generic xilinx purple mipsmips tb0229 mipsmips +qi_lb60 mipsmips PCI5441 nios2 nios2 pci5441 psyent PK1C20 nios2 nios2 pk1c20 psyent EVB64260 powerpc 74xx_7xxevb64260- - EVB64260 -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 5/8] add Ben NanoNote board
Signed-off-by: Xiangfu Liu
Acked-by: Daniel
Acked-by: ChangWei Jia
---
board/xburst/nanonote/Makefile| 45 +++
board/xburst/nanonote/config.mk | 31 +
board/xburst/nanonote/nanonote.c | 96 +++
board/xburst/nanonote/u-boot-nand.lds | 63 ++
include/configs/nanonote.h| 206 +
include/configs/qi_lb60.h | 28 +
6 files changed, 469 insertions(+), 0 deletions(-)
create mode 100644 board/xburst/nanonote/Makefile
create mode 100644 board/xburst/nanonote/config.mk
create mode 100644 board/xburst/nanonote/nanonote.c
create mode 100644 board/xburst/nanonote/u-boot-nand.lds
create mode 100644 include/configs/nanonote.h
create mode 100644 include/configs/qi_lb60.h
diff --git a/board/xburst/nanonote/Makefile b/board/xburst/nanonote/Makefile
new file mode 100644
index 000..2f5b4be
--- /dev/null
+++ b/board/xburst/nanonote/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor,
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/xburst/nanonote/config.mk b/board/xburst/nanonote/config.mk
new file mode 100644
index 000..858e6a2
--- /dev/null
+++ b/board/xburst/nanonote/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2006 Qi Hardware, Inc.
+# Author: Xiangfu Liu
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
+#
+
+ifndef TEXT_BASE
+# ROM version
+# TEXT_BASE = 0x8800
+
+# RAM version
+TEXT_BASE = 0x8010
+endif
diff --git a/board/xburst/nanonote/nanonote.c b/board/xburst/nanonote/nanonote.c
new file mode 100644
index 000..1a577e0
--- /dev/null
+++ b/board/xburst/nanonote/nanonote.c
@@ -0,0 +1,96 @@
+/*
+ * Authors: Xiangfu Liu
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_init(void)
+{
+ /* Initialize NAND Flash Pins */
+ __gpio_as_nand();
+
+ /* Initialize SDRAM pins */
+ __gpio_as_sdram_16bit_4720();
+
+ /* Initialize LCD pins */
+ __gpio_as_lcd_18bit();
+
+ /* Initialize MSC pins */
+ __gpio_as_msc();
+
+ /* Initialize Other pins */
+ unsigned int i;
+ for (i = 0; i < 7; i++){
+ __gpio_as_input(GPIO_KEYIN_BASE + i);
+ __gpio_enable_pull(GPIO_KEYIN_BASE + i);
+ }
+
+ for (i = 0; i < 8; i++) {
+ __gpio_as_output(GPIO_KEYOUT_BASE + i);
+ __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
+ }
+
+ __gpio_as_input(GPIO_KEYIN_8);
+ __gpio_enable_pull(GPIO_KEYIN_8);
+
+ /* enable the TP4, TP5 as UART0 */
+ __gpio_jtag_to_uart0();
+
+ __gpio_as_output(GPIO_AUDIO_POP);
+ __gpio_set_pin(GPIO_AUD
[U-Boot] [PATCH v5 4/8] jz4740 nand driver
Signed-off-by: Xiangfu Liu
Acked-by: Daniel
Acked-by: ChangWei Jia
---
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/jz4740_nand.c | 315
2 files changed, 316 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/jz4740_nand.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 8b598f6..bf2a8f9 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -50,6 +50,7 @@ COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
+COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
endif
COBJS := $(COBJS-y)
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
new file mode 100644
index 000..32b41ef
--- /dev/null
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -0,0 +1,315 @@
+/*
+ * Platform independend driver for JZ4740.
+ *
+ * Copyright (c) 2007 Ingenic Semiconductor Inc.
+ * Author:
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+#include
+
+#include
+#include
+#include
+
+#ifdef CONFIG_NAND_SPL
+#define printf(arg...) do {} while (0)
+#endif
+
+#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB800)
+#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
+#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x1)
+
+#define BIT(x) (1 << (x))
+#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
+#define JZ_NAND_ECC_CTRL_RSBIT(2)
+#define JZ_NAND_ECC_CTRL_RESET BIT(1)
+#define JZ_NAND_ECC_CTRL_ENABLEBIT(0)
+
+#define EMC_SMCR1_OPT_NAND 0x094c4400
+/* Optimize the timing of nand */
+
+static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
+ .eccbytes = 72,
+ .eccpos = {
+ 12, 13, 14, 15, 16, 17, 18, 19,
+ 20, 21, 22, 23, 24, 25, 26, 27,
+ 28, 29, 30, 31, 32, 33, 34, 35,
+ 36, 37, 38, 39, 40, 41, 42, 43,
+ 44, 45, 46, 47, 48, 49, 50, 51,
+ 52, 53, 54, 55, 56, 57, 58, 59,
+ 60, 61, 62, 63, 64, 65, 66, 67,
+ 68, 69, 70, 71, 72, 73, 74, 75,
+ 76, 77, 78, 79, 80, 81, 82, 83},
+ .oobfree = {
+ {.offset = 2,
+.length = 10},
+ {.offset = 84,
+.length = 44}}
+};
+
+#ifdef CONFIG_NAND_SPL
+#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3)
+ #define NAND_BUS_WIDTH 8
+ #define NAND_ROW_CYCLE 3
+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2)
+ #define NAND_BUS_WIDTH 8
+ #define NAND_ROW_CYCLE 2
+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3)
+ #define NAND_BUS_WIDTH 16
+ #define NAND_ROW_CYCLE 3
+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2)
+ #define NAND_BUS_WIDTH 16
+ #define NAND_ROW_CYCLE 2
+#endif
+
+static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ int i;
+ struct nand_chip *this = mtd->priv;
+#if NAND_BUS_WIDTH == 16
+ for (i = 0; i < len; i += 2)
+ buf[i] = readw(this->IO_ADDR_R);
+#elif NAND_BUS_WIDTH == 8
+ for (i = 0; i < len; i++)
+ buf[i] = readb(this->IO_ADDR_R);
+#endif
+}
+
+static u_char nand_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *this = mtd->priv;
+ return readb(this->IO_ADDR_R);
+}
+#endif
+
+static int is_reading;
+
+static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if (ctrl & NAND_ALE)
+ this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
+ else if (ctrl & NAND_CLE)
+ this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
+ else
+ this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
+
+ if (ctrl & NAND_NCE)
+ writel(readl(EMC_NFCSR) | EMC_NFCSR_NFCE1, EMC_NFCSR);
+ else
+ writel(readl(EMC_NFCSR) & ~EMC_NFCSR_NFCE1, EMC_NFCSR);
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+static int jz_nand_device_ready(struct mtd_info *mtd)
+{
+ return (readl(GPIO_PXPIN(2)) & 0x4000) ? 1 : 0;
+}
+
+void board_nand_select_device(struct nand_chip *nand, int chip)
+{
+ /*
+* Don't use "chip" to address the NAND device,
+* generate the cs from the address where it is encoded.
+*/
+}
+
+static int jz_nand_rs_calculate_ecc(struct mtd_info* mtd, const u_char* dat,
+ u_char* ecc_code)
+{
+ uint32_t status;
+
[U-Boot] [PATCH v5 2/8] this is jz4740 head file
Signed-off-by: Xiangfu Liu Acked-by: Daniel Acked-by: ChangWei Jia --- arch/mips/include/asm/jz4740.h | 1380 1 files changed, 1380 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/jz4740.h diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h new file mode 100644 index 000..5be26dc --- /dev/null +++ b/arch/mips/include/asm/jz4740.h @@ -0,0 +1,1380 @@ +/* + * Include file for Ingenic Semiconductor's JZ4740 CPU. + */ +#ifndef __JZ4740_H__ +#define __JZ4740_H__ + +#include +#include + +/* Boot ROM Specification */ +/* NOR Boot config */ +#define JZ4740_NORBOOT_8BIT0x /* 8-bit data bus flash */ +#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ +#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ +/* NAND Boot config */ +#define JZ4740_NANDBOOT_B8R3 0x /* 8-bit bus & 3 row cycles */ +#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ +#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ +#define JZ4740_NANDBOOT_B16R2 0x /* 16-bit bus & 2 row cycles */ + +/* Register Definitions */ +#defineCPM_BASE0xB000 +#defineINTC_BASE 0xB0001000 +#defineTCU_BASE0xB0002000 +#defineWDT_BASE0xB0002000 +#defineRTC_BASE0xB0003000 +#defineGPIO_BASE 0xB001 +#defineAIC_BASE0xB002 +#defineICDC_BASE 0xB002 +#defineMSC_BASE0xB0021000 +#defineUART0_BASE 0xB003 +#defineI2C_BASE0xB0042000 +#defineSSI_BASE0xB0043000 +#defineSADC_BASE 0xB007 +#defineEMC_BASE0xB301 +#defineDMAC_BASE 0xB302 +#defineUHC_BASE0xB303 +#defineUDC_BASE0xB304 +#defineLCD_BASE0xB305 +#defineSLCD_BASE 0xB305 +#defineCIM_BASE0xB306 +#defineETH_BASE0xB310 + +/* + * INTC (Interrupt Controller) + */ +#define INTC_ISR (INTC_BASE + 0x00) +#define INTC_IMR (INTC_BASE + 0x04) +#define INTC_IMSR (INTC_BASE + 0x08) +#define INTC_IMCR (INTC_BASE + 0x0c) +#define INTC_IPR (INTC_BASE + 0x10) + + +/* 1st-level interrupts */ +#define IRQ_I2C1 +#define IRQ_UHC3 +#define IRQ_UART0 9 +#define IRQ_SADC 12 +#define IRQ_MSC14 +#define IRQ_RTC15 +#define IRQ_SSI16 +#define IRQ_CIM17 +#define IRQ_AIC18 +#define IRQ_ETH19 +#define IRQ_DMAC 20 +#define IRQ_TCU2 21 +#define IRQ_TCU1 22 +#define IRQ_TCU0 23 +#define IRQ_UDC24 +#define IRQ_GPIO3 25 +#define IRQ_GPIO2 26 +#define IRQ_GPIO1 27 +#define IRQ_GPIO0 28 +#define IRQ_IPU29 +#define IRQ_LCD30 + +/* 2nd-level interrupts */ +#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ +#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ + +/* + * RTC + */ +#define RTC_RCR(RTC_BASE + 0x00) /* RTC Control Register */ +#define RTC_RSR(RTC_BASE + 0x04) /* RTC Second Register */ +#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ +#define RTC_RGR(RTC_BASE + 0x0c) /* RTC Regulator Register */ + +#define RTC_HCR(RTC_BASE + 0x20) /* Hibernate Control Register */ +#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ +#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ +#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ +#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ +#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ + + +/* RTC Control Register */ +#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ +#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ +#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ +#define RTC_RCR_AF (1 << 4) /* Alarm Flag */ +#define RTC_RCR_AIE(1 << 3) /* Alarm Interrupt Enable */ +#define RTC_RCR_AE (1 << 2) /* Alarm Enable */ +#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ + +/* RTC Regulator Register */ +#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ +#define RTC_RGR_ADJC_BIT 16 +#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) +#define RTC_RGR_NC1HZ_BIT 0 +#define RTC_RGR_NC1HZ_MASK (0x << RTC_RGR_NC1HZ_BIT) + +/* Hibernate Control Register */ +#define RTC_HCR_PD (1 << 0) /* Power Down */ + +/* Hibernate Wakeup Filter Counter Register */ +#
[U-Boot] [PATCH v5 3/8] jz4740 nand spl files
Signed-off-by: Xiangfu Liu
Acked-by: Daniel
Acked-by: ChangWei Jia
---
nand_spl/board/xburst/nanonote/Makefile | 106 +
nand_spl/board/xburst/nanonote/u-boot.lds | 63 +
2 files changed, 169 insertions(+), 0 deletions(-)
create mode 100644 nand_spl/board/xburst/nanonote/Makefile
create mode 100644 nand_spl/board/xburst/nanonote/u-boot.lds
diff --git a/nand_spl/board/xburst/nanonote/Makefile
b/nand_spl/board/xburst/nanonote/Makefile
new file mode 100644
index 000..9775d14
--- /dev/null
+++ b/nand_spl/board/xburst/nanonote/Makefile
@@ -0,0 +1,106 @@
+#
+# (C) Copyright 2006
+# Stefan Roese, DENX Software Engineering, s...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS= -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_NAND_SPL_TEXT_BASE)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL -O2
+
+SOBJS = start.o usbboot.o
+COBJS = nand_boot.o cpu.o jz4740.o jz_serial.o jz4740_nand.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj:= $(OBJTREE)/nand_spl/
+
+ALL= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin
$(nandobj)u-boot-spl-16k.bin
+all: $(obj).depend $(ALL)
+
+#The boot program can load two areas of data from NAND flash to internal SRAM,
one is the normal
+#area up to 8KB starting from NAND flash address 0, the other is the backup
area up to 8KB starting
+#from NAND flash address 0x2000. After reset, the boot program will first read
the normal area data
+#from NAND flash using hardware Reed-Solomon ECC. If no ECC error is detected
or ECC error is
+#correctable, the boot program then branches to internal SRAM at 4 bytes
offset. If it detects an
+#uncorrectable ECC error, it will continue to read the backup area of data
from NAND flash using
+#hardware Reed-Solomon ECC.
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
+ dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
+ cat $< $(nandobj)junk1 > $(nandobj)junk2
+ dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
+ cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
+ dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
+ cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
+ dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
+ rm -f $(nandobj)junk*
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+$(obj)start.S:
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $@
+
+$(obj)usbboot.S:
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/usbboot.S $@
+
+$(obj)cpu.c:
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/cpu.c $@
+
+$(obj)jz4740.c:
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz4740.c $@
+
+$(obj)jz_serial.c:
+ @rm -f $@
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $@
+
+$(obj)nand_boot.c:
+ @rm -f $@
+ ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
+
+$(obj)jz4740_nand.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/drivers/mtd/nand/jz4740_nand.c $@
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/nand_spl/board/xburst/nanonote/u-boot.lds
b/nand_spl/board/xburst/nanonote/u-boot.lds
new file mode 100644
index 000..7042388
--- /dev/null
+++ b/nand_spl/board/xburst/nanonote/u-boot.lds
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2005
+ * Ingenic Semiconductor,
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
[U-Boot] [PATCH v5 1/8] those files are jz4740 base files
Signed-off-by: Xiangfu Liu Acked-by: Daniel Acked-by: ChangWei Jia --- arch/mips/cpu/xburst/Makefile| 50 +++ arch/mips/cpu/xburst/config.mk | 33 ++ arch/mips/cpu/xburst/cpu.c | 160 arch/mips/cpu/xburst/jz4740.c| 266 arch/mips/cpu/xburst/jz_serial.c | 128 ++ arch/mips/cpu/xburst/start.S | 164 arch/mips/cpu/xburst/start_spl.S | 63 +++ arch/mips/cpu/xburst/timer.c | 172 arch/mips/cpu/xburst/usbboot.S | 841 ++ 9 files changed, 1877 insertions(+), 0 deletions(-) create mode 100644 arch/mips/cpu/xburst/Makefile create mode 100644 arch/mips/cpu/xburst/config.mk create mode 100644 arch/mips/cpu/xburst/cpu.c create mode 100644 arch/mips/cpu/xburst/jz4740.c create mode 100644 arch/mips/cpu/xburst/jz_serial.c create mode 100644 arch/mips/cpu/xburst/start.S create mode 100644 arch/mips/cpu/xburst/start_spl.S create mode 100644 arch/mips/cpu/xburst/timer.c create mode 100644 arch/mips/cpu/xburst/usbboot.S diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile new file mode 100644 index 000..a9a6e77 --- /dev/null +++ b/arch/mips/cpu/xburst/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).o + +START = start.o +SOBJS-y= +COBJS-y = cpu.o timer.o jz_serial.o + +COBJS-$(CONFIG_JZ4740) += jz4740.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk new file mode 100644 index 000..fc9b255 --- /dev/null +++ b/arch/mips/cpu/xburst/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2) +MIPSFLAGS:=$(shell \ +if [ "$v" -lt "14" ]; then \ + echo "-mcpu=4kc"; \ +else \ + echo "-march=4kc -mtune=4kc"; \ +fi) + +MIPSFLAGS += -mabicalls -mips32 + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c new file mode 100644 index 000..7b87f8b --- /dev/null +++ b/arch/mips/cpu/xburst/cpu.c @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICUL
[U-Boot] [PATCH v5 0/8] those series patches for add ben nanonote board
Hi Wolfgang those patches are for add xburst jz4740 and Ben NanoNote(named qi_lb60) to U-Boot some info about xburst jz4740: the xburst jz4740 is recently added to linux 2.6.36 and it's support the device Ben NanoNote out of box, this xburst jz4740 cpu have one feature is Boot From USB, there is a small rom in jz4740, but LOW some PIN, the cpu will boot to this small rom, then init cpu and USB module, then we can send 8KB bin file to the cpu by USB(by using 'xbboot' or 'usbboot'[1]). which means if your bootloader is borken,(the first few KBs in NAND) you can always boot the device from usb, then reflash the nand. in OpenMoko FreeRunner, there are NOR and NAND. when people broken the nand bootloader, it's must boot from NOR, reflash the bootloader back when people broken the NAND and NOR, he(she) must reflash by using JTAG but in Ben NanoNote, we just need boot from usb. flash the nand again :) BTW:there are a lot of PMP, Audio device in China use the Xburst cpu, but I think they are all base on u-boot 1.1.6. by working on Ben NanoNote (http://en.qi-hardware.com) one year, we try to update the u-boot to last version and send it to upstream. :) for more info about Ingenic Xburst JZ4740 http://www.ingenic.cn/eng/default.aspx http://www.linux-mips.org/wiki/Ingenic FIXED in [PATCH v3] 1. describe what Jz4740 SoC 2. remove the ENDIANNESS in config.mk 3. don't breaks the 80-charcter-wide rule 4. get rid of #if 0 5. use proper I/O accessors to access registers. 6. remove C++ comments, cleanup code style. FIXED in [PATCH v4] 1. add Entry to MAINTAINERS and boards.cfg 2. add ben nanonote(qi_lb60) to Makefile 3. tested with CROSS_COMPILE=mips_4KCle- ./MAKEALL mips_el FIXED in [PATCH v5] 1. remove nand_spl/nand_boot_jz4740.c 2. some cleanup Xiangfu Liu (8): those files are jz4740 base files this is jz4740 head file jz4740 nand spl files jz4740 nand driver add Ben NanoNote board add entry to MAINTAINERS and boards.cfg modify files for ben nanonote board add software usbboot MAINTAINERS |4 + MAKEALL |4 +- Makefile | 10 + arch/mips/cpu/xburst/Makefile | 50 + arch/mips/cpu/xburst/config.mk| 33 + arch/mips/cpu/xburst/cpu.c| 160 arch/mips/cpu/xburst/jz4740.c | 266 ++ arch/mips/cpu/xburst/jz_serial.c | 128 +++ arch/mips/cpu/xburst/start.S | 164 arch/mips/cpu/xburst/start_spl.S | 63 ++ arch/mips/cpu/xburst/timer.c | 172 arch/mips/cpu/xburst/usbboot.S| 841 ++ arch/mips/include/asm/global_data.h |9 + arch/mips/include/asm/jz4740.h| 1380 + arch/mips/lib/board.c |8 + arch/mips/lib/time.c |2 + board/xburst/nanonote/Makefile| 45 + board/xburst/nanonote/config.mk | 31 + board/xburst/nanonote/nanonote.c | 96 ++ board/xburst/nanonote/u-boot-nand.lds | 63 ++ boards.cfg|1 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/jz4740_nand.c| 327 +++ include/configs/nanonote.h| 206 + include/configs/qi_lb60.h | 28 + nand_spl/board/xburst/nanonote/Makefile | 106 +++ nand_spl/board/xburst/nanonote/u-boot.lds | 63 ++ 27 files changed, 4260 insertions(+), 1 deletions(-) create mode 100644 arch/mips/cpu/xburst/Makefile create mode 100644 arch/mips/cpu/xburst/config.mk create mode 100644 arch/mips/cpu/xburst/cpu.c create mode 100644 arch/mips/cpu/xburst/jz4740.c create mode 100644 arch/mips/cpu/xburst/jz_serial.c create mode 100644 arch/mips/cpu/xburst/start.S create mode 100644 arch/mips/cpu/xburst/start_spl.S create mode 100644 arch/mips/cpu/xburst/timer.c create mode 100644 arch/mips/cpu/xburst/usbboot.S create mode 100644 arch/mips/include/asm/jz4740.h create mode 100644 board/xburst/nanonote/Makefile create mode 100644 board/xburst/nanonote/config.mk create mode 100644 board/xburst/nanonote/nanonote.c create mode 100644 board/xburst/nanonote/u-boot-nand.lds create mode 100644 drivers/mtd/nand/jz4740_nand.c create mode 100644 include/configs/nanonote.h create mode 100644 include/configs/qi_lb60.h create mode 100644 nand_spl/board/xburst/nanonote/Makefile create mode 100644 nand_spl/board/xburst/nanonote/u-boot.lds ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 3/5] jz4740 nand spl files
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hi Scott
>
> I don't see any of my comments on v3 addressed or responded to:
> http://lists.denx.de/pipermail/u-boot/2010-December/083601.html
On 12/14/2010 08:05 AM, Scott Wood wrote:
>> nand_spl/nand_boot_jz4740.c | 344
>> +
>
> As I asked last time, is there any reason you can't use the standard
> nand_boot.c? Your non-SPL NAND driver looks like the type that would
> work with it.
thanks for point out, in next version patches, I will remove the
nand_boot_jz4740.c
>
>> +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
>> +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
>> +AFLAGS += -DCONFIG_NAND_SPL
>> +CFLAGS += -DCONFIG_NAND_SPL -O2
>
> Are you sure you want -O2 and not -Os? What are the space constraints
> for this SPL?
>
the nand_spl must less then 8kb.
~~~
#The boot program can load two areas of data from NAND flash to internal SRAM,
one is the normal
#area up to 8KB starting from NAND flash address 0, the other is the backup
area up to 8KB starting
#from NAND flash address 0x2000. After reset, the boot program will first read
the normal area data
#from NAND flash using hardware Reed-Solomon ECC. If no ECC error is detected
or ECC error is
#correctable, the boot program then branches to internal SRAM at 4 bytes
offset. If it detects an
#uncorrectable ECC error, it will continue to read the backup area of data from
NAND flash using
#hardware Reed-Solomon ECC.
~~~
I try to add "-Os", then I got some compile error:
~~~
mipsel-openwrt-linux-gcc -g -Os -D__KERNEL__
-DCONFIG_SYS_TEXT_BASE=0x8010
-I/home/xiangfu/workspace/PanGu/u-boot.upstream/include -fno-builtin
-ffreestanding -nostdinc -isystem
/home/xiangfu/workspace/PanGu/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/lib/gcc/mipsel-openwrt-linux-uclibc/4.3.3/include
-pipe -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -msoft-float -march=4kc
-mtune=4kc -mabicalls -mips32 -Wall -Wstrict-prototypes -fno-stack-protector
-DCONFIG_NAND_SPL -Os -c -o jz4740_nand.o jz4740_nand.c
jz4740_nand.c: In function 'board_nand_init':
jz4740_nand.c:298: warning: implicit declaration of function 'usb_boot'
cd /home/xiangfu/workspace/PanGu/u-boot.upstream/nand_spl/board/xburst/nanonote
&& mipsel-openwrt-linux-ld -Bstatic -T
/home/xiangfu/workspace/PanGu/u-boot.upstream/nand_spl/board/xburst/nanonote/u-boot.lds
-Ttext 0x8000 $UNDEF_SYM start.o usbboot.o nand_boot.o cpu.o jz4740.o
jz_serial.o jz4740_nand.o \
-Map
/home/xiangfu/workspace/PanGu/u-boot.upstream/nand_spl/u-boot-spl.map \
-o
/home/xiangfu/workspace/PanGu/u-boot.upstream/nand_spl/u-boot-spl
jz4740.o: In function `sdram_init':
jz4740.c:(.text+0x60): undefined reference to `memcpy'
~~~
>> +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
>> +dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
>> +cat $< $(nandobj)junk1 > $(nandobj)junk2
>> +dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
>> +cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
>> +dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
>> +cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
>> +dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
>> +rm -f $(nandobj)junk*
>
> Again, please explain what's going on here. Other boards don't do this.
>
add comments in "Makefile" in next patches.
- --
Best Regards
Xiangfu Liu
http://www.openmobilefree.net
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.10 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/
iEYEARECAAYFAk0p2LEACgkQRRAEFRxkgLSVCwCeIQ3AC86hiUy98sBLoG8Zq1EE
WP8An3a8aIyzzwDJ46I/wBNytwGyJTyK
=YvtK
-END PGP SIGNATURE-
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 4/7] jz4740 nand driver
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 01/05/2011 04:16 AM, Scott Wood wrote: > On Wed, Dec 08, 2010 at 12:20:46AM -0600, Xiangfu Liu wrote: >> +writel(readl(EMC_NFECR) & ~EMC_NFECR_ECCE, EMC_NFECR); > > readl() and other I/O accessors take pointers, not integer addresses. Hi Scott I fixed the others error, only this one I don't know how to do that. can you point me to some example. thanks for your emails. > Use I/O accesors. > U-Boot coding style prohibits declarations mid-block. > Line length. > Please symbolically define what went into that magic number. > > -Scott > - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk0pj4wACgkQRRAEFRxkgLSOgwCfZV/I0kCA+AT9Vu1OlXm3sZdU 9PQAmQGVlXtBePoD3jo0KPympGLKAxu5 =Y7s7 -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/7] jz4740 nand spl files
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 01/05/2011 04:13 AM, Scott Wood wrote: > On Wed, Dec 08, 2010 at 12:20:45AM -0600, Xiangfu Liu wrote: >> Signed-off-by: Xiangfu Liu >> --- >> nand_spl/board/xburst/nanonote/Makefile | 96 >> nand_spl/board/xburst/nanonote/u-boot.lds | 63 ++ >> nand_spl/nand_boot_jz4740.c | 344 >> + >> 3 files changed, 503 insertions(+), 0 deletions(-) >> create mode 100644 nand_spl/board/xburst/nanonote/Makefile >> create mode 100644 nand_spl/board/xburst/nanonote/u-boot.lds >> create mode 100644 nand_spl/nand_boot_jz4740.c > > I don't see any of my comments on v3 addressed or responded to: > http://lists.denx.de/pipermail/u-boot/2010-December/083601.html > Hi Scott thanks the comments, I am working on the nand_boot_jz4740.c now. I try to using the system nand_boot.c, but it's need sometime. I will try to send another patch in next two days. thanks again. > NACK. > > -Scott > - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk0pdWYACgkQRRAEFRxkgLQNsQCfQKwtQzy8+6UjpeL6/BPlvTdn oBgAn2OoHToWrtFSik/OzW8mfirDu5ZU =Igmv -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 0/7] those series patches for add ben nanonote board
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Wolfgang Denk On 12/08/2010 11:44 PM, Wolfgang Denk wrote: > Dear Xiangfu Liu, > > In message <4cff9e15.2040...@openmobilefree.net> you wrote: >> >> I have sended those patches to them. should I add >> " >> Acked-by: Daniel >> Acked-by: ChangWei Jia > > Please do so if and only if they explicitly send you their ACK. ok. got it. > Normally these ACKs schould be sent to the mailing list so we all can oh. the patches I send to them is just the same [PATCH v4 ...] I send to mailing list. just for them easy review the code. I will CC to them next time. :) > see them. > > > And please do not top post / full quote. sorry. - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAkz/qZwACgkQRRAEFRxkgLS7XQCfTaR+NC5twU5d8B26On8s9m7I Pq4An3+zRWvmcdgbYjKwp/ffv80BJ+V+ =wuSD -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 0/7] those series patches for add ben nanonote board
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi All I just got one email form Ingenic people. the "Peter " doesn't work for Ingenic any more, mean the email address is abandon. and there are another two ingenic people for contact window. Daniel ChangWei Jia I have sended those patches to them. should I add " Acked-by: Daniel Acked-by: ChangWei Jia " in next version patch, (I think this patch v4 still not good enough merge to upstream :) Please give me some feedback. very thanks. On 12/08/2010 02:20 PM, Xiangfu Liu wrote: > Hi Wolfgang > those patches are for add xburst jz4740 and Ben NanoNote(named qi_lb60) to > U-Boot > > some info about xburst jz4740: > the xburst jz4740 is recently added to linux 2.6.36 > and it's support the device Ben NanoNote out of box, > > this xburst jz4740 cpu have one feature is Boot From USB, there is a > small rom in jz4740, but LOW some PIN, the cpu will boot to this small > rom, then init cpu and USB module, then we can send 8KB bin file to > the cpu by USB(by using 'xbboot' or 'usbboot'[1]). > > which means if your bootloader is borken,(the first few KBs in NAND) > you can always boot the device from usb, then reflash the nand. > > in OpenMoko FreeRunner, there are NOR and NAND. when people broken the > nand bootloader, it's must boot from NOR, reflash the bootloader back > when people broken the NAND and NOR, he(she) must reflash by using JTAG > but in Ben NanoNote, we just need boot from usb. flash the nand again :) > > BTW:there are a lot of PMP, Audio device in China use the Xburst cpu, > but I think they are all base on u-boot 1.1.6. by working on > Ben NanoNote (http://en.qi-hardware.com) one year, we try to > update the u-boot to last version and send it to upstream. :) > > for more info about Ingenic Xburst JZ4740 > http://www.ingenic.cn/eng/default.aspx > http://www.linux-mips.org/wiki/Ingenic > > > FIXED in [PATCH v3] > 1. describe what Jz4740 SoC > 2. remove the ENDIANNESS in config.mk > 3. don't breaks the 80-charcter-wide rule > 4. get rid of #if 0 > 5. use proper I/O accessors to access registers. > 6. remove C++ comments, cleanup code style. > > FIXED in [PATCH v4] > 1. add Entry to MAINTAINERS and boards.cfg > 2. add ben nanonote(qi_lb60) to Makefile > 3. tested with CROSS_COMPILE=mips_4KCle- ./MAKEALL mips_el > - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAkz/nhUACgkQRRAEFRxkgLSR5QCgk2ry72Dz5k40LyE8qPEETqfD S5MAnjmGgkoYN4nI5eJ7k+X3GMZuj77Z =RCUG -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] remove-flash.c-in-board-dbau1x00
Signed-off-by: Xiangfu Liu
---
Hi
when I run "CROSS_COMPILE=mips_4KCle- ./MAKEALL mips_el". I got those[1] errors.
this patch fixed that error. make board compile fine.
but I am not sure if the bin image works fine in device. please test it.
[1]
==
Configuring for dbau1x00 board...
board/dbau1x00/libdbau1x00.o: In function `flash_init':
/home/xiangfu/u-boot/u-boot.github/board/dbau1x00/flash.c:34: multiple
definition of `flash_init'
drivers/mtd/libmtd.o:/home/xiangfu/u-boot/u-boot.github/drivers/mtd/cfi_flash.c:2027:
first defined here
board/dbau1x00/libdbau1x00.o: In function `write_buff':
/home/xiangfu/u-boot/u-boot.github/board/dbau1x00/flash.c:40: multiple
definition of `write_buff'
drivers/mtd/libmtd.o:/home/xiangfu/u-boot/u-boot.github/drivers/mtd/cfi_flash.c:1247:
first defined here
make: *** [/home/xiangfu/u-boot/u-boot-build/u-boot] Error 1
board/dbau1x00/Makefile |2 +-
board/dbau1x00/flash.c | 43 ---
2 files changed, 1 insertions(+), 44 deletions(-)
delete mode 100644 board/dbau1x00/flash.c
diff --git a/board/dbau1x00/Makefile b/board/dbau1x00/Makefile
index f1594a2..e36a9d2 100644
--- a/board/dbau1x00/Makefile
+++ b/board/dbau1x00/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/dbau1x00/flash.c b/board/dbau1x00/flash.c
deleted file mode 100644
index a2fed1d..000
--- a/board/dbau1x00/flash.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips
*/
-
-/*---
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
- printf ("Skipping flash_init\n");
- return (0);
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- printf ("write_buff not implemented\n");
- return (-1);
-}
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 5/7] add Ben NanoNote board
Signed-off-by: Xiangfu Liu
---
board/xburst/nanonote/Makefile| 45
board/xburst/nanonote/config.mk | 31 ++
board/xburst/nanonote/nanonote.c | 96 +
board/xburst/nanonote/u-boot-nand.lds | 63 +++
include/configs/nanonote.h| 188 +
include/configs/qi_lb60.h | 28 +
6 files changed, 451 insertions(+), 0 deletions(-)
create mode 100644 board/xburst/nanonote/Makefile
create mode 100644 board/xburst/nanonote/config.mk
create mode 100644 board/xburst/nanonote/nanonote.c
create mode 100644 board/xburst/nanonote/u-boot-nand.lds
create mode 100644 include/configs/nanonote.h
create mode 100644 include/configs/qi_lb60.h
diff --git a/board/xburst/nanonote/Makefile b/board/xburst/nanonote/Makefile
new file mode 100644
index 000..2f5b4be
--- /dev/null
+++ b/board/xburst/nanonote/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor,
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/xburst/nanonote/config.mk b/board/xburst/nanonote/config.mk
new file mode 100644
index 000..858e6a2
--- /dev/null
+++ b/board/xburst/nanonote/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2006 Qi Hardware, Inc.
+# Author: Xiangfu Liu
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
+#
+
+ifndef TEXT_BASE
+# ROM version
+# TEXT_BASE = 0x8800
+
+# RAM version
+TEXT_BASE = 0x8010
+endif
diff --git a/board/xburst/nanonote/nanonote.c b/board/xburst/nanonote/nanonote.c
new file mode 100644
index 000..1a577e0
--- /dev/null
+++ b/board/xburst/nanonote/nanonote.c
@@ -0,0 +1,96 @@
+/*
+ * Authors: Xiangfu Liu
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_init(void)
+{
+ /* Initialize NAND Flash Pins */
+ __gpio_as_nand();
+
+ /* Initialize SDRAM pins */
+ __gpio_as_sdram_16bit_4720();
+
+ /* Initialize LCD pins */
+ __gpio_as_lcd_18bit();
+
+ /* Initialize MSC pins */
+ __gpio_as_msc();
+
+ /* Initialize Other pins */
+ unsigned int i;
+ for (i = 0; i < 7; i++){
+ __gpio_as_input(GPIO_KEYIN_BASE + i);
+ __gpio_enable_pull(GPIO_KEYIN_BASE + i);
+ }
+
+ for (i = 0; i < 8; i++) {
+ __gpio_as_output(GPIO_KEYOUT_BASE + i);
+ __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
+ }
+
+ __gpio_as_input(GPIO_KEYIN_8);
+ __gpio_enable_pull(GPIO_KEYIN_8);
+
+ /* enable the TP4, TP5 as UART0 */
+ __gpio_jtag_to_uart0();
+
+ __gpio_as_output(GPIO_AUDIO_POP);
+ __gpio_set_pin(GPIO_AUDIO_POP);
+
+ __gpio_as_output(GPIO_
[U-Boot] [PATCH v4 6/7] add entry to MAINTAINERS and boards.cfg
Signed-off-by: Xiangfu Liu --- MAINTAINERS |4 boards.cfg |1 + 2 files changed, 5 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index f47fca5..c6518f9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -900,6 +900,10 @@ Stefan Roese vct_xxx MIPS32 4Kc +Xiangfu Liu + + qi_lb60 MIPS32 jz4740 + # # Nios-II Systems: # # # diff --git a/boards.cfg b/boards.cfg index 2209676..c7ae650 100644 --- a/boards.cfg +++ b/boards.cfg @@ -202,6 +202,7 @@ EP2500 m68kmcf52x2 ep2500 Mercury microblaze-generic microblaze microblaze microblaze-generic xilinx purple mipsmips tb0229 mipsmips +qi_lb60 mipsmips PCI5441 nios2 nios2 pci5441 psyent PK1C20 nios2 nios2 pk1c20 psyent EVB64260 powerpc 74xx_7xxevb64260- - EVB64260 -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 2/7] this is jz4740 head file
Signed-off-by: Xiangfu Liu --- arch/mips/include/asm/jz4740.h | 1380 1 files changed, 1380 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/jz4740.h diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h new file mode 100644 index 000..5be26dc --- /dev/null +++ b/arch/mips/include/asm/jz4740.h @@ -0,0 +1,1380 @@ +/* + * Include file for Ingenic Semiconductor's JZ4740 CPU. + */ +#ifndef __JZ4740_H__ +#define __JZ4740_H__ + +#include +#include + +/* Boot ROM Specification */ +/* NOR Boot config */ +#define JZ4740_NORBOOT_8BIT0x /* 8-bit data bus flash */ +#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ +#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ +/* NAND Boot config */ +#define JZ4740_NANDBOOT_B8R3 0x /* 8-bit bus & 3 row cycles */ +#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ +#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ +#define JZ4740_NANDBOOT_B16R2 0x /* 16-bit bus & 2 row cycles */ + +/* Register Definitions */ +#defineCPM_BASE0xB000 +#defineINTC_BASE 0xB0001000 +#defineTCU_BASE0xB0002000 +#defineWDT_BASE0xB0002000 +#defineRTC_BASE0xB0003000 +#defineGPIO_BASE 0xB001 +#defineAIC_BASE0xB002 +#defineICDC_BASE 0xB002 +#defineMSC_BASE0xB0021000 +#defineUART0_BASE 0xB003 +#defineI2C_BASE0xB0042000 +#defineSSI_BASE0xB0043000 +#defineSADC_BASE 0xB007 +#defineEMC_BASE0xB301 +#defineDMAC_BASE 0xB302 +#defineUHC_BASE0xB303 +#defineUDC_BASE0xB304 +#defineLCD_BASE0xB305 +#defineSLCD_BASE 0xB305 +#defineCIM_BASE0xB306 +#defineETH_BASE0xB310 + +/* + * INTC (Interrupt Controller) + */ +#define INTC_ISR (INTC_BASE + 0x00) +#define INTC_IMR (INTC_BASE + 0x04) +#define INTC_IMSR (INTC_BASE + 0x08) +#define INTC_IMCR (INTC_BASE + 0x0c) +#define INTC_IPR (INTC_BASE + 0x10) + + +/* 1st-level interrupts */ +#define IRQ_I2C1 +#define IRQ_UHC3 +#define IRQ_UART0 9 +#define IRQ_SADC 12 +#define IRQ_MSC14 +#define IRQ_RTC15 +#define IRQ_SSI16 +#define IRQ_CIM17 +#define IRQ_AIC18 +#define IRQ_ETH19 +#define IRQ_DMAC 20 +#define IRQ_TCU2 21 +#define IRQ_TCU1 22 +#define IRQ_TCU0 23 +#define IRQ_UDC24 +#define IRQ_GPIO3 25 +#define IRQ_GPIO2 26 +#define IRQ_GPIO1 27 +#define IRQ_GPIO0 28 +#define IRQ_IPU29 +#define IRQ_LCD30 + +/* 2nd-level interrupts */ +#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ +#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ + +/* + * RTC + */ +#define RTC_RCR(RTC_BASE + 0x00) /* RTC Control Register */ +#define RTC_RSR(RTC_BASE + 0x04) /* RTC Second Register */ +#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ +#define RTC_RGR(RTC_BASE + 0x0c) /* RTC Regulator Register */ + +#define RTC_HCR(RTC_BASE + 0x20) /* Hibernate Control Register */ +#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ +#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ +#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ +#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ +#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ + + +/* RTC Control Register */ +#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ +#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ +#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ +#define RTC_RCR_AF (1 << 4) /* Alarm Flag */ +#define RTC_RCR_AIE(1 << 3) /* Alarm Interrupt Enable */ +#define RTC_RCR_AE (1 << 2) /* Alarm Enable */ +#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ + +/* RTC Regulator Register */ +#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ +#define RTC_RGR_ADJC_BIT 16 +#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) +#define RTC_RGR_NC1HZ_BIT 0 +#define RTC_RGR_NC1HZ_MASK (0x << RTC_RGR_NC1HZ_BIT) + +/* Hibernate Control Register */ +#define RTC_HCR_PD (1 << 0) /* Power Down */ + +/* Hibernate Wakeup Filter Counter Register */ +#define RTC_HWFCR_BIT 5 +#define
[U-Boot] [PATCH v4 4/7] jz4740 nand driver
Signed-off-by: Xiangfu Liu
---
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/jz4740_nand.c | 252
2 files changed, 253 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/jz4740_nand.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 8b598f6..bf2a8f9 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -50,6 +50,7 @@ COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
+COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
endif
COBJS := $(COBJS-y)
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
new file mode 100644
index 000..e82d7d3
--- /dev/null
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -0,0 +1,252 @@
+/*
+ * Platform independend driver for JZ4740.
+ *
+ * Copyright (c) 2007 Ingenic Semiconductor Inc.
+ * Author:
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+#include
+
+#if defined(CONFIG_CMD_NAND)
+#include
+#include
+#include
+
+#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB800)
+#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
+#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x1)
+
+#define BIT(x) (1 << (x))
+#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
+#define JZ_NAND_ECC_CTRL_RSBIT(2)
+#define JZ_NAND_ECC_CTRL_RESET BIT(1)
+#define JZ_NAND_ECC_CTRL_ENABLEBIT(0)
+
+static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
+ .eccbytes = 72,
+ .eccpos = {
+ 12, 13, 14, 15, 16, 17, 18, 19,
+ 20, 21, 22, 23, 24, 25, 26, 27,
+ 28, 29, 30, 31, 32, 33, 34, 35,
+ 36, 37, 38, 39, 40, 41, 42, 43,
+ 44, 45, 46, 47, 48, 49, 50, 51,
+ 52, 53, 54, 55, 56, 57, 58, 59,
+ 60, 61, 62, 63, 64, 65, 66, 67,
+ 68, 69, 70, 71, 72, 73, 74, 75,
+ 76, 77, 78, 79, 80, 81, 82, 83},
+ .oobfree = {
+ {.offset = 2,
+.length = 10},
+ {.offset = 84,
+.length = 44}}
+};
+
+static int is_reading;
+
+static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if (ctrl & NAND_ALE)
+ this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
+ else if (ctrl & NAND_CLE)
+ this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
+ else
+ this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
+
+ if (ctrl & NAND_NCE)
+ writel(readl(EMC_NFCSR) | EMC_NFCSR_NFCE1, EMC_NFCSR);
+ else
+ writel(readl(EMC_NFCSR) & ~EMC_NFCSR_NFCE1, EMC_NFCSR);
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+static int jz_nand_device_ready(struct mtd_info *mtd)
+{
+ udelay(20);
+ return (readl(GPIO_PXPIN(2)) & 0x4000) ? 1 : 0;
+}
+
+void board_nand_select_device(struct nand_chip *nand, int chip)
+{
+ /*
+* Don't use "chip" to address the NAND device,
+* generate the cs from the address where it is encoded.
+*/
+}
+
+static int jz_nand_rs_calculate_ecc(struct mtd_info* mtd, const u_char* dat,
+ u_char* ecc_code)
+{
+ uint32_t status;
+ int i;
+ volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
+
+ if (is_reading)
+ return 0;
+
+ do {
+ status = readl(EMC_NFINTS);
+ } while(!(status & EMC_NFINTS_ENCF));
+
+ /* disable ecc */
+ writel(readl(EMC_NFECR) & ~EMC_NFECR_ECCE, EMC_NFECR);
+
+ for (i = 0; i < 9; i++)
+ ecc_code[i] = *(paraddr + i);
+
+ return 0;
+}
+
+static void jz_nand_hwctl(struct mtd_info* mtd, int mode)
+{
+ uint32_t reg;
+
+ writel(0, EMC_NFINTS);
+ reg = readl(EMC_NFECR);
+ reg |= JZ_NAND_ECC_CTRL_RESET;
+ reg |= JZ_NAND_ECC_CTRL_ENABLE;
+ reg |= JZ_NAND_ECC_CTRL_RS;
+
+ switch (mode) {
+ case NAND_ECC_READ:
+ reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
+ is_reading = 1;
+ break;
+ case NAND_ECC_WRITE:
+ reg |= JZ_NAND_ECC_CTRL_ENCODING;
+ is_reading = 0;
+ break;
+ default:
+ break;
+ }
+
+ writel(reg, EMC_NFECR);
+}
+
+/* Correct 1~9-bit errors in 512-bytes data */
+static void jz_rs_correct(unsigned char *dat, int idx, int mask)
+{
+
[U-Boot] [PATCH v4 0/7] those series patches for add ben nanonote board
Hi Wolfgang those patches are for add xburst jz4740 and Ben NanoNote(named qi_lb60) to U-Boot some info about xburst jz4740: the xburst jz4740 is recently added to linux 2.6.36 and it's support the device Ben NanoNote out of box, this xburst jz4740 cpu have one feature is Boot From USB, there is a small rom in jz4740, but LOW some PIN, the cpu will boot to this small rom, then init cpu and USB module, then we can send 8KB bin file to the cpu by USB(by using 'xbboot' or 'usbboot'[1]). which means if your bootloader is borken,(the first few KBs in NAND) you can always boot the device from usb, then reflash the nand. in OpenMoko FreeRunner, there are NOR and NAND. when people broken the nand bootloader, it's must boot from NOR, reflash the bootloader back when people broken the NAND and NOR, he(she) must reflash by using JTAG but in Ben NanoNote, we just need boot from usb. flash the nand again :) BTW:there are a lot of PMP, Audio device in China use the Xburst cpu, but I think they are all base on u-boot 1.1.6. by working on Ben NanoNote (http://en.qi-hardware.com) one year, we try to update the u-boot to last version and send it to upstream. :) for more info about Ingenic Xburst JZ4740 http://www.ingenic.cn/eng/default.aspx http://www.linux-mips.org/wiki/Ingenic FIXED in [PATCH v3] 1. describe what Jz4740 SoC 2. remove the ENDIANNESS in config.mk 3. don't breaks the 80-charcter-wide rule 4. get rid of #if 0 5. use proper I/O accessors to access registers. 6. remove C++ comments, cleanup code style. FIXED in [PATCH v4] 1. add Entry to MAINTAINERS and boards.cfg 2. add ben nanonote(qi_lb60) to Makefile 3. tested with CROSS_COMPILE=mips_4KCle- ./MAKEALL mips_el ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 7/7] modify files for ben nanonote board
Signed-off-by: Xiangfu Liu
---
MAKEALL |4 +++-
Makefile| 10 ++
arch/mips/include/asm/global_data.h |9 +
arch/mips/lib/board.c |8
arch/mips/lib/time.c|2 ++
5 files changed, 32 insertions(+), 1 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 767d561..8631cc5 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -541,7 +541,9 @@ LIST_mips=" \
## MIPS Systems(little endian)
#
-LIST_mips4kc_el=""
+LIST_mips4kc_el=" \
+ qi_lb60
+"
LIST_mips5kc_el=""
diff --git a/Makefile b/Makefile
index 0685ef9..62e59e2 100644
--- a/Makefile
+++ b/Makefile
@@ -1176,6 +1176,16 @@ qemu_mips_config : unconfig
@echo "#define CONFIG_QEMU_MIPS 1" >$(obj)include/config.h
@$(MKCONFIG) -a qemu-mips mips mips qemu-mips
+#
+## MIPS32 XBurst jz4740
+#
+qi_lb60_config : unconfig
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+ @echo "Compile NAND boot image for QI LB60"
+ @$(MKCONFIG) -a qi_lb60 mips xburst nanonote xburst
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
#
# Nios
#
diff --git a/arch/mips/include/asm/global_data.h
b/arch/mips/include/asm/global_data.h
index 271a290..256f242 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -39,6 +39,15 @@
typedefstruct global_data {
bd_t*bd;
unsigned long flags;
+#if defined(CONFIG_JZSOC)
+/* There are other clocks in the jz4740 */
+unsigned long cpu_clk;/* CPU core clock */
+unsigned long sys_clk;/* System bus clock */
+unsigned long per_clk;/* Peripheral bus clock */
+unsigned long mem_clk;/* Memory bus clock */
+unsigned long dev_clk;/* Device clock */
+unsigned long fb_base;/* base address of framebuffer */
+#endif
unsigned long baudrate;
unsigned long have_console; /* serial_init() was called */
phys_size_t ram_size; /* RAM size */
diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
index f317124..9115055 100644
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
@@ -136,10 +136,18 @@ static int init_baudrate (void)
* argument, and returns an integer return code, where 0 means
* "continue" and != 0 means "fatal error, hang the system".
*/
+
+#if defined(CONFIG_JZSOC)
+extern int jzsoc_init(void);
+#endif
+
typedef int (init_fnc_t) (void);
init_fnc_t *init_sequence[] = {
board_early_init_f,
+#if defined(CONFIG_JZSOC)
+ jzsoc_init, /* init gpio/clocks/dram etc. */
+#endif
timer_init,
env_init, /* initialize environment */
#ifdef CONFIG_INCA_IP
diff --git a/arch/mips/lib/time.c b/arch/mips/lib/time.c
index 0e66441..653be6c 100644
--- a/arch/mips/lib/time.c
+++ b/arch/mips/lib/time.c
@@ -24,6 +24,7 @@
#include
#include
+#ifndef CONFIG_JZSOC
static unsigned long timestamp;
/* how many counter cycles in a jiffy */
@@ -96,3 +97,4 @@ ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}
+#endif
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 3/7] jz4740 nand spl files
Signed-off-by: Xiangfu Liu
---
nand_spl/board/xburst/nanonote/Makefile | 96
nand_spl/board/xburst/nanonote/u-boot.lds | 63 ++
nand_spl/nand_boot_jz4740.c | 344 +
3 files changed, 503 insertions(+), 0 deletions(-)
create mode 100644 nand_spl/board/xburst/nanonote/Makefile
create mode 100644 nand_spl/board/xburst/nanonote/u-boot.lds
create mode 100644 nand_spl/nand_boot_jz4740.c
diff --git a/nand_spl/board/xburst/nanonote/Makefile
b/nand_spl/board/xburst/nanonote/Makefile
new file mode 100644
index 000..f5d1eb5
--- /dev/null
+++ b/nand_spl/board/xburst/nanonote/Makefile
@@ -0,0 +1,96 @@
+#
+# (C) Copyright 2006
+# Stefan Roese, DENX Software Engineering, s...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+TEXT_BASE = 0x8000
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL -O2
+
+SOBJS = start.o usbboot.o
+COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj:= $(OBJTREE)/nand_spl/
+
+ALL= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin
$(nandobj)u-boot-spl-16k.bin
+all: $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
+ dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
+ cat $< $(nandobj)junk1 > $(nandobj)junk2
+ dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
+ cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
+ dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
+ cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
+ dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
+ rm -f $(nandobj)junk*
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+$(obj)start.S:
+ @rm -f $(obj)start.S
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $(obj)start.S
+
+$(obj)usbboot.S:
+ @rm -f $(obj)usbboot.S
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/usbboot.S $(obj)usbboot.S
+
+$(obj)cpu.c:
+ @rm -f $(obj)cpu.c
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/cpu.c $(obj)cpu.c
+
+$(obj)jz4740.c:
+ @rm -f $(obj)jz4740.c
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz4740.c $(obj)jz4740.c
+
+$(obj)jz_serial.c:
+ @rm -f $(obj)jz_serial.c
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $(obj)jz_serial.c
+
+$(obj)nand_boot_jz4740.c:
+ @rm -f $(obj)nand_boot_jz4740.c
+ ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/nand_spl/board/xburst/nanonote/u-boot.lds
b/nand_spl/board/xburst/nanonote/u-boot.lds
new file mode 100644
index 000..7042388
--- /dev/null
+++ b/nand_spl/board/xburst/nanonote/u-boot.lds
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2005
+ * Ingenic Semiconductor,
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330,
[U-Boot] [PATCH v4 1/7] those files are jz4740 base files
Signed-off-by: Xiangfu Liu --- arch/mips/cpu/xburst/Makefile| 50 +++ arch/mips/cpu/xburst/config.mk | 33 ++ arch/mips/cpu/xburst/cpu.c | 160 arch/mips/cpu/xburst/jz4740.c| 266 arch/mips/cpu/xburst/jz_serial.c | 128 ++ arch/mips/cpu/xburst/start.S | 164 arch/mips/cpu/xburst/start_spl.S | 63 +++ arch/mips/cpu/xburst/timer.c | 172 arch/mips/cpu/xburst/usbboot.S | 841 ++ 9 files changed, 1877 insertions(+), 0 deletions(-) create mode 100644 arch/mips/cpu/xburst/Makefile create mode 100644 arch/mips/cpu/xburst/config.mk create mode 100644 arch/mips/cpu/xburst/cpu.c create mode 100644 arch/mips/cpu/xburst/jz4740.c create mode 100644 arch/mips/cpu/xburst/jz_serial.c create mode 100644 arch/mips/cpu/xburst/start.S create mode 100644 arch/mips/cpu/xburst/start_spl.S create mode 100644 arch/mips/cpu/xburst/timer.c create mode 100644 arch/mips/cpu/xburst/usbboot.S diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile new file mode 100644 index 000..a9a6e77 --- /dev/null +++ b/arch/mips/cpu/xburst/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).o + +START = start.o +SOBJS-y= +COBJS-y = cpu.o timer.o jz_serial.o + +COBJS-$(CONFIG_JZ4740) += jz4740.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk new file mode 100644 index 000..fc9b255 --- /dev/null +++ b/arch/mips/cpu/xburst/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2) +MIPSFLAGS:=$(shell \ +if [ "$v" -lt "14" ]; then \ + echo "-mcpu=4kc"; \ +else \ + echo "-march=4kc -mtune=4kc"; \ +fi) + +MIPSFLAGS += -mabicalls -mips32 + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c new file mode 100644 index 000..22261cf --- /dev/null +++ b/arch/mips/cpu/xburst/cpu.c @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public
[U-Boot] [PATCH v3 4/5] jz4740 nand driver
From: Xiangfu Liu
Signed-off-by: Xiangfu Liu
---
drivers/mtd/nand/jz4740_nand.c | 252
1 files changed, 252 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/jz4740_nand.c
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
new file mode 100644
index 000..390dcbb
--- /dev/null
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -0,0 +1,252 @@
+/*
+ * Platform independend driver for JZ4740.
+ *
+ * Copyright (c) 2007 Ingenic Semiconductor Inc.
+ * Author:
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+#include
+
+#if defined(CONFIG_CMD_NAND)
+#include
+#include
+#include
+
+#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB800)
+#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
+#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x1)
+
+#define BIT(x) (1 << (x))
+#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
+#define JZ_NAND_ECC_CTRL_RSBIT(2)
+#define JZ_NAND_ECC_CTRL_RESET BIT(1)
+#define JZ_NAND_ECC_CTRL_ENABLEBIT(0)
+
+static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
+ .eccbytes = 72,
+ .eccpos = {
+ 12, 13, 14, 15, 16, 17, 18, 19,
+ 20, 21, 22, 23, 24, 25, 26, 27,
+ 28, 29, 30, 31, 32, 33, 34, 35,
+ 36, 37, 38, 39, 40, 41, 42, 43,
+ 44, 45, 46, 47, 48, 49, 50, 51,
+ 52, 53, 54, 55, 56, 57, 58, 59,
+ 60, 61, 62, 63, 64, 65, 66, 67,
+ 68, 69, 70, 71, 72, 73, 74, 75,
+ 76, 77, 78, 79, 80, 81, 82, 83},
+ .oobfree = {
+ {.offset = 2,
+.length = 10},
+ {.offset = 84,
+.length = 44}}
+};
+
+static int is_reading;
+
+static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if (ctrl & NAND_ALE)
+ this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
+ else if (ctrl & NAND_CLE)
+ this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
+ else
+ this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
+
+ if (ctrl & NAND_NCE)
+ writel(readl(EMC_NFCSR) | EMC_NFCSR_NFCE1, EMC_NFCSR);
+ else
+ writel(readl(EMC_NFCSR) & ~EMC_NFCSR_NFCE1, EMC_NFCSR);
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+static int jz_nand_device_ready(struct mtd_info *mtd)
+{
+ udelay(20);
+ return (readl(GPIO_PXPIN(2)) & 0x4000) ? 1 : 0;
+}
+
+void board_nand_select_device(struct nand_chip *nand, int chip)
+{
+ /*
+* Don't use "chip" to address the NAND device,
+* generate the cs from the address where it is encoded.
+*/
+}
+
+static int jz_nand_rs_calculate_ecc(struct mtd_info* mtd, const u_char* dat,
+ u_char* ecc_code)
+{
+ uint32_t reg, status;
+ int i;
+ volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
+
+ if (is_reading)
+ return 0;
+
+ do {
+ status = readl(EMC_NFINTS);
+ } while(!(status & EMC_NFINTS_ENCF));
+
+ /* disable ecc */
+ writel(readl(EMC_NFECR) & ~EMC_NFECR_ECCE, EMC_NFECR);
+
+ for (i = 0; i < 9; i++)
+ ecc_code[i] = *(paraddr + i);
+
+ return 0;
+}
+
+static void jz_nand_hwctl(struct mtd_info* mtd, int mode)
+{
+ uint32_t reg;
+
+ writel(0, EMC_NFINTS);
+ reg = readl(EMC_NFECR);
+ reg |= JZ_NAND_ECC_CTRL_RESET;
+ reg |= JZ_NAND_ECC_CTRL_ENABLE;
+ reg |= JZ_NAND_ECC_CTRL_RS;
+
+ switch (mode) {
+ case NAND_ECC_READ:
+ reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
+ is_reading = 1;
+ break;
+ case NAND_ECC_WRITE:
+ reg |= JZ_NAND_ECC_CTRL_ENCODING;
+ is_reading = 0;
+ break;
+ default:
+ break;
+ }
+
+ writel(reg, EMC_NFECR);
+}
+
+/* Correct 1~9-bit errors in 512-bytes data */
+static void jz_rs_correct(unsigned char *dat, int idx, int mask)
+{
+ int i;
+
+ idx--;
+
+ i = idx + (idx >> 3);
+ if (i >= 512)
+ return;
+
+ mask <<= (idx & 0x7);
+
+ dat[i] ^= mask & 0xff;
+ if (i < 511)
+ dat[i+1] ^= (mask >> 8) & 0xff;
+}
+
+static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
+ u_char *read_ecc, u_char *calc_ecc)
+{
+ int k;
+
[U-Boot] [PATCH v3 5/5] add Ben NanoNote board
From: Xiangfu Liu
Signed-off-by: Xiangfu Liu
---
board/xburst/nanonote/Makefile| 45
board/xburst/nanonote/config.mk | 31 ++
board/xburst/nanonote/nanonote.c | 110 +++
board/xburst/nanonote/u-boot-nand.lds | 63 +++
include/configs/nanonote.h| 188 +
include/configs/qi_lb60.h | 28 +
6 files changed, 465 insertions(+), 0 deletions(-)
create mode 100644 board/xburst/nanonote/Makefile
create mode 100644 board/xburst/nanonote/config.mk
create mode 100644 board/xburst/nanonote/nanonote.c
create mode 100644 board/xburst/nanonote/u-boot-nand.lds
create mode 100644 include/configs/nanonote.h
create mode 100644 include/configs/qi_lb60.h
diff --git a/board/xburst/nanonote/Makefile b/board/xburst/nanonote/Makefile
new file mode 100644
index 000..a4f6bd0
--- /dev/null
+++ b/board/xburst/nanonote/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor,
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/xburst/nanonote/config.mk b/board/xburst/nanonote/config.mk
new file mode 100644
index 000..858e6a2
--- /dev/null
+++ b/board/xburst/nanonote/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2006 Qi Hardware, Inc.
+# Author: Xiangfu Liu
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
+#
+
+ifndef TEXT_BASE
+# ROM version
+# TEXT_BASE = 0x8800
+
+# RAM version
+TEXT_BASE = 0x8010
+endif
diff --git a/board/xburst/nanonote/nanonote.c b/board/xburst/nanonote/nanonote.c
new file mode 100644
index 000..977d034
--- /dev/null
+++ b/board/xburst/nanonote/nanonote.c
@@ -0,0 +1,110 @@
+/*
+ * Authors: Xiangfu Liu
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_init(void)
+{
+ /* Initialize NAND Flash Pins */
+ __gpio_as_nand();
+
+ /* Initialize SDRAM pins */
+ __gpio_as_sdram_16bit_4720();
+
+ /* Initialize LCD pins */
+ __gpio_as_lcd_18bit();
+
+ /* Initialize MSC pins */
+ __gpio_as_msc();
+
+ /* Initialize Other pins */
+ unsigned int i;
+ for (i = 0; i < 7; i++){
+ __gpio_as_input(GPIO_KEYIN_BASE + i);
+ __gpio_enable_pull(GPIO_KEYIN_BASE + i);
+ }
+
+ for (i = 0; i < 8; i++) {
+ __gpio_as_output(GPIO_KEYOUT_BASE + i);
+ __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
+ }
+
+ /* enable the TP4, TP5 as UART0 */
+ __gpio_jtag_to_uart0();
+
+ /*
+* Initialize UART0 pins, in Ben NanoNote uart0 and keyin8 use the
+* same gpio, init the gpio as uart0 cause a keyboard bug. so for
+* end u
[U-Boot] [PATCH v3 2/5] this is jz4740 head file
From: Xiangfu Liu Signed-off-by: Xiangfu Liu --- arch/mips/include/asm/jz4740.h | 1380 1 files changed, 1380 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/jz4740.h diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h new file mode 100644 index 000..5be26dc --- /dev/null +++ b/arch/mips/include/asm/jz4740.h @@ -0,0 +1,1380 @@ +/* + * Include file for Ingenic Semiconductor's JZ4740 CPU. + */ +#ifndef __JZ4740_H__ +#define __JZ4740_H__ + +#include +#include + +/* Boot ROM Specification */ +/* NOR Boot config */ +#define JZ4740_NORBOOT_8BIT0x /* 8-bit data bus flash */ +#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ +#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ +/* NAND Boot config */ +#define JZ4740_NANDBOOT_B8R3 0x /* 8-bit bus & 3 row cycles */ +#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ +#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ +#define JZ4740_NANDBOOT_B16R2 0x /* 16-bit bus & 2 row cycles */ + +/* Register Definitions */ +#defineCPM_BASE0xB000 +#defineINTC_BASE 0xB0001000 +#defineTCU_BASE0xB0002000 +#defineWDT_BASE0xB0002000 +#defineRTC_BASE0xB0003000 +#defineGPIO_BASE 0xB001 +#defineAIC_BASE0xB002 +#defineICDC_BASE 0xB002 +#defineMSC_BASE0xB0021000 +#defineUART0_BASE 0xB003 +#defineI2C_BASE0xB0042000 +#defineSSI_BASE0xB0043000 +#defineSADC_BASE 0xB007 +#defineEMC_BASE0xB301 +#defineDMAC_BASE 0xB302 +#defineUHC_BASE0xB303 +#defineUDC_BASE0xB304 +#defineLCD_BASE0xB305 +#defineSLCD_BASE 0xB305 +#defineCIM_BASE0xB306 +#defineETH_BASE0xB310 + +/* + * INTC (Interrupt Controller) + */ +#define INTC_ISR (INTC_BASE + 0x00) +#define INTC_IMR (INTC_BASE + 0x04) +#define INTC_IMSR (INTC_BASE + 0x08) +#define INTC_IMCR (INTC_BASE + 0x0c) +#define INTC_IPR (INTC_BASE + 0x10) + + +/* 1st-level interrupts */ +#define IRQ_I2C1 +#define IRQ_UHC3 +#define IRQ_UART0 9 +#define IRQ_SADC 12 +#define IRQ_MSC14 +#define IRQ_RTC15 +#define IRQ_SSI16 +#define IRQ_CIM17 +#define IRQ_AIC18 +#define IRQ_ETH19 +#define IRQ_DMAC 20 +#define IRQ_TCU2 21 +#define IRQ_TCU1 22 +#define IRQ_TCU0 23 +#define IRQ_UDC24 +#define IRQ_GPIO3 25 +#define IRQ_GPIO2 26 +#define IRQ_GPIO1 27 +#define IRQ_GPIO0 28 +#define IRQ_IPU29 +#define IRQ_LCD30 + +/* 2nd-level interrupts */ +#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ +#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ + +/* + * RTC + */ +#define RTC_RCR(RTC_BASE + 0x00) /* RTC Control Register */ +#define RTC_RSR(RTC_BASE + 0x04) /* RTC Second Register */ +#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ +#define RTC_RGR(RTC_BASE + 0x0c) /* RTC Regulator Register */ + +#define RTC_HCR(RTC_BASE + 0x20) /* Hibernate Control Register */ +#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ +#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ +#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ +#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ +#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ + + +/* RTC Control Register */ +#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ +#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ +#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ +#define RTC_RCR_AF (1 << 4) /* Alarm Flag */ +#define RTC_RCR_AIE(1 << 3) /* Alarm Interrupt Enable */ +#define RTC_RCR_AE (1 << 2) /* Alarm Enable */ +#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ + +/* RTC Regulator Register */ +#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ +#define RTC_RGR_ADJC_BIT 16 +#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) +#define RTC_RGR_NC1HZ_BIT 0 +#define RTC_RGR_NC1HZ_MASK (0x << RTC_RGR_NC1HZ_BIT) + +/* Hibernate Control Register */ +#define RTC_HCR_PD (1 << 0) /* Power Down */ + +/* Hibernate Wakeup Filter Counter Register */ +#define RTC_HWFCR_BIT
[U-Boot] [PATCH v3 3/5] jz4740 nand spl files
From: Xiangfu Liu
Signed-off-by: Xiangfu Liu
---
nand_spl/board/xburst/nanonote/Makefile | 96
nand_spl/board/xburst/nanonote/u-boot.lds | 63 ++
nand_spl/nand_boot_jz4740.c | 344 +
3 files changed, 503 insertions(+), 0 deletions(-)
create mode 100644 nand_spl/board/xburst/nanonote/Makefile
create mode 100644 nand_spl/board/xburst/nanonote/u-boot.lds
create mode 100644 nand_spl/nand_boot_jz4740.c
diff --git a/nand_spl/board/xburst/nanonote/Makefile
b/nand_spl/board/xburst/nanonote/Makefile
new file mode 100644
index 000..f5d1eb5
--- /dev/null
+++ b/nand_spl/board/xburst/nanonote/Makefile
@@ -0,0 +1,96 @@
+#
+# (C) Copyright 2006
+# Stefan Roese, DENX Software Engineering, s...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+TEXT_BASE = 0x8000
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL -O2
+
+SOBJS = start.o usbboot.o
+COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj:= $(OBJTREE)/nand_spl/
+
+ALL= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin
$(nandobj)u-boot-spl-16k.bin
+all: $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
+ dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
+ cat $< $(nandobj)junk1 > $(nandobj)junk2
+ dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
+ cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
+ dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
+ cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
+ dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
+ rm -f $(nandobj)junk*
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+$(obj)start.S:
+ @rm -f $(obj)start.S
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $(obj)start.S
+
+$(obj)usbboot.S:
+ @rm -f $(obj)usbboot.S
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/usbboot.S $(obj)usbboot.S
+
+$(obj)cpu.c:
+ @rm -f $(obj)cpu.c
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/cpu.c $(obj)cpu.c
+
+$(obj)jz4740.c:
+ @rm -f $(obj)jz4740.c
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz4740.c $(obj)jz4740.c
+
+$(obj)jz_serial.c:
+ @rm -f $(obj)jz_serial.c
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $(obj)jz_serial.c
+
+$(obj)nand_boot_jz4740.c:
+ @rm -f $(obj)nand_boot_jz4740.c
+ ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/nand_spl/board/xburst/nanonote/u-boot.lds
b/nand_spl/board/xburst/nanonote/u-boot.lds
new file mode 100644
index 000..7042388
--- /dev/null
+++ b/nand_spl/board/xburst/nanonote/u-boot.lds
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2005
+ * Ingenic Semiconductor,
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Te
[U-Boot] [PATCH v3 1/5] those files are jz4740 base files
From: Xiangfu Liu Signed-off-by: Xiangfu Liu --- arch/mips/cpu/xburst/Makefile| 50 +++ arch/mips/cpu/xburst/config.mk | 33 ++ arch/mips/cpu/xburst/cpu.c | 160 arch/mips/cpu/xburst/jz4740.c| 267 arch/mips/cpu/xburst/jz_serial.c | 128 ++ arch/mips/cpu/xburst/start.S | 165 arch/mips/cpu/xburst/start_spl.S | 63 +++ arch/mips/cpu/xburst/timer.c | 172 arch/mips/cpu/xburst/usbboot.S | 841 ++ 9 files changed, 1879 insertions(+), 0 deletions(-) create mode 100644 arch/mips/cpu/xburst/Makefile create mode 100644 arch/mips/cpu/xburst/config.mk create mode 100644 arch/mips/cpu/xburst/cpu.c create mode 100644 arch/mips/cpu/xburst/jz4740.c create mode 100644 arch/mips/cpu/xburst/jz_serial.c create mode 100644 arch/mips/cpu/xburst/start.S create mode 100644 arch/mips/cpu/xburst/start_spl.S create mode 100644 arch/mips/cpu/xburst/timer.c create mode 100644 arch/mips/cpu/xburst/usbboot.S diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile new file mode 100644 index 000..a9ab9ed --- /dev/null +++ b/arch/mips/cpu/xburst/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).a + +START = start.o +SOBJS-y= +COBJS-y = cpu.o timer.o jz_serial.o + +COBJS-$(CONFIG_JZ4740) += jz4740.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk new file mode 100644 index 000..fc9b255 --- /dev/null +++ b/arch/mips/cpu/xburst/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2) +MIPSFLAGS:=$(shell \ +if [ "$v" -lt "14" ]; then \ + echo "-mcpu=4kc"; \ +else \ + echo "-march=4kc -mtune=4kc"; \ +fi) + +MIPSFLAGS += -mabicalls -mips32 + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c new file mode 100644 index 000..22261cf --- /dev/null +++ b/arch/mips/cpu/xburst/cpu.c @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Gene
[U-Boot] [PATCH v3 0/5] new cpu, ingenic xburst jz4740
Hi Wolfgang those patches are for add xburst jz4740 and Ben NanoNote to U-Boot some info about xburst jz4740: the xburst jz4740 is recently added to linux 2.6.36 and it's support the device Ben NanoNote out of box, this xburst jz4740 cpu have one feature is Boot From USB, there is a small rom in jz4740, but LOW some PIN, the cpu will boot to this small rom, then init cpu and USB module, then we can send 8KB bin file to the cpu by USB(by using 'xbboot' or 'usbboot'[1]). which means if your bootloader is borken,(the first few KBs in NAND) you can always boot the device from usb, then reflash the nand. in OpenMoko FreeRunner, there are NOR and NAND. when people broken the nand bootloader, it's must boot from NOR, reflash the bootloader back when people broken the NAND and NOR, he(she) must reflash by using JTAG but in Ben NanoNote, we just need boot from usb. flash the nand again :) BTW:there are a lot of PMP, Audio device in China use the Xburst cpu, but I think they are all base on u-boot 1.1.6. by working on Ben NanoNote (http://en.qi-hardware.com) one year, we try to update the u-boot to last version and send it to upstream. :) for more info about Ingenic Xburst JZ4740 http://www.ingenic.cn/eng/default.aspx http://www.linux-mips.org/wiki/Ingenic this PATCH v3[2] fixed: 1. describe what Jz4740 SoC 2. remove the ENDIANNESS in config.mk 3. don't breaks the 80-charcter-wide rule 4. get rid of #if 0 5. use proper I/O accessors to access registers. 6. remove C++ comments, cleanup code style. 7.> +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin > > + dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1 > > + cat $< $(nandobj)junk1 > $(nandobj)junk2 > > + dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3 > > + cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4 > > + dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5 > > + cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6 > > + dd bs=1024 count=256 if=$(nandobj)junk6 of=$@ > > + rm -f $(nandobj)junk* Why do you need all this? when jz4740 boot from nand, it will try load the first 8kb of nand, when the first 8kb ECC is not correct, then it try load the another 8kb by offset 0x2000 of NAND. so those code try to create a bin image put the nand_spl to those two 8kb area. TODO: 1. Entry to MAINTAINERS mssing, Entry to boards.cfg missing. 2. I will try to contact Ingenic people. for add them to Acked-by 3. the '.set mips' ... I am not very understand, hopt I will fixed in next patches 4. try to fix all issue form "Re: [U-Boot] [PATCH 3/5] jz4740 nand spl files" from Scott 5. Please re-read http://www.denx.de/wiki/view/U-Boot/Patches#General_Patch_Submission_Rules try to send much better patches next time :) [1] 'usbboot' and 'xbboot' is part of 'xburst-tools' in Debian we recently upload it to Debian unstable package repos. [2] PATCH v1: I only send one patche, PATCH v2: the five patches, which still need a lot of works :) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/5] add Ben NanoNote board
From: Xiangfu Liu
Signed-off-by: Xiangfu Liu
---
board/xburst/nanonote/Makefile| 45
board/xburst/nanonote/config.mk | 31 ++
board/xburst/nanonote/nanonote.c | 124 ++
board/xburst/nanonote/u-boot-nand.lds | 63 +++
include/configs/nanonote.h| 188 +
include/configs/qi_lb60.h | 28 +
6 files changed, 479 insertions(+), 0 deletions(-)
create mode 100644 board/xburst/nanonote/Makefile
create mode 100644 board/xburst/nanonote/config.mk
create mode 100644 board/xburst/nanonote/nanonote.c
create mode 100644 board/xburst/nanonote/u-boot-nand.lds
create mode 100644 include/configs/nanonote.h
create mode 100644 include/configs/qi_lb60.h
diff --git a/board/xburst/nanonote/Makefile b/board/xburst/nanonote/Makefile
new file mode 100644
index 000..a4f6bd0
--- /dev/null
+++ b/board/xburst/nanonote/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor,
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/xburst/nanonote/config.mk b/board/xburst/nanonote/config.mk
new file mode 100644
index 000..858e6a2
--- /dev/null
+++ b/board/xburst/nanonote/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2006 Qi Hardware, Inc.
+# Author: Xiangfu Liu
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
+#
+
+ifndef TEXT_BASE
+# ROM version
+# TEXT_BASE = 0x8800
+
+# RAM version
+TEXT_BASE = 0x8010
+endif
diff --git a/board/xburst/nanonote/nanonote.c b/board/xburst/nanonote/nanonote.c
new file mode 100644
index 000..ef9552a
--- /dev/null
+++ b/board/xburst/nanonote/nanonote.c
@@ -0,0 +1,124 @@
+/*
+ * Authors: Xiangfu Liu
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_init(void)
+{
+ /*
+* Initialize NAND Flash Pins
+*/
+ __gpio_as_nand();
+
+ /*
+* Initialize SDRAM pins
+*/
+ __gpio_as_sdram_16bit_4720();
+
+ /*
+* Initialize LCD pins
+*/
+ __gpio_as_lcd_18bit();
+
+ /*
+* Initialize MSC pins
+*/
+ __gpio_as_msc();
+
+ /*
+* Initialize Other pins
+*/
+ unsigned int i;
+ for (i = 0; i < 7; i++){
+ __gpio_as_input(GPIO_KEYIN_BASE + i);
+ __gpio_enable_pull(GPIO_KEYIN_BASE + i);
+ }
+
+ for (i = 0; i < 8; i++) {
+ __gpio_as_output(GPIO_KEYOUT_BASE + i);
+ __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
+ }
+
+ /* enable the TP4, TP5 as UART0 */
+ __gpio_jtag_to_uart0();
+
+ /*
+* Initialize UART0 pins, in Ben NanoNote uar
[U-Boot] [PATCH 4/5] jz4740 nand driver
From: Xiangfu Liu
Signed-off-by: Xiangfu Liu
---
drivers/mtd/nand/jz4740_nand.c | 250
1 files changed, 250 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/jz4740_nand.c
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
new file mode 100644
index 000..f661b36
--- /dev/null
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -0,0 +1,250 @@
+/*
+ * Platform independend driver for JZ4740.
+ *
+ * Copyright (c) 2007 Ingenic Semiconductor Inc.
+ * Author:
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+#include
+
+#if defined(CONFIG_CMD_NAND)
+#include
+#include
+#include
+
+#define __nand_ecc_enable()(REG_EMC_NFECR = EMC_NFECR_ECCE |
EMC_NFECR_ERST )
+#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
+
+#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB800)
+#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
+#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x1)
+
+#define BIT(x) (1 << (x))
+#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
+#define JZ_NAND_ECC_CTRL_RSBIT(2)
+#define JZ_NAND_ECC_CTRL_RESET BIT(1)
+#define JZ_NAND_ECC_CTRL_ENABLEBIT(0)
+
+static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
+ .eccbytes = 72,
+ .eccpos = {
+ 12, 13, 14, 15, 16, 17, 18, 19,
+ 20, 21, 22, 23, 24, 25, 26, 27,
+ 28, 29, 30, 31, 32, 33, 34, 35,
+ 36, 37, 38, 39, 40, 41, 42, 43,
+ 44, 45, 46, 47, 48, 49, 50, 51,
+ 52, 53, 54, 55, 56, 57, 58, 59,
+ 60, 61, 62, 63, 64, 65, 66, 67,
+ 68, 69, 70, 71, 72, 73, 74, 75,
+ 76, 77, 78, 79, 80, 81, 82, 83},
+ .oobfree = {
+ {.offset = 2,
+.length = 10},
+ {.offset = 84,
+.length = 44}}
+};
+
+static int is_reading;
+
+static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if (ctrl & NAND_ALE)
+ this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
+ else if (ctrl & NAND_CLE)
+ this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
+ else
+ this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
+
+ if (ctrl & NAND_NCE)
+ REG_EMC_NFCSR |= EMC_NFCSR_NFCE1;
+ else
+ REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+static int jz_nand_device_ready(struct mtd_info *mtd)
+{
+ udelay(20);
+ return (REG_GPIO_PXPIN(2) & 0x4000) ? 1 : 0;
+}
+
+void board_nand_select_device(struct nand_chip *nand, int chip)
+{
+ /*
+* Don't use "chip" to address the NAND device,
+* generate the cs from the address where it is encoded.
+*/
+}
+
+static int jz_nand_rs_calculate_ecc(struct mtd_info* mtd, const u_char* dat,
+ u_char* ecc_code)
+{
+ uint32_t reg, status;
+ int i;
+ volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
+
+ if(is_reading)
+ return 0;
+
+ do {
+ status = REG_EMC_NFINTS;
+ } while(!(status & EMC_NFINTS_ENCF));
+
+ __nand_ecc_disable();
+
+ for(i = 0; i < 9; i++)
+ ecc_code[i] = *(paraddr + i);
+
+ return 0;
+}
+
+static void jz_nand_hwctl(struct mtd_info* mtd, int mode)
+{
+ uint32_t reg;
+ REG_EMC_NFINTS = 0;
+ reg = REG_EMC_NFECR;
+ reg |= JZ_NAND_ECC_CTRL_RESET;
+ reg |= JZ_NAND_ECC_CTRL_ENABLE;
+ reg |= JZ_NAND_ECC_CTRL_RS;
+
+ switch(mode) {
+ case NAND_ECC_READ:
+ reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
+ is_reading = 1;
+ break;
+ case NAND_ECC_WRITE:
+ reg |= JZ_NAND_ECC_CTRL_ENCODING;
+ is_reading = 0;
+ break;
+ default:
+ break;
+ }
+
+ REG_EMC_NFECR = reg;
+}
+
+/* Correct 1~9-bit errors in 512-bytes data */
+static void jz_rs_correct(unsigned char *dat, int idx, int mask)
+{
+ int i;
+
+ idx--;
+
+ i = idx + (idx >> 3);
+ if (i >= 512)
+ return;
+
+ mask <<= (idx & 0x7);
+
+ dat[i] ^= mask & 0xff;
+ if (i < 511)
+ dat[i+1] ^= (mask >> 8) & 0xff;
+}
+
+static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
+ u
[U-Boot] [PATCH 3/5] jz4740 nand spl files
From: Xiangfu Liu
Signed-off-by: Xiangfu Liu
---
nand_spl/board/xburst/nanonote/Makefile | 96 +++
nand_spl/board/xburst/nanonote/u-boot.lds | 63 +
nand_spl/nand_boot_jz4740.c | 395 +
3 files changed, 554 insertions(+), 0 deletions(-)
create mode 100644 nand_spl/board/xburst/nanonote/Makefile
create mode 100644 nand_spl/board/xburst/nanonote/u-boot.lds
create mode 100644 nand_spl/nand_boot_jz4740.c
diff --git a/nand_spl/board/xburst/nanonote/Makefile
b/nand_spl/board/xburst/nanonote/Makefile
new file mode 100644
index 000..f5d1eb5
--- /dev/null
+++ b/nand_spl/board/xburst/nanonote/Makefile
@@ -0,0 +1,96 @@
+#
+# (C) Copyright 2006
+# Stefan Roese, DENX Software Engineering, s...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+TEXT_BASE = 0x8000
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL -O2
+
+SOBJS = start.o usbboot.o
+COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj:= $(OBJTREE)/nand_spl/
+
+ALL= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin
$(nandobj)u-boot-spl-16k.bin
+all: $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
+ dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
+ cat $< $(nandobj)junk1 > $(nandobj)junk2
+ dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
+ cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
+ dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
+ cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
+ dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
+ rm -f $(nandobj)junk*
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+$(obj)start.S:
+ @rm -f $(obj)start.S
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $(obj)start.S
+
+$(obj)usbboot.S:
+ @rm -f $(obj)usbboot.S
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/usbboot.S $(obj)usbboot.S
+
+$(obj)cpu.c:
+ @rm -f $(obj)cpu.c
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/cpu.c $(obj)cpu.c
+
+$(obj)jz4740.c:
+ @rm -f $(obj)jz4740.c
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz4740.c $(obj)jz4740.c
+
+$(obj)jz_serial.c:
+ @rm -f $(obj)jz_serial.c
+ ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $(obj)jz_serial.c
+
+$(obj)nand_boot_jz4740.c:
+ @rm -f $(obj)nand_boot_jz4740.c
+ ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/nand_spl/board/xburst/nanonote/u-boot.lds
b/nand_spl/board/xburst/nanonote/u-boot.lds
new file mode 100644
index 000..7042388
--- /dev/null
+++ b/nand_spl/board/xburst/nanonote/u-boot.lds
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2005
+ * Ingenic Semiconductor,
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Pla
[U-Boot] [PATCH 1/5] those files are jz4740 base files
From: Xiangfu Liu Signed-off-by: Xiangfu Liu --- arch/mips/cpu/xburst/Makefile | 50 +++ arch/mips/cpu/xburst/config.mk| 33 ++ arch/mips/cpu/xburst/cpu.c| 158 +++ arch/mips/cpu/xburst/interrupts.c | 33 ++ arch/mips/cpu/xburst/jz4740.c | 257 +++ arch/mips/cpu/xburst/jz_serial.c | 139 ++ arch/mips/cpu/xburst/start.S | 165 +++ arch/mips/cpu/xburst/start_spl.S | 63 +++ arch/mips/cpu/xburst/timer.c | 174 arch/mips/cpu/xburst/usbboot.S| 880 + 10 files changed, 1952 insertions(+), 0 deletions(-) create mode 100644 arch/mips/cpu/xburst/Makefile create mode 100644 arch/mips/cpu/xburst/config.mk create mode 100644 arch/mips/cpu/xburst/cpu.c create mode 100644 arch/mips/cpu/xburst/interrupts.c create mode 100644 arch/mips/cpu/xburst/jz4740.c create mode 100644 arch/mips/cpu/xburst/jz_serial.c create mode 100644 arch/mips/cpu/xburst/start.S create mode 100644 arch/mips/cpu/xburst/start_spl.S create mode 100644 arch/mips/cpu/xburst/timer.c create mode 100644 arch/mips/cpu/xburst/usbboot.S diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile new file mode 100644 index 000..2e29851 --- /dev/null +++ b/arch/mips/cpu/xburst/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).a + +START = start.o +SOBJS-y= +COBJS-y = cpu.o interrupts.o timer.o jz_serial.o + +COBJS-$(CONFIG_JZ4740) += jz4740.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk new file mode 100644 index 000..f43f53b --- /dev/null +++ b/arch/mips/cpu/xburst/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2) +MIPSFLAGS:=$(shell \ +if [ "$v" -lt "14" ]; then \ + echo "-mcpu=4kc"; \ +else \ + echo "-march=4kc -mtune=4kc"; \ +fi) + +MIPSFLAGS += $(ENDIANNESS) -mabicalls -mips32 + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c new file mode 100644 index 000..682debf --- /dev/null +++ b/arch/mips/cpu/xburst/cpu.c @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * bu
[U-Boot] [PATCH 0/5] [MIPS] add jz4740 base file and Ben NanoNote
Hi Shinya very thanks for your feed pack, and I am really sorry for so later reply. the "[PATCH 1/5] those files are jz4740 base files" is patch v2 of "[PATCH] [MIPS] those files are jz4740 base files" I have try to fix all your comments. only one thing, I am not very understand the "flash cache" stuff, so I maybe still keep the flash ICache DCache like before. please give me some feedback. now I have more time working on U-Boot :) thanks very much. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] MIPS relocation?
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hi Heiko
by applied this patch. both works fine.
On 10/04/2010 10:49 PM, Heiko Schocher wrote:
> Hello Xiangfu,
>
> Xiangfu Liu wrote:
>> Hi Wolfgang Denk
>>
>> since my board (Ben NanoNote) is mips.
>> so I test the those commands in my board.
>>
>> printenv, saveenv: works fine.
>> env print, evn save: make U-Boot hang. (then I must reset the board)
>
> as I thought ... can you try following patch:
>
> From 276bcedbd581b11665a5424b274ae30d07245e1f Mon Sep 17 00:00:00 2001
> From: Heiko Schocher
> Date: Mon, 4 Oct 2010 10:28:58 +0200
> Subject: [PATCH] env: fix cmd_env_sub fct pointers if
> CONFIG_RELOC_FIXUP_WORKS is not defined
>
> commit ea882baf9c17cd142c99e3ff640d3ab01daa5cec introduces
> a command_sub_table for the "env" command. On arm, avr32, m68k,
> mips and sparc architectures, relocation needs manual fixups,
> so add this for this sub command table too.
>
> Tested on the qong board.
>
> Signed-off-by: Heiko Schocher
> ---
> common/cmd_nvedit.c |6 ++
> common/env_common.c |5 +
> 2 files changed, 11 insertions(+), 0 deletions(-)
>
> diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
> index c3d63b8..16f5fb0 100644
> --- a/common/cmd_nvedit.c
> +++ b/common/cmd_nvedit.c
> @@ -837,6 +837,12 @@ static cmd_tbl_t cmd_env_sub[] = {
> U_BOOT_CMD_MKENT(set, CONFIG_SYS_MAXARGS, 0, do_env_set, "", ""),
> };
>
> +#if !defined(CONFIG_RELOC_FIXUP_WORKS)
> +void env_reloc(void) {
> + fixup_cmdtable(cmd_env_sub, ARRAY_SIZE(cmd_env_sub));
> +}
> +#endif
> +
> static int do_env (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> cmd_tbl_t *cp;
> diff --git a/common/env_common.c b/common/env_common.c
> index a415ef8..88f068c 100644
> --- a/common/env_common.c
> +++ b/common/env_common.c
> @@ -227,6 +227,11 @@ int env_import(const char *buf, int check)
>
> void env_relocate (void)
> {
> +#if !defined(CONFIG_RELOC_FIXUP_WORKS)
> + extern void env_reloc(void);
> +
> + env_reloc();
> +#endif
> if (gd->env_valid == 0) {
> #if defined(CONFIG_ENV_IS_NOWHERE) /* Environment not changable */
> set_default_env(NULL);
- --
Best Regards
Xiangfu Liu
http://www.openmobilefree.net
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.10 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/
iEYEARECAAYFAkyp7I4ACgkQRRAEFRxkgLR/RACgmpYBqc74PeMT3DkngPy9zuD6
bAMAoISoyBKy4A1B3aTmLdg0hFsLRYMS
=hr/V
-END PGP SIGNATURE-
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] MIPS relocation?
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Wolfgang Denk since my board (Ben NanoNote) is mips. so I test the those commands in my board. printenv, saveenv: works fine. env print, evn save: make U-Boot hang. (then I must reset the board) - -- my board patch never touch the common/ folder. if I have time I will try to debug. On 10/04/2010 09:03 PM, Wolfgang Denk wrote: > Dear Shinya Kuribayashi, > > with all the discussion about relocation on ARM going on, Heiko and me > wondered if we had similar problems on MIPS. Unfortunately don't we > have to any MIPS board that could be used for testing. > > Could you please tru and check if the current top-of-tree version of > U-Boot still works on MIPS systems? Please check especially if the new > environment commands work, i. e. please try out: > > printenvversus env print > saveenv versus env save > > Thanks in advance! > > Best regards, > > Wolfgang Denk > - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAkyp6DEACgkQRRAEFRxkgLTylQCgkZjmI5Tn3q70/3Lr+NkArWsC HIkAoInQvU3P/PU1N2CWJML9RKfFE9+h =0LVF -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] fix little endian build
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 09/01/2010 08:48 AM, Shinya Kuribayashi wrote: > On 8/31/2010 10:36 AM, Shinya Kuribayashi wrote: >>> As said in the previous mail the patch is tentative and won't >>> work with ELDK, and as fas as I could see nothing has been >>> changed since my version. >> >> So I'm overlooking something, will have to think about it. > > Oh, I remember now. The aim of the patch is to make it possible to > generate elf images in both Big- and Little-endian, using only either > mips_4KC- or mips_4KCle- toolchain: > > # CROSS_COMPILE Target Expected endianness > -- > 1 mips_4KC- dbau1550_config Big-Endian > 2 mips_4KCle- dbau1550_config Big-Endian > 3 mips_4KC- dbau1550_el_config Little-Endian > 4 mips_4KCle- dbau1550_el_config Little-Endian > > And option 2) and 3) may not work when using ELDK. Hi Shinya I will try to look into this issue. thanks for the info. - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAkx9zDMACgkQRRAEFRxkgLQctwCgsdVkbbDSelUzRZLGCQYwe5f6 VpQAniLV3ElD7reDMcQHndKC7yf+MyM0 =XXyq -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] fix little endian build
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 08/31/2010 09:29 AM, Shinya Kuribayashi wrote: > On 8/31/2010 10:00 AM, Xiangfu Liu wrote: >> xian...@openmobilefree:~/u-boot/u-boot.git$ file u-boot >> u-boot: ELF 32-bit LSB executable, MIPS, MIPS32 version 1 (SYSV), statically >> linked, not stripped > > My bad sorry. Could you provide output from readelf? > > $ readelf u-boot xian...@openmobilefree:~/u-boot/u-boot.git$ readelf -h u-boot ELF Header: Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00 Class: ELF32 Data: 2's complement, little endian Version: 1 (current) OS/ABI:UNIX - System V ABI Version: 0 Type: EXEC (Executable file) Machine: MIPS R3000 Version: 0x1 Entry point address: 0xbfc0 Start of program headers: 52 (bytes into file) Start of section headers: 374000 (bytes into file) Flags: 0x50001007, noreorder, pic, cpic, o32, mips32 Size of this header: 52 (bytes) Size of program headers: 32 (bytes) Number of program headers: 2 Size of section headers: 40 (bytes) Number of section headers: 26 Section header string table index: 23 - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAkx8iNkACgkQRRAEFRxkgLS+8wCeKKPIJuwAVWb4QTF2wrsCfr27 T1IAniAZT18XFab/ZZ7nLDxshZplL+KD =rRQF -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] fix little endian build
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 08/30/2010 11:12 PM, Shinya Kuribayashi wrote: > What about the endianness of generated u-boot ELF image then? > > $ CROSS_COMPILE=mips_4KCle- ./MAKEALL dbau1550_el_config > $ file u-boot > Hi Shinya here is the info: xian...@openmobilefree:~/u-boot/u-boot.git$ CROSS_COMPILE=~/u-boot/mips/usr/bin/mips_4KCle- ./MAKEALL dbau1550_el Configuring for dbau1x00 board... board.c: In function 'board_init_r': board.c:331: warning: assignment from incompatible pointer type textdata bss dec hex filename 1218634976 18924 145763 23963 ./u-boot - - SUMMARY Boards compiled: 1 Boards with warnings or errors: 1 ( dbau1550_el ) - -- xian...@openmobilefree:~/u-boot/u-boot.git$ file u-boot u-boot: ELF 32-bit LSB executable, MIPS, MIPS32 version 1 (SYSV), statically linked, not stripped > And could you also provide the version info, please? > > $ mips_4KCle-gcc --version xian...@openmobilefree:~/u-boot/u-boot.git$ ~/u-boot/mips/usr/bin/mips_4KCle-gcc --version mips_4KCle-gcc (GCC) 4.0.0 (DENX ELDK 4.1 4.0.0) Copyright (C) 2005 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAkx8VDUACgkQRRAEFRxkgLSj/QCeJNvYDAaGBdqjstJYFWr97GoY 3xoAn1rDYCJaBEsG3uDw8zfjORGqCm84 =92rb -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] fix little endian build
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 08/30/2010 09:23 PM, Shinya Kuribayashi wrote: > On 8/30/10 6:53 PM, Xiangfu Liu wrote: >> can we apply those patch to MIPS-branch first?? > >> [PATCH 1/2] update the MIPS u-boot.lds > > I'll push 1/2 to u-boot-mips and request pull later. > >> [PATCH 2/2] change the way of build little endian board > > but this 2/2 looks problematic. > > As said in the previous mail the patch is tentative and won't > work with ELDK, and as fas as I could see nothing has been > changed since my version. Let me make sure, have you confirmed > it builds with ELDK? Hi Shinya yes, I think it not break the ELDK build. I have test with BUILD_DIR=../u-boot-build \ MAKEALL_LOGDIR=../u-boot-log \ ./MAKEALL mips_el mips all boards compile fine. - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAkx7tYoACgkQRRAEFRxkgLTqGQCeOFdXGSN3OE5Bb1dBIFwi+oqv 5goAoKjGIiKo7JQJlxpxOqGPA/W5aUEv =RU7F -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fix the c_size, in CSD Version 2.0, it's 22 bits
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Reinhard thanks for reply. On 08/30/2010 07:08 PM, Reinhard Meyer wrote: > Xiangfu Liu schrieb: >> Signed-off-by: Xiangfu Liu >> --- >> include/mmc.h |2 +- >> 1 files changed, 1 insertions(+), 1 deletions(-) >> >> diff --git a/include/mmc.h b/include/mmc.h >> index fcb237e..b913a60 100644 >> --- a/include/mmc.h >> +++ b/include/mmc.h >> @@ -189,12 +189,12 @@ struct mmc_csd >> u8 tran_speed; >> u16 ccc:12, >> read_bl_len:4; >> +u32 c_size:22; >> u64 read_bl_partial:1, >> write_blk_misalign:1, >> read_blk_misalign:1, >> dsr_imp:1, >> rsvd2:2, >> -c_size:12, >> vdd_r_curr_min:3, >> vdd_r_curr_max:3, >> vdd_w_curr_min:3, > > NAK > > This structure approach is awfully broken. LE/BE > issues, c_size spans over a 32 bit boundary! > > The generic MMC works fine with no such structure. > > I already proposed in earlier patches to finally > remove that structure. > > Reinhard > - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAkx7pNoACgkQRRAEFRxkgLRivQCglcRpN3tjUs2ptn3l4e6+JvW0 gV0Aniqr8mgjF3DjR+M70a66DSvte4ew =xfDj -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] fix the c_size, in CSD Version 2.0, it's 22 bits
Signed-off-by: Xiangfu Liu --- include/mmc.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/mmc.h b/include/mmc.h index fcb237e..b913a60 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -189,12 +189,12 @@ struct mmc_csd u8 tran_speed; u16 ccc:12, read_bl_len:4; + u32 c_size:22; u64 read_bl_partial:1, write_blk_misalign:1, read_blk_misalign:1, dsr_imp:1, rsvd2:2, - c_size:12, vdd_r_curr_min:3, vdd_r_curr_max:3, vdd_w_curr_min:3, -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] fix little endian build
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Skuribay, Woflgang can we apply those patch to MIPS-branch first?? On 08/09/2010 11:13 PM, xian...@openmobilefree.net wrote: > From: Xiangfu Liu > > those two patches fix the little endian build. > done by Shinya Kuribayashi. > > Makefile |1 + > arch/mips/config.mk | 27 +-- > arch/mips/cpu/config.mk |8 > board/dbau1x00/u-boot.lds|2 +- > board/gth2/u-boot.lds|2 +- > board/incaip/u-boot.lds |2 +- > board/pb1x00/u-boot.lds |2 +- > board/purple/u-boot.lds |2 +- > board/qemu-mips/u-boot.lds |2 +- > examples/standalone/mips.lds |2 +- > include/configs/pb1x00.h |2 ++ > 11 files changed, 35 insertions(+), 17 deletions(-) > - -- Best Regards Xiangfu Liu http://www.openmobilefree.net -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAkx7f34ACgkQRRAEFRxkgLTkIQCePWThBoVT5a5tt9vf81i4NRth pecAoIYPsUqBP7ZWiJo85vPkMsmnyUAd =Np7C -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MX51EVK: fix return value of get_timer_masked
Hi > Hi Liu: > Thanks for you help, but I need more :) > I'm newbie to such maillist. I post this small patch to check > if everything is OK, but... > > There are something I want know: > 1. Does "base-64 encoded" problem still exist in this message? the last two emails you send are same. first one is "base-64 encoded" second is good. > 2. Should I follow this thread, or resend a new one? > I think send a new one title with "[PATCH] v2". you should use "git send-email" to send patch emails. -- Best Regards Xiangfu Liu http://www.openmobilefree.net ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MX51EVK: fix return value of get_timer_masked
Hi Haibo Li I am try to help on test patch. :) you should not include the reply in your patch. those reply message will goto git commit message which is not needed. On 08/10/2010 10:57 AM, Li Haibo wrote: >> Wolfgang Denk wrote: >>> Dear Stefano, >>> >> >> Hi Wolfgang, >> >>> Can you please have a look at this, and eventually send a pull req? >>> Thanks. >> >> Thanks, I missed it. I would change the name of the maintainer and I >> will set myself for the MX51EVK, because Fred Fan resigned as maintainer >> for this board. >> >> Li, could you please resend your patch as text ? It was sent as base-64 >> encoded, and I cannot directly apply it. >> >> Thanks, >> Stefano Babic >> -- Best Regards Xiangfu Liu http://www.openmobilefree.net ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] change the way of build little endian board
On 08/10/2010 01:10 AM, Mike Frysinger wrote: > On Mon, Aug 9, 2010 at 11:13 AM, wrote: >> add CONFIG_CPU_LITTLE_ENDIAN to little endian board config. >> use -dumpmachine to check if the cross compile. >> >> --- >> Makefile |1 + >> arch/mips/config.mk | 27 +-- >> arch/mips/cpu/config.mk |8 >> include/configs/pb1x00.h |2 ++ > > since this is a mips-specific issue, please prefix your summaries > accordingly. so the subject should be something like: >mips: change the way of build little endian board > > that way non-mips people can easily ignore this e-mail > -mike Hi Mike thanks for the advice. I will do that next time. -- Best Regards Xiangfu Liu http://www.openmobilefree.net ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] change the way of build little endian board
add CONFIG_CPU_LITTLE_ENDIAN to little endian board config. use -dumpmachine to check if the cross compile. Signed-off-by: Xiangfu Liu Acked-by: Shinya Kuribayashi --- Makefile |1 + arch/mips/config.mk | 27 +-- arch/mips/cpu/config.mk |8 include/configs/pb1x00.h |2 ++ 4 files changed, 28 insertions(+), 10 deletions(-) diff --git a/Makefile b/Makefile index 451ccdd..47b5622 100644 --- a/Makefile +++ b/Makefile @@ -2306,6 +2306,7 @@ dbau1550_config : unconfig dbau1550_el_config : unconfig @mkdir -p $(obj)include @echo "#define CONFIG_DBAU1550 1" >$(obj)include/config.h + @echo "#define CONFIG_CPU_LITTLE_ENDIAN" >>$(obj)include/config.h @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00 gth2_config: unconfig diff --git a/arch/mips/config.mk b/arch/mips/config.mk index aa06761..f5d9ac5 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -23,8 +23,6 @@ CROSS_COMPILE ?= mips_4KC- -STANDALONE_LOAD_ADDR = 0x8020 -T mips.lds - PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ # @@ -50,3 +48,28 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic PLATFORM_CPPFLAGS += -msoft-float PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib + +# +# We explicitly add the endianness specifier if needed, this allows +# to compile kernels with a toolchain for the other endianness. We +# carefully avoid to add it redundantly because gcc 3.3/3.4 complains +# when fed the toolchain default! +# +# Certain gcc versions upto gcc 4.1.1 (probably 4.2-subversion as of +# 2006-10-10 don't properly change the predefined symbols if -EB / -EL +# are used, so we kludge that here. A bug has been filed at +# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29413. +# +UNDEF_ALL += -UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ +UNDEF_ALL += -UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ +PREDEF_BE += -DMIPSEB -D_MIPSEB -D__MIPSEB -D__MIPSEB__ +PREDEF_LE += -DMIPSEL -D_MIPSEL -D__MIPSEL -D__MIPSEL__ +ifdef CONFIG_CPU_LITTLE_ENDIAN +PLATFORM_CPPFLAGS += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(UNDEF_ALL) $(PREDEF_LE)) +PLATFORM_LDFLAGS += -EL +else +PLATFORM_CPPFLAGS += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB $(UNDEF_ALL) $(PREDEF_BE)) +PLATFORM_LDFLAGS += -EB +endif + +STANDALONE_LOAD_ADDR = 0x8020 -T mips.lds $(PLATFORM_LDFLAGS) diff --git a/arch/mips/cpu/config.mk b/arch/mips/cpu/config.mk index a173c54..098d6c7 100644 --- a/arch/mips/cpu/config.mk +++ b/arch/mips/cpu/config.mk @@ -28,12 +28,4 @@ else \ echo "-march=4kc -mtune=4kc"; \ fi) -ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) -ENDIANNESS = -EL -else -ENDIANNESS = -EB -endif - -MIPSFLAGS += $(ENDIANNESS) - PLATFORM_CPPFLAGS += $(MIPSFLAGS) diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 5ad745e..49ca07c 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -28,6 +28,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_CPU_LITTLE_ENDIAN + #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_PB1X00 1 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] update the MIPS u-boot.lds
>From the document, if set all arguments in "OUTPUT_FORMAT"
to "tradbigmips", then even add "-EL" to gcc we still get
EB format.
pb1x00 is only used in Little-endian,
so its default endian should be set to LE as well.
Signed-off-by: Xiangfu Liu
Acked-by: Shinya Kuribayashi
---
board/dbau1x00/u-boot.lds|2 +-
board/gth2/u-boot.lds|2 +-
board/incaip/u-boot.lds |2 +-
board/pb1x00/u-boot.lds |2 +-
board/purple/u-boot.lds |2 +-
board/qemu-mips/u-boot.lds |2 +-
examples/standalone/mips.lds |2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds
index 9a6cd1b..3c4fbe3 100644
--- a/board/dbau1x00/u-boot.lds
+++ b/board/dbau1x00/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds
index e6eee9b..aeb0fcc 100644
--- a/board/gth2/u-boot.lds
+++ b/board/gth2/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds
index 9a6cd1b..3c4fbe3 100644
--- a/board/incaip/u-boot.lds
+++ b/board/incaip/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds
index 9a6cd1b..358cc54 100644
--- a/board/pb1x00/u-boot.lds
+++ b/board/pb1x00/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips",
"elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds
index 1881e65..542601a 100644
--- a/board/purple/u-boot.lds
+++ b/board/purple/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index ad058ca..bd16786 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/examples/standalone/mips.lds b/examples/standalone/mips.lds
index 717b201..63a1c92 100644
--- a/examples/standalone/mips.lds
+++ b/examples/standalone/mips.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
SECTIONS
{
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] fix little endian build
From: Xiangfu Liu those two patches fix the little endian build. done by Shinya Kuribayashi. Makefile |1 + arch/mips/config.mk | 27 +-- arch/mips/cpu/config.mk |8 board/dbau1x00/u-boot.lds|2 +- board/gth2/u-boot.lds|2 +- board/incaip/u-boot.lds |2 +- board/pb1x00/u-boot.lds |2 +- board/purple/u-boot.lds |2 +- board/qemu-mips/u-boot.lds |2 +- examples/standalone/mips.lds |2 +- include/configs/pb1x00.h |2 ++ 11 files changed, 35 insertions(+), 17 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] update the MIPS u-boot.lds
>From the document, if set all arguments in "OUTPUT_FORMAT"
to "tradbigmips", then even add "-EL" to gcc we still get
EB format.
pb1x00 is only used in Little-endian,
so its default endian should be set to LE as well
Signed-off-by: Xiangfu Liu
Acked-by: Shinya Kuribayashi
---
Hi Wolfgang
sorry, please ignore the my last email about this patch.
Hi Shinya
thanks for your patient on teach me patch stuff.
I will never stop learning :).
v1:
From the document, if set all arguments in "OUTPUT_FORMAT"
to "tradbigmips", then even add "-EL" to gcc we still get
EB format.
v2:
pb1x00 is only used in Little-endian,
so its default endian should be set to LE as well
v3:
only fix the patch format issue.
board/dbau1x00/u-boot.lds|2 +-
board/gth2/u-boot.lds|2 +-
board/incaip/u-boot.lds |2 +-
board/pb1x00/u-boot.lds |2 +-
board/purple/u-boot.lds |2 +-
board/qemu-mips/u-boot.lds |2 +-
examples/standalone/mips.lds |2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds
index 9a6cd1b..3c4fbe3 100644
--- a/board/dbau1x00/u-boot.lds
+++ b/board/dbau1x00/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds
index e6eee9b..aeb0fcc 100644
--- a/board/gth2/u-boot.lds
+++ b/board/gth2/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds
index 9a6cd1b..3c4fbe3 100644
--- a/board/incaip/u-boot.lds
+++ b/board/incaip/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds
index 9a6cd1b..358cc54 100644
--- a/board/pb1x00/u-boot.lds
+++ b/board/pb1x00/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips",
"elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds
index 1881e65..542601a 100644
--- a/board/purple/u-boot.lds
+++ b/board/purple/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index ad058ca..bd16786 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/examples/standalone/mips.lds b/examples/standalone/mips.lds
index 717b201..63a1c92 100644
--- a/examples/standalone/mips.lds
+++ b/examples/standalone/mips.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
SECTIONS
{
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] update the MIPS u-boot.lds
From: Xiangfu Liu
pb1x00 is only used in Little-endian,
so its default endian should be set to LE as well
Signed-off-by: Xiangfu Liu
Acked-by: Shinya Kuribayashi
---
board/dbau1x00/u-boot.lds|2 +-
board/gth2/u-boot.lds|2 +-
board/incaip/u-boot.lds |2 +-
board/pb1x00/u-boot.lds |2 +-
board/purple/u-boot.lds |2 +-
board/qemu-mips/u-boot.lds |2 +-
examples/standalone/mips.lds |2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds
index 9a6cd1b..3c4fbe3 100644
--- a/board/dbau1x00/u-boot.lds
+++ b/board/dbau1x00/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds
index e6eee9b..aeb0fcc 100644
--- a/board/gth2/u-boot.lds
+++ b/board/gth2/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds
index 9a6cd1b..3c4fbe3 100644
--- a/board/incaip/u-boot.lds
+++ b/board/incaip/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds
index 9a6cd1b..358cc54 100644
--- a/board/pb1x00/u-boot.lds
+++ b/board/pb1x00/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips",
"elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds
index 1881e65..542601a 100644
--- a/board/purple/u-boot.lds
+++ b/board/purple/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index ad058ca..bd16786 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
diff --git a/examples/standalone/mips.lds b/examples/standalone/mips.lds
index 717b201..63a1c92 100644
--- a/examples/standalone/mips.lds
+++ b/examples/standalone/mips.lds
@@ -24,7 +24,7 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
SECTIONS
{
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] update the MIPS u-boot.lds
Hi Shinya On 08/03/2010 07:36 PM, Shinya Kuribayashi wrote: > Aconfccording to MAKEALL script, pb1000_ig is only used in Little- > endian, so its default endian should be set to LE as well. I too > missed this point in my previous patch. > thanks. > With fixing above nits, feel free to add: > > Acked-by: Shinya Kuribayashi > (by the way. I manually added this line to email. is the another way to add "Acked-by" like "Signed-off-by" is "-s") -- Best Regards Xiangfu Liu http://www.openmobilefree.net ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
