Re: [GIT PULL] u-boot-riscv/master
On Wed, Nov 06, 2024 at 08:12:06PM +0800, Leo Liang wrote:
> Hi Tom,
>
> The following changes since commit 56accc56b9aab87ef4809ccc588e1257969cd271:
>
> bios_emulator: fix first argument of pci_{read,write}_config_* function
> calls (2024-11-04 18:01:58 -0600)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to d5f5e778183d5908caa2954b9438614252b806dd:
>
> riscv: Introduce configuration for 64bit version Microblaze V (2024-11-06
> 19:42:54 +0800)
>
> CI result shows no issue:
> https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23239
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom,
The following changes since commit 56accc56b9aab87ef4809ccc588e1257969cd271:
bios_emulator: fix first argument of pci_{read,write}_config_* function calls
(2024-11-04 18:01:58 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to d5f5e778183d5908caa2954b9438614252b806dd:
riscv: Introduce configuration for 64bit version Microblaze V (2024-11-06
19:42:54 +0800)
CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23239
- configs: visionfive2 defconfig: re-enable SPL_SYS_MMCSD_RAW_MODE
- driver: sifive ccache: enable TRUNKCLOCKGATE & REGIONCLOCKGATE
- board: support 64bit Microblaze V
Andreas Schwab (1):
configs: visionfive2: re-enable SPL_SYS_MMCSD_RAW_MODE
Michal Simek (3):
xilinx: mbv: Place DTB by default to DDR location
xilinx: mbv: Align smode_defconfig with upstream QEMU
riscv: Introduce configuration for 64bit version Microblaze V
Nick Hu (1):
driver: sifive ccache: enable TRUNKCLOCKGATE and REGIONCLOCKGATE
arch/riscv/dts/Makefile| 1 +
arch/riscv/dts/xilinx-mbv64.dts| 99 ++
board/xilinx/Kconfig | 2 +-
configs/starfive_visionfive2_defconfig | 3 ++
configs/xilinx_mbv32_smode_defconfig | 12 ++---
configs/xilinx_mbv64_defconfig | 44 +++
configs/xilinx_mbv64_smode_defconfig | 48 +
drivers/cache/cache-sifive-ccache.c| 33 ++--
8 files changed, 232 insertions(+), 10 deletions(-)
create mode 100644 arch/riscv/dts/xilinx-mbv64.dts
create mode 100644 configs/xilinx_mbv64_defconfig
create mode 100644 configs/xilinx_mbv64_smode_defconfig
Best regards,
Leo
Re: [GIT PULL] u-boot-riscv/master
On Tue, Oct 29, 2024 at 08:33:54PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit bfdfc6c12e8ca68fff1a7ed3892c180143a6a0ef: > > Revert "acpi_table: Fix coverity defect in acpi_write_spcr" (2024-10-28 > 20:53:34 -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 239e4705099c7516f3d3cf958f3e540d635a4ed3: > > riscv: dts: mpfs: migrate to OF_UPSTREAM (2024-10-29 19:58:22 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23080 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit bfdfc6c12e8ca68fff1a7ed3892c180143a6a0ef: Revert "acpi_table: Fix coverity defect in acpi_write_spcr" (2024-10-28 20:53:34 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 239e4705099c7516f3d3cf958f3e540d635a4ed3: riscv: dts: mpfs: migrate to OF_UPSTREAM (2024-10-29 19:58:22 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23080 - board: migrate PolarFire to use OF_UPSTREAM - dts: align DT with QEMU amd-microblaze-v-virt platform - riscv: fix resume utility Anton Blanchard (1): riscv: resume needs to be a global Conor Dooley (3): clk: microchip: mpfs: support new syscon based devicetree configuration board: mpfs_icicle: imply new clk driver dependencies riscv: dts: mpfs: migrate to OF_UPSTREAM Michal Simek (1): riscv: mbv: Align DT with QEMU arch/riscv/dts/Makefile| 1 - arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi | 71 arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi | 14 - arch/riscv/dts/mpfs-icicle-kit.dts | 208 arch/riscv/dts/mpfs.dtsi | 511 - arch/riscv/dts/xilinx-mbv32.dts| 30 +- arch/riscv/include/asm/global_data.h | 1 + arch/riscv/lib/interrupts.c| 10 +- board/microchip/mpfs_icicle/Kconfig| 2 + board/xilinx/mbv/Kconfig | 6 +- configs/microchip_mpfs_icicle_defconfig| 4 +- configs/xilinx_mbv32_defconfig | 12 +- drivers/clk/microchip/Kconfig | 2 + drivers/clk/microchip/mpfs_clk.c | 63 +++- drivers/clk/microchip/mpfs_clk.h | 5 +- drivers/clk/microchip/mpfs_clk_cfg.c | 16 +- drivers/clk/microchip/mpfs_clk_periph.c| 37 +-- dts/upstream/src/riscv/Makefile| 6 + 18 files changed, 115 insertions(+), 884 deletions(-) delete mode 100644 arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi delete mode 100644 arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi delete mode 100644 arch/riscv/dts/mpfs-icicle-kit.dts delete mode 100644 arch/riscv/dts/mpfs.dtsi create mode 100644 dts/upstream/src/riscv/Makefile Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Mon, Oct 28, 2024 at 08:24:07PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 3df6145db0ed3430a2af089db5a82372bea3f4d5: > > x86: Missed removal of CMD_BOOTEFI_HELLO_COMPILE (2024-10-27 20:11:36 -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 9e859849e2caa17d730bc4507fd6ef3c7959d3b4: > > riscv: cache: Add CBO instructions (2024-10-28 18:56:54 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23051 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 3df6145db0ed3430a2af089db5a82372bea3f4d5: x86: Missed removal of CMD_BOOTEFI_HELLO_COMPILE (2024-10-27 20:11:36 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 9e859849e2caa17d730bc4507fd6ef3c7959d3b4: riscv: cache: Add CBO instructions (2024-10-28 18:56:54 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23051 - risc-v: Add Zicbom support - board: Support RVVM board - DTS: device tree fixes - configs: Enable some configs E Shattow (2): riscv64: dts: starfive: Star64 ethernet0 phy delay values sync with upstream Linux riscv64: dts: starfive: Mars ethernet0 phy delay values sync with upstream Linux Heinrich Schuchardt (3): cmd: sbi: Add FWFT, MPXY extensions riscv: add missing linefeed in error message configs: visionfive2: enable CONFIG_CMD_ERASEENV LekKit (3): riscv: qemu: Enable booting from NVMe riscv: qemu: Enable EFI framebuffer riscv: qemu: Explicitly advertise RVVM support Maksim Kiselev (2): gpio: dw: Add ngpios DT-property support configs: th1520_lpi4a: Enable CMD_GPIO, DM_GPIO and DWAPB_GPIO driver Mayuresh Chitale (2): riscv: Add support for defining instructions riscv: cache: Add CBO instructions arch/riscv/Kconfig | 6 ++- arch/riscv/include/asm/insn-def.h | 39 ++ arch/riscv/include/asm/sbi.h | 4 +- arch/riscv/lib/cache.c | 96 ++ arch/riscv/lib/fdt_fixup.c | 2 +- board/emulation/qemu-riscv/Kconfig | 2 + board/starfive/visionfive2/spl.c | 6 +-- cmd/riscv/sbi.c| 4 +- configs/starfive_visionfive2_defconfig | 1 + configs/th1520_lpi4a_defconfig | 4 +- drivers/gpio/dwapb_gpio.c | 4 +- include/configs/qemu-riscv.h | 1 + 12 files changed, 159 insertions(+), 10 deletions(-) create mode 100644 arch/riscv/include/asm/insn-def.h Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Tue, Sep 10, 2024 at 10:38:06AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 7b2d4ecd7f6593771dd3118c8bab525d727a91e0: > > Merge branch 'master-spi-fixes' of > https://source.denx.de/u-boot/custodians/u-boot-sh (2024-09-09 13:54:10 -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 1806fed0ce6b56365ecf6b84ce6d17aafd3af979: > > cmd: add rdcycle test to RISC-V exception command (2024-09-10 10:10:43 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/22292 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom,
The following changes since commit 7b2d4ecd7f6593771dd3118c8bab525d727a91e0:
Merge branch 'master-spi-fixes' of
https://source.denx.de/u-boot/custodians/u-boot-sh (2024-09-09 13:54:10 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 1806fed0ce6b56365ecf6b84ce6d17aafd3af979:
cmd: add rdcycle test to RISC-V exception command (2024-09-10 10:10:43 +0800)
CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/22292
- Add rdcycle to RISC-V exception command
- Some fixes and refactoring
Heinrich Schuchardt (7):
clk: sifive: append missing \n to messages
clk: sifive: avoid declaring static variables in includes
board: fix compatible property Milk-V Mars CM
riscv: CONFIG_SPL_FRAMEPOINTER must depend on CONFIG_SPL
riscv: allow to enable SHOW_REGS in main U-Boot only
riscv: show registers in crash dumps by default
cmd: add rdcycle test to RISC-V exception command
Maxim Kochetkov (1):
riscv: define find_{first,next}_zero_bit in asm/bitops.h
arch/riscv/Kconfig | 14
arch/riscv/include/asm/bitops.h | 40 +
arch/riscv/lib/interrupts.c | 7 +++---
board/starfive/visionfive2/spl.c| 15 ++---
cmd/riscv/exception.c | 15 +++--
drivers/clk/analogbits/wrpll-cln28hpc.c | 6 ++---
drivers/clk/sifive/fu540-prci.c | 7 +-
drivers/clk/sifive/fu540-prci.h | 22 --
drivers/clk/sifive/fu740-prci.c | 7 +-
drivers/clk/sifive/fu740-prci.h | 22 --
drivers/clk/sifive/sifive-prci.c| 3 +--
drivers/clk/sifive/sifive-prci.h| 4
12 files changed, 102 insertions(+), 60 deletions(-)
delete mode 100644 drivers/clk/sifive/fu540-prci.h
delete mode 100644 drivers/clk/sifive/fu740-prci.h
Best regards,
Leo
Re: [GIT PULL] u-boot-riscv/master
On Mon, Jul 22, 2024 at 04:29:39PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 5024a96db8ea6ff2e814f4599af9e5faf09296b7: > > Subtree merge tag 'v6.10-dts' of devicetree-rebasing repo [1] into > dts/upstream (2024-07-20 11:15:22 -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to dd3cd9eecc9846e7c37a97c9755d2a83fb995cbb: > > Revert "riscv: dts: jh7110: Enable PLL node in SPL" (2024-07-22 15:42:07 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/21724 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 5024a96db8ea6ff2e814f4599af9e5faf09296b7: Subtree merge tag 'v6.10-dts' of devicetree-rebasing repo [1] into dts/upstream (2024-07-20 11:15:22 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to dd3cd9eecc9846e7c37a97c9755d2a83fb995cbb: Revert "riscv: dts: jh7110: Enable PLL node in SPL" (2024-07-22 15:42:07 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/21724 Andreas Schwab (1): board: sifive: unmatched: remove extra space in fdtfile value Heinrich Schuchardt (2): riscv: add RISC-V fields to bdinfo command riscv: semihosting: correct alignment Leo Yu-Chi Liang (1): Revert "riscv: dts: jh7110: Enable PLL node in SPL" arch/riscv/dts/jh7110-u-boot.dtsi| 4 arch/riscv/lib/Makefile | 1 + arch/riscv/lib/bdinfo.c | 18 ++ arch/riscv/lib/semihosting.S | 2 +- board/sifive/unmatched/unmatched.env | 2 +- 5 files changed, 21 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/lib/bdinfo.c Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Thu, May 30, 2024 at 04:56:49PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 46ff00bea5dd2dd247d5e2fdadbf5dcf8653cd9a: > > Merge tag 'tpm-master-27052024' of > https://source.denx.de/u-boot/custodians/u-boot-tpm (2024-05-27 08:56:02 > -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 1d29c718b7ba09807f8060796d9c21772e3c1b52: > > andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND (2024-05-30 16:01:13 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20920 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 46ff00bea5dd2dd247d5e2fdadbf5dcf8653cd9a: Merge tag 'tpm-master-27052024' of https://source.denx.de/u-boot/custodians/u-boot-tpm (2024-05-27 08:56:02 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 1d29c718b7ba09807f8060796d9c21772e3c1b52: andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND (2024-05-30 16:01:13 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20920 - board: fix support for icicle - board: support Star64 board - andes: minor fixes - riscv: deprecate cache enablement in start.S Conor Dooley (2): board: microchip: icicle: correct type for node offset board: microchip: icicle: make both ethernets optional H Bell (2): board: starfive: support Pine64 Star64 board board: starfive: support Pine64 Star64 board Leo Yu-Chi Liang (3): andes: l2 cache driver: fixes typos and cctl status riscv: remove cache enablement in start.S andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND arch/riscv/cpu/andes/cache.c | 4 +- arch/riscv/cpu/start.S| 4 - arch/riscv/include/asm/arch-andes/csr.h | 2 +- board/microchip/mpfs_icicle/mpfs_icicle.c | 25 +-- board/starfive/visionfive2/spl.c | 89 ++ board/starfive/visionfive2/starfive_visionfive2.c | 4 + doc/board/starfive/index.rst | 1 + doc/board/starfive/pine64_star64.rst | 201 ++ drivers/cache/cache-andes-l2.c| 8 +- 9 files changed, 310 insertions(+), 28 deletions(-) create mode 100644 doc/board/starfive/pine64_star64.rst Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Tue, May 14, 2024 at 09:28:54PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit c8ffd1356d42223cbb8c86280a083cc3c93e6426: > > Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet" > (2024-05-13 09:15:51 -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 2b8dc36b4c515979da330a96d9fcc9bbbe5385fa: > > andes: Unify naming policy for Andes related source (2024-05-14 18:50:47 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20690 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom,
The following changes since commit c8ffd1356d42223cbb8c86280a083cc3c93e6426:
Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"
(2024-05-13 09:15:51 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 2b8dc36b4c515979da330a96d9fcc9bbbe5385fa:
andes: Unify naming policy for Andes related source (2024-05-14 18:50:47
+0800)
CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20690
- RISC-V: Add NULL check after parsing compatible string
- Board: Add Milk-V Mars CM board
- Andes: Unify naming policy
Hanyuan Zhao (1):
riscv: add NULL check before calling strlen in the riscv cpu's get_desc()
Heinrich Schuchardt (6):
board: starfive: function to read eMMC size
board: add support for Milk-V Mars CM
doc: Milk-V Mars CM and Milk-V Mars CM Lite
configs: visionfive2: enable SPL_YMODEM_SUPPORT
starfive: add mac vendor sub-command
riscv: simplify backtrace report
Leo Yu-Chi Liang (1):
andes: Unify naming policy for Andes related source
arch/riscv/Kconfig | 4 +-
arch/riscv/cpu/{andesv5 => andes}/Kconfig | 4 +-
arch/riscv/cpu/{andesv5 => andes}/Makefile | 0
arch/riscv/cpu/{andesv5 => andes}/cache.c | 12 +-
arch/riscv/cpu/{andesv5 => andes}/cpu.c| 0
arch/riscv/cpu/{andesv5 => andes}/spl.c| 0
arch/riscv/include/asm/arch-jh7110/eeprom.h| 7 +
arch/riscv/lib/interrupts.c| 16 +-
board/{AndesTech => andestech}/ae350/Kconfig | 6 +-
board/{AndesTech => andestech}/ae350/MAINTAINERS | 2 +-
board/{AndesTech => andestech}/ae350/Makefile | 0
board/{AndesTech => andestech}/ae350/ae350.c | 2 +-
board/starfive/visionfive2/Kconfig | 9 +
board/starfive/visionfive2/spl.c | 28 ++-
board/starfive/visionfive2/starfive_visionfive2.c | 11 +-
.../starfive/visionfive2/visionfive2-i2c-eeprom.c | 43 -
configs/starfive_visionfive2_defconfig | 1 +
doc/board/{AndesTech => andestech}/adp-ag101p.rst | 0
doc/board/{AndesTech => andestech}/ae350.rst | 0
doc/board/{AndesTech => andestech}/index.rst | 0
doc/board/index.rst| 2 +-
doc/board/starfive/index.rst | 3 +-
doc/board/starfive/milk-v_mars_cm.rst | 193 +
drivers/cache/Kconfig | 6 +-
drivers/cache/Makefile | 2 +-
drivers/cache/{cache-v5l2.c => cache-andes-l2.c} | 40 ++---
drivers/cpu/riscv_cpu.c| 2 +-
27 files changed, 337 insertions(+), 56 deletions(-)
rename arch/riscv/cpu/{andesv5 => andes}/Kconfig (91%)
rename arch/riscv/cpu/{andesv5 => andes}/Makefile (100%)
rename arch/riscv/cpu/{andesv5 => andes}/cache.c (90%)
rename arch/riscv/cpu/{andesv5 => andes}/cpu.c (100%)
rename arch/riscv/cpu/{andesv5 => andes}/spl.c (100%)
rename board/{AndesTech => andestech}/ae350/Kconfig (91%)
rename board/{AndesTech => andestech}/ae350/MAINTAINERS (95%)
rename board/{AndesTech => andestech}/ae350/Makefile (100%)
rename board/{AndesTech => andestech}/ae350/ae350.c (99%)
rename doc/board/{AndesTech => andestech}/adp-ag101p.rst (100%)
rename doc/board/{AndesTech => andestech}/ae350.rst (100%)
rename doc/board/{AndesTech => andestech}/index.rst (100%)
create mode 100644 doc/board/starfive/milk-v_mars_cm.rst
rename drivers/cache/{cache-v5l2.c => cache-andes-l2.c} (84%)
Best regards,
Leo
Re: [GIT PULL] u-boot-riscv/master
On Thu, May 02, 2024 at 12:38:11AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit ff0de1f0557ed7d2dab47ba976a37347a1fdc432: > > Merge patch series "Update PHYTEC SOM Detection" (2024-04-29 10:56:05 -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 19b762cf83f68b9d9a1f14e75d75781cedf4049f: > > board: starfive: Rename spl_soc_init() to spl_dram_init() (2024-05-02 > 00:01:18 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20596 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit ff0de1f0557ed7d2dab47ba976a37347a1fdc432: Merge patch series "Update PHYTEC SOM Detection" (2024-04-29 10:56:05 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 19b762cf83f68b9d9a1f14e75d75781cedf4049f: board: starfive: Rename spl_soc_init() to spl_dram_init() (2024-05-02 00:01:18 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20596 - RISC-V: cmd: Add SBI implementation ID and extension ID - Board: Rename spl_soc_init to spl_dram_init - Board: milkv_duo: Add SPI NOR flash, Ethernet, Sysreset support Heinrich Schuchardt (2): cmd: sbi: add Supervisor Software Events extension cmd: sbi: add coreboot and oreboot implementation IDs Kongyang Liu (10): mmc: cv1800b: Add transmit tap delay config to fix write error sysreset: cv1800b: Add sysreset driver for cv1800b SoC board: sophgo: milkv_duo: Bind sysreset driver configs: milkv_duo: Add sysreset configs board: milkv_duo: Add init code for Milk-V Duo ethernet riscv: dts: sophgo: Add ethernet node configs: milkv_duo: Add ethernet configs spi: cv1800b: Add spi nor flash controller driver for cv1800b SoC riscv: dts: sophgo: Add spi nor flash controller node configs: milkv_duo: Add spi nor configs Lukas Funke (2): board: sifive: Rename spl_soc_init() to spl_dram_init() board: starfive: Rename spl_soc_init() to spl_dram_init() Yu Chien Peter Lin (1): riscv: andesv5: Set default cache line size to 64-bytes arch/riscv/cpu/andesv5/Kconfig | 1 + arch/riscv/cpu/fu540/spl.c | 2 +- arch/riscv/cpu/fu740/spl.c | 2 +- arch/riscv/cpu/jh7110/spl.c | 2 +- arch/riscv/dts/cv1800b-milkv-duo.dts | 18 ++ arch/riscv/dts/cv18xx.dtsi | 40 arch/riscv/include/asm/arch-fu540/spl.h | 2 +- arch/riscv/include/asm/arch-fu740/spl.h | 2 +- arch/riscv/include/asm/arch-jh7110/spl.h | 2 +- arch/riscv/include/asm/sbi.h | 1 + board/sifive/unleashed/spl.c | 4 +- board/sifive/unmatched/spl.c | 4 +- board/sophgo/milkv_duo/Makefile | 3 +- board/sophgo/milkv_duo/board.c | 10 + board/sophgo/milkv_duo/ethernet.c| 79 board/sophgo/milkv_duo/ethernet.h| 11 ++ board/starfive/visionfive2/spl.c | 4 +- cmd/riscv/sbi.c | 3 + configs/milkv_duo_defconfig | 10 + drivers/mmc/cv1800b_sdhci.c | 4 +- drivers/net/designware.c | 1 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/cv1800b_spif.c | 321 +++ drivers/sysreset/Kconfig | 5 + drivers/sysreset/Makefile| 1 + drivers/sysreset/sysreset_cv1800b.c | 64 ++ 27 files changed, 591 insertions(+), 14 deletions(-) create mode 100644 board/sophgo/milkv_duo/ethernet.c create mode 100644 board/sophgo/milkv_duo/ethernet.h create mode 100644 drivers/spi/cv1800b_spif.c create mode 100644 drivers/sysreset/sysreset_cv1800b.c Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Tue, Apr 09, 2024 at 04:25:36PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 069d07396e30aa9be396c1dd3fc158ac199e6843: > > Merge tag 'efi-2024-07-rc1' of > https://source.denx.de/u-boot/custodians/u-boot-efi (2024-04-08 14:33:59 > -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to c1f78a4f632276bb4d77f8c79fe203709a9fa397: > > doc: describe Milk-V Mars board (2024-04-09 11:30:37 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20256 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 069d07396e30aa9be396c1dd3fc158ac199e6843: Merge tag 'efi-2024-07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi (2024-04-08 14:33:59 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to c1f78a4f632276bb4d77f8c79fe203709a9fa397: doc: describe Milk-V Mars board (2024-04-09 11:30:37 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20256 - RISC-V: Support backtrace and improve isa extension parsing - cpu: Add cv1800b SoC support - board: Add Milk-V Mars board support - board: Add Milk-V Duo SD card support Ben Dooks (1): riscv: add backtrace support Conor Dooley (2): riscv: don't read riscv, isa in the riscv cpu's get_desc() riscv: support extension probing using riscv, isa-extensions Heinrich Schuchardt (7): riscv: starfive: MMC card detect riscv: do not set default fdt for VisionFive 2 eeprom: starfive: function get_product_id_from_eeprom() riscv: set fdtfile on Milk-V Mars board: starfive: support Milk-V Mars board riscv: starfive: avoid including common.h doc: describe Milk-V Mars board Kongyang Liu (5): riscv: cpu: cv1800b: Add support for cv1800b SoC riscv: cache: Implement dcache for cv1800b mmc: cv1800b: Add sdhci driver support for cv1800b SoC riscv: dts: sophgo: Add clk node and sdhci node configs: milkv_duo: Add SD card configs Łukasz Stelmach (1): riscv: Move virtio scan to board_late_init() arch/riscv/Kconfig | 22 arch/riscv/Makefile| 4 + arch/riscv/cpu/cpu.c | 60 +++ arch/riscv/cpu/cv1800b/Kconfig | 12 +++ arch/riscv/cpu/cv1800b/Makefile| 7 ++ arch/riscv/cpu/cv1800b/cache.c | 45 arch/riscv/cpu/cv1800b/cpu.c | 9 ++ arch/riscv/cpu/cv1800b/dram.c | 21 arch/riscv/cpu/start.S | 1 + arch/riscv/dts/cv1800b-milkv-duo.dts | 8 ++ arch/riscv/dts/cv1800b.dtsi| 4 + arch/riscv/dts/cv18xx.dtsi | 22 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +- arch/riscv/include/asm/arch-jh7110/eeprom.h| 9 ++ arch/riscv/lib/interrupts.c| 35 +++ board/emulation/qemu-riscv/qemu-riscv.c| 12 +-- board/sophgo/milkv_duo/Kconfig | 4 +- board/starfive/visionfive2/spl.c | 100 +++--- board/starfive/visionfive2/starfive_visionfive2.c | 48 ++--- .../starfive/visionfive2/visionfive2-i2c-eeprom.c | 9 +- configs/milkv_duo_defconfig| 10 ++ configs/starfive_visionfive2_defconfig | 1 - doc/board/starfive/index.rst | 1 + doc/board/starfive/milk-v_mars.rst | 111 doc/board/starfive/visionfive2.rst | 18 drivers/cpu/riscv_cpu.c| 8 +- drivers/mmc/Kconfig| 13 +++ drivers/mmc/Makefile | 1 + drivers/mmc/cv1800b_sdhci.c| 116 + 29 files changed, 649 insertions(+), 64 deletions(-) create mode 100644 arch/riscv/cpu/cv1800b/Kconfig create mode 100644 arch/riscv/cpu/cv1800b/Makefile create mode 100644 arch/riscv/cpu/cv1800b/cache.c create mode 100644 arch/riscv/cpu/cv1800b/cpu.c create mode 100644 arch/riscv/cpu/cv1800b/dram.c create mode 100644 doc/board/starfive/milk-v_mars.rst create mode 100644 drivers/mmc/cv1800b_sdhci.c Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Tue, Mar 26, 2024 at 09:22:27PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit dde373bde392c38649c8c4420e0c98ef8d38d9dc: > > Prepare v2024.04-rc5 (2024-03-25 21:56:50 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 0cfe1bc6ed9b322d2b03ded3175ac5de3ed2b784: > > spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR (2024-03-26 17:31:24 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20075 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit dde373bde392c38649c8c4420e0c98ef8d38d9dc: Prepare v2024.04-rc5 (2024-03-25 21:56:50 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 0cfe1bc6ed9b322d2b03ded3175ac5de3ed2b784: spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR (2024-03-26 17:31:24 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20075 - Fix RISC-V falcon mode booting issue Randolph (1): spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR common/spl/spl_opensbi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Tue, Mar 12, 2024 at 04:51:50PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit f3c979dd0053c082d2df170446923e7ce5edbc2d: > > Prepare v2024.04-rc4 (2024-03-11 13:11:46 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 544af8207c69829b1697f3aa5dd682a299a6dea4: > > board: starfive: maintainer: Add visionfive2 PCIe driver (2024-03-12 > 14:36:13 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19910 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit f3c979dd0053c082d2df170446923e7ce5edbc2d: Prepare v2024.04-rc4 (2024-03-11 13:11:46 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 544af8207c69829b1697f3aa5dd682a299a6dea4: board: starfive: maintainer: Add visionfive2 PCIe driver (2024-03-12 14:36:13 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19910 * riscv: lib: improve extension detection * riscv: sbi: fix display format and global variable storage * sifive: fu740: reduce DDR speed * board: starfive vf2: switch to standard boot and fix DTS Bo Gan (1): riscv: dts: jh7110: Enable PLL node in SPL Conor Dooley (1): riscv: cpu: improve multi-letter extension detection in supports_extension() Heinrich Schuchardt (3): serial: move sbi_dbcn_available to .data section cmd: sbi: Correctly display unknown implementation IDs cmd: sbi: formatting PolarFire Hart Software Services version Leon M. Busch-George (1): riscv: dts: jh7110: fix indentation Minda Chen (2): board: starfive: Update maintainer of VisionFive v2 board board: starfive: maintainer: Add visionfive2 PCIe driver Nam Cao (1): starfive: visionfive2: switch to standard boot Thomas Perrot (1): riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s arch/riscv/cpu/cpu.c | 22 -- arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +- .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 2 +- arch/riscv/dts/jh7110-u-boot.dtsi | 4 board/starfive/visionfive2/MAINTAINERS | 3 ++- cmd/riscv/sbi.c| 3 ++- configs/starfive_visionfive2_defconfig | 2 +- drivers/serial/serial_sbi.c| 2 +- include/configs/starfive-visionfive2.h | 14 +- 9 files changed, 29 insertions(+), 25 deletions(-) Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Wed, Jan 31, 2024 at 06:21:34PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 28760ce8640ff6266bd1c1c568a4a231576f3919: > > Merge tag 'clk-2024.04-rc2' of > https://source.denx.de/u-boot/custodians/u-boot-clk (2024-01-30 07:54:28 > -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 6882255ac3107c58e1153311df8a8270087f8cb3: > > riscv: dts: starfive: add regulator device (2024-01-31 16:52:53 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19505 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 28760ce8640ff6266bd1c1c568a4a231576f3919: Merge tag 'clk-2024.04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-clk (2024-01-30 07:54:28 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 6882255ac3107c58e1153311df8a8270087f8cb3: riscv: dts: starfive: add regulator device (2024-01-31 16:52:53 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19505 * Add RISC-V falcon mode documentation * Add Clang build support * Add cmd to detect Debug Trigger Extension support * Add PWM setting for Unmatched board * Add Milk-V Duo board support * Add new device node and enable new config option for VisionFive2 board * Add second virtio device for RISC-V QEMU Aurelien Jarno (3): board: starfive: handle compatible property in dynamic DT configuration riscv: qemu: enable booting on a second virtio device configs: visionfive2: Disable ENV_IS_NOWHERE Heinrich Schuchardt (1): cmd: sbi: add support for Debug Trigger Extension Kongyang Liu (3): riscv: dts: sophgo: add basic device tree for Milk-V Duo board riscv: sophgo: milkv_duo: initial support added doc: sophgo: milkv_duo: document Milk-V Duo board Lukasz Tekieli (2): net: phy: motorcomm: configure pad drive strength register board: visionfive2: configure PHY pad drive strength Nam Cao (2): riscv: dts: jh7110: add power management unit controller node riscv: dts: starfive: add regulator device Randolph (3): doc: falcon: riscv: Falcon Mode boot on RISC-V spl: riscv: falcon: move fdt blob to specified address configs: andes: add the fdt blob copy address for SPL Vincent Chen (1): board: sifive: spl: Initialized the PWM setting in the SPL stage kleines Filmröllchen (1): riscv: Support building with Clang arch/riscv/Kconfig | 4 + arch/riscv/config.mk | 2 +- arch/riscv/dts/Makefile | 1 + arch/riscv/dts/cv1800b-milkv-duo.dts | 38 + arch/riscv/dts/cv1800b.dtsi | 18 +++ arch/riscv/dts/cv18xx.dtsi | 192 +++ arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 5 + arch/riscv/dts/jh7110.dtsi | 6 + arch/riscv/include/asm/arch-fu740/eeprom.h | 15 ++ arch/riscv/include/asm/sbi.h | 1 + board/AndesTech/ae350/ae350.c| 25 --- board/sifive/unmatched/spl.c | 52 ++ board/sophgo/milkv_duo/Kconfig | 28 board/sophgo/milkv_duo/MAINTAINERS | 6 + board/sophgo/milkv_duo/Makefile | 5 + board/sophgo/milkv_duo/board.c | 9 ++ board/starfive/visionfive2/spl.c | 12 ++ cmd/riscv/sbi.c | 1 + common/spl/Kconfig | 2 +- common/spl/spl_opensbi.c | 15 ++ configs/ae350_rv32_falcon_defconfig | 1 + configs/ae350_rv32_falcon_xip_defconfig | 1 + configs/ae350_rv64_falcon_defconfig | 1 + configs/ae350_rv64_falcon_xip_defconfig | 1 + configs/milkv_duo_defconfig | 23 +++ configs/starfive_visionfive2_defconfig | 1 - doc/board/index.rst | 1 + doc/board/sophgo/index.rst | 8 + doc/board/sophgo/milkv_duo.rst | 64 doc/develop/falcon.rst | 158 +++ drivers/net/phy/motorcomm.c | 130 +++ include/configs/milkv_duo.h | 12 ++ include/configs/qemu-riscv.h | 1 + 33 files changed, 811 insertions(+), 28 deletions(-) create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts create mode 100644 arch/riscv/dts/cv1800b.dtsi create mode 100644 arch/riscv/dts/cv18xx.dtsi create mode 100644 arch/riscv/include/asm/arch-fu740/eeprom.h create mode 100644 board/sophgo/milkv_duo/Kconfig create mode 100644 board/sophgo/milkv_duo/MAINTAINERS create mode 100644 board/sophgo/milkv_duo/Makefile create mode 100644 board/sophgo/milkv_duo/board.c create mode 100644 configs/milkv_duo_defconfig create mode 100644 doc/board/sophgo/index.rst create mode 100644 doc/board/sophgo/milkv_duo.rst create mode 100644 include/configs/milkv_duo.h Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Thu, Dec 14, 2023 at 08:46:14PM +0800, Leo Liang wrote: > Hi Tom, > > On Thu, Dec 14, 2023 at 07:19:02AM -0500, Tom Rini wrote: > > On Thu, Dec 14, 2023 at 10:38:07AM +0800, Leo Yu-Chi Liang(梁育齊) wrote: > > > > > Hi Tom, > > > > > > The following changes since commit > > > 20d0464300c25db673cfb5e4539aa3767606d151: > > > > > > Merge tag 'u-boot-imx-20231212' of > > > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2023-12-12 16:33:57 > > > -0500) > > > > > > are available in the Git repository at: > > > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > > > for you to fetch changes up to 8c785ddb7ae8d675faf558c81a29938cb0ec2b35: > > > > > > riscv: sifive: unmatched: migrate to text environment (2023-12-13 > > > 16:19:43 +0800) > > > > > > CI result shows no issue: > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18889 > > > > > > - VisionFive2: Enable CONFIG_SYSRESET > > > - StarFive: Modify starfive timer driver > > > - AMD/Xilinx: Add MicroBlaze V support > > > - Unmatched: Migrate to text environment > > > > > > > Are all of these really appropriate for a release less than a month away > > or should I take this to -next? Thanks. > > Ah! You're right! > I think merging to -next seems to be more appropriate! > Thanks for the reminder! > OK. It'll be easiest then if you wait until I've merged the next -rc in to next and rebase this PR on top of that. -- Tom signature.asc Description: PGP signature
Re: [GIT PULL] u-boot-riscv/master
Hi Tom, On Thu, Dec 14, 2023 at 07:19:02AM -0500, Tom Rini wrote: > On Thu, Dec 14, 2023 at 10:38:07AM +0800, Leo Yu-Chi Liang(梁育齊) wrote: > > > Hi Tom, > > > > The following changes since commit 20d0464300c25db673cfb5e4539aa3767606d151: > > > > Merge tag 'u-boot-imx-20231212' of > > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2023-12-12 16:33:57 > > -0500) > > > > are available in the Git repository at: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to 8c785ddb7ae8d675faf558c81a29938cb0ec2b35: > > > > riscv: sifive: unmatched: migrate to text environment (2023-12-13 > > 16:19:43 +0800) > > > > CI result shows no issue: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18889 > > > > - VisionFive2: Enable CONFIG_SYSRESET > > - StarFive: Modify starfive timer driver > > - AMD/Xilinx: Add MicroBlaze V support > > - Unmatched: Migrate to text environment > > > > Are all of these really appropriate for a release less than a month away > or should I take this to -next? Thanks. Ah! You're right! I think merging to -next seems to be more appropriate! Thanks for the reminder! Best regards, Leo > -- > Tom
Re: [GIT PULL] u-boot-riscv/master
On Thu, Dec 14, 2023 at 10:38:07AM +0800, Leo Yu-Chi Liang(梁育齊) wrote: > Hi Tom, > > The following changes since commit 20d0464300c25db673cfb5e4539aa3767606d151: > > Merge tag 'u-boot-imx-20231212' of > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2023-12-12 16:33:57 > -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 8c785ddb7ae8d675faf558c81a29938cb0ec2b35: > > riscv: sifive: unmatched: migrate to text environment (2023-12-13 16:19:43 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18889 > > - VisionFive2: Enable CONFIG_SYSRESET > - StarFive: Modify starfive timer driver > - AMD/Xilinx: Add MicroBlaze V support > - Unmatched: Migrate to text environment > Are all of these really appropriate for a release less than a month away or should I take this to -next? Thanks. -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 20d0464300c25db673cfb5e4539aa3767606d151: Merge tag 'u-boot-imx-20231212' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2023-12-12 16:33:57 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 8c785ddb7ae8d675faf558c81a29938cb0ec2b35: riscv: sifive: unmatched: migrate to text environment (2023-12-13 16:19:43 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18889 - VisionFive2: Enable CONFIG_SYSRESET - StarFive: Modify starfive timer driver - AMD/Xilinx: Add MicroBlaze V support - Unmatched: Migrate to text environment Jaehoon Chung (2): riscv: dts: jh7110: Add a gpio-restart node configs: visionfive2: Enable CONFIG_SYSRESET config Kuan Lim Lee (1): timer: starfive: Add Starfive timer support Michal Simek (1): riscv: Add support for AMD/Xilinx MicroBlaze V Yong-Xuan Wang (1): riscv: sifive: unmatched: migrate to text environment arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 2 + arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 5 ++ arch/riscv/dts/xilinx-mbv32.dts | 106 +++ board/sifive/unmatched/unmatched.env | 19 board/xilinx/Kconfig | 3 +- board/xilinx/common/board.c | 5 ++ board/xilinx/mbv/Kconfig | 28 ++ board/xilinx/mbv/MAINTAINERS | 7 ++ board/xilinx/mbv/Makefile| 5 ++ board/xilinx/mbv/board.c | 11 +++ configs/sifive_unmatched_defconfig | 2 +- configs/starfive_visionfive2_defconfig | 1 + configs/xilinx_mbv32_defconfig | 30 +++ configs/xilinx_mbv32_smode_defconfig | 32 +++ drivers/timer/starfive-timer.c | 16 ++-- include/configs/sifive-unmatched.h | 37 include/configs/xilinx_mbv.h | 6 ++ 18 files changed, 273 insertions(+), 46 deletions(-) create mode 100644 arch/riscv/dts/xilinx-mbv32.dts create mode 100644 board/sifive/unmatched/unmatched.env create mode 100644 board/xilinx/mbv/Kconfig create mode 100644 board/xilinx/mbv/MAINTAINERS create mode 100644 board/xilinx/mbv/Makefile create mode 100644 board/xilinx/mbv/board.c create mode 100644 configs/xilinx_mbv32_defconfig create mode 100644 configs/xilinx_mbv32_smode_defconfig create mode 100644 include/configs/xilinx_mbv.h Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Thu, Dec 07, 2023 at 09:46:23PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 2f0282922b2c458eea7f85c500a948a587437b63: > > Prepare v2024.01-rc4 (2023-12-04 13:46:56 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 94533cd9c15a60b74420e53a725fab54d38dd555: > > starfive: visionfive2: add device tree overlay support (2023-12-06 16:05:39 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18812 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 2f0282922b2c458eea7f85c500a948a587437b63: Prepare v2024.01-rc4 (2023-12-04 13:46:56 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 94533cd9c15a60b74420e53a725fab54d38dd555: starfive: visionfive2: add device tree overlay support (2023-12-06 16:05:39 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18812 - StarFive: Add StarFive watchdog driver - VisionFive2: Support device tree overlay for VisionFive2 board - Andes: Fix PLIC-SW setting - RISC-V: Fix NVMe support by implying NVME_PCI for QEMU - RISC-V: Fix binman for 64 bit format load address Chanho Park (4): clk: starfive: jh7110: Add watchdog clocks watchdog: Add StarFive Watchdog driver riscv: dts: jh7110: Add watchdog device tree node configs: visionfive2: Enable watchdog driver Heinrich Schuchardt (1): risc-v: qemu: imply NVME_PCI John Clark (1): starfive: visionfive2: add device tree overlay support Randolph (1): riscv: binman: fix the load field format Yu Chien Peter Lin (1): riscv: andes: Fix enable register settings of PLICSW arch/riscv/dts/binman.dtsi | 14 +- arch/riscv/dts/jh7110.dtsi | 10 + arch/riscv/lib/andes_plicsw.c | 33 ++-- board/emulation/qemu-riscv/Kconfig | 2 +- configs/starfive_visionfive2_defconfig | 5 + drivers/clk/starfive/clk-jh7110.c | 9 + drivers/watchdog/Kconfig | 7 + drivers/watchdog/Makefile | 1 + drivers/watchdog/starfive_wdt.c| 329 + include/configs/starfive-visionfive2.h | 1 + 10 files changed, 382 insertions(+), 29 deletions(-) create mode 100644 drivers/watchdog/starfive_wdt.c Best regards, Leo
Re: [GIT PULL] u-boot-riscv/master
On Thu, Nov 02, 2023 at 06:49:56PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit a803f87202aa48974bdff4d8100464a8288931e4: > > Merge https://source.denx.de/u-boot/custodians/u-boot-mmc (2023-11-01 > 09:44:33 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 9d22d4a7cef7f2fdaf5c060b71574e6f82ea5ff0: > > configs: visionfive2: Enable JH7110 RNG driver (2023-11-02 17:45:53 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18407 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/master
Hi Tom, The following changes since commit a803f87202aa48974bdff4d8100464a8288931e4: Merge https://source.denx.de/u-boot/custodians/u-boot-mmc (2023-11-01 09:44:33 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 9d22d4a7cef7f2fdaf5c060b71574e6f82ea5ff0: configs: visionfive2: Enable JH7110 RNG driver (2023-11-02 17:45:53 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18407 + CI: Use OpenSBI 1.3.1 release for testing + riscv: Support resume after exception + rng: Support RNG provided by RISC-V Zkr ISA extension + board: starfive VF2: Support jtag + board: starfive VF2: Support TRNG driver + board: sifive unmatched: Move kernel load address Chanho Park (7): riscv: cpu: jh7110: Add gpio helper macros board: starfive: spl: Support jtag for VisionFive2 board riscv: import read/write_relaxed functions clk: starfive: jh7110: Add security clocks rng: Add StarFive JH7110 RNG driver riscv: dts: jh7110: Add rng device tree node configs: visionfive2: Enable JH7110 RNG driver Heinrich Schuchardt (3): CI: use OpenSBI 1.3.1 for testing riscv: allow resume after exception rng: Provide a RNG based on the RISC-V Zkr ISA extension Samuel Holland (3): riscv: Sort target configs alphabetically riscv: Align the trap handler to 64 bytes riscv: Weakly define invalidate_icache_range() Yong-Xuan Wang (1): board: sifive: unmatched: move kernel load address to 0x8020 .azure-pipelines.yml | 8 +- .gitlab-ci.yml| 8 +- arch/riscv/Kconfig| 18 +- arch/riscv/cpu/mtrap.S| 2 +- arch/riscv/dts/jh7110.dtsi| 10 ++ arch/riscv/include/asm/arch-jh7110/gpio.h | 85 + arch/riscv/include/asm/io.h | 45 + arch/riscv/lib/cache.c| 2 +- arch/riscv/lib/interrupts.c | 13 ++ board/starfive/visionfive2/spl.c | 23 +++ configs/starfive_visionfive2_defconfig| 2 + doc/api/index.rst | 1 + doc/api/interrupt.rst | 6 + drivers/clk/starfive/clk-jh7110.c | 10 ++ drivers/rng/Kconfig | 14 ++ drivers/rng/Makefile | 2 + drivers/rng/jh7110_rng.c | 274 ++ drivers/rng/riscv_zkr_rng.c | 116 + include/configs/sifive-unmatched.h| 2 +- include/interrupt.h | 45 + 20 files changed, 666 insertions(+), 20 deletions(-) create mode 100644 arch/riscv/include/asm/arch-jh7110/gpio.h create mode 100644 doc/api/interrupt.rst create mode 100644 drivers/rng/jh7110_rng.c create mode 100644 drivers/rng/riscv_zkr_rng.c create mode 100644 include/interrupt.h Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Thu, Oct 19, 2023 at 07:41:24PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 9a0cf3993f71043ba08c315572c54622de42d447: > > Merge branch '2023-10-17-spl-test-some-load-methods' (2023-10-18 08:28:00 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to bc5a50452bd42029d6587e1596b44ff235655e90: > > riscv: Add Zbb support for building U-Boot (2023-10-19 17:29:50 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18215 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 9a0cf3993f71043ba08c315572c54622de42d447: Merge branch '2023-10-17-spl-test-some-load-methods' (2023-10-18 08:28:00 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to bc5a50452bd42029d6587e1596b44ff235655e90: riscv: Add Zbb support for building U-Boot (2023-10-19 17:29:50 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18215 + riscv: Add Zbb support + riscv: Add preliminary RISC-V falcon mode support + riscv: Remove dram_init_banksize() + andes: rearrange PLICSW scheme + visionfive2: enable bootstage configs Chanho Park (1): configs: visionfive2: enable bootstage configs Heinrich Schuchardt (1): riscv: remove dram_init_banksize() Mayuresh Chitale (1): riscv: binman: Fix compilation error Randolph (8): riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy spl: riscv: opensbi: change the default os_type as varible riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol riscv: dts: binman: add condition for opensbi os boot Makefile: delete file *.itb when make clean spl: riscv: add os type for next booting stage andes: config: add riscv falcon mode for ae350 platform riscv: spl: andes: Move the DTB in front of kernel Yu Chien Peter Lin (1): riscv: Add Zbb support for building U-Boot Makefile| 2 +- arch/riscv/Kconfig | 99 +++ arch/riscv/Makefile | 5 +- arch/riscv/cpu/generic/dram.c | 16 - arch/riscv/dts/binman.dtsi | 38 ++-- arch/riscv/include/asm/string.h | 18 ++ arch/riscv/lib/Makefile | 3 + arch/riscv/lib/andes_plicsw.c | 24 arch/riscv/lib/strcmp_zbb.S | 81 + arch/riscv/lib/strlen_zbb.S | 101 arch/riscv/lib/strncmp_zbb.S| 94 + board/AndesTech/ae350/ae350.c | 25 common/spl/spl_fit.c| 3 +- common/spl/spl_opensbi.c| 31 ++ configs/ae350_rv32_falcon_defconfig | 60 +++ configs/ae350_rv32_falcon_xip_defconfig | 61 +++ configs/ae350_rv64_falcon_defconfig | 60 +++ configs/ae350_rv64_falcon_xip_defconfig | 61 +++ configs/starfive_visionfive2_defconfig | 2 + 19 files changed, 738 insertions(+), 46 deletions(-) create mode 100644 arch/riscv/lib/strcmp_zbb.S create mode 100644 arch/riscv/lib/strlen_zbb.S create mode 100644 arch/riscv/lib/strncmp_zbb.S create mode 100644 configs/ae350_rv32_falcon_defconfig create mode 100644 configs/ae350_rv32_falcon_xip_defconfig create mode 100644 configs/ae350_rv64_falcon_defconfig create mode 100644 configs/ae350_rv64_falcon_xip_defconfig Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Thu, Oct 05, 2023 at 04:10:55PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 65b9b3462bec2966911658836983819ab4e4823e: > > Merge branch 'next_pinctrl_sync' of > https://source.denx.de/u-boot/custodians/u-boot-sh (2023-10-02 15:19:02 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 7cfdacbe8020292845bd5eba63b576b8586c433c: > > configs: sifive: enable poweroff command on Unmatched (2023-10-04 18:23:59 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18005 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 65b9b3462bec2966911658836983819ab4e4823e: Merge branch 'next_pinctrl_sync' of https://source.denx.de/u-boot/custodians/u-boot-sh (2023-10-02 15:19:02 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 7cfdacbe8020292845bd5eba63b576b8586c433c: configs: sifive: enable poweroff command on Unmatched (2023-10-04 18:23:59 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18005 + ae350: modify memory layout and target name + ae350: use generic RISC-V timer driver in S-mode + Support bootstage report for RISC-V + Support C extension exception command for RISC-V + Add Starfive timer support Chanho Park (3): riscv: bootstage: correct bootstage_report guard riscv: timer: add timer_get_boot_us for BOOTSTAGE timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE Heinrich Schuchardt (4): cmd/exception: support RISC-V compressed instruction cmd/exception: test RISC-V 16 bit aligned instruction riscv: enable CONFIG_DEBUG_UART by default configs: sifive: enable poweroff command on Unmatched Kuan Lim Lee (1): timer: starfive: Add Starfive timer support Randolph (2): configs: andes: add vender prefix for target name configs: andes: rearrange SPL mode memory layout Yu Chien Peter Lin (1): riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode arch/riscv/Kconfig | 5 +- arch/riscv/cpu/andesv5/Kconfig | 3 +- arch/riscv/dts/Makefile | 2 +- arch/riscv/lib/bootm.c | 2 +- board/AndesTech/ae350/Kconfig| 2 +- cmd/riscv/exception.c| 34 +++-- configs/ae350_rv32_defconfig | 3 +- configs/ae350_rv32_spl_defconfig | 10 ++-- configs/ae350_rv32_spl_xip_defconfig | 7 +-- configs/ae350_rv32_xip_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_spl_defconfig | 11 +++-- configs/ae350_rv64_spl_xip_defconfig | 8 +-- configs/ae350_rv64_xip_defconfig | 2 +- configs/sifive_unmatched_defconfig | 1 + drivers/timer/Kconfig| 16 +- drivers/timer/Makefile | 3 +- drivers/timer/riscv_aclint_timer.c | 23 + drivers/timer/riscv_timer.c | 22 + drivers/timer/starfive-timer.c | 94 20 files changed, 223 insertions(+), 29 deletions(-) create mode 100644 drivers/timer/starfive-timer.c Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Tue, Sep 26, 2023 at 01:21:50PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 15155ab0a3d1f839509bcac620bfb38f950bead6: > > Merge tag 'u-boot-imx-20230923' of > https://source.denx.de/u-boot/custodians/u-boot-imx (2023-09-24 17:15:31 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 16dbe3d9d45527f67d479535a22dc4054ae93e99: > > riscv: set fdtfile on VisionFive 2 (2023-09-26 10:43:02 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17879 > > However, this patch has landed in the "next" branch. > Could we cherry-pick this commit to have this patch on master branch ? > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 15155ab0a3d1f839509bcac620bfb38f950bead6: Merge tag 'u-boot-imx-20230923' of https://source.denx.de/u-boot/custodians/u-boot-imx (2023-09-24 17:15:31 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 16dbe3d9d45527f67d479535a22dc4054ae93e99: riscv: set fdtfile on VisionFive 2 (2023-09-26 10:43:02 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17879 However, this patch has landed in the "next" branch. Could we cherry-pick this commit to have this patch on master branch ? + Fix VisionFive2 booting issue by providing the correct FDT. Heinrich Schuchardt (1): riscv: set fdtfile on VisionFive 2 arch/riscv/Kconfig| 1 + board/starfive/visionfive2/starfive_visionfive2.c | 43 +-- 2 files changed, 42 insertions(+), 2 deletions(-) Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Thu, Sep 21, 2023 at 09:36:01AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit b9b83a86f0e84e837191db120c279a9cc0e3434b: > > Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh > (2023-09-17 09:25:42 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 43177705ab29ed1ccca970096de1ef3c6095e7e6: > > board: visionfive2: Fixup memory size passed to kernel (2023-09-20 20:30:30 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/1 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit b9b83a86f0e84e837191db120c279a9cc0e3434b: Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh (2023-09-17 09:25:42 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 43177705ab29ed1ccca970096de1ef3c6095e7e6: board: visionfive2: Fixup memory size passed to kernel (2023-09-20 20:30:30 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/1 + Fixup memory size passed to kernel Shengyu Qu (2): configs: visionfive2: Enable CONFIG_OF_BOARD_SETUP board: visionfive2: Fixup memory size passed to kernel board/starfive/visionfive2/starfive_visionfive2.c | 7 +++ configs/starfive_visionfive2_defconfig| 1 + 2 files changed, 8 insertions(+) Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Tue, Sep 05, 2023 at 11:30:34AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 493fd3363f6da6a784514657d689c7cda0f390d5: > > nokia_rx51: Remove platform (2023-09-04 21:14:32 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to dfe08374943c0e898fcfaf7327f69e0fb56b7d23: > > risc-v: implement DBCN based debug console (2023-09-05 10:53:55 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17650 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 493fd3363f6da6a784514657d689c7cda0f390d5: nokia_rx51: Remove platform (2023-09-04 21:14:32 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to dfe08374943c0e898fcfaf7327f69e0fb56b7d23: risc-v: implement DBCN based debug console (2023-09-05 10:53:55 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17650 + Implement OpenSBI DBCN extension for early debug console + Fixes for VisionFive2 board + Fix timer missing + Fix L2 LIM issue + Enable PCIE auto enumeration to support USB and NVMe by default + Set eth0 mac address properly + Add __noreturn attribute to spl_invoke_opensbi Chanho Park (1): spl: add __noreturn attribute to spl_invoke_opensbi function Heinrich Schuchardt (2): risc-v: implement DBCN write byte risc-v: implement DBCN based debug console Seung-Woo Kim (1): eeprom: starfive: set eth0 mac address properly Shengyu Qu (6): configs: starfive: Enable PCIE auto enum and NVME/USB stuff for Starfive Visionfive 2 doc: board: starfive: Add more info about supported driver Kconfig: Add SPL_SYS_MALLOC_CLEAR_ON_INIT dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT configs: starfive: Disable SYS_MALLOC_CLEAR_ON_INIT by default Torsten Duwe (2): riscv: allow riscv timer to be instantiated via device tree riscv: jh7110: enable riscv,timer in the device tree Kconfig| 11 + arch/riscv/cpu/jh7110/Kconfig | 1 + arch/riscv/dts/jh7110.dtsi | 9 +++ arch/riscv/include/asm/sbi.h | 1 + arch/riscv/lib/sbi.c | 16 + .../starfive/visionfive2/visionfive2-i2c-eeprom.c | 2 +- common/dlmalloc.c | 6 ++--- common/spl/spl_opensbi.c | 7 +++--- configs/starfive_visionfive2_defconfig | 10 +++- doc/board/starfive/visionfive2.rst | 2 ++ drivers/serial/Kconfig | 5 +++- drivers/serial/serial_sbi.c| 20 drivers/timer/riscv_timer.c| 28 -- include/spl.h | 2 +- 14 files changed, 108 insertions(+), 12 deletions(-) Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Thu, Aug 10, 2023 at 06:32:30PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit ec58228830a1f68e8e65099387cf12c5a91c9e72: > > Merge tag 'x86-pull-20230809' of > https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-09 13:17:34 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 47ed15125cccd98e041cdff3b6bbe675a2418ec2: > > riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE (2023-08-10 10:58:55 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17276 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit ec58228830a1f68e8e65099387cf12c5a91c9e72: Merge tag 'x86-pull-20230809' of https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-09 13:17:34 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 47ed15125cccd98e041cdff3b6bbe675a2418ec2: riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE (2023-08-10 10:58:55 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17276 + Add USB host support on VisionFive2 board + Enable SPI flash support on VisionFive2 board + Enable Random Number Generator in RISC-V QEMU board + Display new SBI extension + Add SPL_ZERO_MEM_BEFORE_USE Kconfig for jh7110 L2 LIM (Loosely-Integrated Memory) Heinrich Schuchardt (2): riscv: qemu: imply CONFIG_DM_RNG cmd/sbi: display new extensions Minda Chen (4): pci: plda: Get correct ECAM offset in multiple PCIe RC case riscv: dts: starfive: Enable pcie0 dts node riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE configs: riscv: starfive: Add VF2 PCIe USB3 XHCI support Shengyu Qu (4): configs: starfive: Enable environment in SPI flash support riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE arch/riscv/Kconfig | 8 arch/riscv/cpu/jh7110/Kconfig| 2 ++ arch/riscv/cpu/jh7110/spl.c | 25 - arch/riscv/cpu/start.S | 12 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +- arch/riscv/include/asm/sbi.h | 2 ++ board/emulation/qemu-riscv/Kconfig | 1 + cmd/riscv/sbi.c | 4 common/init/board_init.c | 3 +++ configs/starfive_visionfive2_defconfig | 14 ++ drivers/pci/pcie_plda_common.c | 5 +++-- 11 files changed, 50 insertions(+), 28 deletions(-) Best regards, Leo
Re: [PULL] u-boot-riscv/master
On 2023/8/2 17:31, Leo Liang wrote: > Hi Bin, > > On Wed, Aug 02, 2023 at 02:27:29PM +0800, Bin Meng wrote: >> Hi Leo, >> >> On Wed, Aug 2, 2023 at 1:49 PM Leo Liang wrote: >> > >> > Hi Tom, >> > >> > The following changes since commit >> > 7755b2200777f72dca87dd169138e95f011bbcb9: >> > >> > Merge tag 'x86-pull-20230801' of >> > https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-01 11:57:55 >> > -0400) >> > >> > are available in the Git repository at: >> > >> > https://source.denx.de/u-boot/custodians/u-boot-riscv.git >> > >> > for you to fetch changes up to 093bd0354e5b947b0bd634bf5ed4041ba075b57d: >> > >> > acpi: Add missing RISC-V acpi_table header (2023-08-02 11:02:33 +0800) >> > >> > CI result shows no issue: >> > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17177 >> > >> > >> > >> > + Fix compilation error for CI when enabling RTL8169 driver >> > + Fix compilation error for pci_mmc.c by adding acpi_table header file >> > + Support StarFive JH7110 PCIe driver >> > + Enable PCI on Unmatched board >> > >> > >> > >> > Heinrich Schuchardt (2): >> > riscv: sifive: initialize PCI on Unmatched >> > acpi: Add missing RISC-V acpi_table header >> > >> > Mason Huo (3): >> > starfive: pci: Add StarFive JH7110 pcie driver >> > configs: starfive-jh7110: Add support for PCIe host driver >> > riscv: dts: starfive: Enable PCIe host controller >> > >> > Minda Chen (5): >> > i2c: designware: Add Kconfig for designware_i2c_pci.c >> > net: rtl8169: Fix compile warning in rtl8169 >> > net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V >> > net: rtl8169: Add one device ID 0x8161 >> > configs: starfive-jh7110: Add CONFIG_RTL8169 >> > >> >> Looks the second half of this series is missed? >> https://patchwork.ozlabs.org/project/uboot/list/?series=365237 >> >> Regards, >> Bin > > Thanks for the reminder! > I did omit this second half of the series by accident! > I will re-send the PR again ASAP! > > Best regards, > Leo Hi Leo and Bin Thanks!
Re: [PULL] u-boot-riscv/master
Hi Bin, On Wed, Aug 02, 2023 at 02:27:29PM +0800, Bin Meng wrote: > Hi Leo, > > On Wed, Aug 2, 2023 at 1:49 PM Leo Liang wrote: > > > > Hi Tom, > > > > The following changes since commit 7755b2200777f72dca87dd169138e95f011bbcb9: > > > > Merge tag 'x86-pull-20230801' of > > https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-01 11:57:55 > > -0400) > > > > are available in the Git repository at: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to 093bd0354e5b947b0bd634bf5ed4041ba075b57d: > > > > acpi: Add missing RISC-V acpi_table header (2023-08-02 11:02:33 +0800) > > > > CI result shows no issue: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17177 > > > > > > > > + Fix compilation error for CI when enabling RTL8169 driver > > + Fix compilation error for pci_mmc.c by adding acpi_table header file > > + Support StarFive JH7110 PCIe driver > > + Enable PCI on Unmatched board > > > > > > > > Heinrich Schuchardt (2): > > riscv: sifive: initialize PCI on Unmatched > > acpi: Add missing RISC-V acpi_table header > > > > Mason Huo (3): > > starfive: pci: Add StarFive JH7110 pcie driver > > configs: starfive-jh7110: Add support for PCIe host driver > > riscv: dts: starfive: Enable PCIe host controller > > > > Minda Chen (5): > > i2c: designware: Add Kconfig for designware_i2c_pci.c > > net: rtl8169: Fix compile warning in rtl8169 > > net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V > > net: rtl8169: Add one device ID 0x8161 > > configs: starfive-jh7110: Add CONFIG_RTL8169 > > > > Looks the second half of this series is missed? > https://patchwork.ozlabs.org/project/uboot/list/?series=365237 > > Regards, > Bin Thanks for the reminder! I did omit this second half of the series by accident! I will re-send the PR again ASAP! Best regards, Leo
Re: [PULL] u-boot-riscv/master
Hi Leo, On Wed, Aug 2, 2023 at 1:49 PM Leo Liang wrote: > > Hi Tom, > > The following changes since commit 7755b2200777f72dca87dd169138e95f011bbcb9: > > Merge tag 'x86-pull-20230801' of > https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-01 11:57:55 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 093bd0354e5b947b0bd634bf5ed4041ba075b57d: > > acpi: Add missing RISC-V acpi_table header (2023-08-02 11:02:33 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17177 > > > > + Fix compilation error for CI when enabling RTL8169 driver > + Fix compilation error for pci_mmc.c by adding acpi_table header file > + Support StarFive JH7110 PCIe driver > + Enable PCI on Unmatched board > > > > Heinrich Schuchardt (2): > riscv: sifive: initialize PCI on Unmatched > acpi: Add missing RISC-V acpi_table header > > Mason Huo (3): > starfive: pci: Add StarFive JH7110 pcie driver > configs: starfive-jh7110: Add support for PCIe host driver > riscv: dts: starfive: Enable PCIe host controller > > Minda Chen (5): > i2c: designware: Add Kconfig for designware_i2c_pci.c > net: rtl8169: Fix compile warning in rtl8169 > net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V > net: rtl8169: Add one device ID 0x8161 > configs: starfive-jh7110: Add CONFIG_RTL8169 > Looks the second half of this series is missed? https://patchwork.ozlabs.org/project/uboot/list/?series=365237 Regards, Bin
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 7755b2200777f72dca87dd169138e95f011bbcb9: Merge tag 'x86-pull-20230801' of https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-01 11:57:55 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 093bd0354e5b947b0bd634bf5ed4041ba075b57d: acpi: Add missing RISC-V acpi_table header (2023-08-02 11:02:33 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17177 + Fix compilation error for CI when enabling RTL8169 driver + Fix compilation error for pci_mmc.c by adding acpi_table header file + Support StarFive JH7110 PCIe driver + Enable PCI on Unmatched board Heinrich Schuchardt (2): riscv: sifive: initialize PCI on Unmatched acpi: Add missing RISC-V acpi_table header Mason Huo (3): starfive: pci: Add StarFive JH7110 pcie driver configs: starfive-jh7110: Add support for PCIe host driver riscv: dts: starfive: Enable PCIe host controller Minda Chen (5): i2c: designware: Add Kconfig for designware_i2c_pci.c net: rtl8169: Fix compile warning in rtl8169 net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V net: rtl8169: Add one device ID 0x8161 configs: starfive-jh7110: Add CONFIG_RTL8169 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 11 +++ arch/riscv/dts/jh7110.dtsi | 74 + arch/riscv/include/asm/acpi_table.h | 11 +++ configs/sifive_unmatched_defconfig | 1 + configs/starfive_visionfive2_defconfig | 8 + drivers/i2c/Kconfig | 9 + drivers/i2c/Makefile | 4 +-- drivers/net/rtl8169.c| 22 - drivers/pci/Kconfig | 13 drivers/pci/Makefile | 2 ++ drivers/pci/pcie_plda_common.c | 116 drivers/pci/pcie_plda_common.h | 118 + drivers/pci/pcie_starfive_jh7110.c | 317 +++ 13 files changed, 694 insertions(+), 12 deletions(-) create mode 100644 arch/riscv/include/asm/acpi_table.h create mode 100644 drivers/pci/pcie_plda_common.c create mode 100644 drivers/pci/pcie_plda_common.h create mode 100644 drivers/pci/pcie_starfive_jh7110.c Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Mon, Jul 24, 2023 at 08:01:22AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 247aa5a191159ea7e03bf1918e22fbbb784cd410: > > Merge branch '2023-07-21-assorted-TI-platform-updates' (2023-07-21 19:33:05 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 6aabe229f8440c4960b904baf3aa33f692eea9a1: > > riscv: define a cache line size for the generic CPU (2023-07-24 13:22:24 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17015 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 247aa5a191159ea7e03bf1918e22fbbb784cd410: Merge branch '2023-07-21-assorted-TI-platform-updates' (2023-07-21 19:33:05 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 6aabe229f8440c4960b904baf3aa33f692eea9a1: riscv: define a cache line size for the generic CPU (2023-07-24 13:22:24 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17015 - Set up per-hart stack before any function call - Sync visionfive2 board DTS with Linux - Define cache line size for USB 3.0 driver for RISC-V CPU Bo Gan (1): riscv: setup per-hart stack earlier Chanho Park (2): configs: visionfive2: add a trailing space to prompt doc: visionfive2: apply a trailing space to the prompt Heinrich Schuchardt (1): riscv: define a cache line size for the generic CPU Xingyu Wu (5): clk: starfive: jh7110: Separate the PLL driver riscv: dts: jh7110: Add PLL clock controller node riscv: dts: jh7110: Add clock source from PLL dt-bindings: clock: jh7110: Modify clock id to be same with Linux clk: starfive: jh7110: Add of_xlate ops and macros for clock id conversion arch/riscv/cpu/generic/Kconfig | 1 + arch/riscv/cpu/start.S | 37 ++ arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 6 ++-- arch/riscv/dts/jh7110-u-boot.dtsi| 1 - arch/riscv/dts/jh7110.dtsi | 16 -- configs/starfive_visionfive2_defconfig | 2 +- doc/board/starfive/visionfive2.rst | 18 +-- drivers/clk/starfive/clk-jh7110-pll.c| 103 +-- drivers/clk/starfive/clk-jh7110.c| 306 +-- drivers/clk/starfive/clk.h | 58 - include/dt-bindings/clock/starfive,jh7110-crg.h | 101 +- 11 files changed, 400 insertions(+), 249 deletions(-) Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Wed, Jul 12, 2023 at 06:58:21AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 8e21064cb3452950b09301baec06d86e37342471: > > Merge tag 'efi-2023-07-rc7' of > https://source.denx.de/u-boot/custodians/u-boot-efi (2023-07-11 13:27:32 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git master > > for you to fetch changes up to 478fedfda42ea2a444991de1696fa0adc8bb16d4: > > doc: t-head: lpi4a: document Lichee PI 4A board (2023-07-12 13:21:41 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/16856 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom,
The following changes since commit 8e21064cb3452950b09301baec06d86e37342471:
Merge tag 'efi-2023-07-rc7' of
https://source.denx.de/u-boot/custodians/u-boot-efi (2023-07-11 13:27:32 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git master
for you to fetch changes up to 478fedfda42ea2a444991de1696fa0adc8bb16d4:
doc: t-head: lpi4a: document Lichee PI 4A board (2023-07-12 13:21:41 +0800)
CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/16856
- Add ethernet driver for StarFive JH7110 SoC
- Add ACLINT mtimer and mswi devices support
- Add Lichee PI 4A board
Bin Meng (3):
riscv: timer: Update the sifive clint timer driver to support aclint
riscv: clint: Update the sifive clint ipi driver to support aclint
riscv: Rename SiFive CLINT to RISC-V ALINT
Yanhong Wang (11):
net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
net: dwc_eth_qos: Add StarFive ethernet driver glue layer
riscv: dts: jh7110: Add ethernet device tree nodes
riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B
doc: board: starfive: Reword the make defconfig information
configs: starfive: Enable ethernet configuration for StarFive VisionFive2
eeprom: starfive: Enable ID EEPROM configuration
riscv: dts: starfive: Add support eeprom device tree node
configs: starfive: Enable ID EEPROM configuration
ram: starfive: Read memory size information from EEPROM
board: starfive: Dynamic configuration of DT for 1.2A and 1.3B
Yixun Lan (4):
riscv: t-head: licheepi4a: initial support added
riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board
configs: th1520_lpi4a_defconfig: Add initial config
doc: t-head: lpi4a: document Lichee PI 4A board
MAINTAINERS
| 2 +-
arch/riscv/Kconfig
| 17 +++--
arch/riscv/cpu/fu540/Kconfig
| 2 +-
arch/riscv/cpu/fu740/Kconfig
| 2 +-
arch/riscv/cpu/generic/Kconfig
| 4 +-
arch/riscv/cpu/jh7110/Kconfig
| 2 +-
arch/riscv/cpu/jh7110/spl.c
| 32 -
arch/riscv/dts/Makefile
| 4 +-
arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi =>
jh7110-starfive-visionfive-2-u-boot.dtsi} | 39 ++-
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
| 12
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
| 69 ---
arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts =>
jh7110-starfive-visionfive-2.dts} | 3 +-
arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
| 40 +++
arch/riscv/dts/jh7110.dtsi
| 69 +++
arch/riscv/dts/th1520-lichee-module-4a.dtsi
| 34 +
arch/riscv/dts/th1520-lichee-pi-4a.dts
| 32 +
arch/riscv/dts/th1520.dtsi
| 406
arch/riscv/include/asm/arch-jh7110/eeprom.h
| 13
arch/riscv/include/asm/global_data.h
| 4 +-
arch/riscv/include/asm/syscon.h
| 2 +-
arch/riscv/lib/Makefile
| 2 +-
arch/riscv/lib/{sifive_clint.c => aclint_ipi.c}
| 31 +++--
board/openpiton/riscv64/Kconfig
| 2 +-
board/sipeed/maix/Kconfig
Re: [PULL] u-boot-riscv/master
On Fri, Apr 21, 2023 at 12:41:14AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 5db4972a5bbdbf9e3af48ffc9bc4fec73b7b6a79: > > Merge tag 'u-boot-nand-20230417' of > https://source.denx.de/u-boot/custodians/u-boot-nand-flash (2023-04-17 > 10:47:33 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 04d16be55404ee07134b4171dea37eff9ad8fa5a: > > riscv: Support CONFIG_REMAKE_ELF (2023-04-20 20:45:08 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/16065 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 5db4972a5bbdbf9e3af48ffc9bc4fec73b7b6a79: Merge tag 'u-boot-nand-20230417' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash (2023-04-17 10:47:33 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 04d16be55404ee07134b4171dea37eff9ad8fa5a: riscv: Support CONFIG_REMAKE_ELF (2023-04-20 20:45:08 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/16065 * Add StarFive VisionFive v2 Board support * Support CONFIG_REMAKE_ELF * Code cleanups for RISC-V architecture Bin Meng (11): riscv: Correct a comment in io.h riscv: Enforce DWARF4 output riscv: Optimize source end address calculation in start.S riscv: Optimize loading relocation type tools: prelink-riscv: Cosmetic style fixes tools: prelink-riscv: Unmap the ELF image when done makefile: riscv: Drop useless argument of prelink-riscv riscv: Change to use positive offset to access relocation entries riscv: Avoid updating the link register riscv: spl: Remove relocation sections riscv: Update alignment for some sections in linker scripts Jianlong Huang (1): dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Kuan Lim Lee (1): pinctrl: starfive: Add StarFive JH7110 driver Samuel Holland (1): riscv: Support CONFIG_REMAKE_ELF Yanhong Wang (15): riscv: cpu: jh7110: Add support for jh7110 SoC cache: starfive: Add StarFive JH7110 support dt-bindings: reset: Add StarFive JH7110 reset definitions reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC dt-bindings: clock: Add StarFive JH7110 clock definitions clk: starfive: Add StarFive JH7110 clock driver ram: starfive: add ddr driver board: starfive: add StarFive VisionFive v2 board support riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC board: starfive: Add Kconfig for StarFive VisionFive v2 Board board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig riscv: dts: jh7110: Add initial StarFive JH7110 device tree riscv: dts: jh7110: Add initial u-boot device tree riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree configs: starfive: add starfive_visionfive2_defconfig Makefile |2 +- arch/riscv/Kconfig|5 + arch/riscv/config.mk |5 +- arch/riscv/cpu/jh7110/Kconfig | 28 ++ arch/riscv/cpu/jh7110/Makefile| 10 + arch/riscv/cpu/jh7110/cpu.c | 23 ++ arch/riscv/cpu/jh7110/dram.c | 38 +++ arch/riscv/cpu/jh7110/spl.c | 64 arch/riscv/cpu/start.S| 28 +- arch/riscv/cpu/u-boot-spl.lds | 27 +- arch/riscv/cpu/u-boot.lds |6 +- arch/riscv/dts/Makefile |3 +- arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi | 69 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts | 12 + arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts | 12 + arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 319 +++ arch/riscv/dts/jh7110-u-boot.dtsi | 99 ++ arch/riscv/dts/jh7110.dtsi| 573 + arch/riscv/include/asm/arch-jh7110/regs.h | 19 ++ arch/riscv/include/asm/arch-jh7110/spl.h | 12 + arch/riscv/include/asm/io.h |2 +- board/starfive/visionfive2/Kconfig| 53 board/starfive/visionfive2/MAINTAINERS|7 + board/starfive/visionfive2/Makefile |7 + board/starfive/visionfive2/spl.c | 87 + board/starfive/visionfive2/starfive_visionfive2.c | 40 +++ configs/starfive_visionfive2_defconfig| 79 + doc/board/index.rst |1 + doc/board/starfive/index.rst |9 + doc/board/starfive/visionfive2.rst| 492 + drivers/cache/cache-sifive-ccache.c |1 + drivers/clk/Kconfig
Re: [PULL] u-boot-riscv/master
On Fri, Feb 17, 2023 at 10:01:54AM -0500, Tom Rini wrote: > On Fri, Feb 17, 2023 at 12:12:18PM +, Leo Liang wrote: > > > Hi Tom, > > > > The following changes since commit faac9dee8e0629326dc122f4624fc4897e3f38b0: > > > > Prepare v2023.04-rc2 (2023-02-13 18:39:15 -0500) > > > > are available in the Git repository at: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to 7574b6476afc1fd76816be6567458f6ca4f44234: > > > > riscv: binman: Add help message for missing blobs (2023-02-17 19:07:48 > > +0800) > > > > CI result shows no issue: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15225 > > > > I've taken this to u-boot/master, but for the rest of the cycle please > make sure any changes for master are clearly bug fixes, and otherwise > apply to next instead. Thanks! Hi Tom, Understood! Thanks for merging this! Best regards, Leo > > -- > Tom
Re: [PULL] u-boot-riscv/master
On Fri, Feb 17, 2023 at 12:12:18PM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit faac9dee8e0629326dc122f4624fc4897e3f38b0: > > Prepare v2023.04-rc2 (2023-02-13 18:39:15 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 7574b6476afc1fd76816be6567458f6ca4f44234: > > riscv: binman: Add help message for missing blobs (2023-02-17 19:07:48 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15225 > I've taken this to u-boot/master, but for the rest of the cycle please make sure any changes for master are clearly bug fixes, and otherwise apply to next instead. Thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom,
The following changes since commit faac9dee8e0629326dc122f4624fc4897e3f38b0:
Prepare v2023.04-rc2 (2023-02-13 18:39:15 -0500)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 7574b6476afc1fd76816be6567458f6ca4f44234:
riscv: binman: Add help message for missing blobs (2023-02-17 19:07:48 +0800)
CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15225
- binman: Add help message if opensbi is absent when building u-boot SPL
- AndesTech: rename cpu and board name to 'andesv5' and 'ae350'
- Clean up cache operation for Andes ae350 platform
Leo Yu-Chi Liang (3):
riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"
riscv: Rename Andes cpu and board names
riscv: ae350: Adjust the memory layout of ae350
Rick Chen (1):
riscv: binman: Add help message for missing blobs
Yu Chien Peter Lin (10):
riscv: global_data.h: Correct the comment for PLICSW
board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init()
driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2
platform
riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()
riscv: ae350: dts: Update L2 cache compatible string
riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL
configs: ae350: Enable v5l2 cache for AE350 platforms in SPL
configs: ae350: Increase maximum retry count for AE350 platforms
configs: ae350: Display CPU and board info for AE350 platforms
driver: cache-v5l2: Fix type casting warning on RV32
arch/riscv/Kconfig | 8
arch/riscv/cpu/{ax25 => andesv5}/Kconfig | 11 +--
arch/riscv/cpu/{ax25 => andesv5}/Makefile | 0
arch/riscv/cpu/andesv5/cache.c | 130
arch/riscv/cpu/andesv5/cpu.c | 50
arch/riscv/cpu/{ax25 => andesv5}/spl.c | 0
arch/riscv/cpu/ax25/cache.c| 172
-
arch/riscv/cpu/ax25/cpu.c | 75
arch/riscv/dts/Makefile| 2 +-
arch/riscv/dts/ae350_32.dts| 2 +-
arch/riscv/dts/ae350_64.dts| 2 +-
arch/riscv/dts/binman.dtsi | 1 +
arch/riscv/include/asm/arch-andes/csr.h| 31
++
arch/riscv/include/asm/global_data.h | 2 +-
board/AndesTech/{ax25-ae350 => ae350}/Kconfig | 8
board/AndesTech/{ax25-ae350 => ae350}/MAINTAINERS | 6 +++---
board/AndesTech/{ax25-ae350 => ae350}/Makefile | 2 +-
board/AndesTech/{ax25-ae350/ax25-ae350.c => ae350/ae350.c} | 17
+
configs/ae350_rv32_defconfig | 5 -
configs/ae350_rv32_spl_defconfig | 13 +
configs/ae350_rv32_spl_xip_defconfig | 13 +
configs/ae350_rv32_xip_defconfig | 5 -
configs/ae350_rv64_defconfig | 5 -
configs/ae350_rv64_spl_defconfig | 13 +
configs/ae350_rv64_spl_xip_defconfig | 13 +
configs/ae350_rv64_xip_defconfig | 5 -
doc/board/AndesTech/{ax25-ae350.rst => ae350.rst} | 16
doc/board/AndesTech/index.rst | 2 +-
drivers/cache/Kconfig | 1 -
drivers/cache/cache-v5l2.c | 36
+--
include/configs/{ax25-ae350.h => ae350.h} | 0
tools/binman/missing-blob-help | 6 ++
32 files changed, 331 insertions(+), 321 deletions(-)
rename arch/riscv/cpu/{ax25 => andesv5}/Kconfig (66%)
rename arch/riscv/cpu/{ax25 => andesv5}/Makefile (100%)
create mode 100644 arch/riscv/cpu/andesv5/cache.c
create mode 100644 arch/riscv/cpu/andesv5/cpu.c
rename arch/riscv/cpu/{ax25 => andesv5}/spl.c (100%)
delete mode 100644 arch/riscv/cpu/ax25/cache.c
delete mode 100644 arch/riscv/cpu/ax25/cpu.c
create mode
Re: [PULL] u-boot-riscv/master
On Thu, Feb 02, 2023 at 06:30:07AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 73a3f5139182a0389d505bf29b0ad4bc29424cf8: > > Merge https://source.denx.de/u-boot/custodians/u-boot-mmc (2023-01-31 > 18:28:07 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 2b0af9feb594b68a75e4f111bde7f55ddb14995d: > > board: sifive: unmatched: enable booting on a second NVME device > (2023-02-01 16:17:59 +0800) > > CI result show no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15011 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 73a3f5139182a0389d505bf29b0ad4bc29424cf8: Merge https://source.denx.de/u-boot/custodians/u-boot-mmc (2023-01-31 18:28:07 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 2b0af9feb594b68a75e4f111bde7f55ddb14995d: board: sifive: unmatched: enable booting on a second NVME device (2023-02-01 16:17:59 +0800) CI result show no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15011 + riscv lib: + optimize memcpy for "dst == src" case + check if u-mode exists before writing mcounteren register + unmatched board config: enable second NVME device on unmatched board + ae350 board: + Adjust memory layout and some CSR setting Aurelien Jarno (1): board: sifive: unmatched: enable booting on a second NVME device Nikita Shubin (1): riscv: cpu: check U-Mode before counteren write Rick Chen (4): riscv: ae350: Enable CCTL_SUEN riscv: ax25: bypass malloc when spl fit boots from ram riscv: memcpy: check src and dst before copy riscv: ae350: support OpenSBI 1.0+ which enable FW_PIC arch/riscv/cpu/ax25/Makefile | 1 + arch/riscv/cpu/ax25/cpu.c | 18 +++--- arch/riscv/cpu/ax25/spl.c | 27 +++ arch/riscv/cpu/cpu.c | 16 arch/riscv/lib/memcpy.S| 2 ++ board/AndesTech/ax25-ae350/Kconfig | 2 +- include/configs/sifive-unmatched.h | 1 + 7 files changed, 51 insertions(+), 16 deletions(-) create mode 100644 arch/riscv/cpu/ax25/spl.c Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Thu, Dec 08, 2022 at 11:23:37AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 14f2d087a3d6347ba0ff7a7e9aaff6955e53e7a8: > > Merge tag 'sound-2023-01-rc4' of > https://source.denx.de/u-boot/custodians/u-boot-efi (2022-12-06 10:07:01 > -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 57b9900cd59ad492f74390515901788459f1e8aa: > > riscv: use imply instead of select for SPL_SEPARATE_BSS (2022-12-08 > 15:50:22 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/14369 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 14f2d087a3d6347ba0ff7a7e9aaff6955e53e7a8: Merge tag 'sound-2023-01-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi (2022-12-06 10:07:01 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 57b9900cd59ad492f74390515901788459f1e8aa: riscv: use imply instead of select for SPL_SEPARATE_BSS (2022-12-08 15:50:22 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/14369 - Kautuk's semihosting patch: move semihosting library from arm directory to common place and add RISC-V support - Zong's Kconfig patch: use "imply" instead of "select" to allow user to decide if SPL_SEPARATE_BSS should be selected Kautuk Consul (3): lib: Add common semihosting library arch/riscv: add semihosting support for RISC-V common/spl/Kconfig: add dependency on SPL_SEMIHOSTING for SPL payload Zong Li (1): riscv: use imply instead of select for SPL_SEPARATE_BSS arch/Kconfig | 2 +- arch/arm/Kconfig | 46 -- arch/arm/lib/semihosting.c | 181 + arch/riscv/include/asm/spl.h | 1 + arch/riscv/lib/Makefile | 2 ++ arch/riscv/lib/interrupts.c | 25 + arch/riscv/lib/semihosting.c | 24 common/spl/Kconfig | 2 +- include/semihosting.h| 11 +++ lib/Kconfig | 47 +++ lib/Makefile | 2 ++ lib/semihosting.c| 186 ++ 12 files changed, 301 insertions(+), 228 deletions(-) create mode 100644 arch/riscv/lib/semihosting.c create mode 100644 lib/semihosting.c Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Wed, Nov 16, 2022 at 06:16:25AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit c4ee4fe92e9be120be6d12718273dec6b63cc7d9: > > Merge tag 'u-boot-imx-20221114' of > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2022-11-14 09:33:36 > -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 591e0f878083925e7afff82e1774ba295a7767aa: > > riscv: enable reset via SBI on PolarFire Icicle Kit (2022-11-15 15:37:17 > +0800) > > CI shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/14105 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit c4ee4fe92e9be120be6d12718273dec6b63cc7d9: Merge tag 'u-boot-imx-20221114' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2022-11-14 09:33:36 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 591e0f878083925e7afff82e1774ba295a7767aa: riscv: enable reset via SBI on PolarFire Icicle Kit (2022-11-15 15:37:17 +0800) CI shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/14105 - Fix and improve microchip's clock driver to allow sync'ing DTS with linux - Improve the help message in "SBI_V02" Kconfig - Improve DTS property "isa-string" parsing rule Conor Dooley (6): dt-bindings: clk: add missing clk ids for microchip mpfs clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() clk: microchip: mpfs: fix reference clock handling clk: microchip: mpfs: fix periph clk parentage clk: microchip: mpfs: fix criticality of peripheral clocks riscv: dts: fix the mpfs's reference clock frequency Heinrich Schuchardt (2): riscv: clarify meaning of CONFIG_SBI_V02 riscv: enable reset via SBI on PolarFire Icicle Kit Yu Chien Peter Lin (1): riscv: Fix detecting FPU support in standard extension arch/riscv/Kconfig | 14 +++--- arch/riscv/cpu/cpu.c | 14 +++--- arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 4 arch/riscv/dts/microchip-mpfs.dtsi | 14 ++ configs/microchip_mpfs_icicle_defconfig | 2 ++ drivers/clk/microchip/Makefile | 2 +- drivers/clk/microchip/mpfs_clk.c | 37 +++-- drivers/clk/microchip/mpfs_clk.h | 20 drivers/clk/microchip/mpfs_clk_cfg.c | 7 +++ drivers/clk/microchip/mpfs_clk_msspll.c | 119 +++ drivers/clk/microchip/mpfs_clk_periph.c | 96 ++-- include/dt-bindings/clock/microchip-mpfs-clock.h | 3 +++ 12 files changed, 249 insertions(+), 83 deletions(-) create mode 100644 drivers/clk/microchip/mpfs_clk_msspll.c Best regards, Leo
Re: [PULL] u-boot-riscv/master
Hi Tom, On Thu, Nov 03, 2022 at 12:57:05PM -0400, Tom Rini wrote: > On Thu, Nov 03, 2022 at 07:04:33AM +, Leo Liang wrote: > > > Hi Tom, > > > > The following changes since commit c8d9ff634fc429db5acf2f5386ea937f0fef1ae7: > > > > Merge branch '2022-10-31-FWU-add-FWU-multi-bank-update-feature-support' > > (2022-11-01 09:32:21 -0400) > > > > are available in the Git repository at: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > Can you please start including a few line summary of the changes in your > pull requests? > Sorry for not including any summary before, will for sure summarize the PRs in the pull requests. > > > > for you to fetch changes up to 7321bad25f18684b53cff4346543fb2da2a2c0d0: > > > > riscv: Update Microchip MPFS Icicle Kit support (2022-11-03 13:27:56 > > +0800) > > > > CI result shows no issue: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13999 > > > > Applied to u-boot/master, thanks! > > -- > Tom Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Thu, Nov 03, 2022 at 07:04:33AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit c8d9ff634fc429db5acf2f5386ea937f0fef1ae7: > > Merge branch '2022-10-31-FWU-add-FWU-multi-bank-update-feature-support' > (2022-11-01 09:32:21 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git Can you please start including a few line summary of the changes in your pull requests? > > for you to fetch changes up to 7321bad25f18684b53cff4346543fb2da2a2c0d0: > > riscv: Update Microchip MPFS Icicle Kit support (2022-11-03 13:27:56 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13999 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom,
The following changes since commit c8d9ff634fc429db5acf2f5386ea937f0fef1ae7:
Merge branch '2022-10-31-FWU-add-FWU-multi-bank-update-feature-support'
(2022-11-01 09:32:21 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 7321bad25f18684b53cff4346543fb2da2a2c0d0:
riscv: Update Microchip MPFS Icicle Kit support (2022-11-03 13:27:56 +0800)
CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13999
Padmarao Begari (4):
riscv: dts: Update memory configuration
riscv: dts: Add QSPI NAND device node
spi: Add Microchip PolarFire SoC QSPI driver
riscv: Update Microchip MPFS Icicle Kit support
Yu Chien Peter Lin (1):
riscv: Rename Andes PLIC to PLICSW
arch/riscv/Kconfig | 6 +--
arch/riscv/cpu/ax25/Kconfig | 2 +-
arch/riscv/dts/ae350-u-boot.dtsi| 2 +-
arch/riscv/dts/ae350_32.dts | 6 +--
arch/riscv/dts/ae350_64.dts | 6 +--
arch/riscv/dts/microchip-mpfs-icicle-kit.dts| 91
arch/riscv/include/asm/global_data.h| 4 +-
arch/riscv/include/asm/syscon.h | 2 +-
arch/riscv/lib/Makefile | 2 +-
arch/riscv/lib/{andes_plic.c => andes_plicsw.c} | 26 +-
board/microchip/mpfs_icicle/Kconfig | 7 +++
configs/microchip_mpfs_icicle_defconfig | 1 +
drivers/spi/Kconfig | 6 +++
drivers/spi/Makefile| 1 +
drivers/spi/microchip_coreqspi.c| 505
drivers/timer/andes_plmt_timer.c| 2 +-
16 files changed, 582 insertions(+), 87 deletions(-)
rename arch/riscv/lib/{andes_plic.c => andes_plicsw.c} (76%)
create mode 100644 drivers/spi/microchip_coreqspi.c
Best regards,
Leo
Re: [PULL] u-boot-riscv/master
On Thu, Oct 20, 2022 at 12:36:23PM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 3724ddf157aab3bd009c1da234b9a1af1621b544: > > Merge branch '2022-10-18-TI-platform-updates' (2022-10-18 18:13:39 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to b3b44c674a473bdd3d53cf5196fae897107af619: > > riscv: ae350: Check firmware_fdt_addr header (2022-10-20 15:26:31 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13866 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 3724ddf157aab3bd009c1da234b9a1af1621b544: Merge branch '2022-10-18-TI-platform-updates' (2022-10-18 18:13:39 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to b3b44c674a473bdd3d53cf5196fae897107af619: riscv: ae350: Check firmware_fdt_addr header (2022-10-20 15:26:31 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13866 Bin Meng (1): riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+ Heinrich Schuchardt (5): cmd/sbi: format RustSBI version number cmd/sbi: error message for failure to get spec version cmd/sbi: user friendly short texts riscv: support building double-float modules k210: fix k210_pll_calc_config() Rick Chen (1): riscv: ae350: Check firmware_fdt_addr header Yu Chien Peter Lin (1): riscv: andes_plic.c: use modified IPI scheme arch/riscv/Kconfig | 15 +++ arch/riscv/Makefile | 15 --- arch/riscv/lib/andes_plic.c | 7 --- board/AndesTech/ax25-ae350/ax25-ae350.c | 2 +- board/emulation/qemu-riscv/Kconfig | 2 +- cmd/riscv/sbi.c | 26 +++--- drivers/clk/clk_k210.c | 2 +- test/dm/k210_pll.c | 2 +- 8 files changed, 50 insertions(+), 21 deletions(-) Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Tue, Sep 06, 2022 at 06:07:36AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 427aa3c9b72b6672f714389a6f71b6cc2841d559: > > Merge tag 'tpm-03092022' of > https://source.denx.de/u-boot/custodians/u-boot-tpm (2022-09-03 14:55:37 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 4a98207b2335b7108e964b831dc92f046c87: > > RISC-V: enable CONFIG_SYSRESET_SBI by default (2022-09-06 13:00:58 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13361 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 427aa3c9b72b6672f714389a6f71b6cc2841d559: Merge tag 'tpm-03092022' of https://source.denx.de/u-boot/custodians/u-boot-tpm (2022-09-03 14:55:37 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 4a98207b2335b7108e964b831dc92f046c87: RISC-V: enable CONFIG_SYSRESET_SBI by default (2022-09-06 13:00:58 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13361 Heinrich Schuchardt (2): cmd/sbi: format KVM version RISC-V: enable CONFIG_SYSRESET_SBI by default Icenowy Zheng (2): dt-bindings: clock: sifive: sync FU740 PRCI clock binding header riscv: dts: sifive: Synchronize FU740 and Unmatched DT Jessica Clarke (1): riscv: dts: Sync important Unmatched pmic and qspi0 changes from Linux arch/riscv/dts/fu740-c000-u-boot.dtsi | 16 ++--- arch/riscv/dts/fu740-c000.dtsi| 91 + arch/riscv/dts/hifive-unmatched-a00.dts | 95 --- cmd/riscv/sbi.c | 14 +++- drivers/clk/sifive/fu740-prci.c | 18 ++--- drivers/clk/sifive/sifive-prci.c | 4 +- drivers/sysreset/Kconfig | 1 + include/dt-bindings/clock/sifive-fu740-prci.h | 25 --- 8 files changed, 129 insertions(+), 135 deletions(-) Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Thu, Aug 11, 2022 at 09:38:31PM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit cdebee1fd9fa04cc4c972f826bae19b28c253eb0: > > Merge branch '2022-08-10-assorted-updates' (2022-08-10 17:49:20 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to aa0eda17cf98448c3ef826204f38c76bf48b3345: > > spl: opensbi: convert scratch options to config (2022-08-11 18:46:41 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13119 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Mon, May 30, 2022 at 11:05:54AM -0400, Tom Rini wrote: > On Sat, May 28, 2022 at 09:02:09AM +, Leo Liang wrote: > > On Fri, May 27, 2022 at 09:30:49AM -0400, Tom Rini wrote: > > > On Fri, May 27, 2022 at 02:36:29AM +, Leo Liang wrote: > > > > > > > Hi Tom, > > > > > > > > The following changes since commit > > > > 7e0edcadb09d55d5319fdc862041fd1b874476f5: > > > > > > > > Merge branch 'master' of > > > > https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 > > > > 23:29:00 -0400) > > > > > > > > are available in the Git repository at: > > > > > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > > > > > for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd: > > > > > > > > riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 > > > > 18:42:34 +0800) > > > > > > > > CI result shows no issue: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131 > > > > > > First, I've applied this to u-boot/master now. Second, will > > > https://patchwork.ozlabs.org/project/uboot/patch/ph7pr14mb5594fd11d1be74284f554bebce...@ph7pr14mb5594.namprd14.prod.outlook.com/ > > > be coming soon? Thanks! > > > > Hi Tom, > > > > This patch you mentioned will not pass CI, and the reason for that > > is the toolchain used for RISC-V in CI does not have corresponding > > settings for zifencei and zicsr. > > (detailed disscussion: > > https://patchwork.ozlabs.org/project/uboot/patch/20220128134713.2322800-1-alexandre.gh...@canonical.com/) > > (CI result: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/440735) > > > > The patch looks valid, but will fail CI on 32-bit configs. > > If we use 32-bit toolchain to test 32-bit configs, then > > problems solved. > > > > Do you have any comments? > > I guess I'm OK with saying we should use a 32bit toolchain for 32bit > riscv, if that's how things should be handled moving forward for > everyone else. > > -- > Tom Hi Tom, Sorry for taking such a long time to reply. Recap: All the "riscv: fix compitible with binutils 2.38" patches that try to support new RISC-V ISA extension will cause U-Boot CI to fail because the toolchain used in U-Boot CI do not support the new multilib settings. (original discussion: https://patchwork.ozlabs.org/project/uboot/patch/20220128134713.2322800-1-alexandre.gh...@canonical.com/) We found that current RISC-V toolchains from kernel.org do not support zifencei and zicsr extensions' multilib settings, regardless of the toolchain version. (Both gcc 11.1.0, 12.1.0 do not support the needed settings. https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/ https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.1.0/) But we also found that if we use recent upstream riscv-gnu-toolchain, we could build an gcc-12.1.0 toolchain that does support multilib settings and could fix this issue. We have provided a Dockerfile as a reference build script[1] and a prebuilt toolchain[2] for U-Boot CI to use. We have also verified the CI process could execute successfully with your base image and the provided riscv64-linux toolchain[3]. I guess the coming update of the toolchain in kernel.org should contain the new multilib settings, so I was wondering if we could replace the riscv64-linux toolchain from kernel.org with this prebuilt toolchain we've provided on github[2] temporarily? After studying a bit of the buildman tool, the earlier idea that "use different toolchains for different board configs" would require an amount of modification, thus we think its best to replace the toolchain temporarily to fix this issue, then the patch could be applied without CI failure. [1] https://github.com/ycliang-andes/riscv-toolchain/blob/master/Dockerfile [2] https://github.com/ycliang-andes/riscv-toolchain/releases/download/v1.0/x86_64-gcc-12.1.0-nolibc-riscv64-linux.tar.xz [3] https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13129
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit cdebee1fd9fa04cc4c972f826bae19b28c253eb0: Merge branch '2022-08-10-assorted-updates' (2022-08-10 17:49:20 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to aa0eda17cf98448c3ef826204f38c76bf48b3345: spl: opensbi: convert scratch options to config (2022-08-11 18:46:41 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13119 Leo Yu-Chi Liang (1): riscv: ae350: Fix XIP config boot failure Nikita Shubin (3): riscv: cpu: set gp before board_init_f_init_reserve spl: opensbi: fix typo spl: opensbi: convert scratch options to config arch/riscv/cpu/start.S | 5 - board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +++-- common/spl/Kconfig | 8 common/spl/spl_opensbi.c| 4 ++-- 4 files changed, 25 insertions(+), 9 deletions(-) Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Sat, May 28, 2022 at 09:02:09AM +, Leo Liang wrote: > On Fri, May 27, 2022 at 09:30:49AM -0400, Tom Rini wrote: > > On Fri, May 27, 2022 at 02:36:29AM +, Leo Liang wrote: > > > > > Hi Tom, > > > > > > The following changes since commit > > > 7e0edcadb09d55d5319fdc862041fd1b874476f5: > > > > > > Merge branch 'master' of > > > https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 > > > 23:29:00 -0400) > > > > > > are available in the Git repository at: > > > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > > > for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd: > > > > > > riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 > > > 18:42:34 +0800) > > > > > > CI result shows no issue: > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131 > > > > First, I've applied this to u-boot/master now. Second, will > > https://patchwork.ozlabs.org/project/uboot/patch/ph7pr14mb5594fd11d1be74284f554bebce...@ph7pr14mb5594.namprd14.prod.outlook.com/ > > be coming soon? Thanks! > > Hi Tom, > > This patch you mentioned will not pass CI, and the reason for that > is the toolchain used for RISC-V in CI does not have corresponding > settings for zifencei and zicsr. > (detailed disscussion: > https://patchwork.ozlabs.org/project/uboot/patch/20220128134713.2322800-1-alexandre.gh...@canonical.com/) > (CI result: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/440735) > > The patch looks valid, but will fail CI on 32-bit configs. > If we use 32-bit toolchain to test 32-bit configs, then > problems solved. > > Do you have any comments? I guess I'm OK with saying we should use a 32bit toolchain for 32bit riscv, if that's how things should be handled moving forward for everyone else. -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/master
On Fri, May 27, 2022 at 09:30:49AM -0400, Tom Rini wrote: > On Fri, May 27, 2022 at 02:36:29AM +, Leo Liang wrote: > > > Hi Tom, > > > > The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5: > > > > Merge branch 'master' of > > https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 23:29:00 > > -0400) > > > > are available in the Git repository at: > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd: > > > > riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 > > 18:42:34 +0800) > > > > CI result shows no issue: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131 > > First, I've applied this to u-boot/master now. Second, will > https://patchwork.ozlabs.org/project/uboot/patch/ph7pr14mb5594fd11d1be74284f554bebce...@ph7pr14mb5594.namprd14.prod.outlook.com/ > be coming soon? Thanks! Hi Tom, This patch you mentioned will not pass CI, and the reason for that is the toolchain used for RISC-V in CI does not have corresponding settings for zifencei and zicsr. (detailed disscussion: https://patchwork.ozlabs.org/project/uboot/patch/20220128134713.2322800-1-alexandre.gh...@canonical.com/) (CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/440735) The patch looks valid, but will fail CI on 32-bit configs. If we use 32-bit toolchain to test 32-bit configs, then problems solved. Do you have any comments? Best regards. Leo > -- > Tom
Re: [PULL] u-boot-riscv/master
On Fri, May 27, 2022 at 02:36:29AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5: > > Merge branch 'master' of > https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 23:29:00 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd: > > riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 > 18:42:34 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131 First, I've applied this to u-boot/master now. Second, will https://patchwork.ozlabs.org/project/uboot/patch/ph7pr14mb5594fd11d1be74284f554bebce...@ph7pr14mb5594.namprd14.prod.outlook.com/ be coming soon? Thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5: Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 23:29:00 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd: riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 18:42:34 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131 Bin Meng (3): riscv: sifive: unmatched: Adjust for big ramdisk image riscv: sifive: unleashed: Set kernel_comp_addr_r for compressed kernel riscv: qemu: Set kernel_comp_addr_r for compressed kernel Heinrich Schuchardt (1): cmd/sbi: add implementation ID 6 - Coffer Leo Yu-Chi Liang (1): riscv: Clean up asm/io.h Michal Simek (1): riscv: remove CONFIG_ARCH_MAP_SYSMEM from io.h Rick Chen (2): riscv: ae350: Fix OF_BOARD boot failure riscv: ae350: Fix OF_BOARD boot failure arch/riscv/include/asm/io.h | 138 --- board/AndesTech/ax25-ae350/Kconfig | 1 + cmd/riscv/sbi.c | 1 + configs/ae350_rv32_spl_defconfig | 1 + configs/ae350_rv32_spl_xip_defconfig | 1 + configs/ae350_rv64_spl_defconfig | 1 + configs/ae350_rv64_spl_xip_defconfig | 1 + doc/board/sifive/unleashed.rst | 2 - include/configs/qemu-riscv.h | 10 ++- include/configs/sifive-unleashed.h | 10 ++- include/configs/sifive-unmatched.h | 10 +-- 11 files changed, 23 insertions(+), 153 deletions(-) Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Wed, Apr 06, 2022 at 04:43:30AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 59bffec43a657598b194b9eb30dc01eec06078c7: > > Merge branch '2022-04-04-platform-updates' (2022-04-05 13:45:22 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 776e8aca0bad2900dc9c12b87dedb732a9f8e39b: > > riscv: alloc space exhausted (2022-04-06 10:58:13 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/11595 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 59bffec43a657598b194b9eb30dc01eec06078c7: Merge branch '2022-04-04-platform-updates' (2022-04-05 13:45:22 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 776e8aca0bad2900dc9c12b87dedb732a9f8e39b: riscv: alloc space exhausted (2022-04-06 10:58:13 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/11595 Heinrich Schuchardt (5): cmd: sbi: add Performance Monitoring Unit Extension riscv: provide missing base extension functions cmd/sbi: add missing SBI information riscv: enable CONFIG_CMD_SBI for QEMU boards riscv: alloc space exhausted Kconfig| 2 +- arch/riscv/Kconfig | 3 --- arch/riscv/include/asm/sbi.h | 4 arch/riscv/lib/sbi.c | 65 + board/emulation/qemu-riscv/Kconfig | 1 + cmd/riscv/sbi.c| 14 +- 6 files changed, 84 insertions(+), 5 deletions(-) Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Wed, Mar 16, 2022 at 10:56:40AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit c149bf41404e34014e37de32fac332892b11bd4a: > > Prepare v2022.04-rc4 (2022-03-14 16:39:08 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to aa34e13346cf727197981c599f688b406005049a: > > pinctrl: k210: Fix bias-pull-up (2022-03-15 17:43:11 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/11297 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom,
The following changes since commit c149bf41404e34014e37de32fac332892b11bd4a:
Prepare v2022.04-rc4 (2022-03-14 16:39:08 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to aa34e13346cf727197981c599f688b406005049a:
pinctrl: k210: Fix bias-pull-up (2022-03-15 17:43:11 +0800)
CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/11297
Damien Le Moal (4):
k210: use the board vendor name rather than the marketing name
k210: dts: add missing power bus clocks
k210: dts: align fpioa node with Linux
spi: dw: Force set K210 fifo length to 31
Niklas Cassel (3):
k210: dts: align plic node with Linux
pinctrl: k210: Fix loop in k210_pc_get_drive()
pinctrl: k210: Fix bias-pull-up
Sean Anderson (1):
spi: dw: Actually mask interrupts
MAINTAINERS| 12 +-
arch/riscv/dts/k210-maix-bit.dts | 3 +-
arch/riscv/dts/k210.dtsi | 177 -
board/sipeed/maix/maix.c | 2 +-
doc/board/sipeed/maix.rst | 20 +--
...ryte,k210-sysctl.txt => canaan,k210-sysctl.txt} | 8 +-
...ndryte,k210-fpioa.txt => canaan,k210-fpioa.txt} | 12 +-
doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt | 4 +-
drivers/clk/Makefile | 2 +-
drivers/clk/{clk_kendryte.c => clk_k210.c} | 4 +-
drivers/pinctrl/Makefile | 2 +-
.../pinctrl/{pinctrl-kendryte.c => pinctrl-k210.c} | 25 ++-
drivers/spi/designware_spi.c | 20 ++-
include/configs/sipeed-maix.h | 2 +-
include/{kendryte => k210}/pll.h | 0
test/dm/k210_pll.c | 2 +-
16 files changed, 174 insertions(+), 121 deletions(-)
rename doc/device-tree-bindings/mfd/{kendryte,k210-sysctl.txt =>
canaan,k210-sysctl.txt} (78%)
rename doc/device-tree-bindings/pinctrl/{kendryte,k210-fpioa.txt =>
canaan,k210-fpioa.txt} (91%)
rename drivers/clk/{clk_kendryte.c => clk_k210.c} (99%)
rename drivers/pinctrl/{pinctrl-kendryte.c => pinctrl-k210.c} (97%)
rename include/{kendryte => k210}/pll.h (100%)
Best regards,
Leo
Re: [PULL] u-boot-riscv/master
On Thu, Feb 10, 2022 at 03:16:03PM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 531c00894577a0a852431adf61ade76925f8b162: > > Merge branch '2022-02-08-TI-platform-updates' (2022-02-08 12:28:04 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 7c08680aa32db12e5a7e2765cfc8b7e8ce8895ff: > > doc: qemu-riscv: Update documentation for QEMU spike machine (2022-02-10 > 11:19:15 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/10941 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 531c00894577a0a852431adf61ade76925f8b162: Merge branch '2022-02-08-TI-platform-updates' (2022-02-08 12:28:04 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 7c08680aa32db12e5a7e2765cfc8b7e8ce8895ff: doc: qemu-riscv: Update documentation for QEMU spike machine (2022-02-10 11:19:15 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/10941 Anup Patel (4): serial: Add RISC-V HTIF console driver riscv: qemu: Enable HTIF console support riscv: qemu: Implement is_flash_available() for MTD NOR doc: qemu-riscv: Update documentation for QEMU spike machine board/emulation/qemu-riscv/Kconfig | 1 + board/emulation/qemu-riscv/qemu-riscv.c | 12 +++ doc/board/emulation/qemu-riscv.rst | 48 ++--- drivers/serial/Kconfig | 8 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_htif.c| 178 6 files changed, 232 insertions(+), 16 deletions(-) create mode 100644 drivers/serial/serial_htif.c Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Fri, Dec 03, 2021 at 02:19:32PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 4a14bfffd42f968ed9d72a780a8d44a9053c5b95: > > Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2021-11-30 > 08:59:22 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to c0ffc12a701621dc72dfc896965cbfe5b0dbf9b4: > > riscv: Enable SPI flash env for SiFive Unmatched. (2021-12-02 16:43:56 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/10128 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 4a14bfffd42f968ed9d72a780a8d44a9053c5b95: Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2021-11-30 08:59:22 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to c0ffc12a701621dc72dfc896965cbfe5b0dbf9b4: riscv: Enable SPI flash env for SiFive Unmatched. (2021-12-02 16:43:56 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/10128 Leo Yu-Chi Liang (1): board: ae350: Support autoboot from RAM Padmarao Begari (5): net: macb: Remove Microchip compatible string i2c: Add Microchip PolarFire SoC I2C driver riscv: dts: Split Microchip device tree riscv: Update Microchip MPFS Icicle Kit support doc: board: Update Microchip MPFS Icicle Kit doc Thomas Skibo (2): riscv: Support booting SiFive Unmatched from SPI. riscv: Enable SPI flash env for SiFive Unmatched. arch/riscv/cpu/fu740/Kconfig | 13 + arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi| 11 + arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 518 +-- arch/riscv/dts/microchip-mpfs.dtsi | 571 + board/microchip/mpfs_icicle/Kconfig| 5 + board/microchip/mpfs_icicle/mpfs_icicle.c | 17 +- board/sifive/unmatched/Kconfig | 1 + board/sifive/unmatched/spl.c | 3 + configs/microchip_mpfs_icicle_defconfig| 1 - configs/sifive_unmatched_defconfig | 6 + doc/board/microchip/mpfs_icicle.rst| 7 +- doc/board/sifive/unmatched.rst | 31 ++ drivers/i2c/Kconfig| 6 + drivers/i2c/Makefile | 1 + drivers/i2c/i2c-microchip.c| 482 + drivers/net/macb.c | 18 +- include/configs/ax25-ae350.h | 13 +- .../interrupt-controller/microchip-mpfs-plic.h | 196 +++ .../dt-bindings/interrupt-controller/riscv-hart.h | 17 + 19 files changed, 1512 insertions(+), 405 deletions(-) create mode 100644 arch/riscv/dts/microchip-mpfs.dtsi create mode 100644 drivers/i2c/i2c-microchip.c create mode 100644 include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Tue, Nov 09, 2021 at 10:40:01AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 52207514ba419a69a8105d16997b025f966c8879: > > Merge branch '2021-11-05-Kconfig-syncs' (2021-11-05 15:38:46 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 990e1e4beae546ddc9c50854c0588d1bea494cd2: > > Fix syntax error (2021-11-08 15:35:55 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9775 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 52207514ba419a69a8105d16997b025f966c8879: Merge branch '2021-11-05-Kconfig-syncs' (2021-11-05 15:38:46 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 990e1e4beae546ddc9c50854c0588d1bea494cd2: Fix syntax error (2021-11-08 15:35:55 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9775 Heinrich Schuchardt (2): riscv: function to retrieve SBI implementation version cmd: sbi: show SBI implementation version Leo Yu-Chi Liang (2): riscv: ae350: Use #if defined instead of CONFIG_IS_ENABLED Fix syntax error Wei Fu (1): riscv: add #define in asm/io.h for some device drivers arch/riscv/include/asm/io.h | 4 arch/riscv/include/asm/sbi.h| 1 + arch/riscv/lib/sbi.c| 19 +++ board/AndesTech/ax25-ae350/ax25-ae350.c | 4 ++-- cmd/riscv/sbi.c | 26 ++ common/image-board.c| 2 +- 6 files changed, 45 insertions(+), 11 deletions(-) Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Wed, Oct 20, 2021 at 03:14:00PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit fb1018106a7bbb1a0d723029f6760b1b1b4d306d: > > Merge branch '2021-10-19-assorted-changes' (2021-10-19 20:45:12 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to ddf4972834fdf33f0a3360ff4a68fde333995113: > > riscv: Avoid io read/write cause wrong result (2021-10-20 10:59:17 +0800) > > SI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9532 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit fb1018106a7bbb1a0d723029f6760b1b1b4d306d: Merge branch '2021-10-19-assorted-changes' (2021-10-19 20:45:12 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to ddf4972834fdf33f0a3360ff4a68fde333995113: riscv: Avoid io read/write cause wrong result (2021-10-20 10:59:17 +0800) SI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9532 Bin Meng (10): board: sifive: Fix a potential build warning in board_fdt_blob_setup() cache: sifive: Fix -Wint-to-pointer-cast warning clk: sifive: Fix -Wint-to-pointer-cast warning gpio: sifive: Fix -Wint-to-pointer-cast warning i2c: ocores: Fix -Wint-to-pointer-cast warning dm: core: Add a new API devfdt_get_addr_index_ptr() dm: Provide dev_read_addr_index_ptr() wrapper net: macb: Fix -Wint-to-pointer-cast warnings ram: sifive: Fix -Wint-to-pointer-cast warnings board: sifive: Fix -Wint-to-pointer-cast warning Nick Hu (1): riscv: Avoid io read/write cause wrong result arch/riscv/include/asm/io.h | 18 +- board/sifive/unleashed/unleashed.c | 6 +++--- board/sifive/unmatched/unmatched.c | 6 +++--- drivers/cache/cache-sifive-ccache.c | 2 +- drivers/clk/sifive/sifive-prci.c| 6 +++--- drivers/core/fdtaddr.c | 11 --- drivers/gpio/sifive-gpio.c | 6 ++ drivers/i2c/ocores_i2c.c| 2 +- drivers/net/macb.c | 11 +++ drivers/ram/sifive/sifive_ddr.c | 8 include/dm/fdtaddr.h| 12 include/dm/read.h | 18 ++ 12 files changed, 67 insertions(+), 39 deletions(-) Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Thu, Oct 07, 2021 at 07:51:00PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit ea67f467a43e4c8852bd1ce1bb75f5dc6c3788d1: > > Merge branch '2021-10-06-assorted-improvements' (2021-10-06 13:46:31 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 1b2b52f29402b5aaadfe4ba11bd3f29bd414: > > riscv: ae350: enable Coherence Manager for ae350 (2021-10-07 16:08:23 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9388 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit ea67f467a43e4c8852bd1ce1bb75f5dc6c3788d1: Merge branch '2021-10-06-assorted-improvements' (2021-10-06 13:46:31 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 1b2b52f29402b5aaadfe4ba11bd3f29bd414: riscv: ae350: enable Coherence Manager for ae350 (2021-10-07 16:08:23 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9388 Heinrich Schuchardt (4): riscv: add missing SBI extension definitions cmd/sbi: use constants instead of numerical values sysreset: provide SBI based sysreset driver configs: enable SYSRESET_SBI on qemu-riscvXX_smode_defconfig Leo Yu-Chi Liang (1): riscv: ae350: enable Coherence Manager for ae350 Samuel Holland (3): serial: Add a debug console using the RISC-V SBI interface riscv: Fix setting no-map in reserved memory nodes riscv: image: Use the first DRAM bank for bootm_low Sean Anderson (4): clk: k210: Fix checking if ulongs are less than 0 k210: clk: Refactor out_of_spec tests test: dm: k210: Reduce duplication in test cases clk: k210: Try harder to get the best config MAINTAINERS | 1 + arch/riscv/cpu/ax25/cpu.c| 42 +++ arch/riscv/cpu/cpu.c | 13 +++- arch/riscv/include/asm/sbi.h | 40 ++- arch/riscv/lib/fdt_fixup.c | 5 +- arch/riscv/lib/sbi.c | 12 cmd/riscv/sbi.c | 30 common/image.c | 2 +- configs/qemu-riscv32_smode_defconfig | 1 + configs/qemu-riscv32_spl_defconfig | 1 + configs/qemu-riscv64_smode_defconfig | 1 + configs/qemu-riscv64_spl_defconfig | 1 + drivers/clk/clk_kendryte.c | 134 +-- drivers/serial/Kconfig | 10 +++ drivers/serial/Makefile | 1 + drivers/serial/serial_sbi.c | 16 + drivers/sysreset/Kconfig | 12 drivers/sysreset/Makefile| 1 + drivers/sysreset/sysreset_sbi.c | 51 + test/dm/k210_pll.c | 36 +- 20 files changed, 313 insertions(+), 97 deletions(-) create mode 100644 drivers/serial/serial_sbi.c create mode 100644 drivers/sysreset/sysreset_sbi.c Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Tue, Sep 07, 2021 at 04:20:50PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit ad320c237bea7ece659efaf6c1d43475e0e5db6a: > > Merge tag 'u-boot-stm32-20210906' of > https://source.denx.de/u-boot/custodians/u-boot-stm (2021-09-06 10:31:56 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 30fa33dc808b8f28185bca9c812225cbc1ec6e8f: > > riscv: lib: modify the indent (2021-09-07 10:34:29 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9018 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit ad320c237bea7ece659efaf6c1d43475e0e5db6a: Merge tag 'u-boot-stm32-20210906' of https://source.denx.de/u-boot/custodians/u-boot-stm (2021-09-06 10:31:56 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 30fa33dc808b8f28185bca9c812225cbc1ec6e8f: riscv: lib: modify the indent (2021-09-07 10:34:29 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9018 Heinrich Schuchardt (3): riscv: enable booting HiFive Unmatched from SATA configs: qemu-riscvXX_spl_defconfig enable CMD_SBI riscv: show code leading to exception Thomas Skibo (1): riscv: Add missing sentinel in ocores_i2c.c Zong Li (5): cache: add sifive composable cache driver common: board_r: support enable_caches for RISC-V riscv: lib: implement enable_caches for sifive cache board: sifive: use ccache driver instead of helper function riscv: lib: modify the indent arch/riscv/Kconfig| 5 +++ arch/riscv/cpu/fu540/Kconfig | 2 + arch/riscv/cpu/fu540/Makefile | 1 - arch/riscv/cpu/fu540/cache.c | 55 --- arch/riscv/cpu/fu740/Kconfig | 2 + arch/riscv/cpu/fu740/Makefile | 1 - arch/riscv/cpu/fu740/cache.c | 55 --- arch/riscv/include/asm/arch-fu540/cache.h | 14 -- arch/riscv/include/asm/arch-fu740/cache.h | 14 -- arch/riscv/include/asm/cache.h| 2 +- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/cache.c| 4 ++ arch/riscv/lib/interrupts.c | 33 ++ arch/riscv/lib/sifive_cache.c | 27 +++ board/sifive/unleashed/unleashed.c| 10 + board/sifive/unmatched/unmatched.c| 11 ++--- common/board_r.c | 4 +- configs/qemu-riscv32_spl_defconfig| 1 + configs/qemu-riscv64_spl_defconfig| 1 + configs/sifive_unmatched_defconfig| 5 +++ drivers/cache/Kconfig | 7 +++ drivers/cache/Makefile| 1 + drivers/cache/cache-sifive-ccache.c | 75 +++ drivers/i2c/ocores_i2c.c | 1 + include/configs/sifive-unmatched.h| 3 ++ 25 files changed, 176 insertions(+), 159 deletions(-) delete mode 100644 arch/riscv/cpu/fu540/cache.c delete mode 100644 arch/riscv/cpu/fu740/cache.c delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h create mode 100644 arch/riscv/lib/sifive_cache.c create mode 100644 drivers/cache/cache-sifive-ccache.c Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Thu, Aug 19, 2021 at 04:56:39PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit a0da2dda4ed9d0aee5265e9cd8876734f9f80e09: > > Prepare v2021.10-rc2 (2021-08-16 14:18:45 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 47d73ba4f4a40f17622d93f96b48e285b73c3061: > > board: sifive: overwrite board_fdt_blob_setup in u-boot proper (2021-08-17 > 19:28:37 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8749 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit a0da2dda4ed9d0aee5265e9cd8876734f9f80e09: Prepare v2021.10-rc2 (2021-08-16 14:18:45 -0400) are available in the Git repository at: g...@source.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 47d73ba4f4a40f17622d93f96b48e285b73c3061: board: sifive: overwrite board_fdt_blob_setup in u-boot proper (2021-08-17 19:28:37 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8749 Dimitri John Ledkov (1): qemu-riscv64_smode: fix extlinux (define preboot) Zong Li (3): riscv: cpu: fu740: Fix typo of date board: sifive: compile stuff only related to SPL in SPL build board: sifive: overwrite board_fdt_blob_setup in u-boot proper arch/riscv/cpu/fu740/spl.c | 2 +- board/sifive/unleashed/Makefile | 4 ++-- board/sifive/unleashed/unleashed.c | 11 +++ board/sifive/unmatched/Makefile | 3 ++- board/sifive/unmatched/unmatched.c | 11 +++ configs/qemu-riscv64_smode_defconfig | 2 ++ 6 files changed, 29 insertions(+), 4 deletions(-)
Re: [PULL] u-boot-riscv/master
On Thu, Jul 22, 2021 at 10:15:10AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit c9204859bbdb924cda811813c545032971656480: > > Merge branch 'master' of git://source.denx.de/u-boot-sh (2021-07-20 > 19:31:40 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 219cb173114c9cfaf1dc7fed21281f2c43c88c9f: > > board: sifive: unmatched: reset USB hub, PCIe-USB bridge, and ULPI device > in SPL (2021-07-21 22:25:15 +0800) > > CI result show no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8344 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit c9204859bbdb924cda811813c545032971656480: Merge branch 'master' of git://source.denx.de/u-boot-sh (2021-07-20 19:31:40 -0400) are available in the Git repository at: g...@source.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 219cb173114c9cfaf1dc7fed21281f2c43c88c9f: board: sifive: unmatched: reset USB hub, PCIe-USB bridge, and ULPI device in SPL (2021-07-21 22:25:15 +0800) CI result show no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8344 Vincent Chen (2): board: sifive: unmatched: refine GEMGXL initialized function in SPL board: sifive: unmatched: reset USB hub, PCIe-USB bridge, and ULPI device in SPL Vitaly Wool (1): riscv: booti: do not force relocation if force_reloc is not set Zong Li (2): board: sifive: remove the command for setting serial number board: sifive: drop stuff related to unmatched revision 1 arch/riscv/dts/Makefile|2 +- .../dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi | 1489 .../dts/hifive-unmatched-a00-rev1-u-boot.dtsi |7 - arch/riscv/dts/hifive-unmatched-a00-rev1.dts |4 - arch/riscv/lib/image.c |7 +- .../sifive/unmatched/hifive-platform-i2c-eeprom.c | 23 +- board/sifive/unmatched/spl.c | 114 +- configs/sifive_unmatched_defconfig |4 - 8 files changed, 81 insertions(+), 1569 deletions(-) delete mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi delete mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi delete mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1.dts Best regards, Leo
Re: [PULL] u-boot-riscv/master
On Wed, Jul 07, 2021 at 11:21:13PM +0800, Leo Liang wrote: > Hi Tom, > > This is a follow up PR for OpenPiton's dts. > > Thanks for the catch. > > The following changes since commit 5617efd2c882562b716a61bc0dc0edda46b045df: > > Merge branch '2021-07-06-platform-updates' (2021-07-06 18:10:10 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to c9135d5a7af2df0e273e0f7e2f6c8132b34aba82: > > riscv: dts: add OpenPiton RISC-V board dts support (2021-07-07 20:34:02 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8100 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/master
Hi Tom, This is a follow up PR for OpenPiton's dts. Thanks for the catch. The following changes since commit 5617efd2c882562b716a61bc0dc0edda46b045df: Merge branch '2021-07-06-platform-updates' (2021-07-06 18:10:10 -0400) are available in the Git repository at: g...@source.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to c9135d5a7af2df0e273e0f7e2f6c8132b34aba82: riscv: dts: add OpenPiton RISC-V board dts support (2021-07-07 20:34:02 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8100 Tianrui Wei (1): riscv: dts: add OpenPiton RISC-V board dts support arch/riscv/dts/openpiton-riscv64.dts | 4 ++-- board/openpiton/riscv64/MAINTAINERS | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) Best regards, Leo
Re: [PULL] u-boot-riscv/master
Hi Tom, Leo, Apologies for making that mistake, and many many thanks for merging our patches! We’ve already fixed the problem with another patch. Many thanks, Tianrui -Original Message- From: Tom Rini Date: Wednesday, July 7, 2021 at 3:52 AM To: Leo Liang Cc: u-boot@lists.denx.de , r...@andestech.com , Tianrui Wei Subject: Re: [PULL] u-boot-riscv/master On Wed, Jul 07, 2021 at 12:02:05AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de: > > Merge branch '2021-07-01-update-CI-containers' (2021-07-05 15:29:44 -0400) > > are available in the Git repository at: > > > g...@source.denx.de<mailto:g...@source.denx.de>:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 4b4159d0f31ca3e0174ccfdce9a24a1fe3671829: > > board: sifive: support spl multi-dtb on unmatched board (2021-07-06 > 20:24:26 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8081 > Please note: w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #address-cells (1) differs from / (2) w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #size-cells (1) differs from / (2) need to be fixed in a follow up PR (and the relevant dts files should be added to the board MAINTAINER file too). That said, applied to u-boot/master, thanks! -- Tom
