[U-Boot] patman and non-ascii names
Hi All,
Just ran into an issue with patman. It's picking up David Müller as a
cc recipient. But seems to barf because of the non-ascii characters in
his name
File "./tools/patman/patman", line 159, in
options.add_maintainers)
File "./tools/patman/series.py", line 238, in MakeCcFile
print(cover_fname, ', '.join(set(cover_cc + all_ccs)), file=fd)
UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position
8: ordinal not in range(128)
When I exclude the patch that David's picked as a Cc there is no problem.
Any suggestions. I assume something involving .decode('utf-8') is required.
Thanks,
Chris
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Re: [U-Boot] patman and non-ascii names
On Wed, Jan 25, 2017 at 10:33 PM, Chris Packham wrote:
> Hi All,
>
> Just ran into an issue with patman. It's picking up David Müller as a
> cc recipient. But seems to barf because of the non-ascii characters in
> his name
>
>
> File "./tools/patman/patman", line 159, in
> options.add_maintainers)
> File "./tools/patman/series.py", line 238, in MakeCcFile
> print(cover_fname, ', '.join(set(cover_cc + all_ccs)), file=fd)
> UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position
> 8: ordinal not in range(128)
>
> When I exclude the patch that David's picked as a Cc there is no problem.
>
> Any suggestions. I assume something involving .decode('utf-8') is required.
>
This seems to work for me but the decode()/encode() makes me think
something is more complicated than it needs to be.
diff --git a/tools/patman/series.py b/tools/patman/series.py
index 38a452edad41..c1b86521aa45 100644
--- a/tools/patman/series.py
+++ b/tools/patman/series.py
@@ -235,7 +235,8 @@ class Series(dict):
if cover_fname:
cover_cc = gitutil.BuildEmailList(self.get('cover_cc', ''))
-print(cover_fname, ', '.join(set(cover_cc + all_ccs)), file=fd)
+cc_list = ', '.join([x.decode('utf-8') for x in
set(cover_cc + all_ccs)])
+print(cover_fname, cc_list.encode('utf-8'), file=fd)
fd.close()
return fname
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[U-Boot] [RFC PATCH v3 02/11] lib: vsprintf: add IPv6 compressed format %pI6c
Add support for "human friendly" IPv6 address representations as
specified in https://www.rfc-editor.org/rfc/rfc5952.txt
This code has been adapted from Linux kernel with minimal modification.
Signed-off-by: Chris Packham
---
Changes in v3: None
Changes in v2: None
include/net6.h | 13 +
lib/vsprintf.c | 154 -
2 files changed, 144 insertions(+), 23 deletions(-)
diff --git a/include/net6.h b/include/net6.h
index b62295181d45..1b82c25ec76e 100644
--- a/include/net6.h
+++ b/include/net6.h
@@ -45,4 +45,17 @@ struct ip6_hdr {
struct in6_addr daddr;
};
+/* :::0:0/96 is reserved for v4 mapped addresses */
+static inline int ipv6_addr_v4mapped(const struct in6_addr *a)
+{
+ return (a->s6_addr32[0] | a->s6_addr32[1] |
+ (a->s6_addr32[2] ^ htonl(0x))) == 0;
+}
+
+/* Intra-Site Automatic Tunnel Addressing Protocol Address */
+static inline int ipv6_addr_is_isatap(const struct in6_addr *a)
+{
+ return (a->s6_addr32[2] | htonl(0x0200)) == htonl(0x02005EFE);
+}
+
#endif /* __NET6_H__ */
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index 874a2951f705..54f1e632fdc1 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -19,6 +19,7 @@
#include
#include
+#include
#define noinline __attribute__((noinline))
/* we use this so that we can do without the ctype library */
@@ -140,6 +141,7 @@ static noinline char *put_dec(char *buf, uint64_t num)
#define LEFT 16 /* left justified */
#define SMALL 32 /* Must be 32 == 0x20 */
#define SPECIAL64 /* 0x */
+#define COMPRESSED 128 /* use compressed format */
/*
* Macro to add a new character to our output string, but only if it will
@@ -301,12 +303,121 @@ static char *mac_address_string(char *buf, char *end, u8
*addr, int field_width,
flags & ~SPECIAL);
}
-static char *ip6_addr_string(char *buf, char *end, u8 *addr, int field_width,
+static char *ip4_string(char *p, u8 *addr)
+{
+ char temp[3]; /* hold each IP quad in reverse order */
+ int i, digits;
+
+ for (i = 0; i < 4; i++) {
+ digits = put_dec_trunc(temp, addr[i]) - temp;
+ /* reverse the digits in the quad */
+ while (digits--)
+ *p++ = temp[digits];
+ if (i != 3)
+ *p++ = '.';
+ }
+ *p = '\0';
+
+ return p;
+}
+
+static char *ip4_addr_string(char *buf, char *end, u8 *addr, int field_width,
int precision, int flags)
{
- /* (8 * 4 hex digits), 7 colons and trailing zero */
- char ip6_addr[8 * 5];
- char *p = ip6_addr;
+ char ip4_addr[sizeof("255.255.255.255")];
+
+ ip4_string(ip4_addr, addr);
+
+ return string(buf, end, ip4_addr, field_width, precision,
+ flags & ~SPECIAL);
+}
+#endif
+
+#ifdef CONFIG_NET6
+static char *ip6_compressed_string(char *p, u8 *addr)
+{
+ int i, j, range;
+ unsigned char zerolength[8];
+ int longest = 1;
+ int colonpos = -1;
+ u16 word;
+ u8 hi, lo;
+ int needcolon = 0;
+ int useIPv4;
+ struct in6_addr in6;
+
+ memcpy(&in6, addr, sizeof(struct in6_addr));
+
+ useIPv4 = ipv6_addr_v4mapped(&in6) || ipv6_addr_is_isatap(&in6);
+
+ memset(zerolength, 0, sizeof(zerolength));
+
+ if (useIPv4)
+ range = 6;
+ else
+ range = 8;
+
+ /* find position of longest 0 run */
+ for (i = 0; i < range; i++) {
+ for (j = i; j < range; j++) {
+ if (in6.s6_addr16[j] != 0)
+ break;
+ zerolength[i]++;
+ }
+ }
+ for (i = 0; i < range; i++) {
+ if (zerolength[i] > longest) {
+ longest = zerolength[i];
+ colonpos = i;
+ }
+ }
+ if (longest == 1) /* don't compress a single 0 */
+ colonpos = -1;
+
+ /* emit address */
+ for (i = 0; i < range; i++) {
+ if (i == colonpos) {
+ if (needcolon || i == 0)
+ *p++ = ':';
+ *p++ = ':';
+ needcolon = 0;
+ i += longest - 1;
+ continue;
+ }
+ if (needcolon) {
+ *p++ = ':';
+ needcolon = 0;
+ }
+ /* hex u16 without leading 0s */
+ word = ntohs(in6.s6_addr16[i]);
+ hi = word >> 8;
+ lo = word & 0xff;
+ if (hi) {
+ if (hi > 0x0f)
+
[U-Boot] [RFC PATCH v3 03/11] lib: net_utils: add string_to_ip6
string_to_ip6 parses an IPv6 address from a string. Parsing v6 addresses
is a bit more complicated than parsing v4 because there are a number of
different formats that can be used.
Signed-off-by: Chris Packham
---
I'm sure the parsing can be better and done in less code with only a
single pass but I haven't yet figured it out. The main problem is that
"::" can represent a variable number of contiguous ":" so when
parsing "::" we can't tell how many half words to skip.
Changes in v3: None
Changes in v2: None
include/net6.h | 3 ++
lib/net_utils.c | 121
2 files changed, 124 insertions(+)
diff --git a/include/net6.h b/include/net6.h
index 1b82c25ec76e..a41eb876fc53 100644
--- a/include/net6.h
+++ b/include/net6.h
@@ -58,4 +58,7 @@ static inline int ipv6_addr_is_isatap(const struct in6_addr
*a)
return (a->s6_addr32[2] | htonl(0x0200)) == htonl(0x02005EFE);
}
+/* Convert a string to an ipv6 address */
+int string_to_ip6(const char *s, struct in6_addr *addr);
+
#endif /* __NET6_H__ */
diff --git a/lib/net_utils.c b/lib/net_utils.c
index d06be22849fb..0be8871e903f 100644
--- a/lib/net_utils.c
+++ b/lib/net_utils.c
@@ -11,6 +11,8 @@
*/
#include
+#include
+#include
struct in_addr string_to_ip(const char *s)
{
@@ -42,3 +44,122 @@ struct in_addr string_to_ip(const char *s)
addr.s_addr = htonl(addr.s_addr);
return addr;
}
+
+#ifdef CONFIG_NET6
+/**
+ * Parses an struct in6_addr from the given string. IPv6 address parsing is a
bit
+ * more complicated than v4 due to the flexible format and some of the special
+ * cases (e.g. v4 mapped).
+ *
+ * Examples of valid strings:
+ * 2001:db8::0:1234:1
+ * 2001:0db8:::::1234:0001
+ * ::1
+ * :::192.168.1.1
+ *
+ * Examples of invalid strings
+ * 2001:db8::0::0 (:: can only appear once)
+ * 2001:db8:192.168.1.1::1 (v4 part can only appear at the end)
+ * 192.168.1.1 (we don't implicity map v4)
+ */
+int string_to_ip6(const char *strpt, struct in6_addr *addrpt)
+{
+ int colon_count = 0;
+ int found_double_colon = 0;
+ int xstart = 0; /* first zero (double colon) */
+ int len = 7;/* num words the double colon represents */
+ int i;
+ const char *s = strpt;
+ struct in_addr zero_ip = {.s_addr = 0};
+
+ if (strpt == NULL)
+ return -1;
+
+ /* First pass, verify the syntax and locate the double colon */
+ for (;;) {
+ while (isxdigit((int)*s))
+ s++;
+ if (*s == '\0')
+ break;
+ if (*s != ':') {
+ if (*s == '.' && len >= 2) {
+ struct in_addr v4;
+ while (s != strpt && *(s - 1) != ':')
+ --s;
+ v4 = string_to_ip(s);
+ if (memcmp(&zero_ip, &v4,
+ sizeof(struct in_addr) != 0)) {
+ len -= 2;
+ break;
+ }
+ }
+ /* This could be a valid address */
+ break;
+ }
+ if (s == strpt) {
+ /* The address begins with a colon */
+ if (*++s != ':')
+ /* Must start with a double colon or a number */
+ goto out_err;
+ } else {
+ s++;
+ if (found_double_colon)
+ len--;
+ else
+ xstart++;
+ }
+
+ if (*s == ':') {
+ if (found_double_colon)
+ /* Two double colons are not allowed */
+ goto out_err;
+ found_double_colon = 1;
+ len -= xstart;
+ s++;
+ }
+
+ if (++colon_count == 7)
+ /* Found all colons */
+ break;
+ }
+
+ if (colon_count == 0)
+ goto out_err;
+ if (*--s == ':')
+ len++;
+
+ /* Second pass, read the address */
+ s = strpt;
+ for (i = 0; i < 8; i++) {
+ int val = 0;
+ char *end;
+
+ if (found_double_colon && i >= xstart && i < xstart + len) {
+ addrpt->s6_addr16[i] = 0;
+ continue;
+ }
+ while (*
[U-Boot] [RFC PATCH v3 04/11] net: add definition of udp_hdr
UDP is the same over IPv4 as it is over other protocols (i.e. IPv6) add
a definition of just the UDP header independent of the IPv4 header that
it may or may not be combined with.
Signed-off-by: Chris Packham
---
Ideally struct ip_udp_hdr would be defined as
struct ip_udp_hdr {
struct ip_hdr ip;
struct udp_hdr udp;
};
Implementing this touches more code that I really want to at this
point. Some of the code that currently uses struct ip_udp_hdr could
probably just use struct ip_hdr instead but some care would need to be
taken to much such a change.
Changes in v3: None
Changes in v2: None
include/net.h | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/net.h b/include/net.h
index 1f4d94735007..10d98d92535b 100644
--- a/include/net.h
+++ b/include/net.h
@@ -375,6 +375,18 @@ struct ip_hdr {
#define IP_HDR_SIZE(sizeof(struct ip_hdr))
/*
+ * UDP header.
+ */
+struct udp_hdr {
+ __be16 udp_src;/* UDP source port */
+ __be16 udp_dst;/* UDP destination port */
+ __be16 udp_len;/* Length of UDP packet */
+ __be16 udp_xsum; /* Checksum */
+};
+
+#define UDP_HDR_SIZE (sizeof(struct udp_hdr))
+
+/*
* Internet Protocol (IP) + UDP header.
*/
struct ip_udp_hdr {
@@ -395,7 +407,6 @@ struct ip_udp_hdr {
};
#define IP_UDP_HDR_SIZE(sizeof(struct ip_udp_hdr))
-#define UDP_HDR_SIZE (IP_UDP_HDR_SIZE - IP_HDR_SIZE)
/*
* Address Resolution Protocol (ARP) header.
--
2.11.0.24.ge6920cf
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[U-Boot] [RFC PATCH v3 01/11] Initial net6.h
The initial net6.h just has the definition of an IPv6 address and IPv6
header. Subsequent changes will build on this.
Signed-off-by: Chris Packham
---
Changes in v3: None
Changes in v2: None
include/net6.h | 48
1 file changed, 48 insertions(+)
create mode 100644 include/net6.h
diff --git a/include/net6.h b/include/net6.h
new file mode 100644
index ..b62295181d45
--- /dev/null
+++ b/include/net6.h
@@ -0,0 +1,48 @@
+/**
+ * Simple IPv6 network layer implementation.
+ *
+ * Based and/or adapted from the IPv4 network layer in net.[hc]
+ *
+ * (C) Copyright 2013 Allied Telesis Labs NZ
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef __NET6_H__
+#define __NET6_H__
+
+struct in6_addr {
+ union {
+ __u8u6_addr8[16];
+ __be16 u6_addr16[8];
+ __be32 u6_addr32[4];
+ } in6_u;
+
+#define s6_addrin6_u.u6_addr8
+#define s6_addr16 in6_u.u6_addr16
+#define s6_addr32 in6_u.u6_addr32
+};
+
+/**
+ * struct ipv6hdr - Internet Protocol V6 (IPv6) header.
+ *
+ * IPv6 packet header as defined in RFC 2460.
+ */
+struct ip6_hdr {
+#if defined(__LITTLE_ENDIAN_BITFIELD)
+ __u8priority:4,
+ version:4;
+#elif defined(__BIG_ENDIAN_BITFIELD)
+ __u8version:4,
+ priority:4;
+#else
+#error "Please fix "
+#endif
+ __u8flow_lbl[3];
+ __be16 payload_len;
+ __u8nexthdr;
+ __u8hop_limit;
+ struct in6_addr saddr;
+ struct in6_addr daddr;
+};
+
+#endif /* __NET6_H__ */
--
2.11.0.24.ge6920cf
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[U-Boot] [RFC PATCH v3 05/11] net: IPv6 skeleton and environment variables
Create net6.c and add CONFIG_NET6 to Kconfig/Makefile. Also add
support for the following environment variables:
- ip6addr
- gateway6
- serverip6
Signed-off-by: Chris Packham
---
Changes in v3: None
Changes in v2:
- Split environment variables from main implementation
- remove "prefixlength6" environment variable. The prefix length is now
set when specifying the address i.e. setenv ip6addr 2001:db8::1/64.
include/env_callback.h | 8 +
include/env_flags.h| 9 +
net/Kconfig| 6 +++-
net/Makefile | 1 +
net/net6.c | 89 ++
5 files changed, 112 insertions(+), 1 deletion(-)
create mode 100644 net/net6.c
diff --git a/include/env_callback.h b/include/env_callback.h
index 90b95b5e6676..97e245bff09d 100644
--- a/include/env_callback.h
+++ b/include/env_callback.h
@@ -60,6 +60,13 @@
#define NET_CALLBACKS
#endif
+#ifdef CONFIG_NET6
+#define NET6_CALLBACKS \
+ "ip6addr:ip6addr," \
+ "serverip6:serverip6,"
+#else
+#define NET6_CALLBACKS
+#endif
/*
* This list of callback bindings is static, but may be overridden by defining
* a new association in the ".callbacks" environment variable.
@@ -68,6 +75,7 @@
ENV_DOT_ESCAPE ENV_FLAGS_VAR ":flags," \
"baudrate:baudrate," \
NET_CALLBACKS \
+ NET6_CALLBACKS \
"loadaddr:loadaddr," \
SILENT_CALLBACK \
SPLASHIMAGE_CALLBACK \
diff --git a/include/env_flags.h b/include/env_flags.h
index 0dcec0689b19..916e4bec394f 100644
--- a/include/env_flags.h
+++ b/include/env_flags.h
@@ -65,6 +65,14 @@ enum env_flags_varaccess {
#define NET_FLAGS
#endif
+#ifdef CONFIG_NET6
+#define NET6_FLAGS \
+ "ip6addr:s," \
+ "serverip6:s,"
+#else
+#define NET6_FLAGS
+#endif
+
#ifndef CONFIG_ENV_OVERWRITE
#define SERIAL_FLAGS "serial#:so,"
#else
@@ -74,6 +82,7 @@ enum env_flags_varaccess {
#define ENV_FLAGS_LIST_STATIC \
ETHADDR_FLAGS \
NET_FLAGS \
+ NET6_FLAGS \
SERIAL_FLAGS \
CONFIG_ENV_FLAGS_LIST_STATIC
diff --git a/net/Kconfig b/net/Kconfig
index 414c5497c758..bc70cc59defd 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -32,6 +32,11 @@ config NET_TFTP_VARS
If unset, timeout and maximum are hard-defined as 1 second
and 10 timouts per TFTP transfer.
+config NET6
+ bool "IPv6 support"
+ help
+ Support for IPv6
+
config BOOTP_PXE_CLIENTARCH
hex
default 0x16 if ARM64
@@ -44,5 +49,4 @@ config BOOTP_VCI_STRING
default "U-Boot.armv8" if ARM64
default "U-Boot.arm" if ARM
default "U-Boot"
-
endif # if NET
diff --git a/net/Makefile b/net/Makefile
index f03d6083268f..b5e8c5c758c9 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_CMD_PING) += ping.o
obj-$(CONFIG_CMD_RARP) += rarp.o
obj-$(CONFIG_CMD_SNTP) += sntp.o
obj-$(CONFIG_CMD_NET) += tftp.o
+obj-$(CONFIG_NET6) += net6.o
diff --git a/net/net6.c b/net/net6.c
new file mode 100644
index ..f778cef5ada9
--- /dev/null
+++ b/net/net6.c
@@ -0,0 +1,89 @@
+/*
+ * Simple IPv6 network layer implementation.
+ *
+ * Based and/or adapted from the IPv4 network layer in net.[hc]
+ *
+ * (C) Copyright 2013 Allied Telesis Labs NZ
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "ndisc.h"
+
+/* Our gateway's IPv6 address */
+struct in6_addr net_gateway6 = ZERO_IPV6_ADDR;
+/* Our IPv6 addr (0 = unknown) */
+struct in6_addr net_ip6 = ZERO_IPV6_ADDR;
+/* set server IPv6 addr (0 = unknown) */
+struct in6_addr net_server_ip6 = ZERO_IPV6_ADDR;
+/* The prefix length of our network */
+u_int32_t net_prefix_length;
+
+static int on_ip6addr(const char *name, const char *value, enum env_op op,
+ int flags)
+{
+ char *v, *s, *strcopy;
+ int i;
+
+ if (flags & H_PROGRAMMATIC)
+ return 0;
+
+ if (op == env_op_delete) {
+ net_prefix_length = 0;
+ net_copy_ip6(&net_ip6, &net_null_addr_ip6);
+ return 0;
+ }
+
+ strcopy = strdup(value);
+ if (strcopy == NULL)
+ return -1;
+
+ net_prefix_length = 128;
+ i = 0;
+ s = strcopy;
+ while (s) {
+ v = strsep(&s, "/");
+ if (!v)
+ break;
+
+ switch (i++) {
+ case 0:
+ string_to_ip6(v, &net_ip6);
+ break;
+ case 1:
+ net_prefix_length = simple_strtoul(v, NULL, 10);
+ break;
+ default:
+ break;
+ }
+ }
+ free(strcopy);
+
+ return 0;
+}
+U_BOOT_ENV_
[U-Boot] [RFC PATCH v3 07/11] net: Add ping6 command and implementation
Signed-off-by: Chris Packham
---
Changes in v3: None
Changes in v2:
- split ping6 support into it's own patch
cmd/Kconfig | 6
cmd/net.c | 28 +++
include/net.h | 4 +--
net/net6.c| 7
net/ping6.c | 111 ++
5 files changed, 154 insertions(+), 2 deletions(-)
create mode 100644 net/ping6.c
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 91bd3fb0b58e..37126577bc65 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -546,6 +546,12 @@ config CMD_PING
help
Send ICMP ECHO_REQUEST to network host
+config CMD_PING6
+ bool "ping6"
+ depends on CMD_NET6
+ help
+ Send ICMPv6 ECHO_REQUEST to network host
+
config CMD_CDP
bool "cdp"
help
diff --git a/cmd/net.c b/cmd/net.c
index df8b6c9b53f0..7f40f257c03c 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
static int netboot_common(enum proto_t, cmd_tbl_t *, int, char * const []);
@@ -281,6 +282,33 @@ U_BOOT_CMD(
);
#endif
+#ifdef CONFIG_CMD_PING6
+int do_ping6(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc < 2)
+ return -1;
+
+ if (string_to_ip6(argv[1], &net_ping_ip6) != 0)
+ return CMD_RET_USAGE;
+
+ if (net_loop(PING6) < 0) {
+ printf("ping6 failed; host %pI6c is not alive\n",
+ &net_ping_ip6);
+ return 1;
+ }
+
+ printf("host %pI6c is alive\n", &net_ping_ip6);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ ping6, 2, 1, do_ping6,
+ "send ICMPv6 ECHO_REQUEST to network host",
+ "pingAddress"
+);
+#endif /* CONFIG_CMD_PING6 */
+
#if defined(CONFIG_CMD_CDP)
static void cdp_update_env(void)
diff --git a/include/net.h b/include/net.h
index b0348adf955e..be75c6c65c6b 100644
--- a/include/net.h
+++ b/include/net.h
@@ -545,8 +545,8 @@ extern ushort net_native_vlan;/* Our
Native VLAN */
extern int net_restart_wrap; /* Tried all network devices */
enum proto_t {
- BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
- TFTPSRV, TFTPPUT, LINKLOCAL
+ BOOTP, RARP, ARP, TFTPGET, DHCP, PING, PING6, DNS, NFS, CDP, NETCONS,
+ SNTP, TFTPSRV, TFTPPUT, LINKLOCAL
};
extern charnet_boot_file_name[1024];/* Boot File name */
diff --git a/net/net6.c b/net/net6.c
index 955a08987be9..8f0c7214f8e1 100644
--- a/net/net6.c
+++ b/net/net6.c
@@ -370,6 +370,13 @@ void net_ip6_handler(struct ethernet_hdr *et, struct
ip6_hdr *ip6, int len)
return;
switch (icmp->icmp6_type) {
+#ifdef CONFIG_CMD_PING6
+ case IPV6_ICMP_ECHO_REQUEST:
+ case IPV6_ICMP_ECHO_REPLY:
+ ping6_receive(et, ip6, len);
+ break;
+#endif /* CONFIG_CMD_PING6 */
+
case IPV6_NDISC_NEIGHBOUR_SOLICITATION:
case IPV6_NDISC_NEIGHBOUR_ADVERTISEMENT:
ndisc_receive(et, ip6, len);
diff --git a/net/ping6.c b/net/ping6.c
new file mode 100644
index ..34796c6a288c
--- /dev/null
+++ b/net/ping6.c
@@ -0,0 +1,111 @@
+/*
+ * net/ping6.c
+ *
+ * (C) Copyright 2013 Allied Telesis Labs NZ
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#define DEBUG
+#include
+#include
+#include
+#include "ndisc.h"
+
+static ushort seq_no;
+
+/* the ipv6 address to ping */
+struct in6_addr net_ping_ip6;
+
+int
+ip6_make_ping(uchar *eth_dst_addr, struct in6_addr *neigh_addr, uchar *pkt)
+{
+ struct echo_msg *msg;
+ __u16 len;
+ uchar *pkt_old = pkt;
+
+ len = sizeof(struct echo_msg);
+
+ pkt += net_set_ether(pkt, eth_dst_addr, PROT_IP6);
+ pkt += ip6_add_hdr(pkt, &net_ip6, neigh_addr, IPPROTO_ICMPV6,
+ IPV6_NDISC_HOPLIMIT, len);
+
+ /* ICMPv6 - Echo */
+ msg = (struct echo_msg *)pkt;
+ msg->icmph.icmp6_type = IPV6_ICMP_ECHO_REQUEST;
+ msg->icmph.icmp6_code = 0;
+ msg->icmph.icmp6_cksum = 0;
+ msg->icmph.icmp6_identifier = 0;
+ msg->icmph.icmp6_sequence = htons(seq_no++);
+ msg->id = msg->icmph.icmp6_identifier; /* these seem redundant */
+ msg->sequence = msg->icmph.icmp6_sequence;
+
+ /* checksum */
+ msg->icmph.icmp6_cksum = csum_ipv6_magic(&net_ip6, neigh_addr, len,
+IPPROTO_ICMPV6,
+csum_partial((__u8 *)msg, len,
0));
+
+ pkt += len;
+
+ return pkt - pkt_old;
+}
+
+int ping6_send(void)
+{
+ uchar *pkt;
+ static uchar mac[6];
+
+ /* always send neighbor solicit */
+
+ memcpy(mac, net_null_ethaddr, 6);
+
+ net_nd_sol_packet_ip6 =
[U-Boot] [RFC PATCH v3 06/11] net: IPv6 support
Adds basic support for IPv6. Neighbor discovery and ping6 are the only
things supported at the moment.
Helped-by: Hanna Hawa [endian & alignment fixes]
Signed-off-by: Chris Packham
---
Now we have something functional. With this and the next patch you can
do something like 'setenv ipaddr6 3ffe::1/64' and 'ping6 3ffe::2' should
work.
I seem to have a problem that when you send a ping6 for a non-existent
address that ends up stuck and the next non-ipv6 net operation tries to
resolve it. I suspect this is because the pending neighbor discovery
information isn't cleaned up properly, I need to look into that.
Changes in v3: None
Changes in v2:
- split ping6 support into separate patch
- split environment variables into separate patch
- change ip6_ndisc_* to ndisc_*, fix CamelCase
include/net.h | 1 +
include/net6.h | 194 +
net/Makefile | 2 +
net/ndisc.c| 266 ++
net/ndisc.h| 25 +
net/net.c | 37 ++-
net/net6.c | 299 +
7 files changed, 823 insertions(+), 1 deletion(-)
create mode 100644 net/ndisc.c
create mode 100644 net/ndisc.h
diff --git a/include/net.h b/include/net.h
index 10d98d92535b..b0348adf955e 100644
--- a/include/net.h
+++ b/include/net.h
@@ -341,6 +341,7 @@ struct vlan_ethernet_hdr {
#define VLAN_ETHER_HDR_SIZE(sizeof(struct vlan_ethernet_hdr))
#define PROT_IP0x0800 /* IP protocol
*/
+#define PROT_IP60x86DD /* IPv6 protocol */
#define PROT_ARP 0x0806 /* IP ARP protocol */
#define PROT_RARP 0x8035 /* IP ARP protocol */
#define PROT_VLAN 0x8100 /* IEEE 802.1q protocol */
diff --git a/include/net6.h b/include/net6.h
index a41eb876fc53..ff97c39a6925 100644
--- a/include/net6.h
+++ b/include/net6.h
@@ -22,6 +22,16 @@ struct in6_addr {
#define s6_addr32 in6_u.u6_addr32
};
+#define IN6ADDRSZ sizeof(struct in6_addr)
+#define INETHADDRSZsizeof(net_ethaddr)
+
+#define IPV6_ADDRSCOPE_INTF0x01
+#define IPV6_ADDRSCOPE_LINK0x02
+#define IPV6_ADDRSCOPE_AMDIN 0x04
+#define IPV6_ADDRSCOPE_SITE0x05
+#define IPV6_ADDRSCOPE_ORG 0x08
+#define IPV6_ADDRSCOPE_GLOBAL 0x0E
+
/**
* struct ipv6hdr - Internet Protocol V6 (IPv6) header.
*
@@ -45,6 +55,145 @@ struct ip6_hdr {
struct in6_addr daddr;
};
+#define IP6_HDR_SIZE (sizeof(struct ip6_hdr))
+
+/* Handy for static initialisations of struct in6_addr, atlhough the
+ * c99 '= { 0 }' idiom might work depending on you compiler. */
+#define ZERO_IPV6_ADDR { { { 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00 } } }
+
+#define IPV6_LINK_LOCAL_PREFIX 0xfe80
+
+enum {
+ __ND_OPT_PREFIX_INFO_END= 0,
+ ND_OPT_SOURCE_LL_ADDR = 1,
+ ND_OPT_TARGET_LL_ADDR = 2,
+ ND_OPT_PREFIX_INFO = 3,
+ ND_OPT_REDIRECT_HDR = 4,
+ ND_OPT_MTU = 5,
+ __ND_OPT_MAX
+};
+
+/* ICMPv6 */
+#define IPPROTO_ICMPV6 58
+/* hop limit for neighbour discovery packets */
+#define IPV6_NDISC_HOPLIMIT 255
+#define NDISC_TIMEOUT 5000UL
+#define NDISC_TIMEOUT_COUNT 3
+
+struct icmp6hdr {
+ __u8icmp6_type;
+#define IPV6_ICMP_ECHO_REQUEST 128
+#define IPV6_ICMP_ECHO_REPLY 129
+#define IPV6_NDISC_ROUTER_SOLICITATION 133
+#define IPV6_NDISC_ROUTER_ADVERTISEMENT134
+#define IPV6_NDISC_NEIGHBOUR_SOLICITATION 135
+#define IPV6_NDISC_NEIGHBOUR_ADVERTISEMENT 136
+#define IPV6_NDISC_REDIRECT137
+ __u8icmp6_code;
+ __be16 icmp6_cksum;
+
+ union {
+ __be32 un_data32[1];
+ __be16 un_data16[2];
+ __u8un_data8[4];
+
+ struct icmpv6_echo {
+ __be16 identifier;
+ __be16 sequence;
+ } u_echo;
+
+ struct icmpv6_nd_advt {
+#if defined(__LITTLE_ENDIAN_BITFIELD)
+ __be32 reserved:5,
+ override:1,
+ solicited:1,
+ router:1,
+ reserved2:24;
+#elif defined(__BIG_ENDIAN_BITFIELD)
+ __be32 router:1,
+ solicited:1,
+ override:1,
+ reserved:29;
+#else
+#error "Please fix "
+#endif
+ }
[U-Boot] [RFC PATCH v3 11/11] net: tsec: enable promiscuous mode
IPv6 neighbor discovery uses various multicast addresses to send the request and receive the response. For neighbor discovery to work properly in U-boot the Ethernet device needs to support joining/leaving various multicast groups or it needs to support multicast/promiscuous mode. For the sake of simplicity the latter approach has been taken. Signed-off-by: Chris Packham Signed-off-by: Chris Packham --- Drivers that support multicast reception have it enabled/disabled with CONFIG_MCAST_TFTP. It wouldn't be too hard to create a separate CONFIG_MCAST that is selected by enabling CONFIG_MCAST_TFTP or CONFIG_NET6 but for now I want to concentrate on getting the rest of the IPv6 code in good shape. Changes in v3: None Changes in v2: None drivers/net/tsec.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 7df4c63acfd7..d97bafec1eb2 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -515,6 +515,10 @@ static void startup_tsec(struct tsec_private *priv) if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) redundant_init(priv); #endif +#ifdef CONFIG_NET6 + /* Enable promiscuous mode */ + setbits_be32(®s->rctrl, 0x8); +#endif /* Enable Transmit and Receive */ setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); -- 2.11.0.24.ge6920cf ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v3 10/11] net: e1000 enable multicast reception
IPv6 neighbor discovery uses various multicast addresses to send the request and receive the response. For neighbor discovery to work properly in U-boot the Ethernet device needs to support joining/leaving various L2 multicast groups or it needs to support multicast/promiscuous mode. For the sake of simplicity the latter approach has been taken. The e1000 hardware has slightly finer grained control in that it is possible to enable support for multicast-promiscuous mode separately from unicast so the extra traffic received is less. Signed-off-by: Chris Packham --- Drivers that support multicast reception have it enabled/disabled with CONFIG_MCAST_TFTP. It wouldn't be too hard to create a separate CONFIG_MCAST that is selected by enabling CONFIG_MCAST_TFTP or CONFIG_NET6. Changes in v3: None Changes in v2: None drivers/net/e1000.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 875682b1b89e..4c26cb4ce68f 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -5067,6 +5067,11 @@ e1000_setup_rctl(struct e1000_hw *hw) rctl &= ~(E1000_RCTL_SZ_4096); rctl |= E1000_RCTL_SZ_2048; rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); + +#ifdef CONFIG_NET6 + rctl |= E1000_RCTL_MPE; +#endif + E1000_WRITE_REG(hw, RCTL, rctl); } -- 2.11.0.24.ge6920cf ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v3 08/11] net: TFTP over IPv6
Add support for UDP/TFTP over IPv6. To support specifying an server IPv6
address in the command square brackets must be used to separate the
address from the filename. e.g
tftpboot6 [2001:db8::1]:zImage
Signed-off-by: Chris Packham
---
Changes in v3: None
Changes in v2:
- Support parsing the server address from the command parameter.
cmd/Kconfig| 9 +
cmd/net.c | 13
include/net.h | 2 +-
include/net6.h | 4
net/net.c | 3 +++
net/net6.c | 64 ++
net/tftp.c | 58
7 files changed, 152 insertions(+), 1 deletion(-)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 37126577bc65..473d354fcb85 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -504,6 +504,15 @@ config CMD_NET
bootp - boot image via network using BOOTP/TFTP protocol
tftpboot - boot image via network using TFTP protocol
+config CMD_NET6
+ bool "ipv6 commands"
+ select NET
+ select NET6
+ default n
+ help
+ IPv6 network commands
+ tftpboot6 - boot image via network using TFTP protocol
+
config CMD_TFTPPUT
bool "tftp put"
help
diff --git a/cmd/net.c b/cmd/net.c
index 7f40f257c03c..e2c295eabb17 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -42,6 +42,19 @@ U_BOOT_CMD(
"[loadAddress] [[hostIPaddr:]bootfilename]"
);
+#ifdef CONFIG_CMD_NET6
+int do_tftpb6(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ return netboot_common(TFTP6, cmdtp, argc, argv);
+}
+
+U_BOOT_CMD(
+ tftpboot6, 3, 1, do_tftpb6,
+ "boot image via network using TFTP protocol",
+ "[loadAddress] [[hostIP6Addr]:][bootfilename]"
+);
+#endif
+
#ifdef CONFIG_CMD_TFTPPUT
int do_tftpput(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
diff --git a/include/net.h b/include/net.h
index be75c6c65c6b..6c968711c37f 100644
--- a/include/net.h
+++ b/include/net.h
@@ -546,7 +546,7 @@ extern int net_restart_wrap; /* Tried all
network devices */
enum proto_t {
BOOTP, RARP, ARP, TFTPGET, DHCP, PING, PING6, DNS, NFS, CDP, NETCONS,
- SNTP, TFTPSRV, TFTPPUT, LINKLOCAL
+ SNTP, TFTPSRV, TFTPPUT, TFTP6, LINKLOCAL
};
extern charnet_boot_file_name[1024];/* Boot File name */
diff --git a/include/net6.h b/include/net6.h
index ff97c39a6925..7ae177738e86 100644
--- a/include/net6.h
+++ b/include/net6.h
@@ -246,6 +246,10 @@ void ping6_start(void);
void ping6_receive(struct ethernet_hdr *et, struct ip6_hdr *ip6,
int len);
+/* Transmit UDP packet using IPv6, performing neighbour discovery if needed */
+int net_send_udp_packet6(uchar *ether, struct in6_addr *dest,
+ int dport, int sport, int len);
+
/* handler for incoming IPv6 echo packet */
void net_ip6_handler(struct ethernet_hdr *et, struct ip6_hdr *ip6,
int len);
diff --git a/net/net.c b/net/net.c
index 527c99f96f9f..567550ef09b6 100644
--- a/net/net.c
+++ b/net/net.c
@@ -454,6 +454,9 @@ restart:
#ifdef CONFIG_CMD_TFTPPUT
case TFTPPUT:
#endif
+#ifdef CONFIG_CMD_NET6
+ case TFTP6:
+#endif
/* always use ARP to get server ethernet address */
tftp_start(protocol);
break;
diff --git a/net/net6.c b/net/net6.c
index 8f0c7214f8e1..5b8a003f1c4a 100644
--- a/net/net6.c
+++ b/net/net6.c
@@ -342,6 +342,50 @@ ip6_add_hdr(uchar *xip, struct in6_addr *src, struct
in6_addr *dest,
return sizeof(struct ip6_hdr);
}
+int
+net_send_udp_packet6(uchar *ether, struct in6_addr *dest, int dport, int
sport, int len)
+{
+ uchar *pkt;
+ struct udp_hdr *udp;
+
+ udp = (struct udp_hdr *)((uchar *)net_tx_packet + net_eth_hdr_size() +
IP6_HDR_SIZE);
+
+ udp->udp_dst = htons(dport);
+ udp->udp_src = htons(sport);
+ udp->udp_len = htons(len + UDP_HDR_SIZE);
+ /* checksum */
+ udp->udp_xsum = 0;
+ udp->udp_xsum = csum_ipv6_magic(&net_ip6, dest, len + UDP_HDR_SIZE,
+ IPPROTO_UDP, csum_partial((__u8 *)udp, len + UDP_HDR_SIZE, 0));
+
+ /* if MAC address was not discovered yet, save the packet and do
neighbour discovery */
+ if (memcmp(ether, net_null_ethaddr, 6) == 0) {
+ net_copy_ip6(&net_nd_sol_packet_ip6, dest);
+ net_nd_packet_mac = ether;
+
+ pkt = net_nd_tx_packet;
+ pkt += net_set_ether(pkt, net_nd_packet_mac, PROT_IP6);
+ pkt += ip6_add_hdr(pkt, &net_ip6, dest, IPPROTO_UDP, 64, len +
UDP_HDR_SIZE);
+ memcpy(pkt, (uchar *)udp, len + UDP_HDR_SIZE);
+
+ /* size of the waiting packet */
+ net_nd_tx_packet_size = (pkt - net_nd_tx_packet) + UDP_HDR_SIZE
+ len;
+
+
[U-Boot] [RFC PATCH v3 09/11] net: IPv6 documentation
Signed-off-by: Chris Packham --- Changes in v3: - Add brief testing section Changes in v2: None README | 3 +++ doc/README.ipv6 | 55 +++ 2 files changed, 58 insertions(+) create mode 100644 doc/README.ipv6 diff --git a/README b/README index a95348a876b4..4ab4a0e74f32 100644 --- a/README +++ b/README @@ -922,6 +922,7 @@ The following options need to be configured: CONFIG_CMD_MTDPARTS * MTD partition support CONFIG_CMD_NAND * NAND support CONFIG_CMD_NETbootp, tftpboot, rarpboot + CONFIG_CMD_NET6 * tftpboot6 CONFIG_CMD_NFSNFS support CONFIG_CMD_PCA953X * PCA953x I2C gpio commands CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command @@ -929,6 +930,8 @@ The following options need to be configured: CONFIG_CMD_PCMCIA * PCMCIA support CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network host + CONFIG_CMD_PING6* send ICMPv6 ECHO_REQUEST to network + host CONFIG_CMD_PORTIO * Port I/O CONFIG_CMD_READ * Read raw data from partition CONFIG_CMD_REGINFO * Register dump diff --git a/doc/README.ipv6 b/doc/README.ipv6 new file mode 100644 index ..b7c2bc417645 --- /dev/null +++ b/doc/README.ipv6 @@ -0,0 +1,55 @@ +IPv6 Support in U-boot +-- +IPv6 support in U-boot can be considered experimental. The commands +currently supported are tftpboot6 and ping6. + +The following environment variables are used +- ip6addr - IPv6 address of the device +- gatewayip6 - IPv6 address of the default gateway +- serverip6 - IPv6 of the tftp server + +Configuration +- +The following configuration option needs to be selected to support IPv6. +- CONFIG_CMD_NET6 +Optionally the following can also be selected to enable the ping6 +command. +- CONFIG_CMD_PING6 + +TFTP Server Configuration +- +At the time of writing U-boot has been tested against tftp-hpa +(https://www.kernel.org/pub/software/network/tftp/) the default Debian +package sets TFTP_ADDRESS=0.0.0.0:69 (in /etc/default/tftpd-hpa) to +support both IPv4 and IPv6 this need to be changed to ':69'. + +Ethernet Driver Requirements + +For IPv6 to operate correctly the Ethernet device needs to support +transmission and reception of L2 multicast packets. Transmission is +usually not a problem. To receive multicast packets the driver needs to +enable promiscuous mode (some devices have the option of just enabling +promiscuous multicast reception). + +Testing using QEMU +-- +Refer to README.x86 for instructions on building u-boot for QEMU. Add +the relevant IPv6 configuration to the configuration (CONFIG_CMD_NET6, +CONFIG_CMD_PING6) and build. + +On the host system run + + sudo qemu-system-i386 -nographic -bios u-boot.rom -net nic -net tap + +At the u-boot command line run + + setenv ipaddr 192.168.1.100 + setenv ip6addr 3ffe::100/64 + +On the host system run + + sudo ip addr add 3ffe::1/64 dev tap0 + sudo ip addr add 192.168.1.1 + +It should now be possible to use ping6 and tftpboot6 to communicate with +the host system from the emulated u-boot environment. -- 2.11.0.24.ge6920cf ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v3 00/11] IPv6 support
This series adds basic IPv6 support to U-boot. It is a reboot of my earlier work on this[1]. This latest version is itself a reboot of work that was last posted to the list in late 2015. Right now I've just rebased against master so functionally it is little different to what was last posted. Most of this is ported from Allied Telesis' additions to u-boot[2]. (Note that I am employed by Allied Telesis[3]). The hard work was done some time ago by Angga, I've cleaned it up and made some improvements with the hope of getting it accepted upstream. A few open issues 1) rxhand_f currently takes an struct in_addr. TFTP doesn't use this (I haven't looked at other users). To support V6 this may need to be a new union, a void * with some kind of flag or nothing if no rxhandler actually cares. It has been suggested that this parameter be removed and any users that care can re-parse the packet. 2) Unit tests. This code needs them. The testing so-far has been ad-hoc manual testing using qemu-x86. 3) Fancy v6 feature xyz. There are a lot of things that _could_ be implemented on top of this (DHCPV6 and SLAAC are two obvious things that stick out). For now I want to concentrate on getting the core code stable and accepted, if anyone else wants to work on either of those features that'd be great. -- [1] - http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/151390 [2] - http://www.alliedtelesis.co.nz/support/gpl/other.html [3] - some of this has been done on work time, other parts have been done in my personal time. Since I'm subscribed to the list using my gmail account I've signed using that. Changes in v3: - Add brief testing section Changes in v2: - Split environment variables from main implementation - remove "prefixlength6" environment variable. The prefix length is now set when specifying the address i.e. setenv ip6addr 2001:db8::1/64. - split ping6 support into separate patch - split environment variables into separate patch - change ip6_ndisc_* to ndisc_*, fix CamelCase - split ping6 support into it's own patch - Support parsing the server address from the command parameter. Chris Packham (11): Initial net6.h lib: vsprintf: add IPv6 compressed format %pI6c lib: net_utils: add string_to_ip6 net: add definition of udp_hdr net: IPv6 skeleton and environment variables net: IPv6 support net: Add ping6 command and implementation net: TFTP over IPv6 net: IPv6 documentation net: e1000 enable multicast reception net: tsec: enable promiscuous mode README | 3 + cmd/Kconfig| 15 ++ cmd/net.c | 41 + doc/README.ipv6| 55 ++ drivers/net/e1000.c| 5 + drivers/net/tsec.c | 4 + include/env_callback.h | 8 + include/env_flags.h| 9 + include/net.h | 18 +- include/net6.h | 262 lib/net_utils.c| 121 + lib/vsprintf.c | 154 ++--- net/Kconfig| 6 +- net/Makefile | 3 + net/ndisc.c| 266 net/ndisc.h| 25 +++ net/net.c | 40 - net/net6.c | 459 + net/ping6.c| 111 net/tftp.c | 58 +++ 20 files changed, 1635 insertions(+), 28 deletions(-) create mode 100644 doc/README.ipv6 create mode 100644 include/net6.h create mode 100644 net/ndisc.c create mode 100644 net/ndisc.h create mode 100644 net/net6.c create mode 100644 net/ping6.c -- 2.11.0.24.ge6920cf ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH v3 09/11] net: IPv6 documentation
On 29/01/2017 8:51 AM, "Tom Rini" wrote: On Wed, Jan 25, 2017 at 10:56:20PM +1300, Chris Packham wrote: > Signed-off-by: Chris Packham > --- > > Changes in v3: > - Add brief testing section [snip] > +Testing using QEMU > +-- > +Refer to README.x86 for instructions on building u-boot for QEMU. Add > +the relevant IPv6 configuration to the configuration (CONFIG_CMD_NET6, > +CONFIG_CMD_PING6) and build. > + > +On the host system run > + > + sudo qemu-system-i386 -nographic -bios u-boot.rom -net nic -net tap > + > +At the u-boot command line run > + > + setenv ipaddr 192.168.1.100 > + setenv ip6addr 3ffe::100/64 > + > +On the host system run > + > + sudo ip addr add 3ffe::1/64 dev tap0 > + sudo ip addr add 192.168.1.1 > + > +It should now be possible to use ping6 and tftpboot6 to communicate with > +the host system from the emulated u-boot environment. So we can test this under qemu? Cool! Yup. Thats been really helpful. That means we should get some test.py tests written to match up with the ipv4 tests we have today. My gut reaction is that qemu-ppce500 should also be able to work too as it's also using the E1000 driver. Yeah my initial plan was to add to/copy from the existing ipv4 tests. There may be a little issue with the default Debian config for tftp-hpa but I assume travis-ci has some way to tweak that. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] patman: Handle non-ascii characters in names
When gathering addresses for the Cc list patman would encounter a
UnicodeDecodeError due to non-ascii characters in the author name.
Address this by explicitly using utf-8 when building the Cc list.
Signed-off-by: Chris Packham
---
On Tue, Feb 7, 2017 at 4:32 AM, Simon Glass wrote:
> Hi Chris,
>
>
> This seems reasonable - can you send this as a patch please?
>
> Regards,
> Simon
Here you go. I've only been able to test with python 2.7 but I think it
should be fine for python 3.x also.
tools/patman/series.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/patman/series.py b/tools/patman/series.py
index 38a452edad41..c1b86521aa45 100644
--- a/tools/patman/series.py
+++ b/tools/patman/series.py
@@ -235,7 +235,8 @@ class Series(dict):
if cover_fname:
cover_cc = gitutil.BuildEmailList(self.get('cover_cc', ''))
-print(cover_fname, ', '.join(set(cover_cc + all_ccs)), file=fd)
+cc_list = ', '.join([x.decode('utf-8') for x in set(cover_cc +
all_ccs)])
+print(cover_fname, cc_list.encode('utf-8'), file=fd)
fd.close()
return fname
--
2.11.0.24.ge6920cf
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[U-Boot] [PATCH v2 2/3] arm: mvebu: add DB-88F6820-AMC board
This board is a plug in card for Marvell's switch system development
kits. Form-factor aside it is similar to the DB-88F6820-GP with the
following differences.
- TCLK is 200MHz
- SPI1 is used
- No SATA
- No MMC
- NAND flash
Reviewed-by: Simon Glass
Signed-off-by: Chris Packham
---
I've used my work email address for the MAINTAINERS entry. Mainly
because it gives a better chance at finding someone else to contact
rather than a random gmail address.
I've also left the copyright assignments to Stefan and Gregory since the
code was derived from the -GP board.
Changes in v2:
- move CONFIG_SPL_xxx_SUPPORT to defconfig
- collect review from Simon
arch/arm/dts/Makefile | 1 +
arch/arm/dts/armada-385-amc.dts | 155 ++
arch/arm/mach-mvebu/Kconfig | 7 ++
board/Marvell/db-88f6820-amc/MAINTAINERS | 6 +
board/Marvell/db-88f6820-amc/Makefile | 7 ++
board/Marvell/db-88f6820-amc/db-88f6820-amc.c | 129 +
board/Marvell/db-88f6820-amc/kwbimage.cfg | 12 ++
configs/db-88f6820-amc_defconfig | 43 +++
include/configs/db-88f6820-amc.h | 123
9 files changed, 483 insertions(+)
create mode 100644 arch/arm/dts/armada-385-amc.dts
create mode 100644 board/Marvell/db-88f6820-amc/MAINTAINERS
create mode 100644 board/Marvell/db-88f6820-amc/Makefile
create mode 100644 board/Marvell/db-88f6820-amc/db-88f6820-amc.c
create mode 100644 board/Marvell/db-88f6820-amc/kwbimage.cfg
create mode 100644 configs/db-88f6820-amc_defconfig
create mode 100644 include/configs/db-88f6820-amc.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1d41d485558d..df572880767f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-375-db.dtb \
armada-388-clearfog.dtb \
armada-388-gp.dtb \
+ armada-385-amc.dtb \
armada-xp-gp.dtb\
armada-xp-maxbcm.dtb\
armada-xp-synology-ds414.dtb\
diff --git a/arch/arm/dts/armada-385-amc.dts b/arch/arm/dts/armada-385-amc.dts
new file mode 100644
index ..858138a3376b
--- /dev/null
+++ b/arch/arm/dts/armada-385-amc.dts
@@ -0,0 +1,155 @@
+/*
+ * Device Tree file for Marvell Armada 385 development board
+ * (DB-88F6820-AMC)
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-385.dtsi"
+#include
+
+/ {
+ model = "Marvell Armada 385 AMC";
+ compatible = "marvell,a385-amc", "marvell,armada385",
"marvell,armada380";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ ethernet0 = ð0;
+ ethernet1 = ð1;
+ spi1 = &spi1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x 0x8000>; /* 2 GB */
+ };
+
+ soc {
+ ranges = ;
+
+ internal-regs {
+ i
[U-Boot] [PATCH v2 1/3] arm: mvebu: create generic 88F6820 config option
88F6820 is a specific Armada-38x chip that is used on the DB-88F6820-GP
board. Rather than having DB_88F6820_GP and TARGET_DB_88F6820_GP which
selects the former. Rename DB_88F6820_GP to 88F6820 so that other boards
using the 88F6820 can be added.
Signed-off-by: Chris Packham
---
Changes in v2: None
arch/arm/mach-mvebu/Kconfig | 4 ++--
arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 220886aa592a..06820a5e4f2c 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -21,7 +21,7 @@ config MV78460
bool
select ARMADA_XP
-config DB_88F6820_GP
+config 88F6820
bool
select ARMADA_38X
@@ -39,7 +39,7 @@ config TARGET_DB_88F6720
config TARGET_DB_88F6820_GP
bool "Support DB-88F6820-GP"
- select DB_88F6820_GP
+ select 88F6820
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
index 49d704a36230..cc3e5e23c0dd 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
@@ -45,7 +45,7 @@ u32 g_dev_id = -1;
u32 mv_board_id_get(void)
{
-#if defined(CONFIG_DB_88F6820_GP)
+#if defined(CONFIG_TARGET_DB_88F6820_GP)
return DB_GP_68XX_ID;
#else
/*
--
2.9.2.518.ged577c6.dirty
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[U-Boot] [PATCH v2 3/3] arm: mvebu: NAND support for DB-88F6820-AMC
Enable the NAND interface on this board.
Signed-off-by: Chris Packham
---
Changes in v2: None
arch/arm/dts/armada-385-amc.dts | 8
configs/db-88f6820-amc_defconfig | 2 ++
include/configs/db-88f6820-amc.h | 4
3 files changed, 14 insertions(+)
diff --git a/arch/arm/dts/armada-385-amc.dts b/arch/arm/dts/armada-385-amc.dts
index 858138a3376b..a5a8a7f186db 100644
--- a/arch/arm/dts/armada-385-amc.dts
+++ b/arch/arm/dts/armada-385-amc.dts
@@ -120,6 +120,14 @@
reg = <0>;
};
};
+
+ flash@d {
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ };
};
pcie-controller {
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
index 5784c4566769..18fcf0eb1438 100644
--- a/configs/db-88f6820-amc_defconfig
+++ b/configs/db-88f6820-amc_defconfig
@@ -12,6 +12,7 @@ CONFIG_BOOTDELAY=3
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
@@ -28,6 +29,7 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h
index 042ded832047..a6d022191eec 100644
--- a/include/configs/db-88f6820-amc.h
+++ b/include/configs/db-88f6820-amc.h
@@ -68,6 +68,10 @@
#define CONFIG_PCI_SCAN_SHOW
#endif
+/* NAND */
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
--
2.9.2.518.ged577c6.dirty
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[U-Boot] [RFC PATCH v1] common/console.c: ensure GD_FLG_SILENT is set or cleared
When CONFIG_SILENT_CONSOLE is defined and the default environment has
silent=1 it is not possible for a user to make the console un-silent if
the environment is not available when console_init_f() is called (for
example because the environment is in SPI).
Add a new helper function console_update_silent() and call it from both
console_init_f() and console_init_r().
Signed-off-by: Chris Packham
---
common/console.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/common/console.c b/common/console.c
index 12293f383624..c7f32434310e 100644
--- a/common/console.c
+++ b/common/console.c
@@ -687,15 +687,22 @@ int console_assign(int file, const char *devname)
return -1;
}
-/* Called before relocation - use serial functions */
-int console_init_f(void)
+static void console_update_silent(void)
{
- gd->have_console = 1;
-
#ifdef CONFIG_SILENT_CONSOLE
if (getenv("silent") != NULL)
gd->flags |= GD_FLG_SILENT;
+ else
+ gd->flags &= ~GD_FLG_SILENT;
#endif
+}
+
+/* Called before relocation - use serial functions */
+int console_init_f(void)
+{
+ gd->have_console = 1;
+
+ console_update_silent();
print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT1_SERIAL);
@@ -831,6 +838,8 @@ int console_init_r(void)
struct list_head *pos;
struct stdio_dev *dev;
+ console_update_silent();
+
#ifdef CONFIG_SPLASH_SCREEN
/*
* suppress all output if splash screen is enabled and we have
--
2.9.2.518.ged577c6.dirty
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Re: [U-Boot] [PATCH v2 1/3] arm: mvebu: create generic 88F6820 config option
Hi Stefan,
On Sat, Sep 24, 2016 at 8:09 PM, Stefan Roese wrote:
> On 22.09.2016 02:56, Chris Packham wrote:
>>
>> 88F6820 is a specific Armada-38x chip that is used on the DB-88F6820-GP
>> board. Rather than having DB_88F6820_GP and TARGET_DB_88F6820_GP which
>> selects the former. Rename DB_88F6820_GP to 88F6820 so that other boards
>> using the 88F6820 can be added.
>>
>> Signed-off-by: Chris Packham
>> ---
>>
>> Changes in v2: None
>
>
> Changed for clearfog here as well while applying.
>
I didn't notice clearfog when I was looking. One potential side-effect
of my change for the clearfog board is that mv_board_id_get() will now
return 0 instead of DB_68XX_ID (0x11). I'm not sure what the
consequences of this are. The AMC board works fine with 0 and
DB_68XX_ID is probably wrong for a board that is not the
db-88f6820-gp. On the other hand the AMC board isn't using a number of
peripherals so I may not have noticed a breakage.
If this does turn out to be a problem the following should be
equivalent to the way things were before (sorry can't send a proper
patch having remote access issues).
--- 8< ---
diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
index 49d704a..cc3e5e2 100644 (file)
--- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
@@ -45,7 +45,7 @@ u32 g_dev_id = -1;
u32 mv_board_id_get(void)
{
-#if defined(CONFIG_TARGET_DB_88F6820_GP)
+#if defined(CONFIG_88F6820)
return DB_GP_68XX_ID;
#else
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[U-Boot] [PATCH] spi: kirkwood_spi: implement mvebu_spi_set_mode()
Set the appropriate bits in the interface config register based
on the SPI_ mode flags.
Signed-off-by: Chris Packham
---
arch/arm/include/asm/arch-mvebu/spi.h | 4
drivers/spi/kirkwood_spi.c| 13 +
2 files changed, 17 insertions(+)
diff --git a/arch/arm/include/asm/arch-mvebu/spi.h
b/arch/arm/include/asm/arch-mvebu/spi.h
index 78869a253d1f..3545aed17347 100644
--- a/arch/arm/include/asm/arch-mvebu/spi.h
+++ b/arch/arm/include/asm/arch-mvebu/spi.h
@@ -52,6 +52,10 @@ struct kwspi_registers {
#define KWSPI_ADRLEN_3BYTE (2 << 8)
#define KWSPI_ADRLEN_4BYTE (3 << 8)
#define KWSPI_ADRLEN_MASK (3 << 8)
+#define KWSPI_CPOL (1 << 11)
+#define KWSPI_CPHA (1 << 12)
+#define KWSPI_TXLSBF (1 << 13)
+#define KWSPI_RXLSBF (1 << 14)
#define KWSPI_IRQUNMASK1 /* unmask SPI interrupt */
#define KWSPI_IRQMASK 0 /* mask SPI interrupt */
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index 6851ba942f51..69a0be9ea5b2 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -271,6 +271,19 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint
hz)
static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct kwspi_registers *reg = plat->spireg;
+ u32 data = readl(®->cfg);
+
+ if (mode & SPI_CPHA)
+ data |= KWSPI_CPHA;
+ if (mode & SPI_CPOL)
+ data |= KWSPI_CPOL;
+ if (mode & SPI_LSB_FIRST)
+ data |= (KWSPI_RXLSBF | KWSPI_TXLSBF);
+
+ writel(data, ®->cfg);
+
return 0;
}
--
2.10.0.479.g7c56b16
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[U-Boot] [RFC PATCH 0/1] 4-byte SPI flash addressing
I'm working on a board that uses a MX25L25735E spi-nor flash chip from Macronix. This is a 32MB chip that uses 4-bytes for addressing. Annoyingly this chip identifies the same as a MX25L25635F the only difference appears to be the size reported (I don't actually have a MX25L25635F so that statement is an educated guess based on the datasheets). What follows is a patch that gets the flash going on the board I'm working on. But I am wondering if instead of a config option I should follow more closely what Linux does and add and addr_width to struct spi_flash which gets set based on the size detected. Chris Packham (1): sf: support chips using 4-byte addressing drivers/mtd/spi/Kconfig | 7 +++ drivers/mtd/spi/sf_internal.h | 5 + drivers/mtd/spi/spi_flash.c | 7 +++ 3 files changed, 19 insertions(+) -- 2.10.0.479.g7c56b16 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH 1/1] sf: support chips using 4-byte addressing
Signed-off-by: Chris Packham
---
drivers/mtd/spi/Kconfig | 7 +++
drivers/mtd/spi/sf_internal.h | 5 +
drivers/mtd/spi/spi_flash.c | 7 +++
3 files changed, 19 insertions(+)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 1f23c8e34e6f..f5020f799d78 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -42,6 +42,13 @@ config SPI_FLASH_BAR
Bank/Extended address registers are used to access the flash
which has size > 16MiB in 3-byte addressing.
+config SPI_FLASH_4B_ADDR
+ bool "SPI flash use 4-byte addressing"
+ depends on SPI_FLASH
+ help
+ Enable 4-byte addressing for SPI flash. This allows use of SPI flash
+ chips which use 4-byte addressing.
+
if SPI_FLASH
config SPI_FLASH_ATMEL
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index cde4cfbf2e32..fef8d1ecc89e 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -26,7 +26,12 @@ enum spi_nor_option_flags {
};
#define SPI_FLASH_3B_ADDR_LEN 3
+#define SPI_FLASH_4B_ADDR_LEN 4
+#ifdef CONFIG_SPI_FLASH_4B_ADDR
+#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_4B_ADDR_LEN)
+#else
#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
+#endif
#define SPI_FLASH_16MB_BOUN0x100
/* CFI Manufacture ID's */
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 7f6e9ae23ea8..bed3ab4762cf 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -25,9 +25,16 @@ DECLARE_GLOBAL_DATA_PTR;
static void spi_flash_addr(u32 addr, u8 *cmd)
{
/* cmd[0] is actual command */
+#ifdef CONFIG_SPI_FLASH_4B_ADDR
+ cmd[1] = addr >> 24;
+ cmd[2] = addr >> 16;
+ cmd[3] = addr >> 8;
+ cmd[4] = addr;
+#else
cmd[1] = addr >> 16;
cmd[2] = addr >> 8;
cmd[3] = addr >> 0;
+#endif
}
static int read_sr(struct spi_flash *flash, u8 *rs)
--
2.10.0.479.g7c56b16
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[U-Boot] [RFC PATCH v2] sf: support chips using 4-byte addressing
SPI chips with >16MB capacity use 4-byte addressing to allow
accessing beyond 16MB. When the size of the SPI flash exceeds 16MB
switch to using 4 byte addressing.
Signed-off-by: Chris Packham
---
Changes in v2:
- automatically detect when 4 byte addressing is needed. This is similar
to how the linux kernel does the same detection
drivers/mtd/spi/sf_internal.h | 4 ++--
drivers/mtd/spi/spi_flash.c | 32 ++--
include/spi_flash.h | 2 ++
3 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index cde4cfbf2e32..db4532849145 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -25,8 +25,8 @@ enum spi_nor_option_flags {
SNOR_F_USE_FSR = BIT(1),
};
-#define SPI_FLASH_3B_ADDR_LEN 3
-#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
+#define SPI_FLASE_MAX_ADDR_WIDTH 4
+#define SPI_FLASH_CMD_LEN (1 + SPI_FLASE_MAX_ADDR_WIDTH)
#define SPI_FLASH_16MB_BOUN0x100
/* CFI Manufacture ID's */
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 7f6e9ae23ea8..a3efaa129231 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -22,12 +22,19 @@
DECLARE_GLOBAL_DATA_PTR;
-static void spi_flash_addr(u32 addr, u8 *cmd)
+static void spi_flash_addr(u32 addr, u8 *cmd, u8 addr_width)
{
/* cmd[0] is actual command */
- cmd[1] = addr >> 16;
- cmd[2] = addr >> 8;
- cmd[3] = addr >> 0;
+ if (addr_width == 4) {
+ cmd[1] = addr >> 24;
+ cmd[2] = addr >> 16;
+ cmd[3] = addr >> 8;
+ cmd[4] = addr;
+ } else {
+ cmd[1] = addr >> 16;
+ cmd[2] = addr >> 8;
+ cmd[3] = addr >> 0;
+ }
}
static int read_sr(struct spi_flash *flash, u8 *rs)
@@ -357,12 +364,13 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32
offset, size_t len)
if (ret < 0)
return ret;
#endif
- spi_flash_addr(erase_addr, cmd);
+ spi_flash_addr(erase_addr, cmd, flash->addr_width);
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
cmd[2], cmd[3], erase_addr);
- ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
+ ret = spi_flash_write_common(flash, cmd, flash->addr_width + 1,
+NULL, 0);
if (ret < 0) {
debug("SF: erase failed\n");
break;
@@ -415,12 +423,12 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32
offset,
chunk_len = min(chunk_len,
(size_t)spi->max_write_size);
- spi_flash_addr(write_addr, cmd);
+ spi_flash_addr(write_addr, cmd, flash->addr_width);
debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len =
%zu\n",
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
- ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
+ ret = spi_flash_write_common(flash, cmd, flash->addr_width + 1,
buf + actual, chunk_len);
if (ret < 0) {
debug("SF: write failed\n");
@@ -492,7 +500,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
return 0;
}
- cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
+ cmdsz = flash->addr_width + 1 + flash->dummy_byte;
cmd = calloc(1, cmdsz);
if (!cmd) {
debug("SF: Failed to allocate cmd\n");
@@ -520,7 +528,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
else
read_len = remain_len;
- spi_flash_addr(read_addr, cmd);
+ spi_flash_addr(read_addr, cmd, flash->addr_width);
ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
if (ret < 0) {
@@ -1154,6 +1162,10 @@ int spi_flash_scan(struct spi_flash *flash)
if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
flash->size <<= 1;
#endif
+ if (flash->size > SPI_FLASH_16MB_BOUN)
+ flash->addr_width = 4;
+ else
+ flash->addr_width = 3;
#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
/* Compute erase sector and command */
diff --git a/include/spi_flash.h b/include/spi_flash.h
index be2fe3f84cb9..c65bf22aee8b 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -39,6 +39,7 @@ struct spi_slave;
*
[U-Boot] [RFC PATCH v1 0/6] pxa3xx_nand updates
I'm looking into the NAND support for the db-88f6820-amc board. There are a number of changes in the pxa3xx_nand driver in Linux that are relevant (not specifically to this boards but to Armada boards in general). Some of these changes are cleanups and some are actual bug fixes. I'd really appreciate some testing on this. It doesn't make my board magically work but I feel like I'm making forward progress. Where applicable I'll Cc the author of the equivalent Linux patch. Perhaps I should put them in the From: line or not they deserve all the credit, I just want to see these changes in u-boot. Chris Packham (6): mtd: nand: pxa3xx_nand: Increase initial buffer size mtd: nand: pxa3xx_nand: use nand_to_mtd() mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing() mtd: nand: pxa3xx_nand: fix early spurious interrupt mtd: nand: pxa3xx-nand: fix random command timeouts mtd: nand: pxa3xx_nand: add support for partial chunks drivers/mtd/nand/pxa3xx_nand.c | 203 ++--- 1 file changed, 127 insertions(+), 76 deletions(-) -- 2.10.0.479.g7c56b16 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v1 1/6] mtd: nand: pxa3xx_nand: Increase initial buffer size
The initial buffer is used for the initial commands used to detect a flash device (STATUS, READID and PARAM). ONFI param page is 256 bytes, and there are three redundant copies to be read. JEDEC param page is 512 bytes, and there are also three redundant copies to be read. Hence this buffer should be at least 512 x 3. This commits rounds the buffer size to 2048. Cc: Ezequiel Garcia Signed-off-by: Chris Packham --- drivers/mtd/nand/pxa3xx_nand.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index dfe8966b56b6..ea0a6f3778bd 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -26,10 +26,13 @@ /* * Define a buffer size for the initial command that detects the flash device: - * STATUS, READID and PARAM. The largest of these is the PARAM command, - * needing 256 bytes. + * STATUS, READID and PARAM. + * ONFI param page is 256 bytes, and there are three redundant copies + * to be read. JEDEC param page is 512 bytes, and there are also three + * redundant copies to be read. + * Hence this buffer should be at least 512 x 3. Let's pick 2048. */ -#define INIT_BUFFER_SIZE 256 +#define INIT_BUFFER_SIZE 2048 /* registers and bit definitions */ #define NDCR (0x00) /* Control register */ @@ -838,14 +841,14 @@ static int prepare_set_command(struct pxa3xx_nand_info *info, int command, break; case NAND_CMD_PARAM: - info->buf_count = 256; + info->buf_count = INIT_BUFFER_SIZE; info->ndcb0 |= NDCB0_CMD_TYPE(0) | NDCB0_ADDR_CYC(1) | NDCB0_LEN_OVRD | command; info->ndcb1 = (column & 0xFF); - info->ndcb3 = 256; - info->data_size = 256; + info->ndcb3 = INIT_BUFFER_SIZE; + info->data_size = INIT_BUFFER_SIZE; break; case NAND_CMD_READID: @@ -1468,6 +1471,7 @@ KEEP_CONFIG: host->row_addr_cycles = 3; else host->row_addr_cycles = 2; + return nand_scan_tail(mtd); } -- 2.10.0.479.g7c56b16 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v1 2/6] mtd: nand: pxa3xx_nand: use nand_to_mtd()
Don't store struct mtd_info in struct pxa3xx_nand_host. Instead use the
one that is already part of struct nand_chip. This brings us in line
with current U-boot and Linux conventions.
Cc: Boris BREZILLON
Signed-off-by: Chris Packham
---
drivers/mtd/nand/pxa3xx_nand.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index ea0a6f3778bd..a7a488260a71 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -147,7 +147,6 @@ enum pxa3xx_nand_variant {
struct pxa3xx_nand_host {
struct nand_chipchip;
- struct mtd_info *mtd;
void*info_data;
/* page size of attached chip */
@@ -380,16 +379,17 @@ static int pxa3xx_nand_init_timings(struct
pxa3xx_nand_host *host)
struct nand_chip *chip = &host->chip;
struct pxa3xx_nand_info *info = host->info_data;
const struct pxa3xx_nand_flash *f = NULL;
+ struct mtd_info *mtd = nand_to_mtd(&host->chip);
int mode, id, ntypes, i;
mode = onfi_get_async_timing_mode(chip);
if (mode == ONFI_TIMING_MODE_UNKNOWN) {
ntypes = ARRAY_SIZE(builtin_flash_types);
- chip->cmdfunc(host->mtd, NAND_CMD_READID, 0x00, -1);
+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
- id = chip->read_byte(host->mtd);
- id |= chip->read_byte(host->mtd) << 0x8;
+ id = chip->read_byte(mtd);
+ id |= chip->read_byte(mtd) << 0x8;
for (i = 0; i < ntypes; i++) {
f = &builtin_flash_types[i];
@@ -682,7 +682,7 @@ static void set_command_address(struct pxa3xx_nand_info
*info,
static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
{
struct pxa3xx_nand_host *host = info->host[info->cs];
- struct mtd_info *mtd = host->mtd;
+ struct mtd_info *mtd = nand_to_mtd(&host->chip);
/* reset data and oob column point to handle data */
info->buf_start = 0;
@@ -733,7 +733,7 @@ static int prepare_set_command(struct pxa3xx_nand_info
*info, int command,
struct mtd_info *mtd;
host = info->host[info->cs];
- mtd = host->mtd;
+ mtd = nand_to_mtd(&host->chip);
addr_cycle = 0;
exec_cmd = 1;
@@ -1220,7 +1220,7 @@ static int pxa3xx_nand_waitfunc(struct mtd_info *mtd,
struct nand_chip *this)
static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
{
struct pxa3xx_nand_host *host = info->host[info->cs];
- struct mtd_info *mtd = host->mtd;
+ struct mtd_info *mtd = nand_to_mtd(&host->chip);
struct nand_chip *chip = mtd_to_nand(mtd);
info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
@@ -1272,7 +1272,7 @@ static int pxa3xx_nand_sensing(struct pxa3xx_nand_host
*host)
const struct nand_sdr_timings *timings;
int ret;
- mtd = info->host[info->cs]->mtd;
+ mtd = nand_to_mtd(&info->host[info->cs]->chip);
chip = mtd_to_nand(mtd);
/* configure default flash values */
@@ -1494,7 +1494,6 @@ static int alloc_nand_resource(struct pxa3xx_nand_info
*info)
mtd = nand_to_mtd(chip);
host = (struct pxa3xx_nand_host *)chip;
info->host[cs] = host;
- host->mtd = mtd;
host->cs = cs;
host->info_data = info;
host->read_id_bytes = 4;
@@ -1569,7 +1568,7 @@ static int pxa3xx_nand_probe(struct pxa3xx_nand_info
*info)
probe_success = 0;
for (cs = 0; cs < pdata->num_cs; cs++) {
- struct mtd_info *mtd = info->host[cs]->mtd;
+ struct mtd_info *mtd = nand_to_mtd(&info->host[cs]->chip);
/*
* The mtd name matches the one used in 'mtdparts' kernel
--
2.10.0.479.g7c56b16
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[U-Boot] [RFC PATCH v1 3/6] mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing()
Since the pxa3xx_nand driver was added there has been a discrepancy in pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min. This brings us into line with the current Linux code. Cc: Antoine Ténart Signed-off-by: Chris Packham --- drivers/mtd/nand/pxa3xx_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index a7a488260a71..784b7585687f 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -345,9 +345,9 @@ static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host, u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000); u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000); u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000); - u32 tWP_min = DIV_ROUND_UP(t->tWC_min - tWH_min, 1000); + u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000); u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000); - u32 tRP_min = DIV_ROUND_UP(t->tRC_min - tREH_min, 1000); + u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000); u32 tR = chip->chip_delay * 1000; u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000); u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000); -- 2.10.0.479.g7c56b16 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v1 4/6] mtd: nand: pxa3xx_nand: fix early spurious interrupt
When the nand is first probe, and upon the first command start, the status bits should be cleared before the interrupts are unmasked. Cc: Robert Jarzmik Signed-off-by: Chris Packham --- drivers/mtd/nand/pxa3xx_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 784b7585687f..3c065169ce9c 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -477,8 +477,8 @@ static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) ndcr |= NDCR_ND_RUN; /* clear status bits and run */ - nand_writel(info, NDCR, 0); nand_writel(info, NDSR, NDSR_MASK); + nand_writel(info, NDCR, 0); nand_writel(info, NDCR, ndcr); } -- 2.10.0.479.g7c56b16 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v1 5/6] mtd: nand: pxa3xx-nand: fix random command timeouts
When 2 commands are submitted in a row, and the second is very quick,
the completion of the second command might never come. This happens
especially if the second command is quick, such as a status read
after an erase
Cc: Robert Jarzmik
Signed-off-by: Chris Packham
---
drivers/mtd/nand/pxa3xx_nand.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 3c065169ce9c..9a43bd11a453 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -619,8 +619,14 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info
*info)
is_ready = 1;
}
+ /*
+* Clear all status bit before issuing the next command, which
+* can and will alter the status bits and will deserve a new
+* interrupt on its own. This lets the controller exit the IRQ
+*/
+ nand_writel(info, NDSR, status);
+
if (status & NDSR_WRCMDREQ) {
- nand_writel(info, NDSR, NDSR_WRCMDREQ);
status &= ~NDSR_WRCMDREQ;
info->state = STATE_CMD_HANDLE;
@@ -641,8 +647,6 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info
*info)
nand_writel(info, NDCB0, info->ndcb3);
}
- /* clear NDSR to let the controller exit the IRQ */
- nand_writel(info, NDSR, status);
if (is_completed)
info->cmd_complete = 1;
if (is_ready)
--
2.10.0.479.g7c56b16
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[U-Boot] [RFC PATCH v1 6/6] mtd: nand: pxa3xx_nand: add support for partial chunks
This commit is needed to properly support the 8-bits ECC configuration
with 4KB pages.
When pages larger than 2 KB are used on platforms using the PXA3xx
NAND controller, the reading/programming operations need to be split
in chunks of 2 KBs or less because the controller FIFO is limited to
about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to
this requirement, the data layout on NAND is a bit strange, with ECC
interleaved with data, at the end of each chunk.
When a 4-bits ECC configuration is used with 4 KB pages, the physical
data layout on the NAND looks like this:
| 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC |
So the data chunks have an equal size, 2080 bytes for each chunk,
which the driver supports properly.
When a 8-bits ECC configuration is used with 4KB pages, the physical
data layout on the NAND looks like this:
| 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30
ECC | 64 spare | 30 ECC |
So, the spare area is stored in its own chunk, which has a different
size than the other chunks. Since OOB is not used by UBIFS, the initial
implementation of the driver has chosen to not support reading this
additional "spare" chunk of data.
Unfortunately, Marvell has chosen to store the BBT signature in the
OOB area. Therefore, if the driver doesn't read this spare area, Linux
has no way of finding the BBT. It thinks there is no BBT, and rewrites
one, which U-Boot does not recognize, causing compatibility problems
between the bootloader and the kernel in terms of NAND usage.
To fix this, this commit implements the support for reading a partial
last chunk. This support is currently only useful for the case of 8
bits ECC with 4 KB pages, but it will be useful in the future to
enable other configurations such as 12 bits and 16 bits ECC with 4 KB
pages, or 8 bits ECC with 8 KB pages, etc. All those configurations
have a "last" chunk that doesn't have the same size as the other
chunks.
In order to implement reading of the last chunk, this commit:
- Adds a number of new fields to the pxa3xx_nand_info to describe how
many full chunks and how many chunks we have, the size of full
chunks and partial chunks, both in terms of data area and spare
area.
- Fills in the step_chunk_size and step_spare_size variables to
describe how much data and spare should be read/written for the
current read/program step.
- Reworks the state machine to accommodate doing the additional read
or program step when a last partial chunk is used.
Cc: Thomas Petazzoni
Signed-off-by: Chris Packham
---
drivers/mtd/nand/pxa3xx_nand.c | 154 ++---
1 file changed, 99 insertions(+), 55 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 9a43bd11a453..4bf6c53c541f 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -193,15 +193,44 @@ struct pxa3xx_nand_info {
int use_spare; /* use spare ? */
int need_wait;
- unsigned intdata_size; /* data to be read from FIFO */
- unsigned intchunk_size; /* split commands chunk size */
- unsigned intoob_size;
+ /* Amount of real data per full chunk */
+ unsigned intchunk_size;
+
+ /* Amount of spare data per full chunk */
unsigned intspare_size;
+
+ /* Number of full chunks (i.e chunk_size + spare_size) */
+ unsigned intnfullchunks;
+
+ /*
+* Total number of chunks. If equal to nfullchunks, then there
+* are only full chunks. Otherwise, there is one last chunk of
+* size (last_chunk_size + last_spare_size)
+*/
+ unsigned intntotalchunks;
+
+ /* Amount of real data in the last chunk */
+ unsigned intlast_chunk_size;
+
+ /* Amount of spare data in the last chunk */
+ unsigned intlast_spare_size;
+
unsigned intecc_size;
unsigned intecc_err_cnt;
unsigned intmax_bitflips;
int retcode;
+ /*
+* Variables only valid during command
+* execution. step_chunk_size and step_spare_size is the
+* amount of real data and spare data in the current
+* chunk. cur_chunk is the current chunk being
+* read/programmed.
+*/
+ unsigned intstep_chunk_size;
+ unsigned intstep_spare_size;
+ unsigned intcur_chunk;
+
/* cached register value */
uint32_treg_ndcr;
uint32_tndtr0cs0;
@@ -426,25 +455,6 @@ static int pxa3xx_nand_init_timings(struct
pxa3xx_nand_host *host)
return 0;
}
-/*
- * Set the data and OOB size, depending on the selected
- * spare a
Re: [U-Boot] [RFC PATCH v1 1/6] mtd: nand: pxa3xx_nand: Increase initial buffer size
On Fri, Oct 21, 2016 at 1:58 AM, Ezequiel Garcia wrote: > On 20 October 2016 at 01:31, Chris Packham wrote: >> The initial buffer is used for the initial commands used to detect >> a flash device (STATUS, READID and PARAM). >> >> ONFI param page is 256 bytes, and there are three redundant copies >> to be read. JEDEC param page is 512 bytes, and there are also three >> redundant copies to be read. Hence this buffer should be at least >> 512 x 3. This commits rounds the buffer size to 2048. >> > > Hey Chris, > > So you are basically picking the commit and commit log from Linux: > > http://lists.infradead.org/pipermail/linux-mtd/2015-August/060721.html > > Shouldn't you mention that somewhere? Indeed. I mentioned it here http://lists.denx.de/pipermail/u-boot/2016-October/270605.html and that was the intent of the Cc line below. I should probably set the From: line to the original author and call out the Linux commit sha1. I wasn't sure of the usual u-boot practice, I could equally squash these all together and say "sync with linux". > >> Cc: Ezequiel Garcia >> Signed-off-by: Chris Packham >> --- >> >> drivers/mtd/nand/pxa3xx_nand.c | 16 ++-- >> 1 file changed, 10 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c >> index dfe8966b56b6..ea0a6f3778bd 100644 >> --- a/drivers/mtd/nand/pxa3xx_nand.c >> +++ b/drivers/mtd/nand/pxa3xx_nand.c >> @@ -26,10 +26,13 @@ >> >> /* >> * Define a buffer size for the initial command that detects the flash >> device: >> - * STATUS, READID and PARAM. The largest of these is the PARAM command, >> - * needing 256 bytes. >> + * STATUS, READID and PARAM. >> + * ONFI param page is 256 bytes, and there are three redundant copies >> + * to be read. JEDEC param page is 512 bytes, and there are also three >> + * redundant copies to be read. >> + * Hence this buffer should be at least 512 x 3. Let's pick 2048. >> */ >> -#define INIT_BUFFER_SIZE 256 >> +#define INIT_BUFFER_SIZE 2048 >> >> /* registers and bit definitions */ >> #define NDCR (0x00) /* Control register */ >> @@ -838,14 +841,14 @@ static int prepare_set_command(struct pxa3xx_nand_info >> *info, int command, >> break; >> >> case NAND_CMD_PARAM: >> - info->buf_count = 256; >> + info->buf_count = INIT_BUFFER_SIZE; >> info->ndcb0 |= NDCB0_CMD_TYPE(0) >> | NDCB0_ADDR_CYC(1) >> | NDCB0_LEN_OVRD >> | command; >> info->ndcb1 = (column & 0xFF); >> - info->ndcb3 = 256; >> - info->data_size = 256; >> + info->ndcb3 = INIT_BUFFER_SIZE; >> + info->data_size = INIT_BUFFER_SIZE; >> break; >> >> case NAND_CMD_READID: >> @@ -1468,6 +1471,7 @@ KEEP_CONFIG: >> host->row_addr_cycles = 3; >> else >> host->row_addr_cycles = 2; >> + > > Spurious change. I suggest to drop it. > Will do. >> return nand_scan_tail(mtd); >> } >> >> -- >> 2.10.0.479.g7c56b16 >> > > > > -- > Ezequiel García, VanguardiaSur > www.vanguardiasur.com.ar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v1] mvebu: db-88f6820-amc: Enable FIT support
Signed-off-by: Chris Packham --- I'm keen to see this for the 88f6820-amc at least but I did wonder if it should be enabled for more of the mvebu boards? Marvell don't really make use of FIT images in their SDKs but I personally find them incredibly useful. It adds about 32KiB to the final image but I think it's well worth it. configs/db-88f6820-amc_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index b9f0ec3e07e6..ba624494ce30 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -8,6 +8,8 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y -- 2.10.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] cmd: load: align cache flush
Prevent cache misalignment message by ensuring that a whole cache line
is flushed.
Signed-off-by: Chris Packham
---
cmd/load.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/load.c b/cmd/load.c
index 65557e4f9ec3..77c3359b29b7 100644
--- a/cmd/load.c
+++ b/cmd/load.c
@@ -997,7 +997,7 @@ static ulong load_serial_ymodem(ulong offset, int mode)
xyzModem_stream_terminate(false, &getcxmodem);
- flush_cache(offset, size);
+ flush_cache(offset, ALIGN(size, ARCH_DMA_MINALIGN));
printf("## Total Size = 0x%08x = %d Bytes\n", size, size);
setenv_hex("filesize", size);
--
2.10.1
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[U-Boot] [PATCH] arm: mvebu: move SYS_MVEBU_PLL_CLOCK to Kconfig
The main PLL frequency is 2GHz for Armada-XP and 1GHZ for Armada 375, 38x and 39x. [ Linux commit ae142bd9976532aa5232ab0b00e621690d8bfe6a ] Signed-off-by: Chris Packham --- See https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=ae142bd99765 I've set the value for ARMADA_3700 and ARMADA_8K to 2GHz. I'm not sure if this is correct but it is the same value that these SoCs would have had when the value was defined in soc.h. arch/arm/mach-mvebu/Kconfig| 6 ++ arch/arm/mach-mvebu/include/mach/soc.h | 3 --- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 6e8026bde253..7733936be540 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -36,6 +36,12 @@ config ARMADA_8K bool select ARM64 +# Armada PLL frequency (used for NAND clock generation) +config SYS_MVEBU_PLL_CLOCK + int + default "20" if ARMADA_XP || ARMADA_3700 || ARMADA_8K + default "10" if ARMADA_38X || ARMADA_375 + # Armada XP/38x SoC types... config MV78230 bool diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 731fe65ae4b4..0f69f3341be0 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -31,9 +31,6 @@ #define CONFIG_SYS_TCLK25000 /* 250MHz */ #endif -/* Armada XP PLL frequency (used for NAND clock generation) */ -#define CONFIG_SYS_MVEBU_PLL_CLOCK 20 - /* SOC specific definations */ #define INTREG_BASE0xd000 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) -- 2.10.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v2 01/10] mtd: nand: pxa3xx_nand: Increase initial buffer size
The initial buffer is used for the initial commands used to detect a flash device (STATUS, READID and PARAM). ONFI param page is 256 bytes, and there are three redundant copies to be read. JEDEC param page is 512 bytes, and there are also three redundant copies to be read. Hence this buffer should be at least 512 x 3. This commits rounds the buffer size to 2048. [ Linux commit c16340973fcb6461474a9f811f7f3ff2f946b24c ] Cc: Ezequiel Garcia Signed-off-by: Chris Packham --- Changes in v2: - Add reference to Linux commit sha1. - Remove spurious change drivers/mtd/nand/pxa3xx_nand.c | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index dfe8966b56b6..8d7f7a845a9d 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -26,10 +26,13 @@ /* * Define a buffer size for the initial command that detects the flash device: - * STATUS, READID and PARAM. The largest of these is the PARAM command, - * needing 256 bytes. + * STATUS, READID and PARAM. + * ONFI param page is 256 bytes, and there are three redundant copies + * to be read. JEDEC param page is 512 bytes, and there are also three + * redundant copies to be read. + * Hence this buffer should be at least 512 x 3. Let's pick 2048. */ -#define INIT_BUFFER_SIZE 256 +#define INIT_BUFFER_SIZE 2048 /* registers and bit definitions */ #define NDCR (0x00) /* Control register */ @@ -838,14 +841,14 @@ static int prepare_set_command(struct pxa3xx_nand_info *info, int command, break; case NAND_CMD_PARAM: - info->buf_count = 256; + info->buf_count = INIT_BUFFER_SIZE; info->ndcb0 |= NDCB0_CMD_TYPE(0) | NDCB0_ADDR_CYC(1) | NDCB0_LEN_OVRD | command; info->ndcb1 = (column & 0xFF); - info->ndcb3 = 256; - info->data_size = 256; + info->ndcb3 = INIT_BUFFER_SIZE; + info->data_size = INIT_BUFFER_SIZE; break; case NAND_CMD_READID: -- 2.10.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v2 00/10] pxa3xx_nand updates
I'm looking into the NAND support for the db-88f6820-amc board. There are a number of changes in the pxa3xx_nand driver in Linux that are relevant (not specifically to this boards but to Armada boards in general). Some of these changes are cleanups and some are actual bug fixes. I'd really appreciate some testing on this. This gives me enough so I can mount and read files out of a ubifs volume created by Linux on the DB-88F6820-AMC board but I don't have access to any other Armada boards to test with. Where applicable I'll Cc the author of the equivalent Linux patch. I've had to tweak a few of them to make them fit u-boot (e.g. to handle platform data) but they should still look pretty close to their Linux counterparts. Note this series is dependent on http://lists.denx.de/pipermail/u-boot/2016-October/270967.html Changes in v2: - Add references to Linux commit sha1. - Remove spurious change in 1/10 - Drop irrelevant Cc from 2/10 - 6/10 to 9/10 are new Chris Packham (10): mtd: nand: pxa3xx_nand: Increase initial buffer size mtd: nand: pxa3xx_nand: use nand_to_mtd() mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing() mtd: nand: pxa3xx_nand: fix early spurious interrupt mtd: nand: pxa3xx-nand: fix random command timeouts nand: pxa3xx: Increase READ_ID buffer and make the size static mtd: pxa3xx_nand: Increase the initial chunk size mtd: pxa3xx_nand: Fix initial controller configuration mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan mtd: nand: pxa3xx_nand: add support for partial chunks drivers/mtd/nand/pxa3xx_nand.c | 294 - 1 file changed, 175 insertions(+), 119 deletions(-) -- 2.10.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v2 03/10] mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing()
Since the pxa3xx_nand driver was added there has been a discrepancy in pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min. This brings us into line with the current Linux code. Signed-off-by: Chris Packham --- Changes in v2: - None drivers/mtd/nand/pxa3xx_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index a5b9332456ec..17cbc8d3d930 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -345,9 +345,9 @@ static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host, u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000); u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000); u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000); - u32 tWP_min = DIV_ROUND_UP(t->tWC_min - tWH_min, 1000); + u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000); u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000); - u32 tRP_min = DIV_ROUND_UP(t->tRC_min - tREH_min, 1000); + u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000); u32 tR = chip->chip_delay * 1000; u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000); u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000); -- 2.10.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v2 02/10] mtd: nand: pxa3xx_nand: use nand_to_mtd()
Don't store struct mtd_info in struct pxa3xx_nand_host. Instead use the
one that is already part of struct nand_chip. This brings us in line
with current U-boot and Linux conventions.
Signed-off-by: Chris Packham
---
Changes in v2:
- Drop irrelevant Cc from commit message
drivers/mtd/nand/pxa3xx_nand.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 8d7f7a845a9d..a5b9332456ec 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -147,7 +147,6 @@ enum pxa3xx_nand_variant {
struct pxa3xx_nand_host {
struct nand_chipchip;
- struct mtd_info *mtd;
void*info_data;
/* page size of attached chip */
@@ -380,16 +379,17 @@ static int pxa3xx_nand_init_timings(struct
pxa3xx_nand_host *host)
struct nand_chip *chip = &host->chip;
struct pxa3xx_nand_info *info = host->info_data;
const struct pxa3xx_nand_flash *f = NULL;
+ struct mtd_info *mtd = nand_to_mtd(&host->chip);
int mode, id, ntypes, i;
mode = onfi_get_async_timing_mode(chip);
if (mode == ONFI_TIMING_MODE_UNKNOWN) {
ntypes = ARRAY_SIZE(builtin_flash_types);
- chip->cmdfunc(host->mtd, NAND_CMD_READID, 0x00, -1);
+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
- id = chip->read_byte(host->mtd);
- id |= chip->read_byte(host->mtd) << 0x8;
+ id = chip->read_byte(mtd);
+ id |= chip->read_byte(mtd) << 0x8;
for (i = 0; i < ntypes; i++) {
f = &builtin_flash_types[i];
@@ -682,7 +682,7 @@ static void set_command_address(struct pxa3xx_nand_info
*info,
static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
{
struct pxa3xx_nand_host *host = info->host[info->cs];
- struct mtd_info *mtd = host->mtd;
+ struct mtd_info *mtd = nand_to_mtd(&host->chip);
/* reset data and oob column point to handle data */
info->buf_start = 0;
@@ -733,7 +733,7 @@ static int prepare_set_command(struct pxa3xx_nand_info
*info, int command,
struct mtd_info *mtd;
host = info->host[info->cs];
- mtd = host->mtd;
+ mtd = nand_to_mtd(&host->chip);
addr_cycle = 0;
exec_cmd = 1;
@@ -1220,7 +1220,7 @@ static int pxa3xx_nand_waitfunc(struct mtd_info *mtd,
struct nand_chip *this)
static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
{
struct pxa3xx_nand_host *host = info->host[info->cs];
- struct mtd_info *mtd = host->mtd;
+ struct mtd_info *mtd = nand_to_mtd(&host->chip);
struct nand_chip *chip = mtd_to_nand(mtd);
info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
@@ -1272,7 +1272,7 @@ static int pxa3xx_nand_sensing(struct pxa3xx_nand_host
*host)
const struct nand_sdr_timings *timings;
int ret;
- mtd = info->host[info->cs]->mtd;
+ mtd = nand_to_mtd(&info->host[info->cs]->chip);
chip = mtd_to_nand(mtd);
/* configure default flash values */
@@ -1493,7 +1493,6 @@ static int alloc_nand_resource(struct pxa3xx_nand_info
*info)
mtd = nand_to_mtd(chip);
host = (struct pxa3xx_nand_host *)chip;
info->host[cs] = host;
- host->mtd = mtd;
host->cs = cs;
host->info_data = info;
host->read_id_bytes = 4;
@@ -1568,7 +1567,7 @@ static int pxa3xx_nand_probe(struct pxa3xx_nand_info
*info)
probe_success = 0;
for (cs = 0; cs < pdata->num_cs; cs++) {
- struct mtd_info *mtd = info->host[cs]->mtd;
+ struct mtd_info *mtd = nand_to_mtd(&info->host[cs]->chip);
/*
* The mtd name matches the one used in 'mtdparts' kernel
--
2.10.1
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[U-Boot] [RFC PATCH v2 07/10] mtd: pxa3xx_nand: Increase the initial chunk size
The chunk size represents the size of the data chunks, which
is used by the controllers that allow to split transfered data.
However, the initial chunk size is used in a non-splitted way,
during device identification. Therefore, it must be large enough
for all the NAND commands issued during device identification.
This includes NAND_CMD_PARAM which was recently changed to
transfer up to 2048 bytes (for the redundant parameter pages).
Thus, the initial chunk size should be 2048 as well.
On Armada 370/XP platforms (NFCv2) booted without the keep-config
devicetree property, this commit fixes a timeout on the NAND_CMD_PARAM
command:
[..]
pxa3xx-nand f10d.nand: This platform can't do DMA on this device
pxa3xx-nand f10d.nand: Wait time out!!!
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x38
nand: Micron MT29F8G08ABABAWP
nand: 1024 MiB, SLC, erase size: 512 KiB, page size: 4096, OOB size: 224
[ Linux commit c7f00c29aa846b00c70bc99ddb6b1cc7e17c47d4 ]
Cc: Ezequiel García
Signed-off-by: Chris Packham
---
Changes in v2:
- new patch
drivers/mtd/nand/pxa3xx_nand.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index d1c6e010f3c0..146ef096ea3f 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1372,7 +1372,7 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
goto KEEP_CONFIG;
/* Set a default chunk size */
- info->chunk_size = 512;
+ info->chunk_size = PAGE_CHUNK_SIZE;
ret = pxa3xx_nand_sensing(host);
if (ret) {
--
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[U-Boot] [RFC PATCH v2 05/10] mtd: nand: pxa3xx-nand: fix random command timeouts
When 2 commands are submitted in a row, and the second is very quick,
the completion of the second command might never come. This happens
especially if the second command is quick, such as a status read
after an erase
[ Linux commit 21fc0ef9652f0c809dc0d3e0a67f1e1bf6ff8255 ]
Cc: Robert Jarzmik
Signed-off-by: Chris Packham
---
Changes in v2:
- Add reference to Linux commit sha1
drivers/mtd/nand/pxa3xx_nand.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 4cd1297e1d59..c97d85782cb1 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -619,8 +619,14 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info
*info)
is_ready = 1;
}
+ /*
+* Clear all status bit before issuing the next command, which
+* can and will alter the status bits and will deserve a new
+* interrupt on its own. This lets the controller exit the IRQ
+*/
+ nand_writel(info, NDSR, status);
+
if (status & NDSR_WRCMDREQ) {
- nand_writel(info, NDSR, NDSR_WRCMDREQ);
status &= ~NDSR_WRCMDREQ;
info->state = STATE_CMD_HANDLE;
@@ -641,8 +647,6 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info
*info)
nand_writel(info, NDCB0, info->ndcb3);
}
- /* clear NDSR to let the controller exit the IRQ */
- nand_writel(info, NDSR, status);
if (is_completed)
info->cmd_complete = 1;
if (is_ready)
--
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[U-Boot] [RFC PATCH v2 04/10] mtd: nand: pxa3xx_nand: fix early spurious interrupt
When the nand is first probe, and upon the first command start, the status bits should be cleared before the interrupts are unmasked. [ Linux commit 0b14392db2e998157d924085d7913e537ec26121 ] Cc: Robert Jarzmik Signed-off-by: Chris Packham --- Changes in v2: - Add reference to Linux commit sha1 drivers/mtd/nand/pxa3xx_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 17cbc8d3d930..4cd1297e1d59 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -477,8 +477,8 @@ static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) ndcr |= NDCR_ND_RUN; /* clear status bits and run */ - nand_writel(info, NDCR, 0); nand_writel(info, NDSR, NDSR_MASK); + nand_writel(info, NDCR, 0); nand_writel(info, NDCR, ndcr); } -- 2.10.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v2 08/10] mtd: pxa3xx_nand: Fix initial controller configuration
The Data Flash Control Register (NDCR) contains two types
of parameters: those that are needed for device identification,
and those that can only be set after device identification.
Therefore, the driver can't set them all at once and instead
needs to configure the first group before nand_scan_ident()
and the second group later.
Let's split pxa3xx_nand_config in two halves, and set the
parameters that depend on the device geometry once this is known.
[ Linux commit 66e8e47eae658dc884e65695a597fdda7a109448 ]
Cc: Ezequiel Garcia
Signed-off-by: Chris Packham
---
Changes in v2:
- New
drivers/mtd/nand/pxa3xx_nand.c | 41 +
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 146ef096ea3f..432219c78831 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -59,7 +59,8 @@
#define NDCR_ND_MODE (0x3 << 21)
#define NDCR_NAND_MODE (0x0)
#define NDCR_CLR_PG_CNT(0x1 << 20)
-#define NDCR_STOP_ON_UNCOR (0x1 << 19)
+#define NFCV1_NDCR_ARB_CNTL(0x1 << 19)
+#define NFCV2_NDCR_STOP_ON_UNCOR (0x1 << 19)
#define NDCR_RD_ID_CNT_MASK(0x7 << 16)
#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
@@ -1226,26 +1227,41 @@ static int pxa3xx_nand_waitfunc(struct mtd_info *mtd,
struct nand_chip *this)
return NAND_STATUS_READY;
}
-static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
+static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)
+{
+ struct pxa3xx_nand_platform_data *pdata = info->pdata;
+
+ /* Configure default flash values */
+ info->chunk_size = PAGE_CHUNK_SIZE;
+ info->reg_ndcr = 0x0; /* enable all interrupts */
+ info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
+ info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
+ info->reg_ndcr |= NDCR_SPARE_EN;
+
+ return 0;
+}
+
+static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info)
{
struct pxa3xx_nand_host *host = info->host[info->cs];
- struct mtd_info *mtd = nand_to_mtd(&host->chip);
+ struct mtd_info *mtd = nand_to_mtd(&info->host[info->cs]->chip);
struct nand_chip *chip = mtd_to_nand(mtd);
info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
-
- return 0;
}
static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
{
+ struct pxa3xx_nand_platform_data *pdata = info->pdata;
uint32_t ndcr = nand_readl(info, NDCR);
/* Set an initial chunk size */
info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
- info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
+ info->reg_ndcr = ndcr &
+ ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);
+ info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
return 0;
@@ -1371,8 +1387,9 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
goto KEEP_CONFIG;
- /* Set a default chunk size */
- info->chunk_size = PAGE_CHUNK_SIZE;
+ ret = pxa3xx_nand_config_ident(info);
+ if (ret)
+ return ret;
ret = pxa3xx_nand_sensing(host);
if (ret) {
@@ -1399,10 +1416,6 @@ KEEP_CONFIG:
}
}
- ret = pxa3xx_nand_config_flash(info);
- if (ret)
- return ret;
-
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
/*
* We'll use a bad block table stored in-flash and don't
@@ -1467,6 +1480,10 @@ KEEP_CONFIG:
host->row_addr_cycles = 3;
else
host->row_addr_cycles = 2;
+
+ if (!pdata->keep_config)
+ pxa3xx_nand_config_tail(info);
+
return nand_scan_tail(mtd);
}
--
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[U-Boot] [RFC PATCH v2 06/10] nand: pxa3xx: Increase READ_ID buffer and make the size static
The read ID count should be made as large as the maximum READ_ID size,
so there's no need to have dynamic size. This commit sets the hardware
maximum read ID count, which should be more than enough on all cases.
Also, we get rid of the read_id_bytes, and use a macro instead.
[ Linux commit b226eca2088004622434cbcc27c6401b64f22d7c]
Cc: Ezequiel García
Signed-off-by: Chris Packham
---
Changes in v2:
- New
drivers/mtd/nand/pxa3xx_nand.c | 29 ++---
1 file changed, 10 insertions(+), 19 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index c97d85782cb1..d1c6e010f3c0 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -110,6 +110,13 @@
#define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
#define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
+/*
+ * This should be large enough to read 'ONFI' and 'JEDEC'.
+ * Let's use 7 bytes, which is the maximum ID count supported
+ * by the controller (see NDCR_RD_ID_CNT_MASK).
+ */
+#define READ_ID_BYTES 7
+
/* macros for registers read/write */
#define nand_writel(info, off, val)\
writel((val), (info)->mmio_base + (off))
@@ -156,8 +163,6 @@ struct pxa3xx_nand_host {
/* calculated from pxa3xx_nand_flash data */
unsigned intcol_addr_cycles;
unsigned introw_addr_cycles;
- size_t read_id_bytes;
-
};
struct pxa3xx_nand_info {
@@ -856,7 +861,7 @@ static int prepare_set_command(struct pxa3xx_nand_info
*info, int command,
break;
case NAND_CMD_READID:
- info->buf_count = host->read_id_bytes;
+ info->buf_count = READ_ID_BYTES;
info->ndcb0 |= NDCB0_CMD_TYPE(3)
| NDCB0_ADDR_CYC(1)
| command;
@@ -1236,23 +1241,10 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info)
static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
{
- /*
-* We set 0 by hard coding here, for we don't support keep_config
-* when there is more than one chip attached to the controller
-*/
- struct pxa3xx_nand_host *host = info->host[0];
uint32_t ndcr = nand_readl(info, NDCR);
- if (ndcr & NDCR_PAGE_SZ) {
- /* Controller's FIFO size */
- info->chunk_size = 2048;
- host->read_id_bytes = 4;
- } else {
- info->chunk_size = 512;
- host->read_id_bytes = 2;
- }
-
/* Set an initial chunk size */
+ info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
@@ -1282,7 +1274,7 @@ static int pxa3xx_nand_sensing(struct pxa3xx_nand_host
*host)
/* configure default flash values */
info->reg_ndcr = 0x0; /* enable all interrupts */
info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
- info->reg_ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
+ info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
/* use the common timing to make a try */
@@ -1499,7 +1491,6 @@ static int alloc_nand_resource(struct pxa3xx_nand_info
*info)
info->host[cs] = host;
host->cs = cs;
host->info_data = info;
- host->read_id_bytes = 4;
mtd->owner = THIS_MODULE;
nand_set_controller_data(chip, host);
--
2.10.1
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[U-Boot] [RFC PATCH v2 09/10] mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan
This commit simplifies the initial configuration performed
by pxa3xx_nand_scan. No functionality change is intended.
[ Linux commit 154f50fbde539c20bbf74854461d932ebdace4d5 ]
Cc: Ezequiel García
Signed-off-by: Chris Packham
---
Changes in v2:
- New
drivers/mtd/nand/pxa3xx_nand.c | 30 ++
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 432219c78831..de897ae41d1e 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1252,7 +1252,7 @@ static void pxa3xx_nand_config_tail(struct
pxa3xx_nand_info *info)
info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
}
-static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
+static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
{
struct pxa3xx_nand_platform_data *pdata = info->pdata;
uint32_t ndcr = nand_readl(info, NDCR);
@@ -1264,7 +1264,6 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand_info *info)
info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
- return 0;
}
static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
@@ -1384,22 +1383,21 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
int ret;
uint16_t ecc_strength, ecc_step;
- if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
- goto KEEP_CONFIG;
-
- ret = pxa3xx_nand_config_ident(info);
- if (ret)
- return ret;
-
- ret = pxa3xx_nand_sensing(host);
- if (ret) {
- dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
-info->cs);
-
- return ret;
+ if (pdata->keep_config) {
+ pxa3xx_nand_detect_config(info);
+ } else {
+ ret = pxa3xx_nand_config_ident(info);
+ if (ret)
+ return ret;
+ ret = pxa3xx_nand_sensing(host);
+ if (ret) {
+ dev_info(&info->pdev->dev,
+"There is no chip on cs %d!\n",
+info->cs);
+ return ret;
+ }
}
-KEEP_CONFIG:
/* Device detection must be done with ECC disabled */
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
nand_writel(info, NDECCCTRL, 0x0);
--
2.10.1
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[U-Boot] [RFC PATCH v2 10/10] mtd: nand: pxa3xx_nand: add support for partial chunks
This commit is needed to properly support the 8-bits ECC configuration
with 4KB pages.
When pages larger than 2 KB are used on platforms using the PXA3xx
NAND controller, the reading/programming operations need to be split
in chunks of 2 KBs or less because the controller FIFO is limited to
about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to
this requirement, the data layout on NAND is a bit strange, with ECC
interleaved with data, at the end of each chunk.
When a 4-bits ECC configuration is used with 4 KB pages, the physical
data layout on the NAND looks like this:
| 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC |
So the data chunks have an equal size, 2080 bytes for each chunk,
which the driver supports properly.
When a 8-bits ECC configuration is used with 4KB pages, the physical
data layout on the NAND looks like this:
| 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30
ECC | 64 spare | 30 ECC |
So, the spare area is stored in its own chunk, which has a different
size than the other chunks. Since OOB is not used by UBIFS, the initial
implementation of the driver has chosen to not support reading this
additional "spare" chunk of data.
Unfortunately, Marvell has chosen to store the BBT signature in the
OOB area. Therefore, if the driver doesn't read this spare area, Linux
has no way of finding the BBT. It thinks there is no BBT, and rewrites
one, which U-Boot does not recognize, causing compatibility problems
between the bootloader and the kernel in terms of NAND usage.
To fix this, this commit implements the support for reading a partial
last chunk. This support is currently only useful for the case of 8
bits ECC with 4 KB pages, but it will be useful in the future to
enable other configurations such as 12 bits and 16 bits ECC with 4 KB
pages, or 8 bits ECC with 8 KB pages, etc. All those configurations
have a "last" chunk that doesn't have the same size as the other
chunks.
In order to implement reading of the last chunk, this commit:
- Adds a number of new fields to the pxa3xx_nand_info to describe how
many full chunks and how many chunks we have, the size of full
chunks and partial chunks, both in terms of data area and spare
area.
- Fills in the step_chunk_size and step_spare_size variables to
describe how much data and spare should be read/written for the
current read/program step.
- Reworks the state machine to accommodate doing the additional read
or program step when a last partial chunk is used.
[ Linux commit c2cdace755b583bae540a9979bff1aa428181b8c ]
Cc: Thomas Petazzoni
Signed-off-by: Chris Packham
---
Changes in v2:
- None
drivers/mtd/nand/pxa3xx_nand.c | 154 ++---
1 file changed, 99 insertions(+), 55 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index de897ae41d1e..365dcaf69f3e 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -199,15 +199,44 @@ struct pxa3xx_nand_info {
int use_spare; /* use spare ? */
int need_wait;
- unsigned intdata_size; /* data to be read from FIFO */
- unsigned intchunk_size; /* split commands chunk size */
- unsigned intoob_size;
+ /* Amount of real data per full chunk */
+ unsigned intchunk_size;
+
+ /* Amount of spare data per full chunk */
unsigned intspare_size;
+
+ /* Number of full chunks (i.e chunk_size + spare_size) */
+ unsigned intnfullchunks;
+
+ /*
+* Total number of chunks. If equal to nfullchunks, then there
+* are only full chunks. Otherwise, there is one last chunk of
+* size (last_chunk_size + last_spare_size)
+*/
+ unsigned intntotalchunks;
+
+ /* Amount of real data in the last chunk */
+ unsigned intlast_chunk_size;
+
+ /* Amount of spare data in the last chunk */
+ unsigned intlast_spare_size;
+
unsigned intecc_size;
unsigned intecc_err_cnt;
unsigned intmax_bitflips;
int retcode;
+ /*
+* Variables only valid during command
+* execution. step_chunk_size and step_spare_size is the
+* amount of real data and spare data in the current
+* chunk. cur_chunk is the current chunk being
+* read/programmed.
+*/
+ unsigned intstep_chunk_size;
+ unsigned intstep_spare_size;
+ unsigned intcur_chunk;
+
/* cached register value */
uint32_treg_ndcr;
uint32_tndtr0cs0;
@@ -432,25 +461,6 @@ static int pxa3xx_nand_init_timings(struct
pxa3xx_nand_host *host)
retur
[U-Boot] [PATCH v2] spi: kirkwood_spi: implement mvebu_spi_set_mode()
Set the appropriate bits in the interface config register based
on the SPI_ mode flags.
Signed-off-by: Chris Packham
---
Changes in v2:
- Clear bits before updating
arch/arm/include/asm/arch-mvebu/spi.h | 4
drivers/spi/kirkwood_spi.c| 15 +++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/include/asm/arch-mvebu/spi.h
b/arch/arm/include/asm/arch-mvebu/spi.h
index 78869a253d1f..3545aed17347 100644
--- a/arch/arm/include/asm/arch-mvebu/spi.h
+++ b/arch/arm/include/asm/arch-mvebu/spi.h
@@ -52,6 +52,10 @@ struct kwspi_registers {
#define KWSPI_ADRLEN_3BYTE (2 << 8)
#define KWSPI_ADRLEN_4BYTE (3 << 8)
#define KWSPI_ADRLEN_MASK (3 << 8)
+#define KWSPI_CPOL (1 << 11)
+#define KWSPI_CPHA (1 << 12)
+#define KWSPI_TXLSBF (1 << 13)
+#define KWSPI_RXLSBF (1 << 14)
#define KWSPI_IRQUNMASK1 /* unmask SPI interrupt */
#define KWSPI_IRQMASK 0 /* mask SPI interrupt */
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index 6851ba942f51..791f3e8099c8 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -271,6 +271,21 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint
hz)
static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct kwspi_registers *reg = plat->spireg;
+ u32 data = readl(®->cfg);
+
+ data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF);
+
+ if (mode & SPI_CPHA)
+ data |= KWSPI_CPHA;
+ if (mode & SPI_CPOL)
+ data |= KWSPI_CPOL;
+ if (mode & SPI_LSB_FIRST)
+ data |= (KWSPI_RXLSBF | KWSPI_TXLSBF);
+
+ writel(data, ®->cfg);
+
return 0;
}
--
2.10.1
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Re: [U-Boot] [PATCH v2] spi: kirkwood_spi: implement mvebu_spi_set_mode()
On 27/10/2016 10:41 PM, "Jagan Teki" wrote: > > On Thu, Oct 27, 2016 at 1:46 PM, Chris Packham wrote: > > Set the appropriate bits in the interface config register based > > on the SPI_ mode flags. > > > > Signed-off-by: Chris Packham > > Missed updating Stefan Reviewed-by tag? please check for next time. That was semi-intentional. I thought v2 was different enough that I didn't want to assume Stefan's review would carry through. > > > --- > > > > Changes in v2: > > - Clear bits before updating > > Applied, thanks! > > -- > Jagan Teki > Free Software Engineer | www.openedev.com > U-Boot, Linux | Upstream Maintainer > Hyderabad, India. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] net: mvgbe: Fix build error with CONFIG_PHYLIB
Commit 5a49f17481bb ("net: mii: Use spatch to update miiphy_register")
updated the mvgbe implementation of smi_reg_read/smi_reg_write. Prior to
that change mvgbe_phy_read and mvgbe_phy_write where used as wrappers to
satisfy the phylib APIs. Because these functions weren't updated in that
commit build errors where triggered when CONFIG_PHYLIB was enabled.
Fix these build errors by removing mvgbe_phy_read and mvgbe_phy_write
and using smi_reg_read/smi_reg_write directly.
Signed-off-by: Chris Packham
---
Looking at this closer it actually appears that the mvgbe driver has 2
places where a mii_dev is created. The first in mvgbe_phylib_init()
which is triggered when CONFIG_PHYLIB is enabled (this is where I
first noticed the build error), the second in mvgbe_initialize() which
is triggered when CONFIG_MII or CONFIG_CMD_MII is enabled.
I think this could do with some more cleaning up. But perhaps the build
error should be fixed first and then we can tackle the cleanup.
drivers/net/mvgbe.c | 25 +++--
1 file changed, 3 insertions(+), 22 deletions(-)
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index c784cdcae265..f833efbe6779 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -177,25 +177,6 @@ static int smi_reg_write(struct mii_dev *bus, int phy_adr,
int devad,
}
#endif
-#if defined(CONFIG_PHYLIB)
-int mvgbe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
- int reg_addr)
-{
- u16 data;
- int ret;
- ret = smi_reg_read(bus->name, phy_addr, reg_addr, &data);
- if (ret)
- return ret;
- return data;
-}
-
-int mvgbe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
- int reg_addr, u16 data)
-{
- return smi_reg_write(bus->name, phy_addr, reg_addr, data);
-}
-#endif
-
/* Stop and checks all queues */
static void stop_queue(u32 * qreg)
{
@@ -676,8 +657,8 @@ int mvgbe_phylib_init(struct eth_device *dev, int phyid)
printf("mdio_alloc failed\n");
return -ENOMEM;
}
- bus->read = mvgbe_phy_read;
- bus->write = mvgbe_phy_write;
+ bus->read = smi_reg_read;
+ bus->write = smi_reg_write;
strcpy(bus->name, dev->name);
ret = mdio_register(bus);
@@ -688,7 +669,7 @@ int mvgbe_phylib_init(struct eth_device *dev, int phyid)
}
/* Set phy address of the port */
- mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
+ smi_reg_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
--
2.10.2
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[U-Boot] [PATCH] tools/kwbimage: add BAUDRATE option
Offset 0x18 in some Marvell datasheets this field is redacted as
"reserved". This offset is actually a set of options and bits 2:0 allow
the selection of the UART baudrate.
Allow a BAUDRATE option to set the UART baudrate for any messages coming
from the BootROM firmware.
Signed-off-by: Chris Packham
---
I don't have a kirkwood datasheet handy so I've only made this part of the v1
image generation. I can add it to v0 if someone can confirm that it's supported.
tools/kwbimage.c | 31 +++
tools/kwbimage.h | 14 +-
2 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 369aba7bcab9..ad182c5c5d9a 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -68,6 +68,7 @@ struct image_cfg_element {
IMAGE_CFG_BINARY,
IMAGE_CFG_PAYLOAD,
IMAGE_CFG_DATA,
+ IMAGE_CFG_BAUDRATE,
} type;
union {
unsigned int version;
@@ -85,6 +86,7 @@ struct image_cfg_element {
unsigned int nandeccmode;
unsigned int nandpagesz;
struct ext_hdr_v0_reg regdata;
+ unsigned int baudrate;
};
};
@@ -195,6 +197,28 @@ static uint32_t image_checksum32(void *start, uint32_t len)
return csum;
}
+static uint8_t baudrate_to_option(unsigned int baudrate)
+{
+ switch (baudrate) {
+ case 2400:
+ return MAIN_HDR_V1_OPT_BAUD_2400;
+ case 4800:
+ return MAIN_HDR_V1_OPT_BAUD_4800;
+ case 9600:
+ return MAIN_HDR_V1_OPT_BAUD_9600;
+ case 19200:
+ return MAIN_HDR_V1_OPT_BAUD_19200;
+ case 38400:
+ return MAIN_HDR_V1_OPT_BAUD_38400;
+ case 57600:
+ return MAIN_HDR_V1_OPT_BAUD_57600;
+ case 115200:
+ return MAIN_HDR_V1_OPT_BAUD_115200;
+ default:
+ return MAIN_HDR_V1_OPT_BAUD_DEFAULT;
+ }
+}
+
static void *image_create_v0(size_t *imagesz, struct image_tool_params *params,
int payloadsz)
{
@@ -398,6 +422,9 @@ static void *image_create_v1(size_t *imagesz, struct
image_tool_params *params,
e = image_find_option(IMAGE_CFG_NAND_BADBLK_LOCATION);
if (e)
main_hdr->nandbadblklocation = e->nandbadblklocation;
+ e = image_find_option(IMAGE_CFG_BAUDRATE);
+ if (e)
+ main_hdr->options = baudrate_to_option(e->baudrate);
binarye = image_find_option(IMAGE_CFG_BINARY);
if (binarye) {
@@ -548,6 +575,10 @@ static int image_create_config_parse_oneline(char *line,
el->type = IMAGE_CFG_DATA;
el->regdata.raddr = strtoul(value1, NULL, 16);
el->regdata.rdata = strtoul(value2, NULL, 16);
+ } else if (!strcmp(keyword, "BAUDRATE")) {
+ char *value = strtok_r(NULL, deliminiters, &saveptr);
+ el->type = IMAGE_CFG_BAUDRATE;
+ el->baudrate = strtoul(value, NULL, 10);
} else {
fprintf(stderr, "Ignoring unknown line '%s'\n", line);
}
diff --git a/tools/kwbimage.h b/tools/kwbimage.h
index e6e3d1d4f9ad..9b06004a0b10 100644
--- a/tools/kwbimage.h
+++ b/tools/kwbimage.h
@@ -82,7 +82,7 @@ struct main_hdr_v1 {
uint32_t srcaddr; /* C-F */
uint32_t destaddr; /* 10-13 */
uint32_t execaddr; /* 14-17 */
- uint8_t reserved3; /* 18 */
+ uint8_t options; /* 18 */
uint8_t nandblocksize; /* 19 */
uint8_t nandbadblklocation;/* 1A */
uint8_t reserved4; /* 1B */
@@ -92,6 +92,18 @@ struct main_hdr_v1 {
};
/*
+ * Main header options
+ */
+#define MAIN_HDR_V1_OPT_BAUD_DEFAULT 0
+#define MAIN_HDR_V1_OPT_BAUD_2400 0x1
+#define MAIN_HDR_V1_OPT_BAUD_4800 0x2
+#define MAIN_HDR_V1_OPT_BAUD_9600 0x3
+#define MAIN_HDR_V1_OPT_BAUD_19200 0x4
+#define MAIN_HDR_V1_OPT_BAUD_38400 0x5
+#define MAIN_HDR_V1_OPT_BAUD_57600 0x6
+#define MAIN_HDR_V1_OPT_BAUD_1152000x7
+
+/*
* Header for the optional headers, version 1 (Armada 370, Armada XP)
*/
struct opt_hdr_v1 {
--
2.10.2
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[U-Boot] [PATCH] tools/kwbimage: add DEBUG option
Offset 0x1 in the generated kwb image file is a set of flags, bit 0
enables debug output from the BootROM firmware. Allow a DEBUG option in
the kwb configuration to request debug output from the BootROM firmware.
Signed-off-by: Chris Packham
---
tools/kwbimage.c | 9 +
tools/kwbimage.h | 2 +-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index ad182c5c5d9a..69844d916965 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -69,6 +69,7 @@ struct image_cfg_element {
IMAGE_CFG_PAYLOAD,
IMAGE_CFG_DATA,
IMAGE_CFG_BAUDRATE,
+ IMAGE_CFG_DEBUG,
} type;
union {
unsigned int version;
@@ -87,6 +88,7 @@ struct image_cfg_element {
unsigned int nandpagesz;
struct ext_hdr_v0_reg regdata;
unsigned int baudrate;
+ unsigned int debug;
};
};
@@ -425,6 +427,9 @@ static void *image_create_v1(size_t *imagesz, struct
image_tool_params *params,
e = image_find_option(IMAGE_CFG_BAUDRATE);
if (e)
main_hdr->options = baudrate_to_option(e->baudrate);
+ e = image_find_option(IMAGE_CFG_DEBUG);
+ if (e)
+ main_hdr->flags = e->debug ? 0x1 : 0;
binarye = image_find_option(IMAGE_CFG_BINARY);
if (binarye) {
@@ -579,6 +584,10 @@ static int image_create_config_parse_oneline(char *line,
char *value = strtok_r(NULL, deliminiters, &saveptr);
el->type = IMAGE_CFG_BAUDRATE;
el->baudrate = strtoul(value, NULL, 10);
+ } else if (!strcmp(keyword, "DEBUG")) {
+ char *value = strtok_r(NULL, deliminiters, &saveptr);
+ el->type = IMAGE_CFG_DEBUG;
+ el->debug = strtoul(value, NULL, 10);
} else {
fprintf(stderr, "Ignoring unknown line '%s'\n", line);
}
diff --git a/tools/kwbimage.h b/tools/kwbimage.h
index 9b06004a0b10..01c2f1f3238b 100644
--- a/tools/kwbimage.h
+++ b/tools/kwbimage.h
@@ -73,7 +73,7 @@ struct kwb_header {
/* Structure of the main header, version 1 (Armada 370, Armada XP) */
struct main_hdr_v1 {
uint8_t blockid; /* 0 */
- uint8_t reserved1; /* 1 */
+ uint8_t flags; /* 1 */
uint16_t reserved2; /* 2-3 */
uint32_t blocksize; /* 4-7 */
uint8_t version; /* 8 */
--
2.10.2
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[U-Boot] [RFC PATCH 1/7] fpga: CONFIG_SYS_FPGA_PROG_FEEDBACK -> CONFIG_FPGA_PROG_FEEDBACK
Prepare for move to Kconfig by removing "SYS" from the existing macros.
Signed-off-by: Chris Packham
---
README | 2 +-
board/astro/mcf5373l/fpga.c | 4 ++--
drivers/fpga/ACEX1K.c| 8
drivers/fpga/cyclon2.c | 10 +-
drivers/fpga/spartan2.c | 22 +++---
drivers/fpga/spartan3.c | 20 ++--
drivers/fpga/virtex2.c | 18 +-
include/configs/M54455EVB.h | 2 +-
include/configs/apf27.h | 2 +-
include/configs/astro_mcf5373l.h | 2 +-
include/configs/mt_ventoux.h | 4 ++--
scripts/config_whitelist.txt | 2 +-
12 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/README b/README
index 47bc215fe9c5..fdc194ab9792 100644
--- a/README
+++ b/README
@@ -2536,7 +2536,7 @@ The following options need to be configured:
Enable support for fpga loadbp command - load partial bitstream
(Xilinx only)
- CONFIG_SYS_FPGA_PROG_FEEDBACK
+ CONFIG_FPGA_PROG_FEEDBACK
Enable printing of hash marks during FPGA configuration.
diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
index 53e00728c3d8..1b53fd2521e3 100644
--- a/board/astro/mcf5373l/fpga.c
+++ b/board/astro/mcf5373l/fpga.c
@@ -128,7 +128,7 @@ int altera_write_fn(const void *buf, size_t len, int flush,
int cookie)
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
WATCHDOG_RESET();
#endif
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
putc('.'); /* let them know we are alive */
#endif
#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
@@ -347,7 +347,7 @@ int xilinx_fastwr_config_fn(void *buf, size_t len, int
flush, int cookie)
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
WATCHDOG_RESET();
#endif
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
putc('.'); /* let them know we are alive */
#endif
#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c
index 1627f0e6ffde..1fb60e5983c3 100644
--- a/drivers/fpga/ACEX1K.c
+++ b/drivers/fpga/ACEX1K.c
@@ -112,7 +112,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void
*buf, size_t bsize)
"done:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->config, fn->status,
fn->clk, fn->data, fn->done);
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
printf ("Loading FPGA Device %d...", cookie);
#endif
@@ -188,7 +188,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void
*buf, size_t bsize)
i --;
} while (i > 0);
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
putc ('.'); /* let them know we are
alive */
#endif
@@ -196,7 +196,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void
*buf, size_t bsize)
CONFIG_FPGA_DELAY ();
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
putc (' '); /* terminate the dotted line */
#endif
@@ -223,7 +223,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void
*buf, size_t bsize)
ret_val = FPGA_SUCCESS;
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
if (ret_val == FPGA_SUCCESS) {
puts ("Done.\n");
}
diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c
index 8ab7679b48f7..2be1c1a40a23 100644
--- a/drivers/fpga/cyclon2.c
+++ b/drivers/fpga/cyclon2.c
@@ -115,7 +115,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf,
size_t bsize)
"done:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->config, fn->status,
fn->write, fn->done);
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
printf ("Loading FPGA Device %d...", cookie);
#endif
@@ -153,13 +153,13 @@ static int CYC2_ps_load(Altera_desc *desc, const void
*buf, size_t bsize)
(*fn->abort) (cookie);
return FPGA_FAIL;
}
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
puts(" OK? ...");
#endif
CONFIG_FPGA_DELAY ();
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
putc (' '); /* terminate t
[U-Boot] [RFC PATCH 0/7] FPGA changes
Patches 1-3,5-6 are moving existing options to Kconfig. I haven't touched all the boards that use these options so they are still present in the whitelist. Hopefully someone more familiar with the zynq boards can build on top of these. Patches 4 and 7 are the functional changes I actually want to introduce. We have some boards where the FPGA images require the reverse bitstream mode. I think this may be some setting in the Xilinx tools but it seems to be permanently set in the images coming out of our hardware team. Chris Packham (7): fpga: CONFIG_SYS_FPGA_PROG_FEEDBACK -> CONFIG_FPGA_PROG_FEEDBACK fpga: add Kconfig support for Xilinx Spartan devices Move CONFIG_FPGA_SPARTAN options to defconfig fpga/spartan3: make output quieter fpga: add Kconfig for CONFIG_FPGA_PROG_FEEDBACK Move FPGA_PROG_FEEDBACK to defconfig fpga/spartan3: add reverse bitstream mode README | 2 +- board/astro/mcf5373l/fpga.c | 4 ++-- configs/PMC440_defconfig | 3 +++ configs/apf27_defconfig | 3 +++ configs/astro_mcf5373l_defconfig | 3 +++ configs/mt_ventoux_defconfig | 3 +++ configs/x600_defconfig | 2 ++ drivers/fpga/ACEX1K.c| 8 drivers/fpga/Kconfig | 24 drivers/fpga/cyclon2.c | 10 +- drivers/fpga/spartan2.c | 22 +++--- drivers/fpga/spartan3.c | 32 ++-- drivers/fpga/virtex2.c | 18 +- include/configs/M54455EVB.h | 2 +- include/configs/PMC440.h | 4 include/configs/apf27.h | 6 -- include/configs/astro_mcf5373l.h | 4 include/configs/mt_ventoux.h | 5 - include/configs/x600.h | 3 --- scripts/config_whitelist.txt | 2 +- 20 files changed, 94 insertions(+), 66 deletions(-) -- 2.10.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH 6/7] Move FPGA_PROG_FEEDBACK to defconfig
Signed-off-by: Chris Packham --- configs/apf27_defconfig | 1 + configs/astro_mcf5373l_defconfig | 1 + configs/mt_ventoux_defconfig | 1 + include/configs/apf27.h | 1 - include/configs/astro_mcf5373l.h | 1 - include/configs/mt_ventoux.h | 2 -- 6 files changed, 3 insertions(+), 4 deletions(-) diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig index f8f177ad56ce..4e0810a2064f 100644 --- a/configs/apf27_defconfig +++ b/configs/apf27_defconfig @@ -23,4 +23,5 @@ CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_SPARTAN3=y +CONFIG_FPGA_PROG_FEEDBACK=y CONFIG_OF_LIBFDT=y diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index 5ea1b66e5b2a..188a2ae6d0b7 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -11,3 +11,4 @@ CONFIG_CMD_I2C=y CONFIG_CMD_CACHE=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_SPARTAN3=y +CONFIG_FPGA_PROG_FEEDBACK=y diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig index d4e58395cf22..10e5ebc20945 100644 --- a/configs/mt_ventoux_defconfig +++ b/configs/mt_ventoux_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_SPARTAN3=y +CONFIG_FPGA_PROG_FEEDBACK=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_ULPI_VIEWPORT_OMAP=y diff --git a/include/configs/apf27.h b/include/configs/apf27.h index 00798fa1027f..df0dde0cdcd2 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -262,7 +262,6 @@ */ #define CONFIG_FPGA_COUNT 1 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ -#define CONFIG_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_CHECK_CTRLC #define CONFIG_SYS_FPGA_CHECK_ERROR diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index d5d6540ec9b9..e5eaec238af7 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -206,7 +206,6 @@ #define CONFIG_FPGA_COUNT 1 #define CONFIG_FPGA_ALTERA #define CONFIG_FPGA_CYCLON2 -#define CONFIG_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_WAIT 1000 /* End of user parameters to be customized */ diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h index b6198dbdf6d3..97fe785ef957 100644 --- a/include/configs/mt_ventoux.h +++ b/include/configs/mt_ventoux.h @@ -42,11 +42,9 @@ * FPGA */ #define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_WAIT 1 #define CONFIG_MAX_FPGA_DEVICES1 #define CONFIG_FPGA_DELAY() udelay(1) -#define CONFIG_FPGA_PROG_FEEDBACK #define CONFIG_SPLASH_SCREEN #define CONFIG_VIDEO_BMP_RLE8 -- 2.10.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH 2/7] fpga: add Kconfig support for Xilinx Spartan devices
Signed-off-by: Chris Packham --- drivers/fpga/Kconfig | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index f3f6bf7f6747..d137ab2df1d7 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -17,4 +17,15 @@ config FPGA_ZYNQMPPL Enable FPGA driver for loading bitstream in BIT and BIN format on Xilinx Zynq UltraScale+ (ZynqMP) device. +config FPGA_SPARTAN3 + bool "Enable Xilinx Spartan-III driver" + depends on FPGA_XILINX + help + Enable FPGA driver for Xilinx Spartan-III devices. + +config FPGA_SPARTAN2 + bool "Enable Xilinx Spartan-II driver" + depends on FPGA_XILINX + help + Enable FPGA driver for Xilinx Spartan-II devices. endmenu -- 2.10.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH 4/7] fpga/spartan3: make output quieter
Suppress some putc calls with CONFIG_SYS_FPGA_PROG_FEEDBACK.
Signed-off-by: Chris Packham
---
drivers/fpga/spartan3.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index 759ad95e2afc..34aa097ab6c2 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -428,7 +428,9 @@ static int spartan3_ss_load(xilinx_desc *desc, const void
*buf, size_t bsize)
CONFIG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie);/* Assert the
clock pin */
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
putc ('*');
+#endif
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {/*
check the time */
puts ("** Timeout waiting for DONE to
clear.\n");
@@ -436,7 +438,9 @@ static int spartan3_ss_load(xilinx_desc *desc, const void
*buf, size_t bsize)
break;
}
}
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
putc ('\n');/* terminate the dotted line */
+#endif
/*
* Run the post configuration function if there is one.
--
2.10.2
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[U-Boot] [RFC PATCH 5/7] fpga: add Kconfig for CONFIG_FPGA_PROG_FEEDBACK
Signed-off-by: Chris Packham --- drivers/fpga/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index d137ab2df1d7..1b3b03c8f938 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -28,4 +28,10 @@ config FPGA_SPARTAN2 depends on FPGA_XILINX help Enable FPGA driver for Xilinx Spartan-II devices. + +config FPGA_PROG_FEEDBACK + bool "FPGA programming feedback" + help + Enable printing of hash marks during FPGA configuration. + endmenu -- 2.10.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH 7/7] fpga/spartan3: add reverse bitstream mode
The Xilinx tools we use appear to give us a bitstream with the bits reversed (compared to what the existing code expects) add a new CONFIG_FPGA_REVERSE_BITSTREAM option which tells the spartan3 driver to output the serial stream with the leftmost bit first. Signed-off-by: Chris Packham --- drivers/fpga/Kconfig| 7 +++ drivers/fpga/spartan3.c | 8 2 files changed, 15 insertions(+) diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 1b3b03c8f938..26b7c864d275 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -29,6 +29,13 @@ config FPGA_SPARTAN2 help Enable FPGA driver for Xilinx Spartan-II devices. +config FPGA_REVERSE_BITSTREAM + bool "Reverse bitstream when programming" + depends on FPGA_SPARTAN3 + help + Some Xilinx tools generate programs that need to be uploaded LSb + first. Set this option if your fpga binary requires this. + config FPGA_PROG_FEEDBACK bool "FPGA programming feedback" help diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 34aa097ab6c2..2a57c8ab77b5 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -392,12 +392,20 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) (*fn->clk) (false, true, cookie); CONFIG_FPGA_DELAY (); /* Write data */ +#ifdef CONFIG_FPGA_REVERSE_BITSTREAM + (*fn->wr) ((val & 0x01), true, cookie); +#else (*fn->wr) ((val & 0x80), true, cookie); +#endif CONFIG_FPGA_DELAY (); /* Assert the clock */ (*fn->clk) (true, true, cookie); CONFIG_FPGA_DELAY (); +#ifdef CONFIG_FPGA_REVERSE_BITSTREAM + val >>= 1; +#else val <<= 1; +#endif i --; } while (i > 0); -- 2.10.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH 3/7] Move CONFIG_FPGA_SPARTAN options to defconfig
Signed-off-by: Chris Packham --- configs/PMC440_defconfig | 3 +++ configs/apf27_defconfig | 2 ++ configs/astro_mcf5373l_defconfig | 2 ++ configs/mt_ventoux_defconfig | 2 ++ configs/x600_defconfig | 2 ++ include/configs/PMC440.h | 4 include/configs/apf27.h | 5 - include/configs/astro_mcf5373l.h | 3 --- include/configs/mt_ventoux.h | 3 --- include/configs/x600.h | 3 --- 10 files changed, 11 insertions(+), 18 deletions(-) diff --git a/configs/PMC440_defconfig b/configs/PMC440_defconfig index cd2f0d2a5b4b..8a2e9c964e14 100644 --- a/configs/PMC440_defconfig +++ b/configs/PMC440_defconfig @@ -16,6 +16,9 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_SPARTAN3=y +CONFIG_FPGA_SPARTAN2=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig index a02e180d2f2c..f8f177ad56ce 100644 --- a/configs/apf27_defconfig +++ b/configs/apf27_defconfig @@ -21,4 +21,6 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_SPARTAN3=y CONFIG_OF_LIBFDT=y diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index 94e931eabadc..5ea1b66e5b2a 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -9,3 +9,5 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_SPARTAN3=y diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig index 9e330a7f44ca..d4e58395cf22 100644 --- a/configs/mt_ventoux_defconfig +++ b/configs/mt_ventoux_defconfig @@ -24,6 +24,8 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_SPARTAN3=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_ULPI_VIEWPORT_OMAP=y diff --git a/configs/x600_defconfig b/configs/x600_defconfig index 65b7d9565aac..0db6b5c6ba20 100644 --- a/configs/x600_defconfig +++ b/configs/x600_defconfig @@ -26,6 +26,8 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_UBI=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_SPARTAN3=y CONFIG_SYS_I2C_DW=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 2e7f6e480323..750f8447220c 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -343,10 +343,6 @@ /*--- * FPGA stuff *--*/ -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_SPARTAN2 -#define CONFIG_FPGA_SPARTAN3 #define CONFIG_FPGA_COUNT 2 /*--- diff --git a/include/configs/apf27.h b/include/configs/apf27.h index a97ba9f39c50..00798fa1027f 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -260,12 +260,7 @@ /* * FPGA */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_FPGA -#endif #define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_SPARTAN3 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ #define CONFIG_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_CHECK_CTRLC diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 0af356bcb49d..d5d6540ec9b9 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -204,9 +204,6 @@ #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE #define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA -#defineCONFIG_FPGA_XILINX -#defineCONFIG_FPGA_SPARTAN3 #define CONFIG_FPGA_ALTERA #define CONFIG_FPGA_CYCLON2 #define CONFIG_FPGA_PROG_FEEDBACK diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h index 1353b11b1250..b6198dbdf6d3 100644 --- a/include/configs/mt_ventoux.h +++ b/include/configs/mt_ventoux.h @@ -42,9 +42,6 @@ * FPGA */ #define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_SPARTAN3 #define CONFIG_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_WAIT 1 #define CONFIG_MAX_FPGA_DEVICES1 diff --git a/include/configs/x600.h b/include/configs/x600.h index 5e51f6535624..a879c4c7c113 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -96,9 +96,6 @@ #define CONFIG_SYS_I2C_RTC_ADDR0x68 /* FPGA config options */ -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_SPARTAN3 #define CONFIG_FPGA_COUNT 1 /* USB EHCI options */ -- 2.10.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] T2080 l2-cache-controller compatible string overwritten by ft_fixup_l2cache
Hi, I was just looking at what it would take to add the T2080 L2 cache to the mpc85xx_edac driver in Linux. At a cursory glance all the registers appear to be there so I figured I'd just add the appropriate entry to the of match table. To my surprise I found that the compatible string in my device tree was overwritten with "cache". I've tracked this down to the CONFIG_SYS_FSL_QORIQ_CHASSIS2 implementation of ft_fixup_l2cache in u-boot. The CONFIG_L2_CACHE version seems to take care to update the device tree node to compatible = "fsl,t2080-l2-cache-controller", "cache"; but the CONFIG_SYS_FSL_QORIQ_CHASSIS2 version just sets this to compatible = "cache"; Is this an over-site or is it intentional? Thanks, Chris ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 1/7] fpga: CONFIG_SYS_FPGA_PROG_FEEDBACK -> CONFIG_FPGA_PROG_FEEDBACK
(dropped addresses that we're bouncing from Cc, hope I got Jagans new address right). On Thu, Nov 24, 2016 at 1:09 AM, Michal Simek wrote: > On 22.11.2016 09:48, Chris Packham wrote: >> Prepare for move to Kconfig by removing "SYS" from the existing macros. >> >> Signed-off-by: Chris Packham >> --- > > This is breaking buildman. You should introduce Kconfig option in first > patch and than this one. > > [u-boot]$ ./tools/buildman/buildman apf27 -c 2 > boards.cfg is up to date. Nothing to do. > Building current source for 1 boards (1 thread, 8 jobs per thread) >arm: + apf27 ) > +comm: file 2 is not in sorted order > +Error: You must add new CONFIG options using Kconfig > +The following new ad-hoc CONFIG options were detected: > +CONFIG_FPGA_PROG_FEEDBACK > + > +Please add these via Kconfig instead. Find a suitable Kconfig > +file and add a 'config' or 'menuconfig' option. > +make[1]: *** [all] Error 1 > +make: *** [sub-make] Error 2 > 001 /1 apf27 So I agree that this should probably be closer to the other two patches. But won't I have the same problem either way. Unless I squash this with "Move FPGA_PROG_FEEDBACK to defconfig" which I can do Is that acceptable to everyone. > > Thanks, > Michal > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 5/7] fpga: add Kconfig for CONFIG_FPGA_PROG_FEEDBACK
On Thu, Nov 24, 2016 at 1:13 AM, Michal Simek wrote: > On 22.11.2016 09:49, Chris Packham wrote: >> Signed-off-by: Chris Packham >> --- >> >> drivers/fpga/Kconfig | 6 ++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig >> index d137ab2df1d7..1b3b03c8f938 100644 >> --- a/drivers/fpga/Kconfig >> +++ b/drivers/fpga/Kconfig >> @@ -28,4 +28,10 @@ config FPGA_SPARTAN2 >> depends on FPGA_XILINX >> help >> Enable FPGA driver for Xilinx Spartan-II devices. >> + >> +config FPGA_PROG_FEEDBACK >> + bool "FPGA programming feedback" >> + help >> + Enable printing of hash marks during FPGA configuration. >> + >> endmenu >> > > I would prefer if you can add depends on here because this feature is > not available on newer drivers. > > It means you have to add some Kconfig things for cyclone. Cyclone, virtex and ACEX1K. I'll see if can do it. Guess I need to start playing with buildman (and/or travis). > > Thanks, > Michal > > > -- > Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 > w: www.monstr.eu p: +42-0-721842854 > Maintainer of Linux kernel - Xilinx Microblaze > Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs > U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 3/7] Move CONFIG_FPGA_SPARTAN options to defconfig
On Thu, Nov 24, 2016 at 1:14 AM, Michal Simek wrote: > On 22.11.2016 09:48, Chris Packham wrote: >> Signed-off-by: Chris Packham >> --- > > Isn't this causing some compilation issue for SPL case? > I have compile tested apf27 and didn't see an issue. I'm guessing none of the FPGA infrastructure is available in SPL. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 3/7] Move CONFIG_FPGA_SPARTAN options to defconfig
On Fri, Nov 25, 2016 at 1:53 PM, Chris Packham wrote: > On Thu, Nov 24, 2016 at 1:14 AM, Michal Simek wrote: >> On 22.11.2016 09:48, Chris Packham wrote: >>> Signed-off-by: Chris Packham >>> --- >> >> Isn't this causing some compilation issue for SPL case? >> > > I have compile tested apf27 and didn't see an issue. I'm guessing none > of the FPGA infrastructure is available in SPL. A better non-guess answer is that yes indeed all of drivers/fgpa is not included in SPL. But CONFIG_FPGA now ends up defined and nm tells me I've probably broken that board nm spl/u-boot-spl | grep fpga_init U fpga_init So how is this usually handled? I can surround the code in board/armadeus/apf27 with #ifndef CONFIG_SPL_BUILD but that seems kind of hacky. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arch: powerpc: Retain compatible property for L2 cache
Instead of setting the compatible property to "cache", append the
desired value retaining what may already be set in the current property.
Signed-off-by: Chris Packham
---
On Thu, Nov 24, 2016 at 6:41 AM, york sun wrote:
> On 11/23/2016 01:43 AM, Chris Packham wrote:
>> Hi,
>>
>> I was just looking at what it would take to add the T2080 L2 cache to
>> the mpc85xx_edac driver in Linux. At a cursory glance all the
>> registers appear to be there so I figured I'd just add the
>> appropriate
>> entry to the of match table.
>>
>> To my surprise I found that the compatible string in my device tree
>> was overwritten with "cache". I've tracked this down to the
>> CONFIG_SYS_FSL_QORIQ_CHASSIS2 implementation of ft_fixup_l2cache in
>> u-boot.
>>
>> The CONFIG_L2_CACHE version seems to take care to update the device
>> tree node to
>>
>> compatible = "fsl,t2080-l2-cache-controller", "cache";
>>
>> but the CONFIG_SYS_FSL_QORIQ_CHASSIS2 version just sets this to
>>
>> compatible = "cache";
>>
>> Is this an over-site or is it intentional?
>>
>
> I don't have any record of this discussion. Kumar wrote and committed
> this change. I hope he remembers.
>
Here's a patch that retains the compatible property from the
original dtb and adds the "cache" value if required. This gets
the value I need through to the kernel.
arch/powerpc/cpu/mpc85xx/fdt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 047c972ac78e..f31df41836d5 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -337,7 +337,8 @@ static inline void ft_fixup_l2cache(void *blob)
fdt_setprop_cell(blob, l2_off, "cache-size", size);
fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
fdt_setprop_cell(blob, l2_off, "cache-level", 2);
- fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+ if (fdt_node_check_compatible(blob, l2_off, "cache") ==
1)
+ fdt_appendprop_string(blob, l2_off,
"compatible", "cache");
}
if (l3_off < 0) {
--
2.10.2
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[U-Boot] [PATCH] powerpc: Retain compatible property for L2 cache
Instead of setting the compatible property to "cache", append the
desired value retaining what may already be set in the current property.
Signed-off-by: Chris Packham
---
On Thu, Nov 24, 2016 at 6:41 AM, york sun wrote:
> On 11/23/2016 01:43 AM, Chris Packham wrote:
>> Hi,
>>
>> I was just looking at what it would take to add the T2080 L2 cache to
>> the mpc85xx_edac driver in Linux. At a cursory glance all the
>> registers appear to be there so I figured I'd just add the
>> appropriate
>> entry to the of match table.
>>
>> To my surprise I found that the compatible string in my device tree
>> was overwritten with "cache". I've tracked this down to the
>> CONFIG_SYS_FSL_QORIQ_CHASSIS2 implementation of ft_fixup_l2cache in
>> u-boot.
>>
>> The CONFIG_L2_CACHE version seems to take care to update the device
>> tree node to
>>
>> compatible = "fsl,t2080-l2-cache-controller", "cache";
>>
>> but the CONFIG_SYS_FSL_QORIQ_CHASSIS2 version just sets this to
>>
>> compatible = "cache";
>>
>> Is this an over-site or is it intentional?
>>
>
> I don't have any record of this discussion. Kumar wrote and committed
> this change. I hope he remembers.
>
(re-sent because I flubbed the subject line and got bounced for Ccing
all arch mainatiners, sorry for the spam)
Here's a patch that retains the compatible property from the
original dtb and adds the "cache" value if required. This gets
the value I need through to the kernel.
If it helps this is also consistent with the Linux documentation for
this binding[1] which states that the compatible property should have
both "-l2-cache-controller" and "cache" as values
[1] - Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt
arch/powerpc/cpu/mpc85xx/fdt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 047c972ac78e..f31df41836d5 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -337,7 +337,8 @@ static inline void ft_fixup_l2cache(void *blob)
fdt_setprop_cell(blob, l2_off, "cache-size", size);
fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
fdt_setprop_cell(blob, l2_off, "cache-level", 2);
- fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+ if (fdt_node_check_compatible(blob, l2_off, "cache") ==
1)
+ fdt_appendprop_string(blob, l2_off,
"compatible", "cache");
}
if (l3_off < 0) {
--
2.10.2
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Re: [U-Boot] [PATCH] powerpc: Retain compatible property for L2 cache
On Thu, Dec 1, 2016 at 6:18 AM, york sun wrote:
> On 11/28/2016 07:10 PM, Chris Packham wrote:
>> Instead of setting the compatible property to "cache", append the
>> desired value retaining what may already be set in the current property.
>>
>> Signed-off-by: Chris Packham
>> ---
>
>
>
>>
>> arch/powerpc/cpu/mpc85xx/fdt.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
>> index 047c972ac78e..f31df41836d5 100644
>> --- a/arch/powerpc/cpu/mpc85xx/fdt.c
>> +++ b/arch/powerpc/cpu/mpc85xx/fdt.c
>> @@ -337,7 +337,8 @@ static inline void ft_fixup_l2cache(void *blob)
>> fdt_setprop_cell(blob, l2_off, "cache-size", size);
>> fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
>> fdt_setprop_cell(blob, l2_off, "cache-level", 2);
>> - fdt_setprop(blob, l2_off, "compatible", "cache", 6);
>> + if (fdt_node_check_compatible(blob, l2_off, "cache")
>> == 1)
>> + fdt_appendprop_string(blob, l2_off,
>> "compatible", "cache");
>> }
>>
>> if (l3_off < 0) {
>>
>
> You drop fdt_setprop, check the compatible "cache" and append it with
> "cache" again? I thought you wanted
>
> compatible = "fsl,t2080-l2-cache-controller", "cache";
I already have "fsl,t2080-l2-cache-controller" in my dts. Really I just want
fdt_appendprop_string(blob, l2_off, "compatible", "cache");
But the check is necessary because we run through this block multiple
times (once per CPU). My initial version was
struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
int len;
char buf[40];
len = sprintf(buf,
"fsl,%c%s-l2-cache-controller",tolower(cpu->name[0]), cpu->name + 1) +
1;
len += sprintf(buf + len, "cache") + 1;
fdt_setprop(blob, l2_off, "compatible", buf, len);
But that's more code.
>
> York
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Re: [U-Boot] [PATCH] mpc85xx: pci: Implement workaround for Erratum A007815
(adding York)
On Thu, Dec 1, 2016 at 4:20 PM, Tony O'Brien
wrote:
> The read-only-write-enable bit is set by default and must be cleared
> to prevent overwriting read-only registers. This should be done
> immediately after resetting the PCI Express controller.
>
> Reviewed-by: Hamish Martin
>
> ---
> Note that this does not implement the whole fix for this erratum,
> just what is necessary for our implementation. Since we are using a
> fixed RC configuration, no support has been added for EP mode or any
> consideration of link-up/down events.
>
> Signed-off-by: Tony O'Brien
> ---
> arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++
> arch/powerpc/include/asm/config_mpc85xx.h | 1 +
> arch/powerpc/include/asm/fsl_pci.h| 4 +++-
> drivers/pci/fsl_pci_init.c| 7 +++
> 4 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> index 402a1ff..aabb56b 100644
> --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> @@ -330,6 +330,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int
> argc, char * const argv[])
> #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
> puts("Work-around for Erratum A009663 enabled\n");
> #endif
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
> + puts("Work-around for Erratum A007815 enabled\n");
> +#endif
>
> return 0;
> }
> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
> b/arch/powerpc/include/asm/config_mpc85xx.h
> index c92bc1e..c298e44 100644
> --- a/arch/powerpc/include/asm/config_mpc85xx.h
> +++ b/arch/powerpc/include/asm/config_mpc85xx.h
> @@ -785,6 +785,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
> #define CONFIG_SYS_FSL_ERRATUM_A006593
> #define CONFIG_SYS_FSL_ERRATUM_A007186
> #define CONFIG_SYS_FSL_ERRATUM_A006379
> +#define CONFIG_SYS_FSL_ERRATUM_A007815
> #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
> #define CONFIG_SYS_FSL_SFP_VER_3_0
>
> diff --git a/arch/powerpc/include/asm/fsl_pci.h
> b/arch/powerpc/include/asm/fsl_pci.h
> index 8bee8ca..cad341e 100644
> --- a/arch/powerpc/include/asm/fsl_pci.h
> +++ b/arch/powerpc/include/asm/fsl_pci.h
> @@ -79,7 +79,9 @@ typedef struct ccsr_pci {
> u32 pme_msg_dis;/* 0x024 - PCIE PME & message disable
> register */
> u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt
> enable register */
> u32 pm_command; /* 0x02c - PCIE PM Command register */
> - charres4[3016]; /* (- #xbf8 #x30)3016 */
> + charres3[2188]; /* (0x8bc - 0x30 = 2188) */
> + u32 dbi_ro_wr_en; /* 0x8bc - DBI read only write enable reg */
> + charres4[824]; /* (0xbf8 - 0x8c0 = 824) */
> u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */
> u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */
>
> diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
> index 52792dc..af20cf0 100644
> --- a/drivers/pci/fsl_pci_init.c
> +++ b/drivers/pci/fsl_pci_init.c
> @@ -543,6 +543,13 @@ void fsl_pci_init(struct pci_controller *hose, struct
> fsl_pci_info *pci_info)
> pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
> }
>
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
> + /* The Read-Only Write Enable bit defaults to 1 instead of 0.
> +* Set to 0 to protect the read-only registers.
> +*/
> + clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
> +#endif
> +
> /* Use generic setup_device to initialize standard pci regs,
> * but do not allocate any windows since any BAR found (such
> * as PCSRBAR) is not in this cpu's memory space.
> --
> 2.10.2
>
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Re: [U-Boot] [PATCH] powerpc: Retain compatible property for L2 cache
On 2/12/2016 6:34 AM, "york sun" wrote:
>
> On 11/30/2016 11:47 PM, Chris Packham wrote:
> > On Thu, Dec 1, 2016 at 6:18 AM, york sun wrote:
> >> On 11/28/2016 07:10 PM, Chris Packham wrote:
> >>> Instead of setting the compatible property to "cache", append the
> >>> desired value retaining what may already be set in the current
property.
> >>>
> >>> Signed-off-by: Chris Packham
> >>> ---
> >>
> >>
> >>
> >>>
> >>> arch/powerpc/cpu/mpc85xx/fdt.c | 3 ++-
> >>> 1 file changed, 2 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c
b/arch/powerpc/cpu/mpc85xx/fdt.c
> >>> index 047c972ac78e..f31df41836d5 100644
> >>> --- a/arch/powerpc/cpu/mpc85xx/fdt.c
> >>> +++ b/arch/powerpc/cpu/mpc85xx/fdt.c
> >>> @@ -337,7 +337,8 @@ static inline void ft_fixup_l2cache(void *blob)
> >>> fdt_setprop_cell(blob, l2_off, "cache-size",
size);
> >>> fdt_setprop_cell(blob, l2_off, "cache-sets",
num_sets);
> >>> fdt_setprop_cell(blob, l2_off, "cache-level",
2);
> >>> - fdt_setprop(blob, l2_off, "compatible",
"cache", 6);
> >>> + if (fdt_node_check_compatible(blob, l2_off,
"cache") == 1)
> >>> + fdt_appendprop_string(blob, l2_off,
"compatible", "cache");
> >>> }
> >>>
> >>> if (l3_off < 0) {
> >>>
> >>
> >> You drop fdt_setprop, check the compatible "cache" and append it with
> >> "cache" again? I thought you wanted
> >>
> >> compatible = "fsl,t2080-l2-cache-controller", "cache";
> >
> > I already have "fsl,t2080-l2-cache-controller" in my dts. Really I just
want
> >
> >fdt_appendprop_string(blob, l2_off, "compatible", "cache");
>
> I see.
>
> >
> > But the check is necessary because we run through this block multiple
> > times (once per CPU). My initial version was
> >
> > struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
> > int len;
> > char buf[40];
> >
> > len = sprintf(buf,
> > "fsl,%c%s-l2-cache-controller",tolower(cpu->name[0]), cpu->name + 1) +
> > 1;
> > len += sprintf(buf + len, "cache") + 1;
> >
> > fdt_setprop(blob, l2_off, "compatible", buf, len);
> >
> > But that's more code.
> >
>
> Ideally we don't have to fix up dts. Since if we have to do it, I like
> the long version better. If the dts doesn't have correct compatible, the
> kernel won't take it, right?
>
Ok. I'll post a v2 based on the long version. As it's a repeat of code in
another block I'll see if i can extract it to a helper function.
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[U-Boot] [PATCH v2] powerpc: Retain compatible property for L2 cache
When setting the compatible property for the L2 cache ensure that we
follow the documented binding by setting both
"-l2-cache-controller" and "cache" as values.
Signed-off-by: Chris Packham
---
Changes in v2:
- extract a helper function to set the compatible property and use it in
both the CONFIG_L2_CACHE and CONFIG_BACKSIDE_L2_CACHE cases.
arch/powerpc/cpu/mpc85xx/fdt.c | 61 +-
1 file changed, 36 insertions(+), 25 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 047c972ac78e..8aaf53a65458 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -180,6 +180,39 @@ static inline void ft_fixup_l3cache(void *blob, int off)
#define ft_fixup_l3cache(x, y)
#endif
+#if defined(CONFIG_L2_CACHE) || \
+ defined(CONFIG_BACKSIDE_L2_CACHE) || \
+ defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+static inline void ft_fixup_l2cache_compatible(void *blob, int off)
+{
+ int len;
+ struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
+
+ if (cpu) {
+ char buf[40];
+
+ if (isdigit(cpu->name[0])) {
+ /* MPC, where == 4-digit number */
+ len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
+ cpu->name) + 1;
+ } else {
+ /* P or T, where == 4-digit number */
+ len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
+ tolower(cpu->name[0]), cpu->name + 1) + 1;
+ }
+
+ /*
+* append "cache" after the NULL character that the previous
+* sprintf wrote. This is how a device tree stores multiple
+* strings in a property.
+*/
+ len += sprintf(buf + len, "cache") + 1;
+
+ fdt_setprop(blob, off, "compatible", buf, len);
+ }
+}
+#endif
+
#if defined(CONFIG_L2_CACHE)
/* return size in kilobytes */
static inline u32 l2cache_size(void)
@@ -215,9 +248,8 @@ static inline u32 l2cache_size(void)
static inline void ft_fixup_l2cache(void *blob)
{
- int len, off;
+ int off;
u32 *ph;
- struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
const u32 line_size = 32;
const u32 num_ways = 8;
@@ -243,28 +275,7 @@ static inline void ft_fixup_l2cache(void *blob)
return ;
}
- if (cpu) {
- char buf[40];
-
- if (isdigit(cpu->name[0])) {
- /* MPC, where == 4-digit number */
- len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
- cpu->name) + 1;
- } else {
- /* P or T, where == 4-digit number */
- len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
- tolower(cpu->name[0]), cpu->name + 1) + 1;
- }
-
- /*
-* append "cache" after the NULL character that the previous
-* sprintf wrote. This is how a device tree stores multiple
-* strings in a property.
-*/
- len += sprintf(buf + len, "cache") + 1;
-
- fdt_setprop(blob, off, "compatible", buf, len);
- }
+ ft_fixup_l2cache_compatible(blob, off);
fdt_setprop(blob, off, "cache-unified", NULL, 0);
fdt_setprop_cell(blob, off, "cache-block-size", line_size);
fdt_setprop_cell(blob, off, "cache-size", size);
@@ -337,7 +348,7 @@ static inline void ft_fixup_l2cache(void *blob)
fdt_setprop_cell(blob, l2_off, "cache-size", size);
fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
fdt_setprop_cell(blob, l2_off, "cache-level", 2);
- fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+ ft_fixup_l2cache_compatible(blob, l2_off);
}
if (l3_off < 0) {
--
2.10.2
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[U-Boot] [RESEND PATCH v2] powerpc: Retain compatible property for L2 cache
When setting the compatible property for the L2 cache ensure that we
follow the documented binding by setting both
"-l2-cache-controller" and "cache" as values.
Signed-off-by: Chris Packham
---
Changes in v2:
- extract a helper function to set the compatible property and use it in
both the CONFIG_L2_CACHE and CONFIG_BACKSIDE_L2_CACHE cases.
arch/powerpc/cpu/mpc85xx/fdt.c | 61 +-
1 file changed, 36 insertions(+), 25 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 12001f85e9fd..67140ba9ee18 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -180,6 +180,39 @@ static inline void ft_fixup_l3cache(void *blob, int off)
#define ft_fixup_l3cache(x, y)
#endif
+#if defined(CONFIG_L2_CACHE) || \
+ defined(CONFIG_BACKSIDE_L2_CACHE) || \
+ defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+static inline void ft_fixup_l2cache_compatible(void *blob, int off)
+{
+ int len;
+ struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
+
+ if (cpu) {
+ char buf[40];
+
+ if (isdigit(cpu->name[0])) {
+ /* MPC, where == 4-digit number */
+ len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
+ cpu->name) + 1;
+ } else {
+ /* P or T, where == 4-digit number */
+ len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
+ tolower(cpu->name[0]), cpu->name + 1) + 1;
+ }
+
+ /*
+* append "cache" after the NULL character that the previous
+* sprintf wrote. This is how a device tree stores multiple
+* strings in a property.
+*/
+ len += sprintf(buf + len, "cache") + 1;
+
+ fdt_setprop(blob, off, "compatible", buf, len);
+ }
+}
+#endif
+
#if defined(CONFIG_L2_CACHE)
/* return size in kilobytes */
static inline u32 l2cache_size(void)
@@ -215,9 +248,8 @@ static inline u32 l2cache_size(void)
static inline void ft_fixup_l2cache(void *blob)
{
- int len, off;
+ int off;
u32 *ph;
- struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
const u32 line_size = 32;
const u32 num_ways = 8;
@@ -243,28 +275,7 @@ static inline void ft_fixup_l2cache(void *blob)
return ;
}
- if (cpu) {
- char buf[40];
-
- if (isdigit(cpu->name[0])) {
- /* MPC, where == 4-digit number */
- len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
- cpu->name) + 1;
- } else {
- /* P or T, where == 4-digit number */
- len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
- tolower(cpu->name[0]), cpu->name + 1) + 1;
- }
-
- /*
-* append "cache" after the NULL character that the previous
-* sprintf wrote. This is how a device tree stores multiple
-* strings in a property.
-*/
- len += sprintf(buf + len, "cache") + 1;
-
- fdt_setprop(blob, off, "compatible", buf, len);
- }
+ ft_fixup_l2cache_compatible(blob, off);
fdt_setprop(blob, off, "cache-unified", NULL, 0);
fdt_setprop_cell(blob, off, "cache-block-size", line_size);
fdt_setprop_cell(blob, off, "cache-size", size);
@@ -337,7 +348,7 @@ static inline void ft_fixup_l2cache(void *blob)
fdt_setprop_cell(blob, l2_off, "cache-size", size);
fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
fdt_setprop_cell(blob, l2_off, "cache-level", 2);
- fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+ ft_fixup_l2cache_compatible(blob, l2_off);
}
if (l3_off < 0) {
--
2.11.0.24.ge6920cf
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[U-Boot] [PATCH] lib: net_utils: make string_to_ip stricter
Previously values greater than 255 were implicitly truncated. Add some
stricter checking to reject addresses with components >255.
With the input "1234192.168.1.1" the old behaviour would truncate the
address to 192.168.1.1. New behaviour rejects the string outright and
returns 0.0.0.0, which for the purposes of IP addresses can be
considered an error.
Signed-off-by: Chris Packham
---
This was part of my long running IPv6 patchset (which I promise I'll get
back to someday). But I feel this stands on it's own merits.
lib/net_utils.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/lib/net_utils.c b/lib/net_utils.c
index cfae84275241..f148b8a70a7d 100644
--- a/lib/net_utils.c
+++ b/lib/net_utils.c
@@ -24,11 +24,16 @@ struct in_addr string_to_ip(const char *s)
for (addr.s_addr = 0, i = 0; i < 4; ++i) {
ulong val = s ? simple_strtoul(s, &e, 10) : 0;
+ if (val > 255) {
+ addr.s_addr = 0;
+ return addr;
+ }
addr.s_addr <<= 8;
addr.s_addr |= (val & 0xFF);
- if (s) {
- s = (*e) ? e+1 : e;
- }
+ if (*e == '.')
+ s = e + 1;
+ else
+ break;
}
addr.s_addr = htonl(addr.s_addr);
--
2.11.0.24.ge6920cf
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Re: [U-Boot] [RESEND PATCH v2] powerpc: Retain compatible property for L2 cache
Hi York, On Tue, Dec 20, 2016 at 6:14 AM, york sun wrote: > On 12/18/2016 11:26 PM, Chris Packham wrote: >> When setting the compatible property for the L2 cache ensure that we >> follow the documented binding by setting both >> "-l2-cache-controller" and "cache" as values. >> >> Signed-off-by: Chris Packham >> --- >> >> Changes in v2: >> - extract a helper function to set the compatible property and use it in >> both the CONFIG_L2_CACHE and CONFIG_BACKSIDE_L2_CACHE cases. > > I guess you meant to remind me about this patch. It is not forgotten. > Actually it is in my test queue. I planned to merge it after another > round of 85xx Kconfig change. I will see if I can merge this one sooner. > Yes. It was mainly because I saw a pull request for mpc85xx and I hadn't seen any feedback (positive or negative) on the most recent change set. No need to accelerate your process if it's in the queue. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] lib: net_utils: make string_to_ip stricter
On Mon, Dec 26, 2016 at 6:23 PM, Simon Glass wrote:
> Hi Chris,
>
> On 20 December 2016 at 11:01, Chris Packham wrote:
>> Previously values greater than 255 were implicitly truncated. Add some
>> stricter checking to reject addresses with components >255.
>>
>> With the input "1234192.168.1.1" the old behaviour would truncate the
>> address to 192.168.1.1. New behaviour rejects the string outright and
>> returns 0.0.0.0, which for the purposes of IP addresses can be
>> considered an error.
>>
>> Signed-off-by: Chris Packham
>> ---
>> This was part of my long running IPv6 patchset (which I promise I'll get
>> back to someday). But I feel this stands on it's own merits.
>>
>> lib/net_utils.c | 11 ---
>> 1 file changed, 8 insertions(+), 3 deletions(-)
>>
>> diff --git a/lib/net_utils.c b/lib/net_utils.c
>> index cfae84275241..f148b8a70a7d 100644
>> --- a/lib/net_utils.c
>> +++ b/lib/net_utils.c
>> @@ -24,11 +24,16 @@ struct in_addr string_to_ip(const char *s)
>>
>> for (addr.s_addr = 0, i = 0; i < 4; ++i) {
>> ulong val = s ? simple_strtoul(s, &e, 10) : 0;
>> + if (val > 255) {
>> + addr.s_addr = 0;
>> + return addr;
>> + }
>> addr.s_addr <<= 8;
>> addr.s_addr |= (val & 0xFF);
>> - if (s) {
>> - s = (*e) ? e+1 : e;
>> - }
>> + if (*e == '.')
>> + s = e + 1;
>> + else
>> + break;
>
> This change seems to be unrelated. Should it be a separate commit?
I should at least mention it's purpose in the commit message. It
ensures that '.' is used as a separator and not some other arbitrary
ascii character.
> Also, what happens with '192.168.4' with this change?
>
Good point. I think it would be parsed as 0.192.168.4 which is clearly
wrong. The else should probably set s_addr to 0 to flag the error.
>> }
>>
>> addr.s_addr = htonl(addr.s_addr);
>> --
>> 2.11.0.24.ge6920cf
>>
>
> Regards,
> Simon
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Re: [U-Boot] [PATCH v2 3/3] configs: kirkwood: Move RTC_MV to DM and Kconfig
On Tue, Aug 7, 2018 at 12:12 AM Stefan Roese wrote: > > Hi Chris, > > On 29.06.2018 00:38, Chris Packham wrote: > > Now that there is DM support in the RTC_MV driver update board configs > > to use it. > > > > Signed-off-by: Chris Packham > > I'm a bit late this time in the release cycle. This one does not apply > any more to master. Could you please rebase this patch and send a new > version (or the series)? Will do. Should be pretty straight forward. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/3] configs: kirkwood: ds109: switch to DM_I2C
Enable DM_I2C and I2C_MVTSWI for the ds109 board. Signed-off-by: Chris Packham --- Changes in v3: None Changes in v2: - new configs/ds109_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index c9207433b374..fd10e6e3c36e 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -18,6 +18,8 @@ CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MVSATA_IDE=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 3/3] configs: kirkwood: Move RTC_MV to DM and Kconfig
Now that there is DM support in the RTC_MV driver update board configs to use it. Signed-off-by: Chris Packham --- I haven't removed this from the whitelist because the nsa310s board lacks device-tree support. Once that board is converted the non-DM code can be removed from RTC_MV and the whitelist updated. Changes in v3: - rebase against u-boot#master Changes in v2: None configs/SBx81LIFKW_defconfig | 2 ++ configs/dns325_defconfig | 5 - configs/dreamplug_defconfig | 5 - configs/ds109_defconfig | 5 - configs/goflexhome_defconfig | 5 - configs/guruplug_defconfig | 5 - configs/nas220_defconfig | 5 - configs/sheevaplug_defconfig | 5 - include/configs/SBx81LIFKW.h | 5 - include/configs/dns325.h | 7 --- include/configs/dreamplug.h | 4 include/configs/ds109.h | 4 include/configs/goflexhome.h | 7 --- include/configs/guruplug.h | 4 include/configs/nas220.h | 7 --- include/configs/sheevaplug.h | 4 16 files changed, 30 insertions(+), 49 deletions(-) diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index 348f861a143b..c786120e7fd4 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -35,5 +35,7 @@ CONFIG_MV88E61XX_SWITCH=y CONFIG_MV88E61XX_CPU_PORT=10 CONFIG_MV88E61XX_PHY_PORTS=0x003 CONFIG_MV88E61XX_FIXED_PORTS=0x300 +CONFIG_DM_RTC=y +CONFIG_RTC_MV=y CONFIG_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index f0ed20992887..d77f7766ee92 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x60 CONFIG_TARGET_DNS325=y CONFIG_IDENT_STRING="\nD-Link DNS-325" CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dns325" +# CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_BOARDINFO is not set @@ -16,7 +17,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y @@ -26,10 +26,13 @@ CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM=y CONFIG_MVSATA_IDE=y # CONFIG_MMC is not set CONFIG_NETDEVICES=y CONFIG_MVGBE=y +CONFIG_DM_RTC=y +CONFIG_RTC_MV=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 8090c9a37793..d7428ae9cd9e 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x60 CONFIG_TARGET_DREAMPLUG=y CONFIG_IDENT_STRING="\nMarvell-DreamPlug" CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dreamplug" +# CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y @@ -15,19 +16,21 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y CONFIG_MVSATA_IDE=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_NETDEVICES=y CONFIG_MVGBE=y +CONFIG_DM_RTC=y +CONFIG_RTC_MV=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index fd10e6e3c36e..6428614c93c3 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x60 CONFIG_TARGET_DS109=y CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ds109" +# CONFIG_SYS_MALLOC_F is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y @@ -12,11 +13,11 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_FAT=y CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y CONFIG_MVSATA_IDE=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y @@ -26,6 +27,8 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_MVGBE=y +CONFIG_DM_RTC=y +CONFIG_RTC_MV=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index c0894c05ea4b..41d896a72504 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x60 CONFIG_TARGET_GOFLEXHOME=y CONFIG_IDENT_STRING="\nSeagate GoFlex Home" CONFIG_DEFAULT_DEVICE_TREE="kirkwood-goflexnet" +# CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_BOARDINFO is not set @@ -16,7 +17,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y @@ -27,10 +27,13 @@ CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y
[U-Boot] [PATCH v3 2/3] configs: move RTC_MV config from mv-plug-common.h to boards
To aid in migrating CONFIG_RTC_MV to Kconfig move the definition of it from mv-plug-common.h to the board config headers that nest it. Signed-off-by: Chris Packham --- Changes in v3: None Changes in v2: None include/configs/dreamplug.h | 4 include/configs/ds109.h | 4 include/configs/guruplug.h | 4 include/configs/mv-plug-common.h | 7 --- include/configs/sheevaplug.h | 4 5 files changed, 16 insertions(+), 7 deletions(-) diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 1c94bf9fa1bf..742232d2d660 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -27,6 +27,10 @@ */ #include "mv-plug-common.h" +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + /* * Environment variables configurations */ diff --git a/include/configs/ds109.h b/include/configs/ds109.h index c06f0058deb5..f8d663714239 100644 --- a/include/configs/ds109.h +++ b/include/configs/ds109.h @@ -30,6 +30,10 @@ */ #include "mv-plug-common.h" +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + /* * Environment variables configurations */ diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index 739ab320f637..3ce021abea84 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -25,6 +25,10 @@ */ #include "mv-plug-common.h" +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + /* * Environment variables configurations */ diff --git a/include/configs/mv-plug-common.h b/include/configs/mv-plug-common.h index 81c07a889a36..f424e2cc6c52 100644 --- a/include/configs/mv-plug-common.h +++ b/include/configs/mv-plug-common.h @@ -22,11 +22,4 @@ */ #include "mv-common.h" -/* - * RTC driver configuration - */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_MV -#endif /* CONFIG_CMD_DATE */ - #endif /* _CONFIG_MARVELL_PLUG_H */ diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index deec71734dc7..12e38b3f12dc 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -29,6 +29,10 @@ */ #include "mv-plug-common.h" +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + /* * Environment variables configurations */ -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] tools: kwboot: Make kwboot more robust on a38x
Hi Baruch, Jon,
On Tue, Aug 14, 2018 at 3:25 AM Baruch Siach wrote:
>
> From: Jon Nettleton
>
> This patch accomplishes 2 things to make the kwboot procedure
> on the a38x more reliable.
>
> 1) We fill the tty with 1K of the magic bootparam. This helps
> with the timing of where the microcode picks up in the read of
> the line to ensure we actually catch the break to go into recovery
> mode
>
> 2) Before starting the xmodem transfer we sleep for 2 seconds
> and then flush the line. This allows all the magic bootparam
> to be flushed from the line and makes the xmodem transfer reliable
> and removes the Bad message failures.
>
> Signed-off-by: Jon Nettleton
> Signed-off-by: Baruch Siach
> ---
Reviewed-by: Chris Packham
Lately I haven't had much luck with using kwboot on a38x. I seem to be
able to get the spl to boot from uart (even better now thanks to this
patch) but the next stage still loads from SPI. I haven't been brave
enough to blank a board to see if that changes behaviour. Are your
experiences any different? I'm wondering if there is something we need
to do in the SPL to figure out that we need to load the next stage via
xmodem.
> tools/kwboot.c | 14 ++
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/tools/kwboot.c b/tools/kwboot.c
> index 50ae2b4b77b1..4be094c9c8d8 100644
> --- a/tools/kwboot.c
> +++ b/tools/kwboot.c
> @@ -286,6 +286,7 @@ kwboot_bootmsg(int tty, void *msg)
> {
> int rc;
> char c;
> + int count;
>
> if (msg == NULL)
> kwboot_printv("Please reboot the target into UART boot
> mode...");
> @@ -297,10 +298,12 @@ kwboot_bootmsg(int tty, void *msg)
> if (rc)
> break;
>
> - rc = kwboot_tty_send(tty, msg, 8);
> - if (rc) {
> - usleep(msg_req_delay * 1000);
> - continue;
> + for (count = 0; count < 128; count++) {
> + rc = kwboot_tty_send(tty, msg, 8);
> + if (rc) {
> + usleep(msg_req_delay * 1000);
> + continue;
> + }
> }
>
> rc = kwboot_tty_recv(tty, &c, 1, msg_rsp_timeo);
> @@ -426,6 +429,9 @@ kwboot_xmodem(int tty, const void *_data, size_t size)
>
> kwboot_printv("Sending boot image...\n");
>
> + sleep(2); /* flush isn't effective without it */
> + tcflush(tty, TCIOFLUSH);
> +
> do {
> struct kwboot_block block;
> int n;
> --
> 2.18.0
>
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Re: [U-Boot] [PATCH] tools: kwboot: Make kwboot more robust on a38x
On Thu, Aug 16, 2018 at 8:38 PM Baruch Siach wrote: > > Hi Chris, > > Chris Packham writes: > > On Tue, Aug 14, 2018 at 3:25 AM Baruch Siach wrote: > >> From: Jon Nettleton > >> > >> This patch accomplishes 2 things to make the kwboot procedure > >> on the a38x more reliable. > >> > >> 1) We fill the tty with 1K of the magic bootparam. This helps > >> with the timing of where the microcode picks up in the read of > >> the line to ensure we actually catch the break to go into recovery > >> mode > >> > >> 2) Before starting the xmodem transfer we sleep for 2 seconds > >> and then flush the line. This allows all the magic bootparam > >> to be flushed from the line and makes the xmodem transfer reliable > >> and removes the Bad message failures. > >> > >> Signed-off-by: Jon Nettleton > >> Signed-off-by: Baruch Siach > >> --- > > > > Reviewed-by: Chris Packham > > Thanks. > > > Lately I haven't had much luck with using kwboot on a38x. I seem to be > > able to get the spl to boot from uart (even better now thanks to this > > patch) but the next stage still loads from SPI. I haven't been brave > > enough to blank a board to see if that changes behaviour. Are your > > experiences any different? I'm wondering if there is something we need > > to do in the SPL to figure out that we need to load the next stage via > > xmodem. > > It works for me here on the Clearfog. > > The code that determines the seconds stage load device is in > arch/arm/mach-mvebu/spl.c:get_boot_device(). Does the code there get it > right? What do you read from CONFIG_BOOTROM_ERR_REG? > I get the following from enabling the debug BOOTROM_REG=0x63001000 boot_device=0x0 SAR_REG=0xcb20b342 boot_device=0x34 BOOTROM_REG=0x63001000 boot_device=0x0 SAR_REG=0xcb20b342 boot_device=0x34 The strapping is for SPI so the second part isn't surprising. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] tools: kwboot: Make kwboot more robust on a38x
On Fri, Aug 17, 2018 at 11:01 AM Chris Packham wrote: > > On Thu, Aug 16, 2018 at 8:38 PM Baruch Siach wrote: > > > > Hi Chris, > > > > Chris Packham writes: > > > On Tue, Aug 14, 2018 at 3:25 AM Baruch Siach wrote: > > >> From: Jon Nettleton > > >> > > >> This patch accomplishes 2 things to make the kwboot procedure > > >> on the a38x more reliable. > > >> > > >> 1) We fill the tty with 1K of the magic bootparam. This helps > > >> with the timing of where the microcode picks up in the read of > > >> the line to ensure we actually catch the break to go into recovery > > >> mode > > >> > > >> 2) Before starting the xmodem transfer we sleep for 2 seconds > > >> and then flush the line. This allows all the magic bootparam > > >> to be flushed from the line and makes the xmodem transfer reliable > > >> and removes the Bad message failures. > > >> > > >> Signed-off-by: Jon Nettleton > > >> Signed-off-by: Baruch Siach > > >> --- > > > > > > Reviewed-by: Chris Packham > > > > Thanks. > > > > > Lately I haven't had much luck with using kwboot on a38x. I seem to be > > > able to get the spl to boot from uart (even better now thanks to this > > > patch) but the next stage still loads from SPI. I haven't been brave > > > enough to blank a board to see if that changes behaviour. Are your > > > experiences any different? I'm wondering if there is something we need > > > to do in the SPL to figure out that we need to load the next stage via > > > xmodem. > > > > It works for me here on the Clearfog. > > > > The code that determines the seconds stage load device is in > > arch/arm/mach-mvebu/spl.c:get_boot_device(). Does the code there get it > > right? What do you read from CONFIG_BOOTROM_ERR_REG? > > > > I get the following from enabling the debug > > BOOTROM_REG=0x63001000 boot_device=0x0 > SAR_REG=0xcb20b342 boot_device=0x34 > BOOTROM_REG=0x63001000 boot_device=0x0 > SAR_REG=0xcb20b342 boot_device=0x34 > > The strapping is for SPI so the second part isn't surprising. (sorry hit send too soon) If I hard code get_boot_device() to return BOOT_DEVICE_UART then kwboot works for me. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] tools: kwboot: Make kwboot more robust on a38x
On Fri, Aug 17, 2018 at 11:06 AM Chris Packham wrote:
>
> On Fri, Aug 17, 2018 at 11:01 AM Chris Packham
> wrote:
> >
> > On Thu, Aug 16, 2018 at 8:38 PM Baruch Siach wrote:
> > >
> > > Hi Chris,
> > >
> > > Chris Packham writes:
> > > > On Tue, Aug 14, 2018 at 3:25 AM Baruch Siach wrote:
> > > >> From: Jon Nettleton
> > > >>
> > > >> This patch accomplishes 2 things to make the kwboot procedure
> > > >> on the a38x more reliable.
> > > >>
> > > >> 1) We fill the tty with 1K of the magic bootparam. This helps
> > > >> with the timing of where the microcode picks up in the read of
> > > >> the line to ensure we actually catch the break to go into recovery
> > > >> mode
> > > >>
> > > >> 2) Before starting the xmodem transfer we sleep for 2 seconds
> > > >> and then flush the line. This allows all the magic bootparam
> > > >> to be flushed from the line and makes the xmodem transfer reliable
> > > >> and removes the Bad message failures.
> > > >>
> > > >> Signed-off-by: Jon Nettleton
> > > >> Signed-off-by: Baruch Siach
> > > >> ---
> > > >
> > > > Reviewed-by: Chris Packham
> > >
> > > Thanks.
> > >
> > > > Lately I haven't had much luck with using kwboot on a38x. I seem to be
> > > > able to get the spl to boot from uart (even better now thanks to this
> > > > patch) but the next stage still loads from SPI. I haven't been brave
> > > > enough to blank a board to see if that changes behaviour. Are your
> > > > experiences any different? I'm wondering if there is something we need
> > > > to do in the SPL to figure out that we need to load the next stage via
> > > > xmodem.
> > >
> > > It works for me here on the Clearfog.
> > >
> > > The code that determines the seconds stage load device is in
> > > arch/arm/mach-mvebu/spl.c:get_boot_device(). Does the code there get it
> > > right? What do you read from CONFIG_BOOTROM_ERR_REG?
> > >
> >
> > I get the following from enabling the debug
> >
> > BOOTROM_REG=0x63001000 boot_device=0x0
> > SAR_REG=0xcb20b342 boot_device=0x34
> > BOOTROM_REG=0x63001000 boot_device=0x0
> > SAR_REG=0xcb20b342 boot_device=0x34
> >
> > The strapping is for SPI so the second part isn't surprising.
>
> (sorry hit send too soon)
>
> If I hard code get_boot_device() to return BOOT_DEVICE_UART then
> kwboot works for me.
And if I revert commit e83e2b390038 ("arm: mvebu: fix boot from UART
when in fallback mode") it works properly.
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[U-Boot] [PATCH] Revert "arm: mvebu: fix boot from UART when in fallback mode"
This reverts commit e83e2b390038c9075642cb243a6292241beb8d73. This
prevents kwboot from overriding the hardware strapped boot source.
Signed-off-by: Chris Packham
---
Sean,
I take it your use case was for when the default boot source doesn't
have a valid image and it falls back to UART? If that's the case I think
we need something in addition to the existing code not instead of.
arch/arm/mach-mvebu/include/mach/soc.h | 6 --
arch/arm/mach-mvebu/spl.c | 9 -
2 files changed, 15 deletions(-)
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h
b/arch/arm/mach-mvebu/include/mach/soc.h
index 623ab4eb8d93..660dd148abc5 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -110,16 +110,10 @@
#define COMPHY_REFCLK_ALIGNMENT(MVEBU_REGISTER(0x182f8))
/* BootROM error register (also includes some status infos) */
-#if defined(CONFIG_ARMADA_38X)
-#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
-#define BOOTROM_ERR_MODE_OFFS 0
-#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
-#else
#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
#define BOOTROM_ERR_MODE_OFFS 28
#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
#define BOOTROM_ERR_MODE_UART 0x6
-#endif
#if defined(CONFIG_ARMADA_375)
/* SAR values for Armada 375 */
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index 50b24f5760b7..4c3933b8354d 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -25,16 +25,7 @@ static u32 get_boot_device(void)
val = readl(CONFIG_BOOTROM_ERR_REG);
boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
-#if defined(CONFIG_ARMADA_38X)
- /*
-* If the bootrom error register contains any else than zeros
-* in the first 8 bits it's an error condition. And in that case
-* try to boot from UART.
-*/
- if (boot_device)
-#else
if (boot_device == BOOTROM_ERR_MODE_UART)
-#endif
return BOOT_DEVICE_UART;
/*
--
2.18.0
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Re: [U-Boot] [PATCH] Revert "arm: mvebu: fix boot from UART when in fallback mode"
On Fri, Aug 17, 2018 at 5:41 PM Sean Nyekjær wrote: > > > > On 17/08/2018 01.30, Chris Packham wrote: > > This reverts commit e83e2b390038c9075642cb243a6292241beb8d73. This > > prevents kwboot from overriding the hardware strapped boot source. > > > > Signed-off-by: Chris Packham > > --- > > Sean, > > > > I take it your use case was for when the default boot source doesn't > > have a valid image and it falls back to UART? If that's the case I think > > we need something in addition to the existing code not instead of. > > Hi, > > My use case was exactly what you are describing. If the default boot > source doesn't have a valid image it falls back til UART and without > this patch the SPL will try default boot source which in most cases are > the old image or non existing. What kind of use case do you have? > It's really hard to read in the datasheet as it's not entirely accurate > on this. Yeah for some reason Marvell deemed it unnecessary to document the fields of that particular register. I can confirm from experience that bits 31:28 do reflect the current boot source when using kwboot to override the HW strapped boot source. I can also confirm your observation that if you manage to kill the boot header but not the final stage u-boot you end up booting the spl over UART but then the next stage boots from SPI. I'll see if I can come up with something that covers both cases. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] Revert "arm: mvebu: fix boot from UART when in fallback mode"
This reverts commit e83e2b390038c9075642cb243a6292241beb8d73. This
prevents kwboot from overriding the hardware strapped boot source.
Signed-off-by: Chris Packham
---
Changes in v2: None
arch/arm/mach-mvebu/include/mach/soc.h | 6 --
arch/arm/mach-mvebu/spl.c | 9 -
2 files changed, 15 deletions(-)
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h
b/arch/arm/mach-mvebu/include/mach/soc.h
index 623ab4eb8d93..660dd148abc5 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -110,16 +110,10 @@
#define COMPHY_REFCLK_ALIGNMENT(MVEBU_REGISTER(0x182f8))
/* BootROM error register (also includes some status infos) */
-#if defined(CONFIG_ARMADA_38X)
-#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
-#define BOOTROM_ERR_MODE_OFFS 0
-#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
-#else
#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
#define BOOTROM_ERR_MODE_OFFS 28
#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
#define BOOTROM_ERR_MODE_UART 0x6
-#endif
#if defined(CONFIG_ARMADA_375)
/* SAR values for Armada 375 */
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index 50b24f5760b7..4c3933b8354d 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -25,16 +25,7 @@ static u32 get_boot_device(void)
val = readl(CONFIG_BOOTROM_ERR_REG);
boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
-#if defined(CONFIG_ARMADA_38X)
- /*
-* If the bootrom error register contains any else than zeros
-* in the first 8 bits it's an error condition. And in that case
-* try to boot from UART.
-*/
- if (boot_device)
-#else
if (boot_device == BOOTROM_ERR_MODE_UART)
-#endif
return BOOT_DEVICE_UART;
/*
--
2.18.0
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[U-Boot] [PATCH v2 2/2] ARM: mach-mvebu: handle fall-back to UART boot
The bootROM in the Armada-38x (and similar) SoC has two modes for UART boot. The first is when the normal boot media is blank (or otherwise missing the kwb header). The second is when the boot sequence has been interrupted with the magic byte sequence on the UART lines. In the first mode the bootROM routine and error code register will indicate that there was an error booting from the configured media in bits 7:0. In the second mode there is no error to indicate but the boot source is provided via bits 31:28. Handle both situations so that kwboot can be used for both boot strapping a blank board and for intercepting a regular boot sequence. Signed-off-by: Chris Packham --- I think this probably applies to more than just the A38X but I've been conservative in restricting this for now. If other Marvell SoCs are found to have the same behaviour we can extend this to cover them. Changes in v2: - new arch/arm/mach-mvebu/include/mach/soc.h | 2 ++ arch/arm/mach-mvebu/spl.c | 10 ++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 660dd148abc5..6e2e14efe0b7 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -114,6 +114,8 @@ #define BOOTROM_ERR_MODE_OFFS 28 #define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) #define BOOTROM_ERR_MODE_UART 0x6 +#define BOOTROM_ERR_CODE_OFFS 0 +#define BOOTROM_ERR_CODE_MASK (0xf << BOOTROM_ERR_CODE_OFFS) #if defined(CONFIG_ARMADA_375) /* SAR values for Armada 375 */ diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 4c3933b8354d..9dd7c84b6874 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -28,6 +28,16 @@ static u32 get_boot_device(void) if (boot_device == BOOTROM_ERR_MODE_UART) return BOOT_DEVICE_UART; +#ifdef CONFIG_ARMADA_38X + /* +* If the bootrom error code contains any other than zeros it's an +* error condition and the bootROM has fallen back to UART boot +*/ + boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS; + if (boot_device) + return BOOT_DEVICE_UART; +#endif + /* * Now check the SAR register for the strapped boot-device */ -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] tools: kwboot: Make kwboot more robust on a38x
On Fri, Aug 17, 2018 at 8:11 PM Jon Nettleton wrote:
>
> On Fri, Aug 17, 2018 at 1:22 AM Chris Packham wrote:
> >
> > On Fri, Aug 17, 2018 at 11:06 AM Chris Packham
> > wrote:
> > >
> > > On Fri, Aug 17, 2018 at 11:01 AM Chris Packham
> > > wrote:
> > > >
> > > > On Thu, Aug 16, 2018 at 8:38 PM Baruch Siach wrote:
> > > > >
> > > > > Hi Chris,
> > > > >
> > > > > Chris Packham writes:
> > > > > > On Tue, Aug 14, 2018 at 3:25 AM Baruch Siach
> > > > > > wrote:
> > > > > >> From: Jon Nettleton
> > > > > >>
> > > > > >> This patch accomplishes 2 things to make the kwboot procedure
> > > > > >> on the a38x more reliable.
> > > > > >>
> > > > > >> 1) We fill the tty with 1K of the magic bootparam. This helps
> > > > > >> with the timing of where the microcode picks up in the read of
> > > > > >> the line to ensure we actually catch the break to go into recovery
> > > > > >> mode
> > > > > >>
> > > > > >> 2) Before starting the xmodem transfer we sleep for 2 seconds
> > > > > >> and then flush the line. This allows all the magic bootparam
> > > > > >> to be flushed from the line and makes the xmodem transfer reliable
> > > > > >> and removes the Bad message failures.
> > > > > >>
> > > > > >> Signed-off-by: Jon Nettleton
> > > > > >> Signed-off-by: Baruch Siach
> > > > > >> ---
> > > > > >
> > > > > > Reviewed-by: Chris Packham
> > > > >
> > > > > Thanks.
> > > > >
> > > > > > Lately I haven't had much luck with using kwboot on a38x. I seem to
> > > > > > be
> > > > > > able to get the spl to boot from uart (even better now thanks to
> > > > > > this
> > > > > > patch) but the next stage still loads from SPI. I haven't been brave
> > > > > > enough to blank a board to see if that changes behaviour. Are your
> > > > > > experiences any different? I'm wondering if there is something we
> > > > > > need
> > > > > > to do in the SPL to figure out that we need to load the next stage
> > > > > > via
> > > > > > xmodem.
> > > > >
> > > > > It works for me here on the Clearfog.
> > > > >
> > > > > The code that determines the seconds stage load device is in
> > > > > arch/arm/mach-mvebu/spl.c:get_boot_device(). Does the code there get
> > > > > it
> > > > > right? What do you read from CONFIG_BOOTROM_ERR_REG?
> > > > >
> > > >
> > > > I get the following from enabling the debug
> > > >
> > > > BOOTROM_REG=0x63001000 boot_device=0x0
> > > > SAR_REG=0xcb20b342 boot_device=0x34
> > > > BOOTROM_REG=0x63001000 boot_device=0x0
> > > > SAR_REG=0xcb20b342 boot_device=0x34
> > > >
> > > > The strapping is for SPI so the second part isn't surprising.
> > >
> > > (sorry hit send too soon)
> > >
> > > If I hard code get_boot_device() to return BOOT_DEVICE_UART then
> > > kwboot works for me.
> >
> > And if I revert commit e83e2b390038 ("arm: mvebu: fix boot from UART
> > when in fallback mode") it works properly.
>
> Chris,
>
> I see the issue. Mainline is still missing another patch from our
> local tree. I don't think Baruch has broken it out and submitted it
> to mainline yet. Look at this #ifndef here.
>
> https://github.com/SolidRun/u-boot/blob/v2018.01-solidrun-a38x/arch/arm/mach-mvebu/spl.c#L35
>
> Basically this allows you to specifically build u-boot for UART
> recovery and short circuits the detected boot device if it is already
> configured. Please try adding that in and verify that it works for
> you.
>
> This also requires u-boot with commit
> 72c4e67d08fe2389754b4ce874d76b1bbd9fef24 and
> CONFIG_MVEBU_SPL_BOOT_DEVICE_UART set in your .config
>
> Thanks,
> Jon
>
> This does bring up the question as to whether Boot Method should be
> individual choices and then we build multiple images named for each
> boot type rather than requiring an individual build for each boot
> type.
That's certainly what Marvell's USP does. But I find it a pain because
you have to remember to load the right image and you waste so much
time sending an image configured for spi over xmodem only to realise
you copied the wrong one. Or you brick a board by writing the UART
version into flash.I like the kwboot method of patching the image on
the fly.
I think the real issue I was experiencing is that there are 2
different behaviours depending on whether your intercepting a normal
boot. Or bringing up a blank board. I've just sent a series to deal
with this http://patchwork.ozlabs.org/patch/958704/ (I got your main
just after sending it, I'll include you in the Cc if there is a
re-roll).
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[U-Boot] mkimage (kwbimage) unmapping more bytes than it maps
Hi,
Mark and I have been looking at a problem we've been experiencing on
our build system.
We're running a number of similarly configured makers and seemingly
randomly one will fail to build one of our kirkwood based targets
(specifically the SBx81LIFXCAT that was recently added) with a
segfault in mkimage. When I tried to run the same build it would work
fine on my PC (in theory the same base install as the makers).
I'd been blaming specific makers as having bad RAM (these things get
hammered so we've had them die before) but Mark managed to track it
down to mmap and munmap disagreeing on the size of the area mapped.
You can see this by running strace on mkimage
strace -y ./tools/mkimage -n ./arch/arm/mach-mvebu/kwbimage.cfg -T
kwbimage -a 0x0080 -e 0x0080 -d u-boot.img u-boot-spl.kwb
...
mmap(NULL, 641024, PROT_READ|PROT_WRITE, MAP_SHARED, 3, 0) = 0x7f1b5ce3e000
...
munmap(0x7f1b5ce3e000, 641028) = 0
Note that the size has been incremented by 4. Most of the time this is
harmless but on our build system the size of the image worked out to
an exact multiple of the page size so the munmap ended up spilling
over and unmapping another page which depending on the in-memory
layout of the process could result in a segfault.
This extra 4 bytes comes from kwbimage.c. Towards the end of
kwbimage_set_header() we have
checksum = cpu_to_le32(image_checksum32((uint32_t *)ptr, sbuf->st_size));
size = write(ifd, &checksum, sizeof(uint32_t));
...
sbuf->st_size += sizeof(uint32_t);
The st_size increment seems like a leftover from commit 4acd2d24b651
("tools: kwbimage: Add image version 1 support for Armada XP / 370")
as aside from the munmap in mkimage nothing else uses it.
This is where Mark and I disagree. A minimal change would simply to
remove the increment of st_size from kwbimage.c. But a more robust fix
would be to have mkimage not trust sbuf after it's been passed to
tparams->set_header.
Is there are preference for how to handle this? I'll follow up this
mail with Marks proposed fix.
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[U-Boot] [PATCH] tools: mkimage: Ensure munmap unmaps the same length that was mapped
From: Mark Tomlinson
The set_header call in kwbimage.c adds a checksum to the end of the
image in addition to setting up the header. It 'helpfully' updates the
st_size to match the fact that the file is now longer. However, mkimage
uses this length in the munmap call. This can lead to unmapping an extra
page, of perhaps required data. When this happens, a SEGV can occur.
To prevent this from happening, the munmap call now uses the same length
that was passed to mmap. This could also have been fixed by not changing
the length in kwbimage.c, however changing it in the main file means
that other plugins will also not fall for the same trap.
Signed-off-by: Mark Tomlinson
Signed-off-by: Chris Packham
[cp: resolve checkpatch complaints]
Tested-by: Chris Packham
---
tools/mkimage.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tools/mkimage.c b/tools/mkimage.c
index e0d4d20be499..6abd4d6a8b22 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -318,6 +318,7 @@ int main(int argc, char **argv)
struct image_type_params *tparams = NULL;
int pad_len = 0;
int dfd;
+ size_t map_len;
params.cmdname = *argv;
params.addr = 0;
@@ -576,7 +577,8 @@ int main(int argc, char **argv)
}
params.file_size = sbuf.st_size;
- ptr = mmap(0, sbuf.st_size, PROT_READ|PROT_WRITE, MAP_SHARED, ifd, 0);
+ map_len = sbuf.st_size;
+ ptr = mmap(0, map_len, PROT_READ | PROT_WRITE, MAP_SHARED, ifd, 0);
if (ptr == MAP_FAILED) {
fprintf (stderr, "%s: Can't map %s: %s\n",
params.cmdname, params.imagefile, strerror(errno));
@@ -600,7 +602,7 @@ int main(int argc, char **argv)
params.cmdname, tparams->name);
}
- (void) munmap((void *)ptr, sbuf.st_size);
+ (void)munmap((void *)ptr, map_len);
/* We're a bit of paranoid */
#if defined(_POSIX_SYNCHRONIZED_IO) && \
--
2.18.0
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[U-Boot] [RFC PATCH v1] mips: add atomic operations
Add mips version of atomic.h and basic atomic operations. These aren't
the optimised versions from the Linux kernel, just basic stubs that
satisfy users that need something to define atomic_inc() etc.
Signed-off-by: Chris Packham
---
At $dayjob we have a mips target that we want to run UBIFS on. UBIFS
requires atomic.h. This is my naive attempt to supply enough of atomic.h
to satisfy UBIFS.
It's no coincidence that this looks like the arm version. I am
wondering if it's worth a asm-generic version leaving architectures that
actually need true atomic operations able to define them.
arch/mips/include/asm/atomic.h | 151 +
1 file changed, 151 insertions(+)
create mode 100644 arch/mips/include/asm/atomic.h
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
new file mode 100644
index ..3ab5684fdef4
--- /dev/null
+++ b/arch/mips/include/asm/atomic.h
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef _ASM_ATOMIC_H
+#define _ASM_ATOMIC_H
+
+#include
+
+typedef struct { volatile int counter; } atomic_t;
+#if BITS_PER_LONG == 32
+typedef struct { volatile long long counter; } atomic64_t;
+#else /* BIT_PER_LONG == 32 */
+typedef struct { volatile long counter; } atomic64_t;
+#endif
+
+#define ATOMIC_INIT(i) { (i) }
+
+#define atomic_read(v) ((v)->counter)
+#define atomic_set(v, i) (((v)->counter) = (i))
+#define atomic64_read(v) atomic_read(v)
+#define atomic64_set(v, i) atomic_set(v, i)
+
+static inline void atomic_add(int i, volatile atomic_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_sub(int i, volatile atomic_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_inc(volatile atomic_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += 1;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_dec(volatile atomic_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= 1;
+ local_irq_restore(flags);
+}
+
+static inline int atomic_dec_and_test(volatile atomic_t *v)
+{
+ unsigned long flags = 0;
+ int val;
+
+ local_irq_save(flags);
+ val = v->counter;
+ v->counter = val -= 1;
+ local_irq_restore(flags);
+
+ return val == 0;
+}
+
+static inline int atomic_add_negative(int i, volatile atomic_t *v)
+{
+ unsigned long flags = 0;
+ int val;
+
+ local_irq_save(flags);
+ val = v->counter;
+ v->counter = val += i;
+ local_irq_restore(flags);
+
+ return val < 0;
+}
+
+static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ *addr &= ~mask;
+ local_irq_restore(flags);
+}
+
+#if BITS_PER_LONG == 32
+
+static inline void atomic64_add(long long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic64_sub(long long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= i;
+ local_irq_restore(flags);
+}
+
+#else /* BIT_PER_LONG == 32 */
+
+static inline void atomic64_add(long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic64_sub(long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= i;
+ local_irq_restore(flags);
+}
+#endif /* BIT_PER_LONG == 32 */
+
+static inline void atomic64_inc(volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += 1;
+ local_irq_restore(flags);
+}
+
+static inline void atomic64_dec(volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= 1;
+ local_irq_restore(flags);
+}
+
+#endif
--
2.18.0
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Re: [U-Boot] [RFC PATCH v1] mips: add atomic operations
On Fri, 7 Sep 2018, 10:24 PM Stefan, wrote: > Hi Chris, > > (added Daniel) > > On 07.09.2018 10:24, Chris Packham wrote: > > Add mips version of atomic.h and basic atomic operations. These aren't > > the optimised versions from the Linux kernel, just basic stubs that > > satisfy users that need something to define atomic_inc() etc. > > > > Signed-off-by: Chris Packham > > > > --- > > At $dayjob we have a mips target that we want to run UBIFS on. UBIFS > > requires atomic.h. This is my naive attempt to supply enough of atomic.h > > to satisfy UBIFS. > > > > It's no coincidence that this looks like the arm version. I am > > wondering if it's worth a asm-generic version leaving architectures that > > actually need true atomic operations able to define them. > > I did a pretty similar job and copied the files from xtensa a few > weeks ago: > > https://patchwork.ozlabs.org/patch/958286/ Weird coincidence. I figured noone had needed ubifs on mips since the need for atomic.h has been there for a while. I'm more than happy for your version to go in since it's part of a bigger series. The only thing missing is 64 bit support (our platform happens to be mips64) but i don't think ubifs cares. > It would be better of course, to have some generic version of this > file. But frankly, I don't have the time right now for this. > Given that the arm, xtensa and now mips are so similar it's probably worth it. I'll see if i can find some cycles to spend on it. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/4] Add include/asm-generic/atomic.h
The arm, xtensa and mips version of atomic.h were already very similar
(the mips one was a copy of xtensa). Combine these implementations
together to produce a generic atomic.h that can be included by these
architectures (and any others that need it in future).
Signed-off-by: Chris Packham
---
include/asm-generic/atomic.h | 150 +++
1 file changed, 150 insertions(+)
create mode 100644 include/asm-generic/atomic.h
diff --git a/include/asm-generic/atomic.h b/include/asm-generic/atomic.h
new file mode 100644
index ..94d0747194af
--- /dev/null
+++ b/include/asm-generic/atomic.h
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _ASM_GENERIC_ATOMIC_H
+#define _ASM_GENERIC_ATOMIC_H
+
+typedef struct { volatile int counter; } atomic_t;
+#if BITS_PER_LONG == 32
+typedef struct { volatile long long counter; } atomic64_t;
+#else /* BIT_PER_LONG == 32 */
+typedef struct { volatile long counter; } atomic64_t;
+#endif
+
+#define ATOMIC_INIT(i) { (i) }
+
+#define atomic_read(v) ((v)->counter)
+#define atomic_set(v, i) ((v)->counter = (i))
+#define atomic64_read(v) atomic_read(v)
+#define atomic64_set(v, i) atomic_set(v, i)
+
+static inline void atomic_add(int i, atomic_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_inc(atomic_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ ++v->counter;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_dec(atomic_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ --v->counter;
+ local_irq_restore(flags);
+}
+
+static inline int atomic_dec_and_test(volatile atomic_t *v)
+{
+ unsigned long flags = 0;
+ int val;
+
+ local_irq_save(flags);
+ val = v->counter;
+ v->counter = val -= 1;
+ local_irq_restore(flags);
+
+ return val == 0;
+}
+
+static inline int atomic_add_negative(int i, volatile atomic_t *v)
+{
+ unsigned long flags = 0;
+ int val;
+
+ local_irq_save(flags);
+ val = v->counter;
+ v->counter = val += i;
+ local_irq_restore(flags);
+
+ return val < 0;
+}
+
+static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ *addr &= ~mask;
+ local_irq_restore(flags);
+}
+
+#if BITS_PER_LONG == 32
+
+static inline void atomic64_add(long long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic64_sub(long long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= i;
+ local_irq_restore(flags);
+}
+
+#else /* BIT_PER_LONG == 32 */
+
+static inline void atomic64_add(long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic64_sub(long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= i;
+ local_irq_restore(flags);
+}
+#endif
+
+static inline void atomic64_inc(volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += 1;
+ local_irq_restore(flags);
+}
+
+static inline void atomic64_dec(volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= 1;
+ local_irq_restore(flags);
+}
+
+#endif
--
2.18.0
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[U-Boot] [PATCH 2/4] ARM: use asm-generic/atomic.h
Make use of asm-generic/atomic.h retaining the smp_mb_... definitions.
Signed-off-by: Chris Packham
---
arch/arm/include/asm/atomic.h | 147 +-
1 file changed, 1 insertion(+), 146 deletions(-)
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 171f4d979281..5822b0a52c0e 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -20,152 +20,8 @@
#error SMP not supported
#endif
-typedef struct { volatile int counter; } atomic_t;
-#if BITS_PER_LONG == 32
-typedef struct { volatile long long counter; } atomic64_t;
-#else /* BIT_PER_LONG == 32 */
-typedef struct { volatile long counter; } atomic64_t;
-#endif
-
-#define ATOMIC_INIT(i) { (i) }
-
-#ifdef __KERNEL__
#include
-
-#define atomic_read(v) ((v)->counter)
-#define atomic_set(v, i) (((v)->counter) = (i))
-#define atomic64_read(v) atomic_read(v)
-#define atomic64_set(v, i) atomic_set(v, i)
-
-static inline void atomic_add(int i, volatile atomic_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter += i;
- local_irq_restore(flags);
-}
-
-static inline void atomic_sub(int i, volatile atomic_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter -= i;
- local_irq_restore(flags);
-}
-
-static inline void atomic_inc(volatile atomic_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter += 1;
- local_irq_restore(flags);
-}
-
-static inline void atomic_dec(volatile atomic_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter -= 1;
- local_irq_restore(flags);
-}
-
-static inline int atomic_dec_and_test(volatile atomic_t *v)
-{
- unsigned long flags = 0;
- int val;
-
- local_irq_save(flags);
- val = v->counter;
- v->counter = val -= 1;
- local_irq_restore(flags);
-
- return val == 0;
-}
-
-static inline int atomic_add_negative(int i, volatile atomic_t *v)
-{
- unsigned long flags = 0;
- int val;
-
- local_irq_save(flags);
- val = v->counter;
- v->counter = val += i;
- local_irq_restore(flags);
-
- return val < 0;
-}
-
-static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- *addr &= ~mask;
- local_irq_restore(flags);
-}
-
-#if BITS_PER_LONG == 32
-
-static inline void atomic64_add(long long i, volatile atomic64_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter += i;
- local_irq_restore(flags);
-}
-
-static inline void atomic64_sub(long long i, volatile atomic64_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter -= i;
- local_irq_restore(flags);
-}
-
-#else /* BIT_PER_LONG == 32 */
-
-static inline void atomic64_add(long i, volatile atomic64_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter += i;
- local_irq_restore(flags);
-}
-
-static inline void atomic64_sub(long i, volatile atomic64_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter -= i;
- local_irq_restore(flags);
-}
-#endif
-
-static inline void atomic64_inc(volatile atomic64_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter += 1;
- local_irq_restore(flags);
-}
-
-static inline void atomic64_dec(volatile atomic64_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter -= 1;
- local_irq_restore(flags);
-}
+#include
/* Atomic operations are already serializing on ARM */
#define smp_mb__before_atomic_dec()barrier()
@@ -174,4 +30,3 @@ static inline void atomic64_dec(volatile atomic64_t *v)
#define smp_mb__after_atomic_inc() barrier()
#endif
-#endif
--
2.18.0
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[U-Boot] [PATCH 0/4] Rationalise atomic.h implementations
This series applies on top of https://patchwork.ozlabs.org/patch/958286/ The intention is to rationalise most of the current implementations of atomic.h. x86 remains as having an arch specific implementation which I don't intend to touch. Chris Packham (4): Add include/asm-generic/atomic.h ARM: use asm-generic/atomic.h mips: use asm-generic/atomic.h xtensa: use asm-generic/atomic.h arch/arm/include/asm/atomic.h| 147 +- arch/mips/include/asm/atomic.h | 44 + arch/xtensa/include/asm/atomic.h | 44 + include/asm-generic/atomic.h | 150 +++ 4 files changed, 153 insertions(+), 232 deletions(-) create mode 100644 include/asm-generic/atomic.h -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/4] mips: use asm-generic/atomic.h
Make use of asm-generic/atomic.h.
Signed-off-by: Chris Packham
---
arch/mips/include/asm/atomic.h | 44 +-
1 file changed, 1 insertion(+), 43 deletions(-)
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 7551bf6e6c2c..c4f08b78200e 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -7,48 +7,6 @@
#define _MIPS_ATOMIC_H
#include
-
-typedef struct { volatile int counter; } atomic_t;
-
-#define ATOMIC_INIT(i) { (i) }
-
-#define atomic_read(v) ((v)->counter)
-#define atomic_set(v, i) ((v)->counter = (i))
-
-static inline void atomic_add(int i, atomic_t *v)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- v->counter += i;
- local_irq_restore(flags);
-}
-
-static inline void atomic_sub(int i, atomic_t *v)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- v->counter -= i;
- local_irq_restore(flags);
-}
-
-static inline void atomic_inc(atomic_t *v)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- ++v->counter;
- local_irq_restore(flags);
-}
-
-static inline void atomic_dec(atomic_t *v)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- --v->counter;
- local_irq_restore(flags);
-}
+#include
#endif
--
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[U-Boot] [PATCH 4/4] xtensa: use asm-generic/atomic.h
Make use of asm-generic/atomic.h.
Signed-off-by: Chris Packham
---
arch/xtensa/include/asm/atomic.h | 44 +---
1 file changed, 1 insertion(+), 43 deletions(-)
diff --git a/arch/xtensa/include/asm/atomic.h b/arch/xtensa/include/asm/atomic.h
index 42b32f5d3d6e..4e3ad5647275 100644
--- a/arch/xtensa/include/asm/atomic.h
+++ b/arch/xtensa/include/asm/atomic.h
@@ -7,48 +7,6 @@
#define _XTENSA_ATOMIC_H
#include
-
-typedef struct { volatile int counter; } atomic_t;
-
-#define ATOMIC_INIT(i) { (i) }
-
-#define atomic_read(v) ((v)->counter)
-#define atomic_set(v, i) ((v)->counter = (i))
-
-static inline void atomic_add(int i, atomic_t *v)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- v->counter += i;
- local_irq_restore(flags);
-}
-
-static inline void atomic_sub(int i, atomic_t *v)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- v->counter -= i;
- local_irq_restore(flags);
-}
-
-static inline void atomic_inc(atomic_t *v)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- ++v->counter;
- local_irq_restore(flags);
-}
-
-static inline void atomic_dec(atomic_t *v)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- --v->counter;
- local_irq_restore(flags);
-}
+#include
#endif
--
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Re: [U-Boot] [PATCH 2/2] configs: kirkwood: Move RTC_MV to DM and Kconfig
On Wed, Jun 27, 2018 at 10:47 PM Chris Packham wrote: > > Now that there is DM support in the RTC_MV driver update board configs > to use it. > > Signed-off-by: Chris Packham > --- > I haven't removed this from the whitelist because the nsa310s board > lacks device-tree support. Once that board is converted the non-DM code > can be removed from RTC_MV and the whitelist updated. I think I have to self NAK this one: https://travis-ci.org/cpackham/u-boot/jobs/397289205 Switching to DM_RTC doesn't play nicely with some boards which also have another rtc. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/3] configs: kirkwood: ds109: switch to DM_I2C
Enable DM_I2C and I2C_MVTSWI for the ds109 board. Signed-off-by: Chris Packham --- Changes in v2: - new configs/ds109_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index c9207433b374..fd10e6e3c36e 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -18,6 +18,8 @@ CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MVSATA_IDE=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/3] configs: move RTC_MV config from mv-plug-common.h to boards
To aid in migrating CONFIG_RTC_MV to Kconfig move the definition of it from mv-plug-common.h to the board config headers that nest it. Signed-off-by: Chris Packham --- Changes in v2: None include/configs/dreamplug.h | 4 include/configs/ds109.h | 4 include/configs/guruplug.h | 4 include/configs/mv-plug-common.h | 7 --- include/configs/sheevaplug.h | 4 5 files changed, 16 insertions(+), 7 deletions(-) diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 1c94bf9fa1bf..742232d2d660 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -27,6 +27,10 @@ */ #include "mv-plug-common.h" +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + /* * Environment variables configurations */ diff --git a/include/configs/ds109.h b/include/configs/ds109.h index c06f0058deb5..f8d663714239 100644 --- a/include/configs/ds109.h +++ b/include/configs/ds109.h @@ -30,6 +30,10 @@ */ #include "mv-plug-common.h" +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + /* * Environment variables configurations */ diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index 04b7e944a461..27096fbb20f3 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -27,6 +27,10 @@ */ #include "mv-plug-common.h" +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + /* * Environment variables configurations */ diff --git a/include/configs/mv-plug-common.h b/include/configs/mv-plug-common.h index 81c07a889a36..f424e2cc6c52 100644 --- a/include/configs/mv-plug-common.h +++ b/include/configs/mv-plug-common.h @@ -22,11 +22,4 @@ */ #include "mv-common.h" -/* - * RTC driver configuration - */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_MV -#endif /* CONFIG_CMD_DATE */ - #endif /* _CONFIG_MARVELL_PLUG_H */ diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index dc6375841ed8..bf684babebf3 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -31,6 +31,10 @@ */ #include "mv-plug-common.h" +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + /* * Environment variables configurations */ -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
