[U-Boot-Users] [PATCH v2] QE UEC: Extend number of supported UECs to 4
Signed-off-by: David Saada <[EMAIL PROTECTED]>
> diff -purN drivers/qe/uec.c.orig drivers/qe/uec.c
--- drivers/qe/uec.c.orig 2008-01-14 11:48:28.0 +0200
+++ drivers/qe/uec.c2008-01-15 09:42:59.11887 +0200
@@ -40,8 +40,13 @@ static uec_info_t eth1_uec_info = {
.tx_clock = CFG_UEC1_TX_CLK,
.eth_type = CFG_UEC1_ETH_TYPE,
},
+#if (CFG_UEC1_ETH_TYPE == FAST_ETH)
+ .num_threads_tx = UEC_NUM_OF_THREADS_1,
+ .num_threads_rx = UEC_NUM_OF_THREADS_1,
+#else
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
@@ -58,8 +63,13 @@ static uec_info_t eth2_uec_info = {
.tx_clock = CFG_UEC2_TX_CLK,
.eth_type = CFG_UEC2_ETH_TYPE,
},
+#if (CFG_UEC2_ETH_TYPE == FAST_ETH)
+ .num_threads_tx = UEC_NUM_OF_THREADS_1,
+ .num_threads_rx = UEC_NUM_OF_THREADS_1,
+#else
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
@@ -68,7 +78,6 @@ static uec_info_t eth2_uec_info = {
.enet_interface = CFG_UEC2_INTERFACE_MODE,
};
#endif
-
#ifdef CONFIG_UEC_ETH3
static uec_info_t eth3_uec_info = {
.uf_info= {
@@ -77,8 +86,13 @@ static uec_info_t eth3_uec_info = {
.tx_clock = CFG_UEC3_TX_CLK,
.eth_type = CFG_UEC3_ETH_TYPE,
},
+#if (CFG_UEC3_ETH_TYPE == FAST_ETH)
+ .num_threads_tx = UEC_NUM_OF_THREADS_1,
+ .num_threads_rx = UEC_NUM_OF_THREADS_1,
+#else
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
@@ -87,6 +101,29 @@ static uec_info_t eth3_uec_info = {
.enet_interface = CFG_UEC3_INTERFACE_MODE,
};
#endif
+#ifdef CONFIG_UEC_ETH4
+static uec_info_t eth4_uec_info = {
+ .uf_info= {
+ .ucc_num= CFG_UEC4_UCC_NUM,
+ .rx_clock = CFG_UEC4_RX_CLK,
+ .tx_clock = CFG_UEC4_TX_CLK,
+ .eth_type = CFG_UEC4_ETH_TYPE,
+ },
+#if (CFG_UEC4_ETH_TYPE == FAST_ETH)
+ .num_threads_tx = UEC_NUM_OF_THREADS_1,
+ .num_threads_rx = UEC_NUM_OF_THREADS_1,
+#else
+ .num_threads_tx = UEC_NUM_OF_THREADS_4,
+ .num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
+ .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .tx_bd_ring_len = 16,
+ .rx_bd_ring_len = 16,
+ .phy_address= CFG_UEC4_PHY_ADDR,
+ .enet_interface = CFG_UEC4_INTERFACE_MODE,
+};
+#endif
static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
{
@@ -1262,6 +1299,10 @@ int uec_initialize(int index)
#ifdef CONFIG_UEC_ETH3
uec_info = ð3_uec_info;
#endif
+ } else if (index == 3) {
+#ifdef CONFIG_UEC_ETH4
+ uec_info = ð4_uec_info;
+#endif
} else {
printf("%s: index is illegal.\n", __FUNCTION__);
return -EINVAL;
> diff -purN net/eth.c.orig net/eth.c
--- net/eth.c.orig 2008-01-14 11:48:28.0 +0200
+++ net/eth.c 2008-01-14 18:59:56.708822000 +0200
@@ -217,6 +217,9 @@ int eth_initialize(bd_t *bis)
#if defined(CONFIG_UEC_ETH3)
uec_initialize(2);
#endif
+#if defined(CONFIG_UEC_ETH4)
+ uec_initialize(3);
+#endif
#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
fec_initialize(bis);
-
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[U-Boot-Users] MMC 4GB with at91sam9260 ...
Hi, I need some help because I want to use an eMMC of 4GB but my U-Boot (1.1.5) see it but can't use it... So I think it is a problem with "Max read data block length" but I don't know what I can change in the code ... Have somebody already try this? Could you help me please? Thanks in advance, Regards, Pierre - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] Warining on 83xx tree
Kim, Could you clean up the warning in 83xx current tree? Thanks, Dave mpc8360emds.c: In function 'ft_board_setup': mpc8360emds.c:327: warning: assignment makes pointer from integer without a cast mpc8360emds.c:329: warning: passing argument 2 of 'fdt_getprop' makes integer from pointer without a cast mpc8360emds.c:334: warning: passing argument 2 of 'fdt_setprop' makes integer from pointer without a cast mpc8360emds.c:341: warning: assignment makes pointer from integer without a cast mpc8360emds.c:343: warning: passing argument 2 of 'fdt_getprop' makes integer from pointer without a cast mpc8360emds.c:348: warning: passing argument 2 of 'fdt_setprop' makes integer from pointer without a cast - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] ColdFire: Fix CFI Flash low level Read/Write macro
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
include/asm-m68k/io.h | 22 --
1 files changed, 8 insertions(+), 14 deletions(-)
diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h
index 91d7592..33c454a 100644
--- a/include/asm-m68k/io.h
+++ b/include/asm-m68k/io.h
@@ -28,19 +28,13 @@
#include
-/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
- * two accesses to memory, which may be undesirable for some devices.
- */
-#define __raw_readb(addr) \
-({ u8 __v = (*(volatile u8 *) (addr)); __v; })
-#define __raw_readw(addr) \
-({ u16 __v = (*(volatile u16 *) (addr)); __v; })
-#define __raw_readl(addr) \
-({ u32 __v = (*(volatile u32 *) (addr)); __v; })
+#define __raw_readb(addr) (*(volatile u8 *)(addr))
+#define __raw_readw(addr) (*(volatile u16 *)(addr))
+#define __raw_readl(addr) (*(volatile u32 *)(addr))
-#define __raw_writeb(addr,b) (void)((*(volatile u8 *) (addr)) = (b))
-#define __raw_writew(addr,w) (void)((*(volatile u16 *) (addr)) = (w))
-#define __raw_writel(addr,l) (void)((*(volatile u32 *) (addr)) = (l))
+#define __raw_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
+#define __raw_writew(w,addr) ((*(volatile u16 *) (addr)) = (w))
+#define __raw_writel(l,addr) ((*(volatile u32 *) (addr)) = (l))
#define readb(addr)in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
@@ -245,8 +239,8 @@ typedef unsigned long phys_addr_t;
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
-static inline void *
-map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+static inline void *map_physmem(phys_addr_t paddr, unsigned long len,
+ unsigned long flags)
{
return (void *)paddr;
}
--
1.5.2
-
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[U-Boot-Users] [PATCH 1/2] ColdFire: Add M5373EVB platform support - 1
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
board/freescale/m5373evb/Makefile | 44 +
board/freescale/m5373evb/config.mk | 25 +++
board/freescale/m5373evb/m5373evb.c | 88 ++
board/freescale/m5373evb/mii.c | 306 +++
board/freescale/m5373evb/nand.c | 114 +
board/freescale/m5373evb/u-boot.lds | 144
6 files changed, 721 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/m5373evb/Makefile
create mode 100644 board/freescale/m5373evb/config.mk
create mode 100644 board/freescale/m5373evb/m5373evb.c
create mode 100644 board/freescale/m5373evb/mii.c
create mode 100644 board/freescale/m5373evb/nand.c
create mode 100644 board/freescale/m5373evb/u-boot.lds
diff --git a/board/freescale/m5373evb/Makefile
b/board/freescale/m5373evb/Makefile
new file mode 100644
index 000..ab0f11e
--- /dev/null
+++ b/board/freescale/m5373evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o mii.o nand.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/freescale/m5373evb/config.mk
b/board/freescale/m5373evb/config.mk
new file mode 100644
index 000..ce014ed
--- /dev/null
+++ b/board/freescale/m5373evb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+# Coldfire contribution by Bernhard Kuhn <[EMAIL PROTECTED]>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0
diff --git a/board/freescale/m5373evb/m5373evb.c
b/board/freescale/m5373evb/m5373evb.c
new file mode 100644
index 000..26b87b9
--- /dev/null
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew ([EMAIL PROTECTED])
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale FireEngine 5373 EVB\n");
+ return 0;
+};
+
+long in
[U-Boot-Users] [PATCH] ColdFire: Update FlexBus CS for MCF532x
Definition update and change from 16bit to 32bit
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
board/freescale/m5329evb/nand.c |4 ++--
include/configs/M5329EVB.h |8
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index fefb42e..344a614 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -63,10 +63,10 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int
cmd)
nand_baseaddr |= CLR_ALE;
break;
case NAND_CTL_SETWP:
- fbcs->csmr2 |= CSMR_WP;
+ fbcs->csmr2 |= FBCS_CSMR_WP;
break;
case NAND_CTL_CLRWP:
- fbcs->csmr2 &= ~CSMR_WP;
+ fbcs->csmr2 &= ~FBCS_CSMR_WP;
break;
}
this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 47d74a3..e956739 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -213,7 +213,7 @@
#ifdef NANDFLASH_SIZE
# define CFG_MAX_NAND_DEVICE 1
-# define CFG_NAND_BASE(CFG_CS2_BASE << 16)
+# define CFG_NAND_BASECFG_CS2_BASE
# define CFG_NAND_SIZE1
# define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
# define NAND_MAX_CHIPS 1
@@ -224,7 +224,7 @@
# define CONFIG_JFFS2_PART_OFFSET 0x
#endif
-#define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
+#define CFG_FLASH_BASE CFG_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -254,12 +254,12 @@
#define CFG_CS0_MASK 0x007f0001
#define CFG_CS0_CTRL 0x1fa0
-#define CFG_CS1_BASE 0x1000
+#define CFG_CS1_BASE 0x1000
#define CFG_CS1_MASK 0x001f0001
#define CFG_CS1_CTRL 0x002A3780
#ifdef NANDFLASH_SIZE
-#define CFG_CS2_BASE 0x2000
+#define CFG_CS2_BASE 0x2000
#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
#define CFG_CS2_CTRL 0x1f60
#endif
--
1.5.2
-
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[U-Boot-Users] [PATCH 2/2] ColdFire: Add M5373EVB platform support - 2
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
MAINTAINERS |1 +
MAKEALL |3 +-
Makefile | 10 ++
cpu/mcf532x/cpu.c | 20 +++-
doc/README.m5373evb | 334 +
include/asm-m68k/immap.h |4 +-
include/asm-m68k/immap_5329.h | 89 +---
include/asm-m68k/m5329.h |5 +
include/configs/M5373EVB.h| 267
9 files changed, 709 insertions(+), 24 deletions(-)
create mode 100644 doc/README.m5373evb
create mode 100644 include/configs/M5373EVB.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2ef2f5c..02698c8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -629,6 +629,7 @@ TsiChung Liew <[EMAIL PROTECTED]>
M5235EVBmcf52x2
M5329EVBmcf532x
+ M5373EVBmcf532x
M54455EVB mcf5445x
Hayden Fraser <[EMAIL PROTECTED]>
diff --git a/MAKEALL b/MAKEALL
index ebc5a22..1f59532 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -641,7 +641,8 @@ LIST_coldfire=" \
M5271EVB\
M5272C3 \
M5282EVB\
- M5329EVB\
+ M5329AFEE \
+ M5373EVB\
M54455EVB \
r5200 \
TASREG \
diff --git a/Makefile b/Makefile
index 1983ca0..f541392 100644
--- a/Makefile
+++ b/Makefile
@@ -1793,6 +1793,16 @@ M5329BFEE_config : unconfig
fi
@$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale
+M5373EVB_config : unconfig
+ @case "$@" in \
+ M5373EVB_config)NAND=16;; \
+ esac; \
+ >include/config.h ; \
+ if [ "$${NAND}" != "0" ] ; then \
+ echo "#define NANDFLASH_SIZE$${NAND}" >
$(obj)include/config.h ; \
+ fi
+ @$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale
+
M54455EVB_config \
M54455EVB_atmel_config \
M54455EVB_intel_config \
diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c
index 89cc8ad..61541ab 100644
--- a/cpu/mcf532x/cpu.c
+++ b/cpu/mcf532x/cpu.c
@@ -64,6 +64,18 @@ int checkcpu(void)
case 0x61:
id = 5327;
break;
+ case 0x65:
+ id = 5373;
+ break;
+ case 0x68:
+ id = 53721;
+ break;
+ case 0x69:
+ id = 5372;
+ break;
+ case 0x6B:
+ id = 5372;
+ break;
}
if (id) {
@@ -84,6 +96,7 @@ void watchdog_reset(void)
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
wdp->sr = 0x; /* Count register */
+ wdp->sr = 0x; /* Count register */
}
int watchdog_disable(void)
@@ -104,8 +117,11 @@ int watchdog_init(void)
/* set timeout and enable watchdog */
wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
- wdog_module |= (wdog_module / 8192);
- wdp->mr = wdog_module;
+#ifdef CONFIG_M5329
+ wdp->mr = (wdog_module / 8192);
+#else
+ wdp->mr = (wdog_module / 4096);
+#endif
wdp->cr = WTM_WCR_EN;
puts("WATCHDOG:enabled\n");
diff --git a/doc/README.m5373evb b/doc/README.m5373evb
new file mode 100644
index 000..62768ac
--- /dev/null
+++ b/doc/README.m5373evb
@@ -0,0 +1,334 @@
+Freescale MCF5373EVB ColdFire Development Board
+
+
+TsiChung Liew([EMAIL PROTECTED])
+Created 11/08/07
+===
+
+
+Changed files:
+==
+
+- board/freescale/m5373evb/m5373evb.c Dram setup
+- board/freescale/m5373evb/mii.c Mii access
+- board/freescale/m5373evb/MakefileMakefile
+- board/freescale/m5373evb/config.mk config make
+- board/freescale/m5373evb/u-boot.lds Linker description
+
+- cpu/mcf532x/cpu.ccpu specific code
+- cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
+- cpu/mcf532x/interrupts.c cpu specific interrupt support
+- cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock
+- cpu/mcf532x/Makefile Makefile
+- cpu/mcf532x/config.mkconfig make
+- cpu/mcf532x/start.S start up assembly code
+
+- doc/README.m5373evb This readme file
+
+- drivers/net/mcffec.c ColdFire common FEC driver
+- drivers/serial/mcfuart.c ColdFire common UART driver
+
+- include/asm-m68k/bitops.hBit operation function export
+- include/asm-m68k/byteorder.h Byte order functions
+- include/asm-m68k/fec.h FEC structure and definition
+- include/asm-m68k/fsl_i2c.h I2C structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h ColdFire specific header file and
driver macros
+- include/asm-m68k/immap_532x.h
[U-Boot-Users] [PATCH] ColdFire: Add modules header files
Add CF specific modules header files
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
include/asm-m68k/coldfire/crossbar.h | 79 +
include/asm-m68k/coldfire/dspi.h | 156 +
include/asm-m68k/coldfire/edma.h | 177
include/asm-m68k/coldfire/flexbus.h | 98
include/asm-m68k/coldfire/lcd.h | 213 ++
include/asm-m68k/coldfire/ssi.h | 175
6 files changed, 898 insertions(+), 0 deletions(-)
create mode 100644 include/asm-m68k/coldfire/crossbar.h
create mode 100644 include/asm-m68k/coldfire/dspi.h
create mode 100644 include/asm-m68k/coldfire/edma.h
create mode 100644 include/asm-m68k/coldfire/flexbus.h
create mode 100644 include/asm-m68k/coldfire/lcd.h
create mode 100644 include/asm-m68k/coldfire/ssi.h
diff --git a/include/asm-m68k/coldfire/crossbar.h
b/include/asm-m68k/coldfire/crossbar.h
new file mode 100644
index 000..a9c724c
--- /dev/null
+++ b/include/asm-m68k/coldfire/crossbar.h
@@ -0,0 +1,79 @@
+/*
+ * Cross Bar Switch Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew ([EMAIL PROTECTED])
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CROSSBAR_H__
+#define __CROSSBAR_H__
+
+/*
+* Cross-bar switch (XBS)
+*/
+typedef struct xbs {
+ u32 prs1; /* 0x100 Priority Register Slave 1 */
+ u32 res1[3];/* 0x104 - 0F */
+ u32 crs1; /* 0x110 Control Register Slave 1 */
+ u32 res2[187]; /* 0x114 - 0x3FF */
+
+ u32 prs4; /* 0x400 Priority Register Slave 4 */
+ u32 res3[3];/* 0x404 - 0F */
+ u32 crs4; /* 0x410 Control Register Slave 4 */
+ u32 res4[123]; /* 0x414 - 0x5FF */
+
+ u32 prs6; /* 0x600 Priority Register Slave 6 */
+ u32 res5[3];/* 0x604 - 0F */
+ u32 crs6; /* 0x610 Control Register Slave 6 */
+ u32 res6[59]; /* 0x614 - 0x6FF */
+
+ u32 prs7; /* 0x700 Priority Register Slave 7 */
+ u32 res7[3];/* 0x704 - 0F */
+ u32 crs7; /* 0x710 Control Register Slave 7 */
+} xbs_t;
+
+/* Bit definitions and macros for PRS group */
+#define XBS_PRS_M0(x) (((x)&0x0007)) /* Core */
+#define XBS_PRS_M1(x) (((x)&0x0007)<<4) /* eDMA */
+#define XBS_PRS_M2(x) (((x)&0x0007)<<8) /* FEC0 */
+#define XBS_PRS_M3(x) (((x)&0x0007)<<12) /* FEC1 */
+#define XBS_PRS_M5(x) (((x)&0x0007)<<20) /* PCI
controller */
+#define XBS_PRS_M6(x) (((x)&0x0007)<<24) /* USB OTG */
+#define XBS_PRS_M7(x) (((x)&0x0007)<<28) /* Serial Boot
*/
+
+/* Bit definitions and macros for CRS group */
+#define XBS_CRS_PARK(x)(((x)&0x0007)) /*
Master parking ctrl */
+#define XBS_CRS_PCTL(x)(((x)&0x0003)<<4) /*
Parking mode ctrl */
+#define XBS_CRS_ARB(0x0100)/* Arbitration Mode */
+#define XBS_CRS_RO (0x8000)/* Read Only */
+
+#define XBS_CRS_PCTL_PARK_FIELD(0)
+#define XBS_CRS_PCTL_PARK_ON_LAST (1)
+#define XBS_CRS_PCTL_PARK_NONE (2)
+#define XBS_CRS_PCTL_PARK_CORE (0)
+#define XBS_CRS_PCTL_PARK_EDMA (1)
+#define XBS_CRS_PCTL_PARK_FEC0 (2)
+#define XBS_CRS_PCTL_PARK_FEC1 (3)
+#define XBS_CRS_PCTL_PARK_PCI (5)
+#define XBS_CRS_PCTL_PARK_USB (6)
+#define XBS_CRS_PCTL_PARK_SBF (7)
+
+#endif /* __CROSSBAR_H__ */
diff --git a/include/asm-m68k/coldfire/dspi.h b/include/asm-m68k/coldfire/dspi.h
new file mode 100644
index 000..3c579d3
--- /dev/null
+++ b/include/asm-m68k/coldfire/dspi.h
@@ -0,0 +1,156 @@
+/*
+ * MCF5227x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale
[U-Boot-Users] [PATCH] ColdFire: PCI and misc updates for MCF5445x
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
cpu/mcf5445x/cpu_init.c |1 -
cpu/mcf5445x/pci.c | 61 --
cpu/mcf5445x/start.S| 25 ++---
include/asm-m68k/immap.h|8 +++---
include/asm-m68k/m5445x.h | 14 +-
include/configs/M54455EVB.h | 14 +
6 files changed, 46 insertions(+), 77 deletions(-)
diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c
index 6622eee..585216d 100644
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -113,7 +113,6 @@ int cpu_init_r(void)
#ifdef CONFIG_MCFTMR
volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
- u32 oscillator = CFG_RTC_OSCILLATOR;
rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0x;
rtcex->gocl = CFG_RTC_OSCILLATOR & 0x;
diff --git a/cpu/mcf5445x/pci.c b/cpu/mcf5445x/pci.c
index 8ace536..0398469 100644
--- a/cpu/mcf5445x/pci.c
+++ b/cpu/mcf5445x/pci.c
@@ -46,48 +46,18 @@ int pci_##rw##_cfg_##size(struct pci_controller *hose,
\
u16 cfg_type = 0; \
addr = ((offset & 0xfc) | cfg_type | (dev) | 0x8000); \
out_be32(hose->cfg_addr, addr); \
- __asm__ __volatile__("nop");\
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
out_be32(hose->cfg_addr, addr & 0x7fff);\
- __asm__ __volatile__("nop");\
return 0; \
}
PCI_OP(read, byte, u8 *, in_8, 3)
PCI_OP(read, word, u16 *, in_le16, 2)
+PCI_OP(read, dword, u32 *, in_le32, 0)
PCI_OP(write, byte, u8, out_8, 3)
PCI_OP(write, word, u16, out_le16, 2)
PCI_OP(write, dword, u32, out_le32, 0)
-int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
- int offset, u32 * val)
-{
- u32 addr;
- u32 tmpv;
- u32 mask = 2; /* word access */
- /* Read lower 16 bits */
- addr = ((offset & 0xfc) | (dev) | 0x8000);
- out_be32(hose->cfg_addr, addr);
- __asm__ __volatile__("nop");
- *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
- out_be32(hose->cfg_addr, addr & 0x7fff);
- __asm__ __volatile__("nop");
-
- /* Read upper 16 bits */
- offset += 2;
- addr = ((offset & 0xfc) | 1 | (dev) | 0x8000);
- out_be32(hose->cfg_addr, addr);
- __asm__ __volatile__("nop");
- tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
- out_be32(hose->cfg_addr, addr & 0x7fff);
- __asm__ __volatile__("nop");
-
- /* combine results into dword value */
- *val = (tmpv << 16) | *val;
-
- return 0;
-}
-
void pci_mcf5445x_init(struct pci_controller *hose)
{
volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
@@ -95,7 +65,7 @@ void pci_mcf5445x_init(struct pci_controller *hose)
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
u32 barEn = 0;
- pciarb->acr = 0x001f001f;
+ pciarb->acr = 0x001F001F;
/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
PCIREQ2, PCIGNT2 */
@@ -104,53 +74,58 @@ void pci_mcf5445x_init(struct pci_controller *hose)
GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;
+ /* Assert reset bit */
+ pci->gscr |= PCI_GSCR_PR;
+
pci->tcr1 |= PCI_TCR1_P;
/* Initiator windows */
- pci->iw0btar = CFG_PCI_MEM_PHYS;
- pci->iw1btar = CFG_PCI_IO_PHYS;
- pci->iw2btar = CFG_PCI_CFG_PHYS;
+ pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16);
+ pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16);
+ pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);
pci->iwcr =
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
+ pci->icr = 0;
+
/* Enable bus master and mem access */
- pci->scr = PCI_SCR_MW | PCI_SCR_B | PCI_SCR_M;
+ pci->scr = PCI_SCR_B | PCI_SCR_M;
/* Cache line size and master latency */
- pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xFF);
+ pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
pci->cr2 = 0;
#ifdef CFG_PCI_BAR0
pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN;
- barEn |= PCI_TCR1_B0E;
+ barEn |= PCI_TCR2_B0E;
#endif
#ifdef CFG_PCI_BAR1
pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN;
- barEn |= PCI_TCR1_B1E;
+ barEn |= PCI_TCR2_B1E;
#endif
#ifdef CFG_PCI_BAR2
pci->bar2 = PCI_BAR_
[U-Boot-Users] [PATCH] ColdFire: MCF5445x header files cleanup
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
include/asm-m68k/immap_5445x.h | 521
include/asm-m68k/m5445x.h | 302 +---
2 files changed, 46 insertions(+), 777 deletions(-)
diff --git a/include/asm-m68k/immap_5445x.h b/include/asm-m68k/immap_5445x.h
index d091d7b..ef8930e 100644
--- a/include/asm-m68k/immap_5445x.h
+++ b/include/asm-m68k/immap_5445x.h
@@ -33,6 +33,7 @@
#define MMAP_FEC0 0xFC03
#define MMAP_FEC1 0xFC034000
#define MMAP_RTC 0xFC03C000
+#define MMAP_SCM2 0xFC04
#define MMAP_EDMA 0xFC044000
#define MMAP_INTC0 0xFC048000
#define MMAP_INTC1 0xFC04C000
@@ -63,11 +64,18 @@
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C4000
#define MMAP_ATA 0x9000
-
-/*
-* ATA
-*/
-
+#define MMAP_USBHW 0xFC0B
+#define MMAP_USBCAPS 0xFC0B0100
+#define MMAP_USBEHCI 0xFC0B0140
+#define MMAP_USBOTG0xFC0B01A0
+
+#include
+#include
+#include
+#include
+#include
+
+/* ATA */
typedef struct atac {
/* PIO */
u8 toff;/* 0x00 */
@@ -117,379 +125,7 @@ typedef struct atac {
u8 rsvd6[106];
} atac_t;
-/*
-* Cross-bar switch (XBS)
-*/
-
-typedef struct xbs {
- u8 resv0[0x100];
- u32 prs1; /* XBS Priority Register */
- u8 resv1[0xC];
- u32 crs1; /* XBS Control Register */
- u8 resv2[0xEC];
- u32 prs2; /* XBS Priority Register */
- u8 resv3[0xC];
- u32 crs2; /* XBS Control Register */
- u8 resv4[0xEC];
- u32 prs3; /* XBS Priority Register */
- u8 resv5[0xC];
- u32 crs3; /* XBS Control Register */
- u8 resv6[0xEC];
- u32 prs4; /* XBS Priority Register */
- u8 resv7[0xC];
- u32 crs4; /* XBS Control Register */
- u8 resv8[0xEC];
- u32 prs5; /* XBS Priority Register */
- u8 resv9[0xC];
- u32 crs5; /* XBS Control Register */
- u8 resv10[0xEC];
- u32 prs6; /* XBS Priority Register */
- u8 resv11[0xC];
- u32 crs6; /* XBS Control Register */
- u8 resv12[0xEC];
- u32 prs7; /* XBS Priority Register */
- u8 resv13[0xC];
- u32 crs7; /* XBS Control Register */
-} xbs_t;
-
-/*
-* FlexBus Chip Selects (FBCS)
-*/
-
-typedef struct fbcs {
- u32 csar0; /* Chip-select Address Register */
- u32 csmr0; /* Chip-select Mask Register */
- u32 cscr0; /* Chip-select Control Register */
- u32 csar1; /* Chip-select Address Register */
- u32 csmr1; /* Chip-select Mask Register */
- u32 cscr1; /* Chip-select Control Register */
- u32 csar2; /* Chip-select Address Register */
- u32 csmr2; /* Chip-select Mask Register */
- u32 cscr2; /* Chip-select Control Register */
- u32 csar3; /* Chip-select Address Register */
- u32 csmr3; /* Chip-select Mask Register */
- u32 cscr3; /* Chip-select Control Register */
-} fbcs_t;
-
-/*
-* Enhanced DMA (EDMA)
-*/
-
-typedef struct edma {
- u32 cr;
- u32 es;
- u8 resv0[0x6];
- u16 erq;
- u8 resv1[0x6];
- u16 eei;
- u8 serq;
- u8 cerq;
- u8 seei;
- u8 ceei;
- u8 cint;
- u8 cerr;
- u8 ssrt;
- u8 cdne;
- u8 resv2[0x6];
- u16 intr;
- u8 resv3[0x6];
- u16 err;
- u8 resv4[0xD0];
- u8 dchpri0;
- u8 dchpri1;
- u8 dchpri2;
- u8 dchpri3;
- u8 dchpri4;
- u8 dchpri5;
- u8 dchpri6;
- u8 dchpri7;
- u8 dchpri8;
- u8 dchpri9;
- u8 dchpri10;
- u8 dchpri11;
- u8 dchpri12;
- u8 dchpri13;
- u8 dchpri14;
- u8 dchpri15;
- u8 resv5[0xEF0];
- u32 tcd0_saddr;
- u16 tcd0_attr;
- u16 tcd0_soff;
- u32 tcd0_nbytes;
- u32 tcd0_slast;
- u32 tcd0_daddr;
- union {
- u16 tcd0_citer_elink;
- u16 tcd0_citer;
- };
- u16 tcd0_doff;
- u32 tcd0_dlast_sga;
- union {
- u16 tcd0_biter_elink;
- u16 tcd0_biter;
[U-Boot-Users] [PATCH] ColdFire: MCF532x header files cleanup
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
include/asm-m68k/immap_5329.h | 193 +---
include/asm-m68k/m5329.h | 281 -
2 files changed, 6 insertions(+), 468 deletions(-)
diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h
index 271c276..7ff0b93 100644
--- a/include/asm-m68k/immap_5329.h
+++ b/include/asm-m68k/immap_5329.h
@@ -68,6 +68,12 @@
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C
+#include
+#include
+#include
+#include
+#include
+
/* System control module registers */
typedef struct scm1_ctrl {
u32 mpr0; /* 0x00 Master Privilege Register 0 */
@@ -159,61 +165,6 @@ typedef struct scm2_ctrl {
u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
} scm2_t;
-/* Cross-Bar Switch Module */
-typedef struct xbs_ctrl {
- u32 prs1; /* 0x100 Priority Register Slave 1 */
- u32 res1[3];/* 0x104 - 0F */
- u32 crs1; /* 0x110 Control Register Slave 1 */
- u32 res2[187]; /* 0x114 - 0x3FF */
-
- u32 prs4; /* 0x400 Priority Register Slave 4 */
- u32 res3[3];/* 0x404 - 0F */
- u32 crs4; /* 0x410 Control Register Slave 4 */
- u32 res4[123]; /* 0x414 - 0x5FF */
-
- u32 prs6; /* 0x600 Priority Register Slave 6 */
- u32 res5[3];/* 0x604 - 0F */
- u32 crs6; /* 0x610 Control Register Slave 6 */
- u32 res6[59]; /* 0x614 - 0x6FF */
-
- u32 prs7; /* 0x700 Priority Register Slave 7 */
- u32 res7[3];/* 0x704 - 0F */
- u32 crs7; /* 0x710 Control Register Slave 7 */
-} xbs_t;
-
-/* Flexbus module Chip select registers */
-typedef struct fbcs_ctrl {
- u16 csar0; /* 0x00 Chip-Select Address Register 0 */
- u16 res0;
- u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
- u32 cscr0; /* 0x08 Chip-Select Control Register 0 */
-
- u16 csar1; /* 0x0C Chip-Select Address Register 1 */
- u16 res1;
- u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
- u32 cscr1; /* 0x14 Chip-Select Control Register 1 */
-
- u16 csar2; /* 0x18 Chip-Select Address Register 2 */
- u16 res2;
- u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
- u32 cscr2; /* 0x20 Chip-Select Control Register 2 */
-
- u16 csar3; /* 0x24 Chip-Select Address Register 3 */
- u16 res3;
- u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
- u32 cscr3; /* 0x2C Chip-Select Control Register 3 */
-
- u16 csar4; /* 0x30 Chip-Select Address Register 4 */
- u16 res4;
- u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
- u32 cscr4; /* 0x38 Chip-Select Control Register 4 */
-
- u16 csar5; /* 0x3C Chip-Select Address Register 5 */
- u16 res5;
- u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
- u32 cscr5; /* 0x44 Chip-Select Control Register 5 */
-} fbcs_t;
-
/* FlexCan module registers */
typedef struct can_ctrl {
u32 mcr;/* 0x00 Module Configuration register */
@@ -255,64 +206,6 @@ typedef struct scm3_ctrl {
u32 cfdtr; /* 0x7C Core Fault Data Register */
} scm3_t;
-/* eDMA module registers */
-typedef struct edma_ctrl {
- u32 cr; /* 0x00 Control Register */
- u32 es; /* 0x04 Error Status Register */
- u16 res1[3];/* 0x08 - 0x0D */
- u16 erq;/* 0x0E Enable Request Register */
- u16 res2[3];/* 0x10 - 0x15 */
- u16 eei;/* 0x16 Enable Error Interrupt Request */
- u8 serq;/* 0x18 Set Enable Request */
- u8 cerq;/* 0x19 Clear Enable Request */
- u8 seei;/* 0x1A Set Enable Error Interrupt Request */
- u8 ceei;/* 0x1B Clear Enable Error Interrupt Request */
- u8 cint;/* 0x1C Clear Interrupt Enable Register */
- u8 cerr;/* 0x1D Clear Error Register */
- u8 ssrt;/* 0x1E Set START Bit Register */
- u8 cdne;/* 0x1F Clear DONE Status Bit Register */
- u16 res3[3];/* 0x20 - 0x25 */
- u16 intr; /* 0x26 Interrupt Request Register */
- u16 res4[3];/* 0x28 - 0x2D */
- u16 err;/* 0x2E Error Register */
- u32 res5[52]; /* 0x30 - 0xFF */
- u8 dchpri0; /* 0x100 Channel 0 Priority Register */
- u8 dchpri1; /* 0x101 Channel 1 Priority
[U-Boot-Users] [PATCH] ColdFire: Add modules header files
Add CF specific modules header files
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
include/asm-m68k/coldfire/crossbar.h | 79 +
include/asm-m68k/coldfire/dspi.h | 156 +
include/asm-m68k/coldfire/edma.h | 177
include/asm-m68k/coldfire/flexbus.h | 98
include/asm-m68k/coldfire/lcd.h | 213 ++
include/asm-m68k/coldfire/ssi.h | 175
6 files changed, 898 insertions(+), 0 deletions(-)
create mode 100644 include/asm-m68k/coldfire/crossbar.h
create mode 100644 include/asm-m68k/coldfire/dspi.h
create mode 100644 include/asm-m68k/coldfire/edma.h
create mode 100644 include/asm-m68k/coldfire/flexbus.h
create mode 100644 include/asm-m68k/coldfire/lcd.h
create mode 100644 include/asm-m68k/coldfire/ssi.h
diff --git a/include/asm-m68k/coldfire/crossbar.h
b/include/asm-m68k/coldfire/crossbar.h
new file mode 100644
index 000..a9c724c
--- /dev/null
+++ b/include/asm-m68k/coldfire/crossbar.h
@@ -0,0 +1,79 @@
+/*
+ * Cross Bar Switch Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew ([EMAIL PROTECTED])
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CROSSBAR_H__
+#define __CROSSBAR_H__
+
+/*
+* Cross-bar switch (XBS)
+*/
+typedef struct xbs {
+ u32 prs1; /* 0x100 Priority Register Slave 1 */
+ u32 res1[3];/* 0x104 - 0F */
+ u32 crs1; /* 0x110 Control Register Slave 1 */
+ u32 res2[187]; /* 0x114 - 0x3FF */
+
+ u32 prs4; /* 0x400 Priority Register Slave 4 */
+ u32 res3[3];/* 0x404 - 0F */
+ u32 crs4; /* 0x410 Control Register Slave 4 */
+ u32 res4[123]; /* 0x414 - 0x5FF */
+
+ u32 prs6; /* 0x600 Priority Register Slave 6 */
+ u32 res5[3];/* 0x604 - 0F */
+ u32 crs6; /* 0x610 Control Register Slave 6 */
+ u32 res6[59]; /* 0x614 - 0x6FF */
+
+ u32 prs7; /* 0x700 Priority Register Slave 7 */
+ u32 res7[3];/* 0x704 - 0F */
+ u32 crs7; /* 0x710 Control Register Slave 7 */
+} xbs_t;
+
+/* Bit definitions and macros for PRS group */
+#define XBS_PRS_M0(x) (((x)&0x0007)) /* Core */
+#define XBS_PRS_M1(x) (((x)&0x0007)<<4) /* eDMA */
+#define XBS_PRS_M2(x) (((x)&0x0007)<<8) /* FEC0 */
+#define XBS_PRS_M3(x) (((x)&0x0007)<<12) /* FEC1 */
+#define XBS_PRS_M5(x) (((x)&0x0007)<<20) /* PCI
controller */
+#define XBS_PRS_M6(x) (((x)&0x0007)<<24) /* USB OTG */
+#define XBS_PRS_M7(x) (((x)&0x0007)<<28) /* Serial Boot
*/
+
+/* Bit definitions and macros for CRS group */
+#define XBS_CRS_PARK(x)(((x)&0x0007)) /*
Master parking ctrl */
+#define XBS_CRS_PCTL(x)(((x)&0x0003)<<4) /*
Parking mode ctrl */
+#define XBS_CRS_ARB(0x0100)/* Arbitration Mode */
+#define XBS_CRS_RO (0x8000)/* Read Only */
+
+#define XBS_CRS_PCTL_PARK_FIELD(0)
+#define XBS_CRS_PCTL_PARK_ON_LAST (1)
+#define XBS_CRS_PCTL_PARK_NONE (2)
+#define XBS_CRS_PCTL_PARK_CORE (0)
+#define XBS_CRS_PCTL_PARK_EDMA (1)
+#define XBS_CRS_PCTL_PARK_FEC0 (2)
+#define XBS_CRS_PCTL_PARK_FEC1 (3)
+#define XBS_CRS_PCTL_PARK_PCI (5)
+#define XBS_CRS_PCTL_PARK_USB (6)
+#define XBS_CRS_PCTL_PARK_SBF (7)
+
+#endif /* __CROSSBAR_H__ */
diff --git a/include/asm-m68k/coldfire/dspi.h b/include/asm-m68k/coldfire/dspi.h
new file mode 100644
index 000..3c579d3
--- /dev/null
+++ b/include/asm-m68k/coldfire/dspi.h
@@ -0,0 +1,156 @@
+/*
+ * MCF5227x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale
Re: [U-Boot-Users] [PATCH 1/2] Add support for a Freescale non-CPM SPIcontroller
> > fsl_spi.h might be a bit too general? How about non-8xxx Freescale > > processors? > > f > > > The naming convention was modeled after 'fsl_i2c', which surely isn't > universal to all Freescale I2C controllers either. In Linux, this > driver is called 'mpc83xx', which we've learned here is a bit too > specialized. I'll happily change the name, but don't know what that > should be. also, I have no idea for this name, how about the mpc8xxx_spi.c[h]? Best Regards, Dave - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [[PATCH] Resubmit] QE UEC: Extend number of supported UECs to 4
On Mon, 2008-01-14 at 19:24 +0200, David Saada wrote: > Description: David, You may delete the 'Description' in commit log > This patch extends the number of supported UECs to 4. Note that the > problem of QE thread resources exhaustion is resolved by setting the > correct number of QE threads according to Ethernet type (GBE or FE). The patch have whitespace, please clean up. Thanks, Dave Applying 'Resubmit] QE UEC: Extend number of supported UECs to 4' Adds trailing whitespace. .dotest/patch:7:#if (CFG_UEC1_ETH_TYPE == FAST_ETH) Adds trailing whitespace. .dotest/patch:21:#if (CFG_UEC2_ETH_TYPE == FAST_ETH) Adds trailing whitespace. .dotest/patch:43:#if (CFG_UEC3_ETH_TYPE == FAST_ETH) Adds trailing whitespace. .dotest/patch:65:#if (CFG_UEC4_ETH_TYPE == FAST_ETH) fatal: corrupt patch at line 107 Patch failed at 0001. - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 1/8] ColdFire: Add MCF547x_8x cpu arch
Guennadi, > At least this patch seems line-wrapped to me. Above is just one example. Will change to git-send-email, that should take care of it. >Is this really the correct comment here? I see the code is copied >from lib_m68k/time.c. Isn't lib_m68k going to be linked with this >board? Won't symbols conflict then? Obviously they don't, as you >are running this code, just I don't see immediately how this >works. And if CONFIG_SLTTMR is not defined, looks like get_timer >will be undefined, right? Is this the intended behaviour? The MCF547x_8x is a bit different from the rest of the Coldfire, it does not have dtimer nor pit. The only timer it has are slicetimer and general purpose timer. There won't be a conflict if any two or any three of these CONFIG_SLTTMR, CONFIG_MCFTMR or CONFIG_MCFPIT are defined as the same time. The only conflict functions are get_tbclk and get_ticks in slicetimer.c. I will remove them at once. Regards, TsiChung - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] ColdFire: Add modules header files
Wolfgang, I created a coldfire folder under asm-m68k, 6 modules were relocated to the new directory. I re-send some of the patches. Do I have to resubmit all the patches or just the affected patches from the changes? Regards, TsiChung -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Sent: Saturday, January 12, 2008 8:08 AM To: Liew Tsi Chung Cc: u-boot Subject: Re: [U-Boot-Users] [PATCH] ColdFire: Add modules header files In message <[EMAIL PROTECTED]> you wrote: > ColdFire: Add modules header files > > Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]> > --- > include/asm-m68k/crossbar.h | 79 > include/asm-m68k/dspi.h | 156 +++ > include/asm-m68k/edma.h | 177 +++ > include/asm-m68k/flexbus.h | 98 > include/asm-m68k/lcd.h | 213 > +++ > include/asm-m68k/ssi.h | 175 +++ > 6 files changed, 898 insertions(+), 0 deletions(-) create mode > 100644 include/asm-m68k/crossbar.h create mode 100644 > include/asm-m68k/dspi.h create mode 100644 include/asm-m68k/edma.h > create mode 100644 include/asm-m68k/flexbus.h create mode 100644 > include/asm-m68k/lcd.h create mode 100644 include/asm-m68k/ssi.h I understand that these are ColdFire specific files, which are probably not relevant to other, non-CF m68k systems? I think this should be visible from the file name. How about creating a directory ofr ColdFire related headers so we don't pollute the global name space too much? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED] Another dream that failed. There's nothing sadder. -- Kirk, "This side of Paradise", stardate 3417.3 - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] OneNAND: Separate U-Boot dependent code from OneNAND
OneNAND: Separate U-Boot dependent code from OneNAND
Signed-off-by: Kyungmin Park <[EMAIL PROTECTED]>
---
diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile
index 2049413..92074b2 100644
--- a/drivers/mtd/onenand/Makefile
+++ b/drivers/mtd/onenand/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB:= $(obj)libonenand.a
-COBJS := onenand_base.o onenand_bbt.o
+COBJS := onenand_uboot.o onenand_base.o onenand_bbt.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/drivers/mtd/onenand/onenand_base.c
b/drivers/mtd/onenand/onenand_base.c
index 7983a4a..d4003a2 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -1271,24 +1271,4 @@ void onenand_release(struct mtd_info *mtd)
{
}
-/*
- * OneNAND initialization at U-Boot
- */
-struct mtd_info onenand_mtd;
-struct onenand_chip onenand_chip;
-
-void onenand_init(void)
-{
- memset(&onenand_mtd, 0, sizeof(struct mtd_info));
- memset(&onenand_chip, 0, sizeof(struct onenand_chip));
-
- onenand_chip.base = (void *)CFG_ONENAND_BASE;
- onenand_mtd.priv = &onenand_chip;
-
- onenand_scan(&onenand_mtd, 1);
-
- puts("OneNAND: ");
- print_size(onenand_mtd.size, "\n");
-}
-
#endif /* CONFIG_CMD_ONENAND */
diff --git a/drivers/mtd/onenand/onenand_uboot.c
b/drivers/mtd/onenand/onenand_uboot.c
new file mode 100644
index 000..bd7466a
--- /dev/null
+++ b/drivers/mtd/onenand/onenand_uboot.c
@@ -0,0 +1,41 @@
+/*
+ * drivers/mtd/onenand/onenand_uboot.c
+ *
+ * Copyright (C) 2005-2008 Samsung Electronics
+ * Kyungmin Park <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * OneNAND initialization at U-Boot
+ */
+
+#include
+
+#ifdef CONFIG_CMD_ONENAND
+
+#include
+#include
+#include
+
+struct mtd_info onenand_mtd;
+struct onenand_chip onenand_chip;
+
+void onenand_init(void)
+{
+ memset(&onenand_mtd, 0, sizeof(struct mtd_info));
+ memset(&onenand_chip, 0, sizeof(struct onenand_chip));
+
+ onenand_chip.base = (void *) CFG_ONENAND_BASE;
+ onenand_mtd.priv = &onenand_chip;
+
+ onenand_scan(&onenand_mtd, 1);
+
+ puts("OneNAND: ");
+ print_size(onenand_mtd.size, "\n");
+}
+
+#endif /* CONFIG_CMD_ONENAND */
-
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Re: [U-Boot-Users] resend #2 [PATCH 1/5]: add AcTux board support (common)
In message <[EMAIL PROTECTED]> you wrote: > > > I have kept the small version of the mach-types.h patch to fir the list size > > limit - the full version of the patch, with mach-types.h generated from the > > current ARM machine database, is at: > > > > http://www.schwingen.org/actux.diff > > > > cu > > Michael > > > > Signed-off-by: Michael Schwingen <[EMAIL PROTECTED]> > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 2ef2f5c..9291f48 100644 > Nack, > > I've an error when applying this patch > fatal: corrupt patch at line 56 > Patch failed at 0014. Sorry, forgot to mention this - I wnet ahead and updated the mach-types file. Please rebase your patches against TOT, and your patch size should go down significantly. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED] Computers make excellent and efficient servants, but I have no wish to serve under them. Captain, a starship also runs on loyalty to one man. And nothing can replace it or him. -- Spock, "The Ultimate Computer", stardate 4729.4 - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 2/2] ColdFire: Add M5373EVB platform support - 2
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
MAINTAINERS |1 +
MAKEALL |3 +-
Makefile | 10 ++
cpu/mcf532x/cpu.c | 20 +++-
doc/README.m5373evb | 334 +
include/asm-m68k/immap.h |4 +-
include/asm-m68k/immap_5329.h | 89 +---
include/asm-m68k/m5329.h |5 +
include/configs/M5373EVB.h| 267
9 files changed, 709 insertions(+), 24 deletions(-)
create mode 100644 doc/README.m5373evb
create mode 100644 include/configs/M5373EVB.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2ef2f5c..02698c8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -629,6 +629,7 @@ TsiChung Liew <[EMAIL PROTECTED]>
M5235EVBmcf52x2
M5329EVBmcf532x
+ M5373EVBmcf532x
M54455EVB mcf5445x
Hayden Fraser <[EMAIL PROTECTED]>
diff --git a/MAKEALL b/MAKEALL
index ebc5a22..1f59532 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -641,7 +641,8 @@ LIST_coldfire=" \
M5271EVB\
M5272C3 \
M5282EVB\
- M5329EVB\
+ M5329AFEE \
+ M5373EVB\
M54455EVB \
r5200 \
TASREG \
diff --git a/Makefile b/Makefile
index 1983ca0..f541392 100644
--- a/Makefile
+++ b/Makefile
@@ -1793,6 +1793,16 @@ M5329BFEE_config : unconfig
fi
@$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale
+M5373EVB_config : unconfig
+ @case "$@" in \
+ M5373EVB_config)NAND=16;; \
+ esac; \
+ >include/config.h ; \
+ if [ "$${NAND}" != "0" ] ; then \
+ echo "#define NANDFLASH_SIZE$${NAND}" >
$(obj)include/config.h ; \
+ fi
+ @$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale
+
M54455EVB_config \
M54455EVB_atmel_config \
M54455EVB_intel_config \
diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c
index 89cc8ad..61541ab 100644
--- a/cpu/mcf532x/cpu.c
+++ b/cpu/mcf532x/cpu.c
@@ -64,6 +64,18 @@ int checkcpu(void)
case 0x61:
id = 5327;
break;
+ case 0x65:
+ id = 5373;
+ break;
+ case 0x68:
+ id = 53721;
+ break;
+ case 0x69:
+ id = 5372;
+ break;
+ case 0x6B:
+ id = 5372;
+ break;
}
if (id) {
@@ -84,6 +96,7 @@ void watchdog_reset(void)
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
wdp->sr = 0x; /* Count register */
+ wdp->sr = 0x; /* Count register */
}
int watchdog_disable(void)
@@ -104,8 +117,11 @@ int watchdog_init(void)
/* set timeout and enable watchdog */
wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
- wdog_module |= (wdog_module / 8192);
- wdp->mr = wdog_module;
+#ifdef CONFIG_M5329
+ wdp->mr = (wdog_module / 8192);
+#else
+ wdp->mr = (wdog_module / 4096);
+#endif
wdp->cr = WTM_WCR_EN;
puts("WATCHDOG:enabled\n");
diff --git a/doc/README.m5373evb b/doc/README.m5373evb
new file mode 100644
index 000..62768ac
--- /dev/null
+++ b/doc/README.m5373evb
@@ -0,0 +1,334 @@
+Freescale MCF5373EVB ColdFire Development Board
+
+
+TsiChung Liew([EMAIL PROTECTED])
+Created 11/08/07
+===
+
+
+Changed files:
+==
+
+- board/freescale/m5373evb/m5373evb.c Dram setup
+- board/freescale/m5373evb/mii.c Mii access
+- board/freescale/m5373evb/MakefileMakefile
+- board/freescale/m5373evb/config.mk config make
+- board/freescale/m5373evb/u-boot.lds Linker description
+
+- cpu/mcf532x/cpu.ccpu specific code
+- cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
+- cpu/mcf532x/interrupts.c cpu specific interrupt support
+- cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock
+- cpu/mcf532x/Makefile Makefile
+- cpu/mcf532x/config.mkconfig make
+- cpu/mcf532x/start.S start up assembly code
+
+- doc/README.m5373evb This readme file
+
+- drivers/net/mcffec.c ColdFire common FEC driver
+- drivers/serial/mcfuart.c ColdFire common UART driver
+
+- include/asm-m68k/bitops.hBit operation function export
+- include/asm-m68k/byteorder.h Byte order functions
+- include/asm-m68k/fec.h FEC structure and definition
+- include/asm-m68k/fsl_i2c.h I2C structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h ColdFire specific header file and
driver macros
+- include/asm-m68k/immap_532x.h
[U-Boot-Users] [PATCH 1/2] ColdFire: Add M5373EVB platform support - 1
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
board/freescale/m5373evb/Makefile | 44 +
board/freescale/m5373evb/config.mk | 25 +++
board/freescale/m5373evb/m5373evb.c | 88 ++
board/freescale/m5373evb/mii.c | 306 +++
board/freescale/m5373evb/nand.c | 114 +
board/freescale/m5373evb/u-boot.lds | 144
6 files changed, 721 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/m5373evb/Makefile
create mode 100644 board/freescale/m5373evb/config.mk
create mode 100644 board/freescale/m5373evb/m5373evb.c
create mode 100644 board/freescale/m5373evb/mii.c
create mode 100644 board/freescale/m5373evb/nand.c
create mode 100644 board/freescale/m5373evb/u-boot.lds
diff --git a/board/freescale/m5373evb/Makefile
b/board/freescale/m5373evb/Makefile
new file mode 100644
index 000..ab0f11e
--- /dev/null
+++ b/board/freescale/m5373evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o mii.o nand.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/freescale/m5373evb/config.mk
b/board/freescale/m5373evb/config.mk
new file mode 100644
index 000..ce014ed
--- /dev/null
+++ b/board/freescale/m5373evb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+# Coldfire contribution by Bernhard Kuhn <[EMAIL PROTECTED]>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0
diff --git a/board/freescale/m5373evb/m5373evb.c
b/board/freescale/m5373evb/m5373evb.c
new file mode 100644
index 000..26b87b9
--- /dev/null
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew ([EMAIL PROTECTED])
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale FireEngine 5373 EVB\n");
+ return 0;
+};
+
+long in
Re: [U-Boot-Users] resend #2 [PATCH 1/5]: add AcTux board support (common)
On 09:02 Mon 14 Jan , Michael Schwingen wrote: > Hi, > > 2nd resend of the previous patch set with formatting fixed (hopefully). > > The patch adds 4 boards, called AcTux-1 .. AcTux-4. This patch contains the > files that > contain changes for multiple boards, the board-specific files follow as > separate patches. > > I have kept the small version of the mach-types.h patch to fir the list size > limit - the full version of the patch, with mach-types.h generated from the > current ARM machine database, is at: > > http://www.schwingen.org/actux.diff > > cu > Michael > > Signed-off-by: Michael Schwingen <[EMAIL PROTECTED]> > > diff --git a/MAINTAINERS b/MAINTAINERS > index 2ef2f5c..9291f48 100644 Nack, I've an error when applying this patch fatal: corrupt patch at line 56 Patch failed at 0014. could you fix it and resend your patch thanks - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] ColdFire: MCF5445x header files cleanup
From: TsiChungLiew <[EMAIL PROTECTED]>
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
include/asm-m68k/immap_5445x.h | 521
include/asm-m68k/m5445x.h | 302 +---
2 files changed, 46 insertions(+), 777 deletions(-)
diff --git a/include/asm-m68k/immap_5445x.h b/include/asm-m68k/immap_5445x.h
index d091d7b..ef8930e 100644
--- a/include/asm-m68k/immap_5445x.h
+++ b/include/asm-m68k/immap_5445x.h
@@ -33,6 +33,7 @@
#define MMAP_FEC0 0xFC03
#define MMAP_FEC1 0xFC034000
#define MMAP_RTC 0xFC03C000
+#define MMAP_SCM2 0xFC04
#define MMAP_EDMA 0xFC044000
#define MMAP_INTC0 0xFC048000
#define MMAP_INTC1 0xFC04C000
@@ -63,11 +64,18 @@
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C4000
#define MMAP_ATA 0x9000
-
-/*
-* ATA
-*/
-
+#define MMAP_USBHW 0xFC0B
+#define MMAP_USBCAPS 0xFC0B0100
+#define MMAP_USBEHCI 0xFC0B0140
+#define MMAP_USBOTG0xFC0B01A0
+
+#include
+#include
+#include
+#include
+#include
+
+/* ATA */
typedef struct atac {
/* PIO */
u8 toff;/* 0x00 */
@@ -117,379 +125,7 @@ typedef struct atac {
u8 rsvd6[106];
} atac_t;
-/*
-* Cross-bar switch (XBS)
-*/
-
-typedef struct xbs {
- u8 resv0[0x100];
- u32 prs1; /* XBS Priority Register */
- u8 resv1[0xC];
- u32 crs1; /* XBS Control Register */
- u8 resv2[0xEC];
- u32 prs2; /* XBS Priority Register */
- u8 resv3[0xC];
- u32 crs2; /* XBS Control Register */
- u8 resv4[0xEC];
- u32 prs3; /* XBS Priority Register */
- u8 resv5[0xC];
- u32 crs3; /* XBS Control Register */
- u8 resv6[0xEC];
- u32 prs4; /* XBS Priority Register */
- u8 resv7[0xC];
- u32 crs4; /* XBS Control Register */
- u8 resv8[0xEC];
- u32 prs5; /* XBS Priority Register */
- u8 resv9[0xC];
- u32 crs5; /* XBS Control Register */
- u8 resv10[0xEC];
- u32 prs6; /* XBS Priority Register */
- u8 resv11[0xC];
- u32 crs6; /* XBS Control Register */
- u8 resv12[0xEC];
- u32 prs7; /* XBS Priority Register */
- u8 resv13[0xC];
- u32 crs7; /* XBS Control Register */
-} xbs_t;
-
-/*
-* FlexBus Chip Selects (FBCS)
-*/
-
-typedef struct fbcs {
- u32 csar0; /* Chip-select Address Register */
- u32 csmr0; /* Chip-select Mask Register */
- u32 cscr0; /* Chip-select Control Register */
- u32 csar1; /* Chip-select Address Register */
- u32 csmr1; /* Chip-select Mask Register */
- u32 cscr1; /* Chip-select Control Register */
- u32 csar2; /* Chip-select Address Register */
- u32 csmr2; /* Chip-select Mask Register */
- u32 cscr2; /* Chip-select Control Register */
- u32 csar3; /* Chip-select Address Register */
- u32 csmr3; /* Chip-select Mask Register */
- u32 cscr3; /* Chip-select Control Register */
-} fbcs_t;
-
-/*
-* Enhanced DMA (EDMA)
-*/
-
-typedef struct edma {
- u32 cr;
- u32 es;
- u8 resv0[0x6];
- u16 erq;
- u8 resv1[0x6];
- u16 eei;
- u8 serq;
- u8 cerq;
- u8 seei;
- u8 ceei;
- u8 cint;
- u8 cerr;
- u8 ssrt;
- u8 cdne;
- u8 resv2[0x6];
- u16 intr;
- u8 resv3[0x6];
- u16 err;
- u8 resv4[0xD0];
- u8 dchpri0;
- u8 dchpri1;
- u8 dchpri2;
- u8 dchpri3;
- u8 dchpri4;
- u8 dchpri5;
- u8 dchpri6;
- u8 dchpri7;
- u8 dchpri8;
- u8 dchpri9;
- u8 dchpri10;
- u8 dchpri11;
- u8 dchpri12;
- u8 dchpri13;
- u8 dchpri14;
- u8 dchpri15;
- u8 resv5[0xEF0];
- u32 tcd0_saddr;
- u16 tcd0_attr;
- u16 tcd0_soff;
- u32 tcd0_nbytes;
- u32 tcd0_slast;
- u32 tcd0_daddr;
- union {
- u16 tcd0_citer_elink;
- u16 tcd0_citer;
- };
- u16 tcd0_doff;
- u32 tcd0_dlast_sga;
- union {
- u16 tcd0_biter
[U-Boot-Users] [PATCH] ColdFire: MCF532x header files cleanup
From: TsiChungLiew <[EMAIL PROTECTED]>
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
include/asm-m68k/immap_5329.h | 193 +---
include/asm-m68k/m5329.h | 281 -
2 files changed, 6 insertions(+), 468 deletions(-)
diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h
index 271c276..7ff0b93 100644
--- a/include/asm-m68k/immap_5329.h
+++ b/include/asm-m68k/immap_5329.h
@@ -68,6 +68,12 @@
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C
+#include
+#include
+#include
+#include
+#include
+
/* System control module registers */
typedef struct scm1_ctrl {
u32 mpr0; /* 0x00 Master Privilege Register 0 */
@@ -159,61 +165,6 @@ typedef struct scm2_ctrl {
u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
} scm2_t;
-/* Cross-Bar Switch Module */
-typedef struct xbs_ctrl {
- u32 prs1; /* 0x100 Priority Register Slave 1 */
- u32 res1[3];/* 0x104 - 0F */
- u32 crs1; /* 0x110 Control Register Slave 1 */
- u32 res2[187]; /* 0x114 - 0x3FF */
-
- u32 prs4; /* 0x400 Priority Register Slave 4 */
- u32 res3[3];/* 0x404 - 0F */
- u32 crs4; /* 0x410 Control Register Slave 4 */
- u32 res4[123]; /* 0x414 - 0x5FF */
-
- u32 prs6; /* 0x600 Priority Register Slave 6 */
- u32 res5[3];/* 0x604 - 0F */
- u32 crs6; /* 0x610 Control Register Slave 6 */
- u32 res6[59]; /* 0x614 - 0x6FF */
-
- u32 prs7; /* 0x700 Priority Register Slave 7 */
- u32 res7[3];/* 0x704 - 0F */
- u32 crs7; /* 0x710 Control Register Slave 7 */
-} xbs_t;
-
-/* Flexbus module Chip select registers */
-typedef struct fbcs_ctrl {
- u16 csar0; /* 0x00 Chip-Select Address Register 0 */
- u16 res0;
- u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
- u32 cscr0; /* 0x08 Chip-Select Control Register 0 */
-
- u16 csar1; /* 0x0C Chip-Select Address Register 1 */
- u16 res1;
- u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
- u32 cscr1; /* 0x14 Chip-Select Control Register 1 */
-
- u16 csar2; /* 0x18 Chip-Select Address Register 2 */
- u16 res2;
- u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
- u32 cscr2; /* 0x20 Chip-Select Control Register 2 */
-
- u16 csar3; /* 0x24 Chip-Select Address Register 3 */
- u16 res3;
- u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
- u32 cscr3; /* 0x2C Chip-Select Control Register 3 */
-
- u16 csar4; /* 0x30 Chip-Select Address Register 4 */
- u16 res4;
- u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
- u32 cscr4; /* 0x38 Chip-Select Control Register 4 */
-
- u16 csar5; /* 0x3C Chip-Select Address Register 5 */
- u16 res5;
- u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
- u32 cscr5; /* 0x44 Chip-Select Control Register 5 */
-} fbcs_t;
-
/* FlexCan module registers */
typedef struct can_ctrl {
u32 mcr;/* 0x00 Module Configuration register */
@@ -255,64 +206,6 @@ typedef struct scm3_ctrl {
u32 cfdtr; /* 0x7C Core Fault Data Register */
} scm3_t;
-/* eDMA module registers */
-typedef struct edma_ctrl {
- u32 cr; /* 0x00 Control Register */
- u32 es; /* 0x04 Error Status Register */
- u16 res1[3];/* 0x08 - 0x0D */
- u16 erq;/* 0x0E Enable Request Register */
- u16 res2[3];/* 0x10 - 0x15 */
- u16 eei;/* 0x16 Enable Error Interrupt Request */
- u8 serq;/* 0x18 Set Enable Request */
- u8 cerq;/* 0x19 Clear Enable Request */
- u8 seei;/* 0x1A Set Enable Error Interrupt Request */
- u8 ceei;/* 0x1B Clear Enable Error Interrupt Request */
- u8 cint;/* 0x1C Clear Interrupt Enable Register */
- u8 cerr;/* 0x1D Clear Error Register */
- u8 ssrt;/* 0x1E Set START Bit Register */
- u8 cdne;/* 0x1F Clear DONE Status Bit Register */
- u16 res3[3];/* 0x20 - 0x25 */
- u16 intr; /* 0x26 Interrupt Request Register */
- u16 res4[3];/* 0x28 - 0x2D */
- u16 err;/* 0x2E Error Register */
- u32 res5[52]; /* 0x30 - 0xFF */
- u8 dchpri0; /* 0x100 Channel 0 Priority Register */
- u8 dchpri1;
[U-Boot-Users] [PATCH] xsengine: rename board_post_init to board_late_init
missing migration from "Cleanup of some init functions"
in c837dcb1a316745092567bfe4fb266d0941884ff
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[EMAIL PROTECTED]>
diff --git a/board/xsengine/xsengine.c b/board/xsengine/xsengine.c
index 23d56c4..65923e9 100644
--- a/board/xsengine/xsengine.c
+++ b/board/xsengine/xsengine.c
@@ -47,7 +47,7 @@ int board_init (void)
return 0;
}
-int board_post_init (void)
+int board_late_init (void)
{
setenv ("stdout", "serial");
setenv ("stderr", "serial");
diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h
index 766617e..635ec8b 100644
--- a/include/configs/xsengine.h
+++ b/include/configs/xsengine.h
@@ -33,7 +33,7 @@
#define CONFIG_XSENGINE1
#define CONFIG_MMC 1
#define CONFIG_DOS_PARTITION 1
-#define BOARD_POST_INIT1
+#define BOARD_LATE_INIT1
#undef CONFIG_USE_IRQ /* we don't need
IRQ/FIQ stuff */
#define CFG_HZ 3686400 /* incrementer freq:
3.6864 MHz */
--
1.5.3.7
-
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[U-Boot-Users] [PATCH] ColdFire: Add modules header files
From: TsiChungLiew <[EMAIL PROTECTED]>
Add CF specific modules header files
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
include/asm-m68k/coldfire/crossbar.h | 79 +
include/asm-m68k/coldfire/dspi.h | 156 +
include/asm-m68k/coldfire/edma.h | 177
include/asm-m68k/coldfire/flexbus.h | 98
include/asm-m68k/coldfire/lcd.h | 213 ++
include/asm-m68k/coldfire/ssi.h | 175
6 files changed, 898 insertions(+), 0 deletions(-)
create mode 100644 include/asm-m68k/coldfire/crossbar.h
create mode 100644 include/asm-m68k/coldfire/dspi.h
create mode 100644 include/asm-m68k/coldfire/edma.h
create mode 100644 include/asm-m68k/coldfire/flexbus.h
create mode 100644 include/asm-m68k/coldfire/lcd.h
create mode 100644 include/asm-m68k/coldfire/ssi.h
diff --git a/include/asm-m68k/coldfire/crossbar.h
b/include/asm-m68k/coldfire/crossbar.h
new file mode 100644
index 000..a9c724c
--- /dev/null
+++ b/include/asm-m68k/coldfire/crossbar.h
@@ -0,0 +1,79 @@
+/*
+ * Cross Bar Switch Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew ([EMAIL PROTECTED])
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CROSSBAR_H__
+#define __CROSSBAR_H__
+
+/*
+* Cross-bar switch (XBS)
+*/
+typedef struct xbs {
+ u32 prs1; /* 0x100 Priority Register Slave 1 */
+ u32 res1[3];/* 0x104 - 0F */
+ u32 crs1; /* 0x110 Control Register Slave 1 */
+ u32 res2[187]; /* 0x114 - 0x3FF */
+
+ u32 prs4; /* 0x400 Priority Register Slave 4 */
+ u32 res3[3];/* 0x404 - 0F */
+ u32 crs4; /* 0x410 Control Register Slave 4 */
+ u32 res4[123]; /* 0x414 - 0x5FF */
+
+ u32 prs6; /* 0x600 Priority Register Slave 6 */
+ u32 res5[3];/* 0x604 - 0F */
+ u32 crs6; /* 0x610 Control Register Slave 6 */
+ u32 res6[59]; /* 0x614 - 0x6FF */
+
+ u32 prs7; /* 0x700 Priority Register Slave 7 */
+ u32 res7[3];/* 0x704 - 0F */
+ u32 crs7; /* 0x710 Control Register Slave 7 */
+} xbs_t;
+
+/* Bit definitions and macros for PRS group */
+#define XBS_PRS_M0(x) (((x)&0x0007)) /* Core */
+#define XBS_PRS_M1(x) (((x)&0x0007)<<4) /* eDMA */
+#define XBS_PRS_M2(x) (((x)&0x0007)<<8) /* FEC0 */
+#define XBS_PRS_M3(x) (((x)&0x0007)<<12) /* FEC1 */
+#define XBS_PRS_M5(x) (((x)&0x0007)<<20) /* PCI
controller */
+#define XBS_PRS_M6(x) (((x)&0x0007)<<24) /* USB OTG */
+#define XBS_PRS_M7(x) (((x)&0x0007)<<28) /* Serial Boot
*/
+
+/* Bit definitions and macros for CRS group */
+#define XBS_CRS_PARK(x)(((x)&0x0007)) /*
Master parking ctrl */
+#define XBS_CRS_PCTL(x)(((x)&0x0003)<<4) /*
Parking mode ctrl */
+#define XBS_CRS_ARB(0x0100)/* Arbitration Mode */
+#define XBS_CRS_RO (0x8000)/* Read Only */
+
+#define XBS_CRS_PCTL_PARK_FIELD(0)
+#define XBS_CRS_PCTL_PARK_ON_LAST (1)
+#define XBS_CRS_PCTL_PARK_NONE (2)
+#define XBS_CRS_PCTL_PARK_CORE (0)
+#define XBS_CRS_PCTL_PARK_EDMA (1)
+#define XBS_CRS_PCTL_PARK_FEC0 (2)
+#define XBS_CRS_PCTL_PARK_FEC1 (3)
+#define XBS_CRS_PCTL_PARK_PCI (5)
+#define XBS_CRS_PCTL_PARK_USB (6)
+#define XBS_CRS_PCTL_PARK_SBF (7)
+
+#endif /* __CROSSBAR_H__ */
diff --git a/include/asm-m68k/coldfire/dspi.h b/include/asm-m68k/coldfire/dspi.h
new file mode 100644
index 000..3c579d3
--- /dev/null
+++ b/include/asm-m68k/coldfire/dspi.h
@@ -0,0 +1,156 @@
+/*
+ * MCF5227x Internal Memory Map
+
Re: [U-Boot-Users] [PATCH] MPC8313eRDB/MPC8349ITX: fix board Makefile for silent build (with -s)
On Mon, 14 Jan 2008 09:01:40 -0600 (CST) Kumar Gala <[EMAIL PROTECTED]> wrote: > > Signed-off-by: Kumar Gala <[EMAIL PROTECTED]> > --- > board/freescale/mpc8313erdb/Makefile |2 +- > board/freescale/mpc8349itx/Makefile |2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > applied and extended to 8315rdb. Thanks, Kim - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH u-boot-mpc83xx] Changes in uboot DDR configuration for MPC8313eRDB
On Mon, 14 Jan 2008 09:41:14 +0530 (IST) Poonam_Aggrwal-b10812 <[EMAIL PROTECTED]> wrote: > From: Poonam Aggrwal <[EMAIL PROTECTED]> > > These changes were identified by HighSmith Bill ,Mazzyar and Joseph for > DDR configuration in u-boot code. Some are related to performance, some > affect stability and some correct few basic errors in the current > configuration. applied. Thanks, Kim - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] Enable the isdram command on the MPC8360EMDS board
On Sat, 12 Jan 2008 13:24:14 -0500 Jerry Van Baren <[EMAIL PROTECTED]> wrote: > The isdram command prints out decoded information the "serial presence > detect" (SPD) chip on the SDRAM SIMMs. This can be very helpful when > debugging memory configuration problems. > > Signed-off-by: Gerald Van Baren <[EMAIL PROTECTED]> > --- applied. Thanks, Kim - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 4/4] mpc83xx: Add the support for MPC8315ERDB board
On Fri, 11 Jan 2008 18:48:24 +0800 Dave Liu <[EMAIL PROTECTED]> wrote: > The features list: > - Boot from NOR Flash > - DDR2 266MHz hardcoded configuration > - Local bus NOR Flash R/W operation > - I2C, UART, MII and RTC > - eTSEC0/1 support > - PCI host > > Signed-off-by: Dave Liu <[EMAIL PROTECTED]> > --- applied. Thanks, Kim - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 3/4] mpc83xx: Add config of eTSEC emergency priority in SPCR
On Fri, 11 Jan 2008 18:46:50 +0800 Dave Liu <[EMAIL PROTECTED]> wrote: > The TSEC emergency priority definition of 831x/837x > is different than the definition of 834x in SPCR register. > > Add the other config of TSEC emergency priority into > cpu_init.c > > Signed-off-by: Dave Liu <[EMAIL PROTECTED]> > --- applied. Thanks, Kim - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 1/4] mpc83xx: Remove cache config fromMPC8360ERDK.h
On Fri, 11 Jan 2008 04:23:11 -0700 "Liu Dave" <[EMAIL PROTECTED]> wrote: > Sorry, have one typo in the commit log > > Kim, could you help me change from MPC8360ERDB to MPC8360ERDK manually? > fixed and applied. Thanks, Kim - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] mpc83xx: fix phy-connection-type fixup code
use tree passed to us in local blob, not global fdt.
Also use fdt_path_offset to convert to relative offset, since absolute
reference is needed to check for rgmii-id mode string value.
Signed-off-by: Kim Phillips <[EMAIL PROTECTED]>
---
board/freescale/mpc8360emds/mpc8360emds.c | 24 +++-
1 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c
b/board/freescale/mpc8360emds/mpc8360emds.c
index 2fcef8b..c1691ae 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -318,28 +318,34 @@ void ft_board_setup(void *blob, bd_t *bd)
const char *prop;
const char *path;
- nodeoffset = fdt_path_offset(fdt, "/aliases");
+ nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
#if defined(CONFIG_HAS_ETH0)
/* fixup UCC 1 if using rgmii-id mode */
path = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
if (path) {
- prop = fdt_getprop(blob, nodeoffset,
- "phy-connection-type",
0);
+ path = fdt_path_offset(blob, path);
+ prop = fdt_getprop(blob, path,
+ "phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
- fdt_setprop(blob, nodeoffset,
"phy-connection-type",
- "rgmii-rxid",
sizeof("rgmii-rxid"));
+ fdt_setprop(blob, path,
+ "phy-connection-type",
+ "rgmii-rxid",
+ sizeof("rgmii-rxid"));
}
#endif
#if defined(CONFIG_HAS_ETH1)
/* fixup UCC 2 if using rgmii-id mode */
path = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
if (path) {
- prop = fdt_getprop(blob, nodeoffset,
- "phy-connection-type",
0);
+ path = fdt_path_offset(blob, path);
+ prop = fdt_getprop(blob, path,
+ "phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
- fdt_setprop(blob, nodeoffset,
"phy-connection-type",
- "rgmii-rxid",
sizeof("rgmii-rxid"));
+ fdt_setprop(blob, path,
+ "phy-connection-type",
+ "rgmii-rxid",
+ sizeof("rgmii-rxid"));
}
#endif
}
--
1.5.3
-
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Re: [U-Boot-Users] [PATCH 1/1] xsengine: rename board_post_init to board_late_init
On Mon, Jan 14, 2008 at 10:38:55PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote: > diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h > index 766617e..d167e01 100644 > --- a/include/configs/xsengine.h > +++ b/include/configs/xsengine.h > @@ -33,7 +33,7 @@ > #define CONFIG_XSENGINE 1 > #define CONFIG_MMC 1 > #define CONFIG_DOS_PARTITION 1 > -#define BOARD_POST_INIT 1 > +#define OARD_LATE_INIT 1 A typo here ^ ? > #undef CONFIG_USE_IRQ /* we don't > need IRQ/FIQ stuff */ > #define CFG_HZ 3686400 /* incrementer > freq: 3.6864 MHz */ Best regards, ladis - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 1/1] xsengine: rename board_post_init to board_late_init
missing migration from "Cleanup of some init functions"
in c837dcb1a316745092567bfe4fb266d0941884ff
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[EMAIL PROTECTED]>
diff --git a/board/xsengine/xsengine.c b/board/xsengine/xsengine.c
index 23d56c4..65923e9 100644
--- a/board/xsengine/xsengine.c
+++ b/board/xsengine/xsengine.c
@@ -47,7 +47,7 @@ int board_init (void)
return 0;
}
-int board_post_init (void)
+int board_late_init (void)
{
setenv ("stdout", "serial");
setenv ("stderr", "serial");
diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h
index 766617e..d167e01 100644
--- a/include/configs/xsengine.h
+++ b/include/configs/xsengine.h
@@ -33,7 +33,7 @@
#define CONFIG_XSENGINE1
#define CONFIG_MMC 1
#define CONFIG_DOS_PARTITION 1
-#define BOARD_POST_INIT1
+#define OARD_LATE_INIT 1
#undef CONFIG_USE_IRQ /* we don't need
IRQ/FIQ stuff */
#define CFG_HZ 3686400 /* incrementer freq:
3.6864 MHz */
--
1.5.3.7
-
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[U-Boot-Users] [PATCH 0/1] ARM: remove useless function board_post_init
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[EMAIL PROTECTED]>
diff --git a/board/ixdp425/ixdp425.c b/board/ixdp425/ixdp425.c
index 2a33d6d..e0d7637 100644
--- a/board/ixdp425/ixdp425.c
+++ b/board/ixdp425/ixdp425.c
@@ -38,11 +38,6 @@ DECLARE_GLOBAL_DATA_PTR;
/*
* Miscelaneous platform dependent initialisations
*/
-int board_post_init (void)
-{
- return (0);
-}
-
int board_init (void)
{
/* arch number of IXDP */
diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c
index a1a310a..3445a3a 100644
--- a/board/prodrive/pdnb3/pdnb3.c
+++ b/board/prodrive/pdnb3/pdnb3.c
@@ -48,11 +48,6 @@ static unsigned long old_val = 0;
/*
* Miscelaneous platform dependent initialisations
*/
-int board_post_init(void)
-{
- return (0);
-}
-
int board_init(void)
{
/* arch number of PDNB3 */
diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c
index 528d323..56b1cd4 100644
--- a/board/xm250/xm250.c
+++ b/board/xm250/xm250.c
@@ -52,14 +52,6 @@ sleep (int i)
int
/**/
-board_post_init (void)
-/**/
-{
- return (0);
-}
-
-int
-/**/
board_init (void)
/**/
{
--
1.5.3.7
-
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Re: [U-Boot-Users] [PATCH] Correct NAND erase percentage output
On Mon, 14 Jan 2008, Dirk Behme wrote: Aha! Here it is... :) > > For NAND erase sizes smaller than one NAND erase block, erase percentage > output becomes grater than 100% e.g. > > -- cut -- > > nand info > Device 0: NAND 64MiB 1,8V 8-bit, sector size 16 KiB > > nand erase 0x10 0x2000 > NAND erase: device 0 offset 0x10, size 0x2000 > Erasing at 0x10 -- 200% complete. > OK > > > -- cut -- > > Correct this and give user a warning that more is erased than specified: > > -- cut -- > > nand erase 0x10 0x2000 > NAND erase: device 0 offset 0x10, size 0x2000 > Warning: Erase size 0x2000 smaller than one erase block 0x4000 > Erasing 0x4000 instead > Erasing at 0x10 -- 100% complete. > OK > > > -- cut -- > > This patch is against u-boot-nand-flash.git. > > Signed-off-by: Dirk Behme <[EMAIL PROTECTED]> > > --- ** * [EMAIL PROTECTED]KOI8 Net < > The impossible we do immediately. * * Las Vegas NV, USA < > Miracles require 24-hour notice. * ** - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 6/8] ColdFire: Add MCF547x_8x FEC driver
Liew Tsi Chung wrote:
> Ben,
>
> Yes. I agree the function name is not very descriptive. Will
> mcdmafec_initialize() work (mcdma - multi-channel dma)? I can't name it
> specific to coldfire, because this driver will also work on MPC8220.
>
> Regards,
> TsiChung
>
>
>
Sure, that's better.
>> diff --git a/net/eth.c b/net/eth.c
>> index 5d9e9c1..fd3dc85 100644
>> --- a/net/eth.c
>> +++ b/net/eth.c
>> @@ -61,6 +61,7 @@ extern int uec_initialize(int); extern int
>> bfin_EMAC_initialize(bd_t *); extern int
>> atstk1000_eth_initialize(bd_t *); extern int
>> mcffec_initialize(bd_t*);
>> +extern int fecdma_initialize(bd_t*);
>>
>>
>
> Can you pick a more descriptive name than fecdma, please. At the very
> least it should be mcffecdma so we know it's Coldfire.
>
>
>>
>> #ifdef CONFIG_API
>> extern void (*push_packet)(volatile void *, int); @@ -272,6 +273,9 @@
>>
>
>
>> int eth_initialize(bd_t *bis) #if defined(CONFIG_MCFFEC)
>> mcffec_initialize(bis);
>> #endif
>> +#if defined(CONFIG_FSLDMAFEC)
>> +fecdma_initialize(bis);
>> +#endif
>>
>> if (!eth_devices) {
>> puts ("No ethernet found.\n");
>>
>>
>
>
>
-
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[U-Boot-Users] [PATCH] Fix arm926ejs compile when SKIP_LOWLEVEL_INIT is on
Fix arm926ejs compile when SKIP_LOWLEVEL_INIT is on. cpu/arm926ejs/start.o: In function `cpu_init_crit': .../cpu/arm926ejs/start.S:227: undefined reference to `lowlevel_init' Signed-off-by: Stelian Pop <[EMAIL PROTECTED]> --- cpu/arm926ejs/start.S |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S index 725c663..aa09fbf 100644 --- a/cpu/arm926ejs/start.S +++ b/cpu/arm926ejs/start.S @@ -198,8 +198,7 @@ _start_armboot: * * */ - - +#ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: /* * flush v4 I/D caches @@ -225,6 +224,8 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + /* * * -- 1.5.3.3 -- Stelian Pop <[EMAIL PROTECTED]> - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] Enable the isdram command on the MPC8360EMDS board
Jon Loeliger wrote: > On Sat, 2008-01-12 at 12:24, Jerry Van Baren wrote: > >> Hi Kim, >> >> The isdram command is controlled separately from the rest of the i2c >> commands (CONFIG_CMD_I2C + CONFIG_CMD_SDRAM). I did this originally >> because the isdram command was arguably a memory consuming luxury. >> Luxuries tend to become necessities over time... >> >> Larry Johnson submitted a patch yesterday to extend the decoding and >> printout to include DDR2 fields, making this even more useful (and jdl >> is claiming a share of the credit ;-). >> >> gvb > > I'm not claiming any credit for it, but if I do the > following command: > > $ git show d9b94f28a442b001 -- cpu/mpc85xx/spd_sdram.c > > Someone who impersonated me quite well appears to have > checked in whole bunch of DDR2 decode stuff way back in > July of 2005. [snip] > Weird, huh? > > jdl Hi Jon, I'm kinda loosing the thread here. I think we are talking about two totally different decodes of the same data. What I'm crediting Larry for isn't the decoding you are pointing to. You did machine decoding to make the DDR2 _work,_ which is invaluable. Larry did the decoding to improve the human-readable output of the "isdram" command. This isn't invaluable in quite the same way, but still is really nice to be able to dump the SPD and decode it into ASCII for the poor developer. I don't know if your board(s) have CONFIG_CMD_SDRAM defined (it is off by default) - doesn't look like it. If not, turn it on and try it out. Best regards, gvb - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] Fix incorrect address test in AT91F_DataflashSelect
Fix incorrect address test in AT91F_DataflashSelect().
Signed-off-by: Stelian Pop <[EMAIL PROTECTED]>
---
drivers/mtd/dataflash.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/dataflash.c b/drivers/mtd/dataflash.c
index 4084ff7..2421407 100644
--- a/drivers/mtd/dataflash.c
+++ b/drivers/mtd/dataflash.c
@@ -309,7 +309,7 @@ AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash
pFlash,
for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++)
if ( dataflash_info[i].id
- && int) addr) & 0xFF00) ==
+ && int) *addr) & 0xFF00) ==
dataflash_info[i].logical_address)) {
addr_valid = 1;
break;
--
1.5.3.3
--
Stelian Pop <[EMAIL PROTECTED]>
-
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[U-Boot-Users] [PATCH] Improve DataFlash CS definition.
Use a structure instead of the error prone unnamed array to
define the possible dataflash banks.
Signed-off-by: Stelian Pop <[EMAIL PROTECTED]>
---
drivers/mtd/dataflash.c | 31 ++-
1 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/dataflash.c b/drivers/mtd/dataflash.c
index 91903c8..4084ff7 100644
--- a/drivers/mtd/dataflash.c
+++ b/drivers/mtd/dataflash.c
@@ -26,17 +26,22 @@
AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
static AT91S_DataFlash DataFlashInst;
+struct dataflash_addr {
+ unsigned long addr;
+ int cs;
+};
+
#ifdef CONFIG_AT91SAM9260EK
-int cs[][CFG_MAX_DATAFLASH_BANKS] = {
+struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
{CFG_DATAFLASH_LOGIC_ADDR_CS1, 1}
};
#elif defined(CONFIG_AT91SAM9263EK)
-int cs[][CFG_MAX_DATAFLASH_BANKS] = {
- {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0} /* Logical adress, CS */
+struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
+ {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
};
#else
-int cs[][CFG_MAX_DATAFLASH_BANKS] = {
+struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
{CFG_DATAFLASH_LOGIC_ADDR_CS3, 3}
};
@@ -114,7 +119,7 @@ int AT91F_DataflashInit (void)
dataflash_info[i].Desc.state = IDLE;
dataflash_info[i].id = 0;
dataflash_info[i].Device.pages_number = 0;
- dfcode = AT91F_DataflashProbe (cs[i][1],
+ dfcode = AT91F_DataflashProbe (cs[i].cs,
&dataflash_info[i].Desc);
switch (dfcode) {
@@ -123,9 +128,9 @@ int AT91F_DataflashInit (void)
dataflash_info[i].Device.pages_size = 528;
dataflash_info[i].Device.page_offset = 10;
dataflash_info[i].Device.byte_mask = 0x300;
- dataflash_info[i].Device.cs = cs[i][1];
+ dataflash_info[i].Device.cs = cs[i].cs;
dataflash_info[i].Desc.DataFlash_state = IDLE;
- dataflash_info[i].logical_address = cs[i][0];
+ dataflash_info[i].logical_address = cs[i].addr;
dataflash_info[i].id = dfcode;
found[i] += dfcode;;
break;
@@ -135,9 +140,9 @@ int AT91F_DataflashInit (void)
dataflash_info[i].Device.pages_size = 528;
dataflash_info[i].Device.page_offset = 10;
dataflash_info[i].Device.byte_mask = 0x300;
- dataflash_info[i].Device.cs = cs[i][1];
+ dataflash_info[i].Device.cs = cs[i].cs;
dataflash_info[i].Desc.DataFlash_state = IDLE;
- dataflash_info[i].logical_address = cs[i][0];
+ dataflash_info[i].logical_address = cs[i].addr;
dataflash_info[i].id = dfcode;
found[i] += dfcode;;
break;
@@ -147,9 +152,9 @@ int AT91F_DataflashInit (void)
dataflash_info[i].Device.pages_size = 1056;
dataflash_info[i].Device.page_offset = 11;
dataflash_info[i].Device.byte_mask = 0x700;
- dataflash_info[i].Device.cs = cs[i][1];
+ dataflash_info[i].Device.cs = cs[i].cs;
dataflash_info[i].Desc.DataFlash_state = IDLE;
- dataflash_info[i].logical_address = cs[i][0];
+ dataflash_info[i].logical_address = cs[i].addr;
dataflash_info[i].id = dfcode;
found[i] += dfcode;;
break;
@@ -159,9 +164,9 @@ int AT91F_DataflashInit (void)
dataflash_info[i].Device.pages_size = 1056;
dataflash_info[i].Device.page_offset = 11;
dataflash_info[i].Device.byte_mask = 0x700;
- dataflash_info[i].Device.cs = cs[i][1];
+ dataflash_info[i].Device.cs = cs[i].cs;
dataflash_info[i].Desc.DataFlash_state = IDLE;
- dataflash_info[i].logical_address = cs[i][0];
+ dataflash_info[i].logical_address = cs[i].addr;
dataflash_info[i].id = dfcode;
found[i] += dfcode;;
break;
--
1.5.3.3
--
Stelian Pop <[EMAIL PROTECTED]>
-
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[U-Boot-Users] [PATCH] Correct NAND erase percentage output
For NAND erase sizes smaller than one NAND erase block, erase
percentage output becomes grater than 100% e.g.
-- cut --
> nand info
Device 0: NAND 64MiB 1,8V 8-bit, sector size 16 KiB
> nand erase 0x10 0x2000
NAND erase: device 0 offset 0x10, size 0x2000
Erasing at 0x10 -- 200% complete.
OK
>
-- cut --
Correct this and give user a warning that more is erased than specified:
-- cut --
> nand erase 0x10 0x2000
NAND erase: device 0 offset 0x10, size 0x2000
Warning: Erase size 0x2000 smaller than one erase block 0x4000
Erasing 0x4000 instead
Erasing at 0x10 -- 100% complete.
OK
>
-- cut --
This patch is against u-boot-nand-flash.git.
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
--- drivers/mtd/nand/nand_util.c_orig 2008-01-14 21:13:10.0 +0100
+++ drivers/mtd/nand/nand_util.c2008-01-14 21:46:53.0 +0100
@@ -153,6 +153,13 @@ int nand_erase_opts(nand_info_t *meminfo
priv_nand->bbt = NULL;
}
+ if(erase_length < meminfo->erasesize) {
+ printf("Warning: Erase size 0x%08x smaller than one " \
+ "erase block 0x%08x\n",erase_length, meminfo->erasesize);
+ printf(" Erasing 0x%08x instead\n", meminfo->erasesize);
+ erase_length = meminfo->erasesize;
+ }
+
for (;
erase.addr < opts->offset + erase_length;
erase.addr += meminfo->erasesize) {
-
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Re: [U-Boot-Users] [PATCH]ppc_4xx:netstal HCU5 board: added various fixes and POST
In message <[EMAIL PROTECTED]> you wrote:
> Moved some code to nestal/common/nm_bsp.c.
> Added support for the vxWorks EDR.
> Enable trace for Lauterbach, if present.
> Added support for POST.
...
> + if (mfspr(dbcr0) & 0x8000) { /* External debugger alive */
> + /* enable trace facilty for Lauterback
/*
* enable trace facilty for Lauterbach
...
> - /*---+
> - | Set priority for all PLB3 devices to 0.
> - | Set PLB3 arbiter to fair mode.
> - +---*/
> + /*---
> + * Set priority for all PLB3 devices to 0.
> + * Set PLB3 arbiter to fair mode.
> + *---*/
...
> - /*---+
> - | Set priority for all PLB4 devices to 0.
> - +---*/
> + /*---
> + * Set priority for all PLB4 devices to 0.
> + *---*/
If you change multiline comments, then please do it right. The
preferred style for long (multi-line) comments is:
/*
* This is the preferred style for multi-line
* comments in the Linux kernel source code.
* Please use it consistently.
*
* Description: A column of asterisks on the left side,
* with beginning and ending almost-blank lines.
*/
> + /* TLB#12: */
> + tlbentry( CFG_CS_2 + 0x100, SZ_16M, CFG_CS_2 + 0x100, 1,
> AC_R|AC_W|AC_X|SA_G|SA_I )
Here and in some other places: please mind the maximum line length.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED]
"If the code and the comments disagree, then both are probably
wrong."- Norm Schryer
-
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Re: [U-Boot-Users] [PATCH 6/8] ColdFire: Add MCF547x_8x FEC driver
Ben,
Yes. I agree the function name is not very descriptive. Will
mcdmafec_initialize() work (mcdma - multi-channel dma)? I can't name it
specific to coldfire, because this driver will also work on MPC8220.
Regards,
TsiChung
> diff --git a/net/eth.c b/net/eth.c
> index 5d9e9c1..fd3dc85 100644
> --- a/net/eth.c
> +++ b/net/eth.c
> @@ -61,6 +61,7 @@ extern int uec_initialize(int); extern int
> bfin_EMAC_initialize(bd_t *); extern int
> atstk1000_eth_initialize(bd_t *); extern int
> mcffec_initialize(bd_t*);
> +extern int fecdma_initialize(bd_t*);
>
Can you pick a more descriptive name than fecdma, please. At the very
least it should be mcffecdma so we know it's Coldfire.
>
> #ifdef CONFIG_API
> extern void (*push_packet)(volatile void *, int); @@ -272,6 +273,9 @@
> int eth_initialize(bd_t *bis) #if defined(CONFIG_MCFFEC)
> mcffec_initialize(bis);
> #endif
> +#if defined(CONFIG_FSLDMAFEC)
> + fecdma_initialize(bis);
> +#endif
>
> if (!eth_devices) {
> puts ("No ethernet found.\n");
>
-
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Re: [U-Boot-Users] [PATCH]ppc_4xx:netstal/common define routines used by all boards
In message <[EMAIL PROTECTED]> you wrote:
> Added some routines used by all Netstal boards nm_show_print and
> common_misc_init_r and the very specific code to handle our SW installation
> procedure (set_params_for_sw_install).
>
> Signed-off-by: Niklaus Giger <[EMAIL PROTECTED]>
> ---
> board/netstal/common/nm_bsp.c | 131
> -
> 1 files changed, 116 insertions(+), 15 deletions(-)
>
> diff --git a/board/netstal/common/nm_bsp.c b/board/netstal/common/nm_bsp.c
> index a9de45e..2c1d483 100644
> --- a/board/netstal/common/nm_bsp.c
> +++ b/board/netstal/common/nm_bsp.c
> @@ -20,22 +20,123 @@
>
> #include
> #include
> +#include
>
> -#ifdef CONFIG_CMD_BSP
> -/*
> - * Command nm_bsp: Netstal Maschinen BSP specific command
> - */
> -int nm_bsp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define DEFAULT_ETH_ADDR "ethaddr"
> +
> +extern void hcu_led_set(u32 value);
> +extern u32 get_serial_number(void);
> +extern u32 hcu_get_slot(void);
> +
> +enum {
> + /* HW_GENERATION_HCU1 is no longer supported */
> + HW_GENERATION_HCU2 = 0x10,
> + HW_GENERATION_HCU3 = 0x10,
> + HW_GENERATION_HCU4 = 0x20,
> + HW_GENERATION_HCU5 = 0x30,
> + HW_GENERATION_MCU = 0x08,
> + HW_GENERATION_MCU20 = 0x0a,
> + HW_GENERATION_MCU25 = 0x09,
> +};
> +
> +
> +void nm_show_print(int generation, int index, int hw_capabilities)
> +{
> + int j;
> + /* reset ANSI terminal color mode */
> + printf ("\x1B""[0m""Netstal Maschinen AG: ");
> + if (generation == HW_GENERATION_HCU3)
> + printf("HCU3: index %d", index);
> + else if (generation == HW_GENERATION_HCU4)
> + printf("HCU4: index %d", index);
> + else if (generation == HW_GENERATION_HCU5)
> + printf("HCU5: index %d", index);
> + else if (generation == HW_GENERATION_MCU25)
> + printf("MCU25: index %d", index);
else
???
You probably want to do this in a loop over an array of structs
matching "generation" IDs with names - will become more readable and
less error prone. And eventually smaller code, too.
> + }
> +
> + /* IP-Adress update */
> + {
> + IPaddr_t ipaddr;
> + char *ipstring;
Please don't do this. Declare the vaiable at entry into this funtion.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED]
A direct quote from the Boss: "We passed over a lot of good people to
get the ones we hired."
-
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[U-Boot-Users] [PATCH] nand: fsl_upm: convert to updated MTD NAND infrastructure
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
drivers/mtd/nand/fsl_upm.c | 68 +++
include/linux/mtd/fsl_upm.h |3 ++
2 files changed, 20 insertions(+), 51 deletions(-)
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
index 5cc410a..4775cdc 100644
--- a/drivers/mtd/nand/fsl_upm.c
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -61,51 +61,28 @@ static void fsl_upm_setup(struct fsl_upm *upm)
eieio();
}
-static void fun_cmdfunc(struct mtd_info *mtd, unsigned command, int column,
- int page_addr)
+static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd->priv;
struct fsl_upm_nand *fun = chip->priv;
- fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
-
- if (command == NAND_CMD_SEQIN) {
- int readcmd;
-
- if (column >= mtd->oobblock) {
- /* OOB area */
- column -= mtd->oobblock;
- readcmd = NAND_CMD_READOOB;
- } else if (column < 256) {
- /* First 256 bytes --> READ0 */
- readcmd = NAND_CMD_READ0;
- } else {
- column -= 256;
- readcmd = NAND_CMD_READ1;
- }
- fsl_upm_run_pattern(&fun->upm, fun->width, readcmd);
- }
-
- fsl_upm_run_pattern(&fun->upm, fun->width, command);
+ if (!(ctrl & fun->last_ctrl)) {
+ fsl_upm_end_pattern(&fun->upm);
- fsl_upm_end_pattern(&fun->upm);
+ if (cmd == NAND_CMD_NONE)
+ return;
- fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
-
- if (column != -1)
- fsl_upm_run_pattern(&fun->upm, fun->width, column);
+ fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
+ }
- if (page_addr != -1) {
- fsl_upm_run_pattern(&fun->upm, fun->width, page_addr);
- fsl_upm_run_pattern(&fun->upm, fun->width,
- (page_addr >> 8) & 0xFF);
- if (chip->chipsize > (32 << 20)) {
- fsl_upm_run_pattern(&fun->upm, fun->width,
- (page_addr >> 16) & 0x0f);
- }
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if (ctrl & NAND_ALE)
+ fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
+ else if (ctrl & NAND_CLE)
+ fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
}
- fsl_upm_end_pattern(&fun->upm);
+ fsl_upm_run_pattern(&fun->upm, fun->width, cmd);
if (fun->wait_pattern) {
/*
@@ -119,13 +96,6 @@ static void fun_cmdfunc(struct mtd_info *mtd, unsigned
command, int column,
}
}
-static void nand_write_byte(struct mtd_info *mtd, u_char byte)
-{
- struct nand_chip *chip = mtd->priv;
-
- out_8(chip->IO_ADDR_W, byte);
-}
-
static u8 nand_read_byte(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
@@ -164,10 +134,6 @@ static int nand_verify_buf(struct mtd_info *mtd, const
u_char *buf, int len)
return 0;
}
-static void nand_hwcontrol(struct mtd_info *mtd, int cmd)
-{
-}
-
static int nand_dev_ready(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
@@ -184,14 +150,14 @@ int fsl_upm_nand_init(struct nand_chip *chip, struct
fsl_upm_nand *fun)
fsl_upm_setup(&fun->upm);
+ fun->last_ctrl = NAND_CLE;
+
chip->priv = fun;
chip->chip_delay = fun->chip_delay;
- chip->eccmode = NAND_ECC_SOFT;
- chip->cmdfunc = fun_cmdfunc;
- chip->hwcontrol = nand_hwcontrol;
+ chip->ecc.mode = NAND_ECC_SOFT;
+ chip->cmd_ctrl = fun_cmd_ctrl;
chip->read_byte = nand_read_byte;
chip->read_buf = nand_read_buf;
- chip->write_byte = nand_write_byte;
chip->write_buf = nand_write_buf;
chip->verify_buf = nand_verify_buf;
chip->dev_ready = nand_dev_ready;
diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h
index 634ff02..5f0016d 100644
--- a/include/linux/mtd/fsl_upm.h
+++ b/include/linux/mtd/fsl_upm.h
@@ -32,6 +32,9 @@ struct fsl_upm_nand {
int wait_pattern;
int (*dev_ready)(void);
int chip_delay;
+
+ /* no need to fill */
+ int last_ctrl;
};
extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun);
--
1.5.2.2
-
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[U-Boot-Users] [PATCH v2 2/2] mpc83xx: MPC8360E-RDK: add support for NAND
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
board/freescale/mpc8360erdk/Makefile |2 +-
board/freescale/mpc8360erdk/nand.c | 75 ++
include/configs/MPC8360ERDK.h| 24 +++
3 files changed, 100 insertions(+), 1 deletions(-)
create mode 100644 board/freescale/mpc8360erdk/nand.c
diff --git a/board/freescale/mpc8360erdk/Makefile
b/board/freescale/mpc8360erdk/Makefile
index acc9544..97ae11d 100644
--- a/board/freescale/mpc8360erdk/Makefile
+++ b/board/freescale/mpc8360erdk/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o
+COBJS := $(BOARD).o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/mpc8360erdk/nand.c
b/board/freescale/mpc8360erdk/nand.c
new file mode 100644
index 000..7c06a3f
--- /dev/null
+++ b/board/freescale/mpc8360erdk/nand.c
@@ -0,0 +1,75 @@
+/*
+ * MPC8360E-RDK support for the NAND on FSL UPM
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *Anton Vorontsov <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include
+
+#if defined(CONFIG_CMD_NAND)
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct immap *im = (struct immap *)CFG_IMMR;
+
+static const u32 upm_array[] = {
+ 0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */
+ 0xfff33c31, 0xfc30, 0xfc30, 0xfc30, /* Words 4 to 7 */
+ 0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */
+ 0x3c31, 0xfc30, 0xfc30, 0xfc30, /* Words 12 to 15 */
+ 0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */
+ 0xfff3fc31, 0xfc30, 0xfc30, 0xfc30, /* Words 20 to 23 */
+ 0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */
+ 0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */
+ 0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */
+ 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */
+ 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */
+ 0xfffdfc30, 0xfc30, 0xfc30, 0xfc31, /* Words 44 to 47 */
+ 0xfc30, 0xfc00, 0xfc00, 0xfc00, /* Words 48 to 51 */
+ 0xfc00, 0xfc00, 0xfc00, 0xfc00, /* Words 52 to 55 */
+ 0xfc00, 0xfc00, 0xfc00, 0xfc01, /* Words 56 to 59 */
+ 0xfc00, 0xfc00, 0xfc00, 0xfc01, /* Words 60 to 63 */
+};
+
+static int dev_ready(void)
+{
+ if (in_be32(&im->qepio.ioport[4].pdat) & 0x2000) {
+ debug("nand ready\n");
+ return 1;
+ }
+
+ debug("nand busy\n");
+ return 0;
+}
+
+static struct fsl_upm_nand fun = {
+ .upm = {
+ .array = upm_array,
+ .io_addr = (void *)CFG_NAND_BASE,
+ },
+ .width = 1,
+ .upm_cmd_offset = 8,
+ .upm_addr_offset = 16,
+ .dev_ready = dev_ready,
+ .wait_pattern = 1,
+ .chip_delay = 50,
+};
+
+int board_nand_init(struct nand_chip *nand)
+{
+ fun.upm.mxmr = &im->lbus.mamr;
+ fun.upm.mdr = &im->lbus.mdr;
+ fun.upm.mar = &im->lbus.mar;
+ return fsl_upm_nand_init(nand, &fun);
+}
+#endif /* CONFIG_CMD_NAND */
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index e6d0c5e..b258d91 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -186,6 +186,11 @@
* NAND flash on the local bus
*/
#define CFG_NAND_BASE 0x6000
+#define CONFIG_CMD_NAND1
+#define CONFIG_NAND_FSL_UPM1
+#define CFG_MAX_NAND_DEVICE1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
#define CFG_LBLAWAR1_PRELIM0x801b /* Access window size 4K */
@@ -514,23 +519,42 @@
"fdtfile=dtb\0"\
"fsfile=fs\0"\
"ubootfile=u-boot.bin\0"\
+ "mtdparts=mtdparts=6000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
"setbootargs=setenv bootargs console=$consoledev,$baudrate "\
"$mtdparts panic=1\0"\
"adddhcpargs=setenv bootargs $bootargs ip=on\0"\
"addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
"$gatewayip:$netmask:$hostname:$netdev:off "\
"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
+ "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
+ "rootfstype=jffs2 rw\0"\
"tftp_get_uboot=tftp 10 $ubootfile\0"\
"tftp_get_kernel=tftp $loadaddr $bootfile\0"\
"tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
"tftp_get_fs=tft
[U-Boot-Users] [PATCH v2 1/2] nand: FSL UPM NAND driver
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
drivers/mtd/nand/Makefile |2 +
drivers/mtd/nand/fsl_upm.c | 201 +++
include/linux/mtd/fsl_upm.h | 39
3 files changed, 242 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/fsl_upm.c
create mode 100644 include/linux/mtd/fsl_upm.h
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 42864f9..244fa09 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -32,6 +32,8 @@ COBJS-y += nand_ecc.o
COBJS-y += nand_bbt.o
COBJS-y += nand_util.o
+COBJS-y += fsl_upm.o
+
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
new file mode 100644
index 000..5cc410a
--- /dev/null
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -0,0 +1,201 @@
+/*
+ * FSL UPM NAND driver
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *Anton Vorontsov <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include
+
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_FSL_UPM)
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define FSL_UPM_MxMR_OP_NO (0 << 28) /* normal operation */
+#define FSL_UPM_MxMR_OP_WA (1 << 28) /* write array */
+#define FSL_UPM_MxMR_OP_RA (2 << 28) /* read array */
+#define FSL_UPM_MxMR_OP_RP (3 << 28) /* run pattern */
+
+static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
+{
+ out_be32(upm->mxmr, FSL_UPM_MxMR_OP_RP | pat_offset);
+}
+
+static void fsl_upm_end_pattern(struct fsl_upm *upm)
+{
+ out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
+ while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
+ eieio();
+}
+
+static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd)
+{
+ out_be32(upm->mar, cmd << (32 - width * 8));
+ out_8(upm->io_addr, 0x0);
+}
+
+static void fsl_upm_setup(struct fsl_upm *upm)
+{
+ int i;
+
+ /* write upm array */
+ out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA);
+
+ for (i = 0; i < 64; i++) {
+ out_be32(upm->mdr, upm->array[i]);
+ out_8(upm->io_addr, 0x0);
+ }
+
+ /* normal operation */
+ out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
+ while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
+ eieio();
+}
+
+static void fun_cmdfunc(struct mtd_info *mtd, unsigned command, int column,
+ int page_addr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_upm_nand *fun = chip->priv;
+
+ fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
+
+ if (command == NAND_CMD_SEQIN) {
+ int readcmd;
+
+ if (column >= mtd->oobblock) {
+ /* OOB area */
+ column -= mtd->oobblock;
+ readcmd = NAND_CMD_READOOB;
+ } else if (column < 256) {
+ /* First 256 bytes --> READ0 */
+ readcmd = NAND_CMD_READ0;
+ } else {
+ column -= 256;
+ readcmd = NAND_CMD_READ1;
+ }
+ fsl_upm_run_pattern(&fun->upm, fun->width, readcmd);
+ }
+
+ fsl_upm_run_pattern(&fun->upm, fun->width, command);
+
+ fsl_upm_end_pattern(&fun->upm);
+
+ fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
+
+ if (column != -1)
+ fsl_upm_run_pattern(&fun->upm, fun->width, column);
+
+ if (page_addr != -1) {
+ fsl_upm_run_pattern(&fun->upm, fun->width, page_addr);
+ fsl_upm_run_pattern(&fun->upm, fun->width,
+ (page_addr >> 8) & 0xFF);
+ if (chip->chipsize > (32 << 20)) {
+ fsl_upm_run_pattern(&fun->upm, fun->width,
+ (page_addr >> 16) & 0x0f);
+ }
+ }
+
+ fsl_upm_end_pattern(&fun->upm);
+
+ if (fun->wait_pattern) {
+ /*
+* Some boards/chips needs this. At least on MPC8360E-RDK we
+* need it. Probably weird chip, because I don't see any need
+* for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
+* 0-2 unexpected busy states per block read.
+*/
+ while (!fun->dev_ready())
+ debug("unexpected busy state\n");
+ }
+}
+
+static void nand_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ out_8(chip->IO_ADDR_W, byte);
+}
+
+static u8 nand_read_byte(struct mtd_info *mtd)
+{
+ struc
Re: [U-Boot-Users] [PATCH 3/5] nand: FSL UPM NAND driver
On Thu, Jan 10, 2008 at 06:31:06PM +0100, Stefan Roese wrote: > On Wednesday 09 January 2008, Anton Vorontsov wrote: > > Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]> > > This seems to be based on the current NAND infrastructure. You might have > noticed that I'm trying right now to merge the patches from William Yuul with > the Linux 2.6.22 based NAND subsystem. This is great news. Though, using u-boot-nand-flash tree I see that write.jffs2 isn't actually working (bad blocks skipping unimplemented), and read.jffs2 is unimplemented in whole... Without .jffs2 variants nand support is almost useless. :-/ Unfortunately I don't have much time to help you with these updating efforts, implementing .jffs2... so I'd be glad if you'll ack second version of the patch[1] so we'll able to use it today with old nand layer. And I'll provide another patch[2] for your tree, that will update fsl_upm to use new infrastructure (tested to work on good blocks). Will send [1] and [2] real soon now. Thanks. - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] Enable the isdram command on the MPC8360EMDS board
On Sat, 2008-01-12 at 12:24, Jerry Van Baren wrote:
> Hi Kim,
>
> The isdram command is controlled separately from the rest of the i2c
> commands (CONFIG_CMD_I2C + CONFIG_CMD_SDRAM). I did this originally
> because the isdram command was arguably a memory consuming luxury.
> Luxuries tend to become necessities over time...
>
> Larry Johnson submitted a patch yesterday to extend the decoding and
> printout to include DDR2 fields, making this even more useful (and jdl
> is claiming a share of the credit ;-).
>
> gvb
I'm not claiming any credit for it, but if I do the
following command:
$ git show d9b94f28a442b001 -- cpu/mpc85xx/spd_sdram.c
Someone who impersonated me quite well appears to have
checked in whole bunch of DDR2 decode stuff way back in
July of 2005.
For example:
+/*
+ * Convert a two-nibble BCD value into a cycle time.
+ * While the spec calls for nano-seconds, picos are returned.
+ *
+ * This implements the tables for bytes 9, 23 and 25 for both
+ * DDR I and II. No allowance for distinguishing the invalid
+ * fields absent for DDR I yet present in DDR II is made.
+ * (That is, cycle times of .25, .33, .66 and .75 ns are
+ * allowed for both DDR II and I.)
+ */
+
unsigned int
-banksize(unsigned char row_dens)
+convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
{
- return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
+ /*
+* Table look up the lower nibble, allow DDR I & II.
+*/
+ unsigned int tenths_ps[16] = {
+ 0,
+ 100,
+ 200,
+ 300,
+ 400,
+ 500,
+ 600,
+ 700,
+ 800,
+ 900,
+ 250,
+ 330,/* FIXME: Is 333 better/valid? */
+ 660,/* FIXME: Is 667 better/valid? */
+ 750,
+ 0, /* undefined */
+ 0 /* undefined */
+ };
+
Weird, huh?
jdl
-
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Re: [U-Boot-Users] [PATCH 2/4] TSEC: Add the support for RealTek RTL8211B PHY
Andy Fleming wrote: > On Jan 11, 2008 4:45 AM, Dave Liu <[EMAIL PROTECTED]> wrote: > >> Add the support of RealTek RTL8211B PHY, the RTL8211B >> PHY only supports RGMII and MII mode. >> >> Signed-off-by: Dave Liu <[EMAIL PROTECTED]> >> > > Ok, Dave confirmed that this code is needed for this PHY. > > Acked-by: Andy Fleming <[EMAIL PROTECTED]> > > OK, I'll pull it in. Thanks guys. regards, Ben - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] ppc4xx: Refactor ECC POST for AMCC Denali core
Jerry Van Baren wrote:
> Stefan Roese wrote:
>> Hi Jerry,
>>
>> On Monday 14 January 2008, Jerry Van Baren wrote:
>
> [snip]
Hi Stefan and Jerry,
I just sent a response to Jerry's original e-mail, before seeing these
comments.
>>> As you should have picked up by now, a sync (forcing all I/O to
>>> complete) followed by eieio is silly - the eieio is superfluous. Seeing
>>> syncs/isyncs/eieios sprinkled in code is an indication that the author
>>> didn't understand what was going on and, as a result, kept hitting the
>>> problem with a bigger and bigger hammer until it appeared to have gone
>>> away.
>>
>> Now I'm glad that I'm not the author of this code. ;) But I admit that
>> I did use this "hammer" in the past.
>
> As have we all. The only difference is that most of us don't get
> caught. ;-) Open source and git: it both exposes and attributes all
> stupidity. :-D
So, unlike proprietary code, it gets fixed. :-)
> [snip]
>
>> From what I see, the ECC test code uses in_be32() and friends to
>> access the memory. And these access functions have all necessary
>> barriers already built into. So most likely the additional barriers
>> were never necessary at all. Or perhaps the code was changed from
>> using pointer access to in_be32() access.
>>
>> Nevertheless the changes from Larry are looking good to me. But I also
>> forwarded them to the original author of the code for review.
>
> Good, that is what I wanted to get across - someone familiar with the
> code and the processor reviews what, why, when, and how (Larry, you, the
> original author, the list, etc.).
>
> I figured that there must have been barriers that didn't show up in the
> patch since it "mostly works." I'm suspicious that there is a missing
> or misplaced barrier. The "sync ; eieio" pixie dust that Larry removed
> makes me suspicious that something is missing going into the test. In
> that case, the removed "sync" probably *IS* necessary, but that needs to
> be understood and commented (and possibly moved to a better location).
I'm not convinced about in_be32() et al. yet. Section 2.10.3 of the AMCC
PPC440 User's manual says that an "msync" (sync) is required between the
memory access and the control-register access. ("mbar" (eieio) is not
sufficient because the control-register access is not treated as I/O.)
If I'm reading these correctly, in_be32() does a "sync", load, "twi"
(which I don't understand), and "isync". out_be32() does a "sync" and a
store. Thus, neither force completion of the I/O before exiting.
Am I right then that I should include a specific sync before accessing
the SDRAM control registers?
>> Thanks again for your comments.
>>
>> /me goes to mark jvb's mail as important to easier find it as
>> reference. :)
>
> :-) Thanks.
>
>> Best regards,
>> Stefan
>
> Ditto,
> gvb
Best regards,
Larry
-
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Re: [U-Boot-Users] [PATCH] ppc4xx: Refactor ECC POST for AMCC Denali core
Jerry Van Baren wrote:
> Larry Johnson wrote:
>> The ECC POST reported intermittent failures running after power-up on
>> the Korat PPC440EPx board. Even when the test passed, the debugging
>> output occasionally reported additional unexpected ECC errors.
>>
>> This refactoring had two main objectives: (1) minimize the code executed
>> with ECC enabled during the tests, and (2) add more checking of the
>> results so any unexpected ECC errors would cause the test to fail.
>>
>> So far, the refactored test has not reported any intermittent failures.
>> Further, synchronization instructions appear no longer to be require, so
>> have been removed. If intermittent failures do occur in the future, the
>> refactoring should make the causes easier to identify.
>
> WHOOP, WHOOP, WHOOP, red alert! "[S]ynchronization instructions appear
> no longer to be require[d], so have been removed".
>
> Synchronization instructions either *ARE* required or *ARE NOT*
> required, there is no "appear". When sync instructions appear to not be
> required, but actually are required, that is when really obscure bugs
> start happening in the dead of winter off the coast of Alaska / Siberia
> and your boss asks you if you have warm clothes.
>
> I am not familiar with the 4xx family or the PowerPC core that is used
> in it but...
>
> [snip]
>
>> -static int test_ecc(unsigned long ecc_addr)
>> +static int test_ecc(uint32_t ecc_addr)
>> {
>> -unsigned long value;
>> -volatile unsigned *const ecc_mem = (volatile unsigned *) ecc_addr;
>> -int pret;
>> +uint32_t value;
>> +volatile uint32_t *const ecc_mem = (volatile uint32_t *)ecc_addr;
>> int ret = 0;
>>
>> -sync();
>> -eieio();
>> WATCHDOG_RESET();
>
> The combination of "sync" and "eieio" is a strong indication of someone
> sprinkling pixie dust rather than understanding the problem.
>
> "Sync" forces all pending I/O (read/write) operations to be completed
> all the way to memory/hardware register before the instruction
> continues. Sync guarantees *WHEN* the I/O will complete: NOW. This is
> a big hammer: it can cause a significant performance hit because it
> stalls the processor BUT it is guaranteed effective (except for the
> places that need an both an isync and a sync combination - thankfully, I
> believe that is only needed in special cases when playing with the
> processor's control registers).
>
> "Eieio" (enforce in-order execution of I/O) is a barrier that says all
> I/O that goes before it must be completed before any I/O that goes after
> it is started. It *DOES NOT* guarantee *WHEN* the preceding
> reads/writes will be completed. Theoretically, the bus interface unit
> (BIU) could hold the whole shootin' match for 10 minutes before it does
> the preceding I/O followed by the succeeding I/O. Eieio is much less
> draconian to the processor than sync (which is why eieios are preferred)
> but an eieio may or may not cause the intended synchronizing result if
> you are relying on a write or read causing the proper effect *NOW*. Note
> that eieios are NOPs to processor cores that don't reorder I/O.
>
> Some PowerPC cores (e.g. the 74xx family) can reorder reads and writes
> in the bus interface unit (some cores, such as the 603e, do *not*
> reorder reads and writes). This is a performance enhancement... writes
> (generally) are non-blocking to the processor core where a read causes
> the processor to have to wait for the data (which cascades into pipeline
> stalls and performance hits). The bus is a highly oversubscribed
> resource (core speed / bus speed can be 8x or more). As a result, you
> want to get reads done ASAP (if possible) and thus it is beneficial to
> move a read ahead of a write.
>
> As you should have picked up by now, a sync (forcing all I/O to
> complete) followed by eieio is silly - the eieio is superfluous. Seeing
> syncs/isyncs/eieios sprinkled in code is an indication that the author
> didn't understand what was going on and, as a result, kept hitting the
> problem with a bigger and bigger hammer until it appeared to have gone
> away.
>
> Besides read/write reordering problems, the bus interface unit (BIU) can
> "short circuit" a read that follows a write to the same address. This
> is very likely to be implemented in a given core - it offers a very good
> speed up traded off against a modest increase in complexity to the BIU.
> The problem is (for instance), if you configure your EDC to store an
> invalid EDC flag, do a write to a test location (which gets held in the
> BIU because the bus is busy), followed by a read of the test location
> (expecting to see an EDC failure), the BIU could return the queued *but
> unwritten* write value.
>
> OK, enough lecturing...
>
> Repeated disclaimer: What I write here is applicable for more complex
> PowerPC implementations. It may not be applicable for the particular
> 4xx core you are running on. I am n
[U-Boot-Users] [[PATCH] Resubmit] QE UEC: Extend number of supported UECs to 4
Description:
This patch extends the number of supported UECs to 4. Note that the
problem of QE thread resources exhaustion is resolved by setting the
correct number of QE threads according to Ethernet type (GBE or FE).
Signed-off-by: David Saada <[EMAIL PROTECTED]>
> diff -purN drivers/qe/uec.c.orig drivers/qe/uec.c
--- drivers/qe/uec.c.orig 2008-01-14 11:48:28.0 +0200
+++ drivers/qe/uec.c2008-01-14 19:03:55.248775000 +0200
@@ -40,8 +40,13 @@ static uec_info_t eth1_uec_info = {
.tx_clock = CFG_UEC1_TX_CLK,
.eth_type = CFG_UEC1_ETH_TYPE,
},
+#if (CFG_UEC1_ETH_TYPE == FAST_ETH)
+ .num_threads_tx = UEC_NUM_OF_THREADS_1,
+ .num_threads_rx = UEC_NUM_OF_THREADS_1,
+#else
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
@@ -58,8 +63,13 @@ static uec_info_t eth2_uec_info = {
.tx_clock = CFG_UEC2_TX_CLK,
.eth_type = CFG_UEC2_ETH_TYPE,
},
+#if (CFG_UEC2_ETH_TYPE == FAST_ETH)
+ .num_threads_tx = UEC_NUM_OF_THREADS_1,
+ .num_threads_rx = UEC_NUM_OF_THREADS_1,
+#else
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
@@ -68,7 +78,6 @@ static uec_info_t eth2_uec_info = {
.enet_interface = CFG_UEC2_INTERFACE_MODE,
};
#endif
-
#ifdef CONFIG_UEC_ETH3
static uec_info_t eth3_uec_info = {
.uf_info= {
@@ -77,8 +86,13 @@ static uec_info_t eth3_uec_info = {
.tx_clock = CFG_UEC3_TX_CLK,
.eth_type = CFG_UEC3_ETH_TYPE,
},
+#if (CFG_UEC3_ETH_TYPE == FAST_ETH)
+ .num_threads_tx = UEC_NUM_OF_THREADS_1,
+ .num_threads_rx = UEC_NUM_OF_THREADS_1,
+#else
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
@@ -87,6 +101,29 @@ static uec_info_t eth3_uec_info = {
.enet_interface = CFG_UEC3_INTERFACE_MODE,
};
#endif
+#ifdef CONFIG_UEC_ETH4
+static uec_info_t eth4_uec_info = {
+ .uf_info= {
+ .ucc_num= CFG_UEC4_UCC_NUM,
+ .rx_clock = CFG_UEC4_RX_CLK,
+ .tx_clock = CFG_UEC4_TX_CLK,
+ .eth_type = CFG_UEC4_ETH_TYPE,
+ },
+#if (CFG_UEC4_ETH_TYPE == FAST_ETH)
+ .num_threads_tx = UEC_NUM_OF_THREADS_1,
+ .num_threads_rx = UEC_NUM_OF_THREADS_1,
+#else
+ .num_threads_tx = UEC_NUM_OF_THREADS_4,
+ .num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
+ .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .tx_bd_ring_len = 16,
+ .rx_bd_ring_len = 16,
+ .phy_address= CFG_UEC4_PHY_ADDR,
+ .enet_interface = CFG_UEC4_INTERFACE_MODE,
+};
+#endif
static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
{
@@ -1262,6 +1299,10 @@ int uec_initialize(int index)
#ifdef CONFIG_UEC_ETH3
uec_info = ð3_uec_info;
#endif
+ } else if (index == 3) {
+#ifdef CONFIG_UEC_ETH4
+ uec_info = ð4_uec_info;
+#endif
} else {
printf("%s: index is illegal.\n", __FUNCTION__);
return -EINVAL;
> diff -purN net/eth.c.orig net/eth.c
--- net/eth.c.orig 2008-01-14 11:48:28.0 +0200
+++ net/eth.c 2008-01-14 18:59:56.708822000 +0200
@@ -217,6 +217,9 @@ int eth_initialize(bd_t *bis)
#if defined(CONFIG_UEC_ETH3)
uec_initialize(2);
#endif
+#if defined(CONFIG_UEC_ETH4)
+ uec_initialize(3);
+#endif
#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
fec_initialize(bis);
-
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Re: [U-Boot-Users] [PATCH] ppc4xx: Refactor ECC POST for AMCC Denali core
Stefan Roese wrote: > Hi Jerry, > > On Monday 14 January 2008, Jerry Van Baren wrote: [snip] >> As you should have picked up by now, a sync (forcing all I/O to >> complete) followed by eieio is silly - the eieio is superfluous. Seeing >> syncs/isyncs/eieios sprinkled in code is an indication that the author >> didn't understand what was going on and, as a result, kept hitting the >> problem with a bigger and bigger hammer until it appeared to have gone >> away. > > Now I'm glad that I'm not the author of this code. ;) But I admit that I did > use this "hammer" in the past. As have we all. The only difference is that most of us don't get caught. ;-) Open source and git: it both exposes and attributes all stupidity. :-D [snip] > From what I see, the ECC test code uses in_be32() and friends to access the > memory. And these access functions have all necessary barriers already built > into. So most likely the additional barriers were never necessary at all. Or > perhaps the code was changed from using pointer access to in_be32() access. > > Nevertheless the changes from Larry are looking good to me. But I also > forwarded them to the original author of the code for review. Good, that is what I wanted to get across - someone familiar with the code and the processor reviews what, why, when, and how (Larry, you, the original author, the list, etc.). I figured that there must have been barriers that didn't show up in the patch since it "mostly works." I'm suspicious that there is a missing or misplaced barrier. The "sync ; eieio" pixie dust that Larry removed makes me suspicious that something is missing going into the test. In that case, the removed "sync" probably *IS* necessary, but that needs to be understood and commented (and possibly moved to a better location). > Thanks again for your comments. > > /me goes to mark jvb's mail as important to easier find it as reference. :) :-) Thanks. > Best regards, > Stefan Ditto, gvb - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] Add attribute POST_PREREL to ECC memory POST
On Sunday 13 January 2008, Larry Johnson wrote: > Signed-off-by: Larry Johnson <[EMAIL PROTECTED]> Acked-by: Stefan Roese <[EMAIL PROTECTED]> Wolfgang, will you pull this patch directly? Best regards, Stefan = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED] = - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] Using UBoot with VxWorks
Has anyone had any success with or know of any resources for booting VxWorks 6 using UBoot? Please send replies to [EMAIL PROTECTED] -- This message was sent from a MailNull anti-spam account. You can get your free account and take control over your email by visiting the following URL. http://mailnull.com/ - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] ppc4xx: Refactor ECC POST for AMCC Denali core
Hi Jerry,
On Monday 14 January 2008, Jerry Van Baren wrote:
> Larry Johnson wrote:
> > The ECC POST reported intermittent failures running after power-up on
> > the Korat PPC440EPx board. Even when the test passed, the debugging
> > output occasionally reported additional unexpected ECC errors.
> >
> > This refactoring had two main objectives: (1) minimize the code executed
> > with ECC enabled during the tests, and (2) add more checking of the
> > results so any unexpected ECC errors would cause the test to fail.
> >
> > So far, the refactored test has not reported any intermittent failures.
> > Further, synchronization instructions appear no longer to be require, so
> > have been removed. If intermittent failures do occur in the future, the
> > refactoring should make the causes easier to identify.
>
> WHOOP, WHOOP, WHOOP, red alert! "[S]ynchronization instructions appear
> no longer to be require[d], so have been removed".
Yes, this sounds suspicious. Thanks for jumping in.
> Synchronization instructions either *ARE* required or *ARE NOT*
> required, there is no "appear". When sync instructions appear to not be
> required, but actually are required, that is when really obscure bugs
> start happening in the dead of winter off the coast of Alaska / Siberia
> and your boss asks you if you have warm clothes.
:)
> I am not familiar with the 4xx family or the PowerPC core that is used
> in it but...
>
> [snip]
>
> > -static int test_ecc(unsigned long ecc_addr)
> > +static int test_ecc(uint32_t ecc_addr)
> > {
> > - unsigned long value;
> > - volatile unsigned *const ecc_mem = (volatile unsigned *) ecc_addr;
> > - int pret;
> > + uint32_t value;
> > + volatile uint32_t *const ecc_mem = (volatile uint32_t *)ecc_addr;
> > int ret = 0;
> >
> > - sync();
> > - eieio();
> > WATCHDOG_RESET();
>
> The combination of "sync" and "eieio" is a strong indication of someone
> sprinkling pixie dust rather than understanding the problem.
>
> "Sync" forces all pending I/O (read/write) operations to be completed
> all the way to memory/hardware register before the instruction
> continues. Sync guarantees *WHEN* the I/O will complete: NOW. This is
> a big hammer: it can cause a significant performance hit because it
> stalls the processor BUT it is guaranteed effective (except for the
> places that need an both an isync and a sync combination - thankfully, I
> believe that is only needed in special cases when playing with the
> processor's control registers).
>
> "Eieio" (enforce in-order execution of I/O) is a barrier that says all
> I/O that goes before it must be completed before any I/O that goes after
> it is started. It *DOES NOT* guarantee *WHEN* the preceding
> reads/writes will be completed. Theoretically, the bus interface unit
> (BIU) could hold the whole shootin' match for 10 minutes before it does
> the preceding I/O followed by the succeeding I/O. Eieio is much less
> draconian to the processor than sync (which is why eieios are preferred)
> but an eieio may or may not cause the intended synchronizing result if
> you are relying on a write or read causing the proper effect *NOW*.
> Note that eieios are NOPs to processor cores that don't reorder I/O.
>
> Some PowerPC cores (e.g. the 74xx family) can reorder reads and writes
> in the bus interface unit (some cores, such as the 603e, do *not*
> reorder reads and writes). This is a performance enhancement... writes
> (generally) are non-blocking to the processor core where a read causes
> the processor to have to wait for the data (which cascades into pipeline
> stalls and performance hits). The bus is a highly oversubscribed
> resource (core speed / bus speed can be 8x or more). As a result, you
> want to get reads done ASAP (if possible) and thus it is beneficial to
> move a read ahead of a write.
>
> As you should have picked up by now, a sync (forcing all I/O to
> complete) followed by eieio is silly - the eieio is superfluous. Seeing
> syncs/isyncs/eieios sprinkled in code is an indication that the author
> didn't understand what was going on and, as a result, kept hitting the
> problem with a bigger and bigger hammer until it appeared to have gone
> away.
Now I'm glad that I'm not the author of this code. ;) But I admit that I did
use this "hammer" in the past.
> Besides read/write reordering problems, the bus interface unit (BIU) can
> "short circuit" a read that follows a write to the same address. This
> is very likely to be implemented in a given core - it offers a very good
> speed up traded off against a modest increase in complexity to the BIU.
> The problem is (for instance), if you configure your EDC to store an
> invalid EDC flag, do a write to a test location (which gets held in the
> BIU because the bus is busy), followed by a read of the test location
> (expecting to see an EDC failure), the BIU could return the queued *but
> unwritten* write value.
>
> OK, enough lecturing...
>
> Repeated disclaimer: W
Re: [U-Boot-Users] [PATCH 2/4] TSEC: Add the support for RealTek RTL8211B PHY
On Jan 11, 2008 4:45 AM, Dave Liu <[EMAIL PROTECTED]> wrote: > Add the support of RealTek RTL8211B PHY, the RTL8211B > PHY only supports RGMII and MII mode. > > Signed-off-by: Dave Liu <[EMAIL PROTECTED]> Ok, Dave confirmed that this code is needed for this PHY. Acked-by: Andy Fleming <[EMAIL PROTECTED]> - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 1/2] Add support for a Freescale non-CPM SPIcontroller
Wolfgang Denk wrote: > In message <[EMAIL PROTECTED]> you wrote: > >> please put this into fsl_spi.h to reuse for different 8xxx family. >> > > fsl_spi.h might be a bit too general? How about non-8xxx Freescale > processors? > f > The naming convention was modeled after 'fsl_i2c', which surely isn't universal to all Freescale I2C controllers either. In Linux, this driver is called 'mpc83xx', which we've learned here is a bit too specialized. I'll happily change the name, but don't know what that should be. regards, Ben - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH]ppc_4xx:netstal HCU5 board: added various fixes and POST
On Monday 14 January 2008, Niklaus Giger wrote:
> Moved some code to nestal/common/nm_bsp.c.
> Added support for the vxWorks EDR.
> Enable trace for Lauterbach, if present.
> Added support for POST.
>
> Signed-off-by: Niklaus Giger <[EMAIL PROTECTED]>
> ---
> board/netstal/hcu5/Makefile |3 +-
> board/netstal/hcu5/README.txt |3 -
> board/netstal/hcu5/hcu5.c | 201
> ++--- board/netstal/hcu5/init.S |
> 63 +
> board/netstal/hcu5/sdram.c| 74 +++
> 5 files changed, 149 insertions(+), 195 deletions(-)
>
> diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile
> index 27398b9..9645e45 100644
> --- a/board/netstal/hcu5/Makefile
> +++ b/board/netstal/hcu5/Makefile
> @@ -23,9 +23,10 @@ include $(TOPDIR)/config.mk
> LIB = $(obj)lib$(BOARD).a
>
> vpath hcu_flash.c ../common
> +vpath nm_bsp.c ../common
>
> # NOBJS : Netstal common objects
> -NOBJS= hcu_flash.o
> +NOBJS= hcu_flash.o nm_bsp.o
> COBJS= $(BOARD).o sdram.o
> SOBJS= init.o
>
> diff --git a/board/netstal/hcu5/README.txt b/board/netstal/hcu5/README.txt
> index 3118da9..c205108 100644
> --- a/board/netstal/hcu5/README.txt
> +++ b/board/netstal/hcu5/README.txt
> @@ -10,9 +10,6 @@ TODO:
> - Fix RTS/CTS problem (HW?)
>CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after
>Switching to interrupt driven serial input mode
> -- Make vxWorks start from u-boot. Possible reasons
> -- Does vxWorks need an entry for the Machine Check interrupt like this
> - tlbentry( 0x4000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ?
>
> Caveats:
>
> diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
> index 8c23e4d..9b3aeed 100644
> --- a/board/netstal/hcu5/hcu5.c
> +++ b/board/netstal/hcu5/hcu5.c
> @@ -22,12 +22,14 @@
> #include
> #include
> #include
> -#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> void hcu_led_set(u32 value);
> -
> +int board_with_pci(void);
> +extern void nm_show_print(int generation, int index, int hw_capabilities);
> +extern void set_params_for_sw_install(int install_requested, char
> *board_name ); +extern void common_misc_init_r(void);
> extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
>
> #undef BOOTSTRAP_OPTION_A_ACTIVE
> @@ -42,23 +44,10 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
> #define SDR0_ECID2 0x0082
> #define SDR0_ECID3 0x0083
>
> -#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e0)
> +#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e0)
> #define SYS_SLOT_ADDRESS (CFG_CPLD + 0x0040)
> -
> -#define DEFAULT_ETH_ADDR "ethaddr"
> -/* ethaddr for first or etha1ddr for second ethernet */
> -
> -enum {
> - /* HW_GENERATION_HCU1 is no longer supported */
> - HW_GENERATION_HCU2 = 0x10,
> - HW_GENERATION_HCU3 = 0x10,
> - HW_GENERATION_HCU4 = 0x20,
> - HW_GENERATION_HCU5 = 0x30,
> - HW_GENERATION_MCU = 0x08,
> - HW_GENERATION_MCU20 = 0x0a,
> - HW_GENERATION_MCU25 = 0x09,
> -};
> -
> +#define HCU_DIGITAL_IO_REGISTER (CFG_CPLD + 0x050)
> +#define HCU_SW_INSTALL_REQUESTED 0x10
>
> /*
> * This function is run very early, out of flash, and before devices are
> @@ -72,7 +61,6 @@ enum {
>
> int board_early_init_f(void)
> {
> - u32 reg;
>
> #ifdef BOOTSTRAP_OPTION_A_ACTIVE
> /* Booting with Bootstrap Option A
> @@ -172,12 +160,6 @@ int board_early_init_f(void)
> mtsdr(sdr_pfc0, 0x3E00);/* Pin function: */
> mtsdr(sdr_pfc1, 0x00848000);/* Pin function: UART0 has 4 pins */
>
> - /* PCI arbiter enabled */
> - mfsdr(sdr_pci0, reg);
> - mtsdr(sdr_pci0, 0x8000 | reg);
> -
> - pci_pre_init(0);
> -
> /* setup BOOT FLASH */
> mtsdr(SDR0_CUST0, 0xC0082350);
>
> @@ -192,33 +174,27 @@ int board_pre_init(void)
>
> #endif
>
> +int sys_install_requested(void)
> +{
> + u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
> + return (*ioValuePtr & HCU_SW_INSTALL_REQUESTED) != 0;
You are accessing CPLD registers here, right? Please use the correct accessor
functions like in_be16(). And please check for other places where you access
CPLD or other peripheral stuff via pointer access. This will break at some
time if you don't use the correct access functions.
> +}
> +
> int checkboard(void)
> {
> - unsigned int j;
> u16 *hwVersReg= (u16 *) HCU_HW_VERSION_REGISTER;
> u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
> u16 generation = *boardVersReg & 0xf0;
> u16 index = *boardVersReg & 0x0f;
Here too. Please fix this.
> u32 ecid0, ecid1, ecid2, ecid3;
>
> - printf("Netstal Maschinen AG: ");
> - if (generation == HW_GENERATION_HCU3)
> - printf("HCU3: index %d", index);
> - else if (generation == HW_GENERATION_HCU4)
> - printf("HCU4: index %d", index);
> - else if (generation == HW_GENERA
Re: [U-Boot-Users] [PATCH]ppc_4xx:netstal/common define routines used by all boards
On Monday 14 January 2008, Niklaus Giger wrote:
> Added some routines used by all Netstal boards nm_show_print and
> common_misc_init_r and the very specific code to handle our SW installation
> procedure (set_params_for_sw_install).
>
> Signed-off-by: Niklaus Giger <[EMAIL PROTECTED]>
> ---
> board/netstal/common/nm_bsp.c | 131
> - 1 files changed, 116
> insertions(+), 15 deletions(-)
>
> diff --git a/board/netstal/common/nm_bsp.c b/board/netstal/common/nm_bsp.c
> index a9de45e..2c1d483 100644
> --- a/board/netstal/common/nm_bsp.c
> +++ b/board/netstal/common/nm_bsp.c
> @@ -20,22 +20,123 @@
>
> #include
> #include
> +#include
>
> -#ifdef CONFIG_CMD_BSP
> -/*
> - * Command nm_bsp: Netstal Maschinen BSP specific command
> - */
> -int nm_bsp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define DEFAULT_ETH_ADDR "ethaddr"
> +
> +extern void hcu_led_set(u32 value);
> +extern u32 get_serial_number(void);
> +extern u32 hcu_get_slot(void);
> +
> +enum {
> + /* HW_GENERATION_HCU1 is no longer supported */
> + HW_GENERATION_HCU2 = 0x10,
> + HW_GENERATION_HCU3 = 0x10,
> + HW_GENERATION_HCU4 = 0x20,
> + HW_GENERATION_HCU5 = 0x30,
> + HW_GENERATION_MCU = 0x08,
> + HW_GENERATION_MCU20 = 0x0a,
> + HW_GENERATION_MCU25 = 0x09,
> +};
> +
> +
> +void nm_show_print(int generation, int index, int hw_capabilities)
> +{
> + int j;
Empty line after var declaration.
> + /* reset ANSI terminal color mode */
> + printf ("\x1B""[0m""Netstal Maschinen AG: ");
Either use space after the function (here "print") all the time in this file
or never (which is what I prefer).
> + if (generation == HW_GENERATION_HCU3)
> + printf("HCU3: index %d", index);
> + else if (generation == HW_GENERATION_HCU4)
> + printf("HCU4: index %d", index);
> + else if (generation == HW_GENERATION_HCU5)
> + printf("HCU5: index %d", index);
> + else if (generation == HW_GENERATION_MCU25)
> + printf("MCU25: index %d", index);
> + printf(" HW 0x%x\n", hw_capabilities);
> + for (j = 0;j < 6; j++) {
> + hcu_led_set(1 << j);
> + udelay(200 * 1000);
> + }
> +}
> +
> +void set_params_for_sw_install(int install_requested, char *board_name )
> {
> - printf("%s: flag %d, argc %d, argv[0] %s\n", __FUNCTION__,
> -flag, argc, argv[0]);
> - printf("Netstal Maschinen BSP specific command. None at the moment.\n");
> - return 0;
> + if (install_requested) {
> + char string[128];
Newline.
> + printf("\n\n%s SW-Installation: %d patching boot parameters\n",
> +board_name, install_requested);
> + setenv("bootdelay", "0");
> + setenv("loadaddr", "0x0100");
> + setenv("serverip", "172.25.1.1");
> + setenv("bootcmd", "run install");
> + sprintf(string, "tftp ${loadaddr} admin/sw_on_hd; "
> + "tftp ${loadaddr} installer/%s_sw_inst; "
> + "run boot_sw_inst", board_name);
> + setenv("install", string);
> + sprintf(string, "setenv bootargs emac(0,0)c:%s/%s_sw_inst "
> + "e=${ipaddr} h=${serverip} f=0x1000; bootvx
> ${loadaddr}\0",
> + board_name, board_name);
> + setenv("boot_sw_inst", string);
> + }
> +}
> +
> +void common_misc_init_r(void)
> +{
> + char *s = getenv(DEFAULT_ETH_ADDR);
> + char *e;
> + int i;
> + u32 serial = get_serial_number();
> +
> + for (i = 0; i < 6; ++i) {
> + gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
> + if (s)
> + s = (*e) ? e + 1 : e;
> + }
> +
> + if (gd->bd->bi_enetaddr[3] == 0 &&
> + gd->bd->bi_enetaddr[4] == 0 &&
> + gd->bd->bi_enetaddr[5] == 0) {
> + char ethaddr[22];
> +
> + /* Must be in sync with CONFIG_ETHADDR */
> + gd->bd->bi_enetaddr[0] = 0x00;
> + gd->bd->bi_enetaddr[1] = 0x60;
> + gd->bd->bi_enetaddr[2] = 0x13;
> + gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
> + gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
> + gd->bd->bi_enetaddr[5] = hcu_get_slot();
> + sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
> + gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
> + gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
> + gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
> + printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
> +ethaddr, serial);
> + setenv(DEFAULT_ETH_ADDR, ethaddr);
> + }
> +
> + /* IP-Adress update */
> + {
Why do you need this "{" here? Doesn't really make sense to me.
Please fix and resubmit.
Thanks.
[U-Boot-Users] [PATCH] MPC8313eRDB/MPC8349ITX: fix board Makefile for silent build (with -s)
Signed-off-by: Kumar Gala <[EMAIL PROTECTED]> --- board/freescale/mpc8313erdb/Makefile |2 +- board/freescale/mpc8349itx/Makefile |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile index a987e51..e97ba81 100644 --- a/board/freescale/mpc8313erdb/Makefile +++ b/board/freescale/mpc8313erdb/Makefile @@ -32,7 +32,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB):$(obj).depend $(OBJS) - $(AR) crv $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/freescale/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile index 31bcdb8..265e341 100644 --- a/board/freescale/mpc8349itx/Makefile +++ b/board/freescale/mpc8349itx/Makefile @@ -31,7 +31,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB):$(obj).depend $(OBJS) - $(AR) crv $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) -- 1.5.3.7 - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] ppc_4xx:netstal/common fixes wrong check for flash erase
On Monday 14 January 2008, Niklaus Giger wrote:
> Fixed an error in the Netstal specific code, where sometimes a flash was
> declared as not erased, even when it was.
>
> Signed-off-by: Niklaus Giger <[EMAIL PROTECTED]>
> ---
> board/netstal/common/hcu_flash.c | 10 +++---
> 1 files changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/board/netstal/common/hcu_flash.c
> b/board/netstal/common/hcu_flash.c index be2cb37..d41d579 100644
> --- a/board/netstal/common/hcu_flash.c
> +++ b/board/netstal/common/hcu_flash.c
> @@ -30,6 +30,9 @@
> * Modified 6/6/2007
> * Added isync
> * Niklaus Giger, Netstal Maschinen, [EMAIL PROTECTED]
> + * Modified 13/3/2007
> + * Removed check whether flash is already erased. Gave false errors.
> + * Niklaus Giger, Netstal Maschinen, [EMAIL PROTECTED]
Don't add commit logs to the source code. We have git for this. So please add
descriptive commit texts to your commit logs.
> *
> */
>
> @@ -480,7 +483,6 @@ int write_buff (flash_info_t * info, uchar * src, ulong
> addr, ulong cnt) * Write a word to Flash, returns:
> * 0 - OK
> * 1 - write timeout
> - * 2 - Flash not erased
> */
> static int write_word (flash_info_t * info, ulong dest, ulong data)
> {
> @@ -491,12 +493,6 @@ static int write_word (flash_info_t * info, ulong
> dest, ulong data) ulong start;
> int i;
>
> - /* Check if Flash is (sufficiently) erased */
> - if ((*((volatile FLASH_WORD_SIZE *) dest) &
> - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
> - return (2);
> - }
> -
Wow. I don't think you really solve this problem with this patch. You are just
lucky that everything works with this change. Could be that the pointer
accesses are the main source of this problem. I suggest that you try to move
to the common CFI driver which now supports non CFI flash chips via the JEDEC
code.
Best regards,
Stefan
=
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED]
=
-
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It's the best place to buy or sell services for
just about anything Open Source.
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Re: [U-Boot-Users] [PATCH]ppc_4xx: Netstal HCU5 board. Added POST. Various fixes
On Monday 14 January 2008, Niklaus Giger wrote:
> Various fixes. Reduced rom_size from 384 to 320 kB.
> Environment is now in flash.
> Added POST, support for OF.
I suggest to change this commit text into something like this:
- Various fixes
- Reduced rom_size from 384 to 320 kB
- Environment is now in flash
- Added POST
- Support for OF
Better overview, don't you think?
More comments below.
> Signed-off-by: Niklaus Giger <[EMAIL PROTECTED]>
> ---
> board/netstal/hcu5/config.mk |2 +-
> include/configs/hcu5.h | 61
> + 2 files changed, 44
> insertions(+), 19 deletions(-)
>
> diff --git a/board/netstal/hcu5/config.mk b/board/netstal/hcu5/config.mk
> index cfd5744..05b879f 100644
> --- a/board/netstal/hcu5/config.mk
> +++ b/board/netstal/hcu5/config.mk
> @@ -21,7 +21,7 @@
> # Netstal Maschinen AG: HCU5 boards
> #
>
> -TEXT_BASE = 0xFFFa
> +TEXT_BASE = 0xFFFb
Again, upper case or lower case please.
> PLATFORM_CPPFLAGS += -DCONFIG_440=1
>
> diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
> index 1440838..05185d2 100644
> --- a/include/configs/hcu5.h
> +++ b/include/configs/hcu5.h
> @@ -48,9 +48,10 @@
> * Base addresses -- Note these are effective addresses where the
> * actual resources get mapped (not physical addresses)
> *--*/
> -#define CFG_MONITOR_LEN (384 * 1024)/* Reserve 384 kB for
> Monitor */
> +#define CFG_MONITOR_LEN (320 * 1024)/* Reserve 320 kB for Monitor
> */
> #define CFG_MALLOC_LEN (256 * 1024)/* Reserve 256 kB for
> malloc() */
>
> +#define CFG_TLB_FOR_BOOT_FLASH 3
> #define CFG_BOOT_BASE_ADDR 0xfff0
> #define CFG_SDRAM_BASE 0x /* _must_ be 0
> */
> #define CFG_FLASH_BASE 0xfff8 /* start of FLASH
> */
> @@ -97,6 +98,7 @@
> #undef CONFIG_SERIAL_SOFTWARE_FIFO
> #undef CONFIG_UART1_CONSOLE
>
> +#undef CONFIG_CMD_HWFLOW
> #define CFG_BAUDRATE_TABLE \
> {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
>
> @@ -105,8 +107,8 @@
> *--*/
>
> #undef CFG_ENV_IS_IN_NVRAM
> -#undef CFG_ENV_IS_IN_FLASH
> -#define CFG_ENV_IS_IN_EEPROM
> +#define CFG_ENV_IS_IN_FLASH
> +#undef CFG_ENV_IS_IN_EEPROM
> #undef CFG_ENV_IS_NOWHERE
>
> #ifdef CFG_ENV_IS_IN_EEPROM
> @@ -121,21 +123,30 @@
> /* Put the environment in Flash */
> #define CFG_ENV_SECT_SIZE0x1 /* size of one complete sector
> */
> #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
> -#define CFG_ENV_SIZE0x1 /* Total Size of Environment
> Sector */
> +#define CFG_ENV_SIZE8*1024 /* 8 KB Environment Sector
> */
>
> /* Address and size of Redundant Environment Sector */
> #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
> #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
> +/*
> +#undef CFG_ENV_ADDR_REDUND
> +#undef CFG_ENV_SIZE_REDUND
> +*/
Please remove it when it's not used/defined.
> #endif
>
> /*---
> * DDR SDRAM
> *--*/
> #define CFG_MBYTES_SDRAM(128)/* 128 MB or 256 MB
> */
> -#define CFG_DDR_CACHED_ADDR 0x4000 /* setup 2nd TLB cached here
> */
> +#define CFG_DDR_CACHED_ADDR 0x5000 /* setup 2nd TLB cached here
> */
> #undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization
> */
> #define CONFIG_DDR_ECC 1 /* enable ECC
> */
>
> +/* Following two definitions must be kept in sync with config.h of vxWorks
> */ +#define USER_RESERVED_MEM ( 0) /* in kB */
> +#define PM_RESERVED_MEM ( 64) /* in kB: pmLib reserved area size
> */ +#define CONFIG_PRAM ( USER_RESERVED_MEM + PM_RESERVED_MEM ) +
> /*---
> * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
> * the second internal I2C controller of the PPC440EPx
> @@ -167,7 +178,7 @@
>
> /* Setup some board specific values for the default environment variables
> */ #define CONFIG_HOSTNAMEhcu5
> -#define CONFIG_IPADDR172.25.1.42
> +#define CONFIG_IPADDR172.25.1.99
> #define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG
> MAC */ #define CONFIG_OVERWRITE_ETHADDR_ONCE
> #define CONFIG_SERVERIP 172.25.1.3
> @@ -189,13 +200,23 @@
> "bootfile=hcu5/uImage\0"\
> "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
> "load=tftp 10 hcu5/u-boot.bin\0
Re: [U-Boot-Users] [PATCH]ppc_4xx: Netstal HCU4 board. Added POST. Various fixes
On Monday 14 January 2008, Niklaus Giger wrote: > Various fixes. Reduced rom_size from 384 to 320 kB. > Environment is now in flash. > Added POST, support for OF. > > Signed-off-by: Niklaus Giger <[EMAIL PROTECTED]> > --- > board/netstal/hcu4/config.mk |2 +- > include/configs/hcu4.h | 33 - > 2 files changed, 21 insertions(+), 14 deletions(-) > > diff --git a/board/netstal/hcu4/config.mk b/board/netstal/hcu4/config.mk > index 376609a..2c0d595 100644 > --- a/board/netstal/hcu4/config.mk > +++ b/board/netstal/hcu4/config.mk > @@ -21,7 +21,7 @@ > # Netstal Maschinen AG: HCU4 boards > # > > -TEXT_BASE = 0xFFFa > +TEXT_BASE = 0xFFFb Either use lower case or upper case characters but don't mix them in one define. I know it was present in the original version too and must have slipped through. Please clean up and resubmit. Thanks. Best regards, Stefan = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED] = - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] ppc_4xx:Fix post spr.c for PPC405
On Monday 14 January 2008, Niklaus Giger wrote: > post/cpu/ppc4xx/spr.c contained a few checks for registers only present > for PPC440 and derivates processor. > > Signed-off-by: Niklaus Giger <[EMAIL PROTECTED]> After applying your patch via "git-am" I noticed the following log message using "git-log": commit a2a47d9203a1249637d16e5fc4a1e7ed7bcf8fc2 Author: Niklaus Giger <[EMAIL PROTECTED]> Date: Mon Jan 14 14:04:42 2008 +0100 ppc_4xx:Fix post spr.c for PPC405 --Boundary-01=_q31iH91amNpeawe Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit post/cpu/ppc4xx/spr.c contained a few checks for registers only present for PPC440 and derivates processor. Signed-off-by: Niklaus Giger <[EMAIL PROTECTED]> Somehow your mailer has corrupted the commit text. I'll fix this manually. But please make sure this doesn't happen again. I strongly suggest that you look into "git-send-email" and it's configuration. This makes sending patches real easy and errors via mailer are impossible. Thanks. Best regards, Stefan = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED] = - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] ppc4xx: Refactor ECC POST for AMCC Denali core
Larry Johnson wrote:
> The ECC POST reported intermittent failures running after power-up on
> the Korat PPC440EPx board. Even when the test passed, the debugging
> output occasionally reported additional unexpected ECC errors.
>
> This refactoring had two main objectives: (1) minimize the code executed
> with ECC enabled during the tests, and (2) add more checking of the
> results so any unexpected ECC errors would cause the test to fail.
>
> So far, the refactored test has not reported any intermittent failures.
> Further, synchronization instructions appear no longer to be require, so
> have been removed. If intermittent failures do occur in the future, the
> refactoring should make the causes easier to identify.
WHOOP, WHOOP, WHOOP, red alert! "[S]ynchronization instructions appear
no longer to be require[d], so have been removed".
Synchronization instructions either *ARE* required or *ARE NOT*
required, there is no "appear". When sync instructions appear to not be
required, but actually are required, that is when really obscure bugs
start happening in the dead of winter off the coast of Alaska / Siberia
and your boss asks you if you have warm clothes.
I am not familiar with the 4xx family or the PowerPC core that is used
in it but...
[snip]
> -static int test_ecc(unsigned long ecc_addr)
> +static int test_ecc(uint32_t ecc_addr)
> {
> - unsigned long value;
> - volatile unsigned *const ecc_mem = (volatile unsigned *) ecc_addr;
> - int pret;
> + uint32_t value;
> + volatile uint32_t *const ecc_mem = (volatile uint32_t *)ecc_addr;
> int ret = 0;
>
> - sync();
> - eieio();
> WATCHDOG_RESET();
The combination of "sync" and "eieio" is a strong indication of someone
sprinkling pixie dust rather than understanding the problem.
"Sync" forces all pending I/O (read/write) operations to be completed
all the way to memory/hardware register before the instruction
continues. Sync guarantees *WHEN* the I/O will complete: NOW. This is
a big hammer: it can cause a significant performance hit because it
stalls the processor BUT it is guaranteed effective (except for the
places that need an both an isync and a sync combination - thankfully, I
believe that is only needed in special cases when playing with the
processor's control registers).
"Eieio" (enforce in-order execution of I/O) is a barrier that says all
I/O that goes before it must be completed before any I/O that goes after
it is started. It *DOES NOT* guarantee *WHEN* the preceding
reads/writes will be completed. Theoretically, the bus interface unit
(BIU) could hold the whole shootin' match for 10 minutes before it does
the preceding I/O followed by the succeeding I/O. Eieio is much less
draconian to the processor than sync (which is why eieios are preferred)
but an eieio may or may not cause the intended synchronizing result if
you are relying on a write or read causing the proper effect *NOW*.
Note that eieios are NOPs to processor cores that don't reorder I/O.
Some PowerPC cores (e.g. the 74xx family) can reorder reads and writes
in the bus interface unit (some cores, such as the 603e, do *not*
reorder reads and writes). This is a performance enhancement... writes
(generally) are non-blocking to the processor core where a read causes
the processor to have to wait for the data (which cascades into pipeline
stalls and performance hits). The bus is a highly oversubscribed
resource (core speed / bus speed can be 8x or more). As a result, you
want to get reads done ASAP (if possible) and thus it is beneficial to
move a read ahead of a write.
As you should have picked up by now, a sync (forcing all I/O to
complete) followed by eieio is silly - the eieio is superfluous. Seeing
syncs/isyncs/eieios sprinkled in code is an indication that the author
didn't understand what was going on and, as a result, kept hitting the
problem with a bigger and bigger hammer until it appeared to have gone away.
Besides read/write reordering problems, the bus interface unit (BIU) can
"short circuit" a read that follows a write to the same address. This
is very likely to be implemented in a given core - it offers a very good
speed up traded off against a modest increase in complexity to the BIU.
The problem is (for instance), if you configure your EDC to store an
invalid EDC flag, do a write to a test location (which gets held in the
BIU because the bus is busy), followed by a read of the test location
(expecting to see an EDC failure), the BIU could return the queued *but
unwritten* write value.
OK, enough lecturing...
Repeated disclaimer: What I write here is applicable for more complex
PowerPC implementations. It may not be applicable for the particular
4xx core you are running on. I am not familiar with the 4xx core.
The reason sync/eieio is very likely VITAL in a EDC test is that...
1) The EDC is being reconfigured in a way that can cause latent EDC
faults. If
[U-Boot-Users] [PATCH]ppc_4xx:netstal HCU5 board: added various fixes and POST
Moved some code to nestal/common/nm_bsp.c.
Added support for the vxWorks EDR.
Enable trace for Lauterbach, if present.
Added support for POST.
Signed-off-by: Niklaus Giger <[EMAIL PROTECTED]>
---
board/netstal/hcu5/Makefile |3 +-
board/netstal/hcu5/README.txt |3 -
board/netstal/hcu5/hcu5.c | 201 ++---
board/netstal/hcu5/init.S | 63 +
board/netstal/hcu5/sdram.c| 74 +++
5 files changed, 149 insertions(+), 195 deletions(-)
diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile
index 27398b9..9645e45 100644
--- a/board/netstal/hcu5/Makefile
+++ b/board/netstal/hcu5/Makefile
@@ -23,9 +23,10 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).a
vpath hcu_flash.c ../common
+vpath nm_bsp.c ../common
# NOBJS : Netstal common objects
-NOBJS = hcu_flash.o
+NOBJS = hcu_flash.o nm_bsp.o
COBJS = $(BOARD).o sdram.o
SOBJS = init.o
diff --git a/board/netstal/hcu5/README.txt b/board/netstal/hcu5/README.txt
index 3118da9..c205108 100644
--- a/board/netstal/hcu5/README.txt
+++ b/board/netstal/hcu5/README.txt
@@ -10,9 +10,6 @@ TODO:
- Fix RTS/CTS problem (HW?)
CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after
Switching to interrupt driven serial input mode
-- Make vxWorks start from u-boot. Possible reasons
-- Does vxWorks need an entry for the Machine Check interrupt like this
- tlbentry( 0x4000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ?
Caveats:
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index 8c23e4d..9b3aeed 100644
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -22,12 +22,14 @@
#include
#include
#include
-#include
DECLARE_GLOBAL_DATA_PTR;
void hcu_led_set(u32 value);
-
+int board_with_pci(void);
+extern void nm_show_print(int generation, int index, int hw_capabilities);
+extern void set_params_for_sw_install(int install_requested, char *board_name
);
+extern void common_misc_init_r(void);
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
#undef BOOTSTRAP_OPTION_A_ACTIVE
@@ -42,23 +44,10 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
#define SDR0_ECID2 0x0082
#define SDR0_ECID3 0x0083
-#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e0)
+#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e0)
#define SYS_SLOT_ADDRESS (CFG_CPLD + 0x0040)
-
-#define DEFAULT_ETH_ADDR "ethaddr"
-/* ethaddr for first or etha1ddr for second ethernet */
-
-enum {
- /* HW_GENERATION_HCU1 is no longer supported */
- HW_GENERATION_HCU2 = 0x10,
- HW_GENERATION_HCU3 = 0x10,
- HW_GENERATION_HCU4 = 0x20,
- HW_GENERATION_HCU5 = 0x30,
- HW_GENERATION_MCU = 0x08,
- HW_GENERATION_MCU20 = 0x0a,
- HW_GENERATION_MCU25 = 0x09,
-};
-
+#define HCU_DIGITAL_IO_REGISTER(CFG_CPLD + 0x050)
+#define HCU_SW_INSTALL_REQUESTED 0x10
/*
* This function is run very early, out of flash, and before devices are
@@ -72,7 +61,6 @@ enum {
int board_early_init_f(void)
{
- u32 reg;
#ifdef BOOTSTRAP_OPTION_A_ACTIVE
/* Booting with Bootstrap Option A
@@ -172,12 +160,6 @@ int board_early_init_f(void)
mtsdr(sdr_pfc0, 0x3E00);/* Pin function: */
mtsdr(sdr_pfc1, 0x00848000);/* Pin function: UART0 has 4 pins */
- /* PCI arbiter enabled */
- mfsdr(sdr_pci0, reg);
- mtsdr(sdr_pci0, 0x8000 | reg);
-
- pci_pre_init(0);
-
/* setup BOOT FLASH */
mtsdr(SDR0_CUST0, 0xC0082350);
@@ -192,33 +174,27 @@ int board_pre_init(void)
#endif
+int sys_install_requested(void)
+{
+ u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
+ return (*ioValuePtr & HCU_SW_INSTALL_REQUESTED) != 0;
+}
+
int checkboard(void)
{
- unsigned int j;
u16 *hwVersReg= (u16 *) HCU_HW_VERSION_REGISTER;
u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
u16 generation = *boardVersReg & 0xf0;
u16 index = *boardVersReg & 0x0f;
u32 ecid0, ecid1, ecid2, ecid3;
- printf("Netstal Maschinen AG: ");
- if (generation == HW_GENERATION_HCU3)
- printf("HCU3: index %d", index);
- else if (generation == HW_GENERATION_HCU4)
- printf("HCU4: index %d", index);
- else if (generation == HW_GENERATION_HCU5)
- printf("HCU5: index %d", index);
- printf(" HW 0x%02x\n", *hwVersReg & 0xff);
+ nm_show_print(generation, index, *hwVersReg & 0xff);
mfsdr(SDR0_ECID0, ecid0);
mfsdr(SDR0_ECID1, ecid1);
mfsdr(SDR0_ECID2, ecid2);
mfsdr(SDR0_ECID3, ecid3);
printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
- for (j = 0;j < 6; j++) {
- hcu_led_set(1 << j);
- udelay(200 * 1000);
- }
return 0;
}
@@ -239,7 +215,7 @@ void hcu_led_set(u32
[U-Boot-Users] [PATCH]ppc_4xx:netstal/common define routines used by all boards
Added some routines used by all Netstal boards nm_show_print and
common_misc_init_r and the very specific code to handle our SW installation
procedure (set_params_for_sw_install).
Signed-off-by: Niklaus Giger <[EMAIL PROTECTED]>
---
board/netstal/common/nm_bsp.c | 131 -
1 files changed, 116 insertions(+), 15 deletions(-)
diff --git a/board/netstal/common/nm_bsp.c b/board/netstal/common/nm_bsp.c
index a9de45e..2c1d483 100644
--- a/board/netstal/common/nm_bsp.c
+++ b/board/netstal/common/nm_bsp.c
@@ -20,22 +20,123 @@
#include
#include
+#include
-#ifdef CONFIG_CMD_BSP
-/*
- * Command nm_bsp: Netstal Maschinen BSP specific command
- */
-int nm_bsp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DEFAULT_ETH_ADDR "ethaddr"
+
+extern void hcu_led_set(u32 value);
+extern u32 get_serial_number(void);
+extern u32 hcu_get_slot(void);
+
+enum {
+ /* HW_GENERATION_HCU1 is no longer supported */
+ HW_GENERATION_HCU2 = 0x10,
+ HW_GENERATION_HCU3 = 0x10,
+ HW_GENERATION_HCU4 = 0x20,
+ HW_GENERATION_HCU5 = 0x30,
+ HW_GENERATION_MCU = 0x08,
+ HW_GENERATION_MCU20 = 0x0a,
+ HW_GENERATION_MCU25 = 0x09,
+};
+
+
+void nm_show_print(int generation, int index, int hw_capabilities)
+{
+ int j;
+ /* reset ANSI terminal color mode */
+ printf ("\x1B""[0m""Netstal Maschinen AG: ");
+ if (generation == HW_GENERATION_HCU3)
+ printf("HCU3: index %d", index);
+ else if (generation == HW_GENERATION_HCU4)
+ printf("HCU4: index %d", index);
+ else if (generation == HW_GENERATION_HCU5)
+ printf("HCU5: index %d", index);
+ else if (generation == HW_GENERATION_MCU25)
+ printf("MCU25: index %d", index);
+ printf(" HW 0x%x\n", hw_capabilities);
+ for (j = 0;j < 6; j++) {
+ hcu_led_set(1 << j);
+ udelay(200 * 1000);
+ }
+}
+
+void set_params_for_sw_install(int install_requested, char *board_name )
{
- printf("%s: flag %d, argc %d, argv[0] %s\n", __FUNCTION__,
- flag, argc, argv[0]);
- printf("Netstal Maschinen BSP specific command. None at the moment.\n");
- return 0;
+ if (install_requested) {
+ char string[128];
+ printf("\n\n%s SW-Installation: %d patching boot parameters\n",
+ board_name, install_requested);
+ setenv("bootdelay", "0");
+ setenv("loadaddr", "0x0100");
+ setenv("serverip", "172.25.1.1");
+ setenv("bootcmd", "run install");
+ sprintf(string, "tftp ${loadaddr} admin/sw_on_hd; "
+ "tftp ${loadaddr} installer/%s_sw_inst; "
+ "run boot_sw_inst", board_name);
+ setenv("install", string);
+ sprintf(string, "setenv bootargs emac(0,0)c:%s/%s_sw_inst "
+ "e=${ipaddr} h=${serverip} f=0x1000; bootvx
${loadaddr}\0",
+ board_name, board_name);
+ setenv("boot_sw_inst", string);
+ }
+}
+
+void common_misc_init_r(void)
+{
+ char *s = getenv(DEFAULT_ETH_ADDR);
+ char *e;
+ int i;
+ u32 serial = get_serial_number();
+
+ for (i = 0; i < 6; ++i) {
+ gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+
+ if (gd->bd->bi_enetaddr[3] == 0 &&
+ gd->bd->bi_enetaddr[4] == 0 &&
+ gd->bd->bi_enetaddr[5] == 0) {
+ char ethaddr[22];
+
+ /* Must be in sync with CONFIG_ETHADDR */
+ gd->bd->bi_enetaddr[0] = 0x00;
+ gd->bd->bi_enetaddr[1] = 0x60;
+ gd->bd->bi_enetaddr[2] = 0x13;
+ gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
+ gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
+ gd->bd->bi_enetaddr[5] = hcu_get_slot();
+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
+ gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
+ gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
+ gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
+ printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
+ ethaddr, serial);
+ setenv(DEFAULT_ETH_ADDR, ethaddr);
+ }
+
+ /* IP-Adress update */
+ {
+ IPaddr_t ipaddr;
+ char *ipstring;
+
+ ipstring = getenv("ipaddr");
+ if (ipstring == 0)
+ ipaddr = string_to_ip("172.25.1.99");
+ else
+ ipaddr = string_to_ip(ipstring);
+ if ((ipaddr & 0xff) != (32 + hcu_get_slot())) {
+ char tmp[22];
+
+
[U-Boot-Users] [PATCH] ppc_4xx:netstal/common fixes wrong check for flash erase
Fixed an error in the Netstal specific code, where sometimes a flash was
declared as not erased, even when it was.
Signed-off-by: Niklaus Giger <[EMAIL PROTECTED]>
---
board/netstal/common/hcu_flash.c | 10 +++---
1 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/board/netstal/common/hcu_flash.c b/board/netstal/common/hcu_flash.c
index be2cb37..d41d579 100644
--- a/board/netstal/common/hcu_flash.c
+++ b/board/netstal/common/hcu_flash.c
@@ -30,6 +30,9 @@
* Modified 6/6/2007
* Added isync
* Niklaus Giger, Netstal Maschinen, [EMAIL PROTECTED]
+ * Modified 13/3/2007
+ * Removed check whether flash is already erased. Gave false errors.
+ * Niklaus Giger, Netstal Maschinen, [EMAIL PROTECTED]
*
*/
@@ -480,7 +483,6 @@ int write_buff (flash_info_t * info, uchar * src, ulong
addr, ulong cnt)
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
- * 2 - Flash not erased
*/
static int write_word (flash_info_t * info, ulong dest, ulong data)
{
@@ -491,12 +493,6 @@ static int write_word (flash_info_t * info, ulong dest,
ulong data)
ulong start;
int i;
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *) dest) &
- (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
-
for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
int flag;
--
1.5.2.5
--
Niklaus Giger
Netstal Maschinen AG
CH-8752 Naefels
-
Check out the new SourceForge.net Marketplace.
It's the best place to buy or sell services for
just about anything Open Source.
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[U-Boot-Users] [PATCH]ppc_4xx: Netstal HCU5 board. Added POST. Various fixes
Various fixes. Reduced rom_size from 384 to 320 kB.
Environment is now in flash.
Added POST, support for OF.
Signed-off-by: Niklaus Giger <[EMAIL PROTECTED]>
---
board/netstal/hcu5/config.mk |2 +-
include/configs/hcu5.h | 61 +
2 files changed, 44 insertions(+), 19 deletions(-)
diff --git a/board/netstal/hcu5/config.mk b/board/netstal/hcu5/config.mk
index cfd5744..05b879f 100644
--- a/board/netstal/hcu5/config.mk
+++ b/board/netstal/hcu5/config.mk
@@ -21,7 +21,7 @@
# Netstal Maschinen AG: HCU5 boards
#
-TEXT_BASE = 0xFFFa
+TEXT_BASE = 0xFFFb
PLATFORM_CPPFLAGS += -DCONFIG_440=1
diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
index 1440838..05185d2 100644
--- a/include/configs/hcu5.h
+++ b/include/configs/hcu5.h
@@ -48,9 +48,10 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*--*/
-#define CFG_MONITOR_LEN(384 * 1024)/* Reserve 384 kB for
Monitor */
+#define CFG_MONITOR_LEN(320 * 1024)/* Reserve 320 kB for Monitor
*/
#define CFG_MALLOC_LEN (256 * 1024)/* Reserve 256 kB for malloc()
*/
+#define CFG_TLB_FOR_BOOT_FLASH 3
#define CFG_BOOT_BASE_ADDR 0xfff0
#define CFG_SDRAM_BASE 0x /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff8 /* start of FLASH */
@@ -97,6 +98,7 @@
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CONFIG_UART1_CONSOLE
+#undef CONFIG_CMD_HWFLOW
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
@@ -105,8 +107,8 @@
*--*/
#undef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_FLASH
-#defineCFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_EEPROM
#undef CFG_ENV_IS_NOWHERE
#ifdef CFG_ENV_IS_IN_EEPROM
@@ -121,21 +123,30 @@
/* Put the environment in Flash */
#define CFG_ENV_SECT_SIZE 0x1 /* size of one complete sector
*/
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
-#defineCFG_ENV_SIZE0x1 /* Total Size of Environment
Sector */
+#defineCFG_ENV_SIZE8*1024 /* 8 KB Environment Sector
*/
/* Address and size of Redundant Environment Sector*/
#define CFG_ENV_ADDR_REDUND(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND(CFG_ENV_SIZE)
+/*
+#undef CFG_ENV_ADDR_REDUND
+#undef CFG_ENV_SIZE_REDUND
+*/
#endif
/*---
* DDR SDRAM
*--*/
#define CFG_MBYTES_SDRAM(128) /* 128 MB or 256 MB
*/
-#define CFG_DDR_CACHED_ADDR0x4000 /* setup 2nd TLB cached here
*/
+#define CFG_DDR_CACHED_ADDR0x5000 /* setup 2nd TLB cached here
*/
#undef CONFIG_DDR_DATA_EYE/* Do not use DDR2 optimization
*/
#define CONFIG_DDR_ECC 1 /* enable ECC
*/
+/* Following two definitions must be kept in sync with config.h of vxWorks */
+#define USER_RESERVED_MEM ( 0) /* in kB */
+#define PM_RESERVED_MEM ( 64) /* in kB: pmLib reserved area size */
+#define CONFIG_PRAM ( USER_RESERVED_MEM + PM_RESERVED_MEM )
+
/*---
* I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
* the second internal I2C controller of the PPC440EPx
@@ -167,7 +178,7 @@
/* Setup some board specific values for the default environment variables */
#define CONFIG_HOSTNAMEhcu5
-#define CONFIG_IPADDR 172.25.1.42
+#define CONFIG_IPADDR 172.25.1.99
#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC
*/
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_SERVERIP172.25.1.3
@@ -189,13 +200,23 @@
"bootfile=hcu5/uImage\0"\
"rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
"load=tftp 10 hcu5/u-boot.bin\0"\
- "update=protect off FFFa ;era FFFa ;" \
- "cp.b 10 FFFa 6\0" \
+ "update=protect off FFFb ;era FFFb ;" \
+ "cp.b 10 FFFb 5\0" \
"upd=run load;run update\0" \
- "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \
- "setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \
- " h=${serverip} u=dpu pw=ne
[U-Boot-Users] [PATCH]ppc_4xx: Netstal HCU4 board. Added POST. Various fixes
Various fixes. Reduced rom_size from 384 to 320 kB.
Environment is now in flash.
Added POST, support for OF.
Signed-off-by: Niklaus Giger <[EMAIL PROTECTED]>
---
board/netstal/hcu4/config.mk |2 +-
include/configs/hcu4.h | 33 -
2 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/board/netstal/hcu4/config.mk b/board/netstal/hcu4/config.mk
index 376609a..2c0d595 100644
--- a/board/netstal/hcu4/config.mk
+++ b/board/netstal/hcu4/config.mk
@@ -21,7 +21,7 @@
# Netstal Maschinen AG: HCU4 boards
#
-TEXT_BASE = 0xFFFa
+TEXT_BASE = 0xFFFb
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG -g
diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h
index 0e259bb..037bda5 100644
--- a/include/configs/hcu4.h
+++ b/include/configs/hcu4.h
@@ -46,7 +46,7 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*--*/
-#define CFG_MONITOR_LEN(384 * 1024)/* Reserve 384 kB for
Monitor */
+#define CFG_MONITOR_LEN(320 * 1024)/* Reserve 320 kB for Monitor
*/
#define CFG_MALLOC_LEN (256 * 1024)/* Reserve 256 kB for malloc()
*/
@@ -105,8 +105,7 @@
*--*/
#undef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_FLASH
-#defineCFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_IS_IN_FLASH
#undef CFG_ENV_IS_NOWHERE
#ifdef CFG_ENV_IS_IN_EEPROM
@@ -120,7 +119,7 @@
/* Put the environment in Flash */
#define CFG_ENV_SECT_SIZE 0x1 /* size of one complete sector
*/
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
-#defineCFG_ENV_SIZE0x1 /* Total Size of Environment
Sector */
+#defineCFG_ENV_SIZE8*1024 /* 8 KB Environment Sector
*/
/* Address and size of Redundant Environment Sector*/
#define CFG_ENV_ADDR_REDUND(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
@@ -158,7 +157,7 @@
/* Setup some board specific values for the default environment variables */
#define CONFIG_HOSTNAMEhcu4
-#define CONFIG_IPADDR 172.25.1.42
+#define CONFIG_IPADDR 172.25.1.99
#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_SERVERIP172.25.1.3
@@ -180,12 +179,12 @@
"rootpath=/home/diagnose/eldk/ppc_4xx\0"\
"bootfile=/tftpboot/hcu4/uImage\0" \
"load=tftp 10 hcu4/u-boot.bin\0"\
- "update=protect off FFFa ;era FFFa ;" \
- "cp.b 10 FFFa 6\0" \
+ "update=protect off FFFB ;era FFFC ;" \
+ "cp.b 10 FFFB 5\0" \
"upd=run load;run update\0" \
"vx=tftp ${loadaddr} hcu4_vx_rom;" \
- "setenv bootargs emac(0,0)hcu4_vx_rom e=${ipaddr} " \
- " h=${serverip} u=dpu pw=netstal8752 tn=hcu4 f=0x3008;" \
+ "vx=tftp ${loadaddr} hcu4/hcu4_vx_rom;" \
+ "setenv bootargs emac(0,0)c:hcu4/hcu4_vx_rom e=${ipaddr} " \
"bootvx ${loadaddr}\0" \
""
#define CONFIG_BOOTCOMMAND "run vx"
@@ -221,7 +220,6 @@
#include
#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BSP
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
@@ -250,9 +248,10 @@
CFG_POST_ETHER| \
CFG_POST_SPR)
+#define CFG_POST_UART_TABLE{UART0_BASE}
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CONFIG_LOGBUFFER
-#define CFG_POST_CACHE_ADDR0x7fff /* free virtual address */
+#define CFG_POST_CACHE_ADDR0x0080 /* free virtual address */
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
/*---
@@ -280,13 +279,14 @@
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW1 /* enable loopw command */
-#define CONFIG_ZERO_BOOTDELAY_CHECK/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*---
* External Bus Controller (EBC) Setup
*/
+#define CFG_EBC_CFG0x9840
+
/* Memory Bank 0 (Flash Bank 0) initialization
*/
#define CFG_EBC_PB0AP 0x02005400
#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1
[U-Boot-Users] [PATCH] ppc_4xx:Fix post spr.c for PPC405
post/cpu/ppc4xx/spr.c contained a few checks for registers only present
for PPC440 and derivates processor.
Signed-off-by: Niklaus Giger <[EMAIL PROTECTED]>
---
post/cpu/ppc4xx/spr.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c
index 3e74634..c12e378 100644
--- a/post/cpu/ppc4xx/spr.c
+++ b/post/cpu/ppc4xx/spr.c
@@ -80,7 +80,9 @@ static struct {
{0x107, "SPRG7",0x, 0x},
{0x10c, "TBL", 0x, 0x},
{0x10d, "TBU", 0x, 0x},
+#ifdef CONFIG_440
{0x11e, "PIR", 0x000f, 0x},
+#endif
{0x130, "DBSR", 0x, 0x},
{0x134, "DBCR0",0x, 0x},
{0x135, "DBCR1",0x, 0x},
@@ -95,6 +97,7 @@ static struct {
{0x13f, "DVC2", 0x, 0x},
{0x150, "TSR", 0x, 0x},
{0x154, "TCR", 0x, 0x},
+#ifdef CONFIG_440
{0x190, "IVOR0",0xfff0, 0x0100},
{0x191, "IVOR1",0xfff0, 0x0200},
{0x192, "IVOR2",0xfff0, 0x0300},
@@ -111,6 +114,7 @@ static struct {
{0x19d, "IVOR13", 0xfff0, 0x1300},
{0x19e, "IVOR14", 0xfff0, 0x1400},
{0x19f, "IVOR15", 0xfff0, 0x2000},
+#endif
{0x23a, "MCSRR0", 0x, 0x},
{0x23b, "MCSRR1", 0x, 0x},
{0x23c, "MCSR", 0x, 0x},
@@ -131,8 +135,10 @@ static struct {
{0x395, "DTV1", 0x, 0x},
{0x396, "DTV2", 0x, 0x},
{0x397, "DTV3", 0x, 0x},
+#ifdef CONFIG_440
{0x398, "DVLIM",0x0fc1f83f, 0x0001f800},
{0x399, "IVLIM",0x0fc1f83f, 0x0001f800},
+#endif
{0x39b, "RSTCFG", 0x, 0x},
{0x39c, "DCDBTRL", 0x, 0x},
{0x39d, "DCDBTRH", 0x, 0x},
--
1.5.2.5
--
Niklaus Giger
Netstal Maschinen AG
CH-8752 Naefels-
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Re: [U-Boot-Users] ppc_4xx: POST_SPR reports an error with DVLIM
Am Montag 14 Januar 2008 13:20:24 schrieb Stefan Roese: > Hi Niklaus, > > On Monday 14 January 2008, Niklaus Giger wrote: > > I added POST (including POST_SPR) to my PPC440EPx based hcu5 board. > > > > After running I did see by executin "log show" > > <..> > > <4>POST spr The value of DVLIM special register is incorrect: 0x > > <4>FAILED > > > > I close inspection revealed that DVLIM is set to the correct value in > > _start_440, but afterwards reset to 0 in dflush. > > I'm pretty sure you are not using the latest version here. I recently > committed a patch from Larry to fix this problem by saving and restoring the > DVLIM register in this routine. Please give the current version in the > official U-Boot repo a try and let me know if the problem still exists. Sorry for the noise, I forgot to do git pull again and missed therefore Larrys fix from last friday. <..> -- Niklaus Giger Netstal Maschinen AG CH-8752 Naefels - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] ppc_4xx: POST_SPR reports an error with DVLIM
Hi Niklaus, On Monday 14 January 2008, Niklaus Giger wrote: > I added POST (including POST_SPR) to my PPC440EPx based hcu5 board. > > After running I did see by executin "log show" > <..> > <4>POST spr The value of DVLIM special register is incorrect: 0x > <4>FAILED > > I close inspection revealed that DVLIM is set to the correct value in > _start_440, but afterwards reset to 0 in dflush. I'm pretty sure you are not using the latest version here. I recently committed a patch from Larry to fix this problem by saving and restoring the DVLIM register in this routine. Please give the current version in the official U-Boot repo a try and let me know if the problem still exists. > Are there any special reasons, why dflush should manipulate DVLIM? DVLIM can be modified for a locked d-cache for example. > Or would it be okay to submit a patch like: > diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S > index a730604..b8c33cc 100644 > --- a/cpu/ppc4xx/start.S > +++ b/cpu/ppc4xx/start.S > @@ -1700,8 +1700,6 @@ trap_reloc: > rlwinm r8,r9,0,15,13 > rlwinm r8,r8,0,17,15 > mtmsr r8 > - addir3,r0,0x > - mtspr dvlim,r3 I'm wondering right now, if setting DVLIM to 0 is correct here. Shouldn't it be set to the default value 0x0001f800? Any comments? Thanks. Best regards, Stefan = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED] = - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] ppc_4xx: POST_SPR reports an error with DVLIM
Hi I added POST (including POST_SPR) to my PPC440EPx based hcu5 board. After running I did see by executin "log show" <..> <4>POST spr The value of DVLIM special register is incorrect: 0x <4>FAILED I close inspection revealed that DVLIM is set to the correct value in _start_440, but afterwards reset to 0 in dflush. Are there any special reasons, why dflush should manipulate DVLIM? Or would it be okay to submit a patch like: diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index a730604..b8c33cc 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1700,8 +1700,6 @@ trap_reloc: rlwinm r8,r9,0,15,13 rlwinm r8,r8,0,17,15 mtmsr r8 - addir3,r0,0x - mtspr dvlim,r3 mfspr r3,ivpr addir4,r0,1024 mtctr r4 --- Best regards -- Niklaus Giger Netstal Maschinen AG CH-8752 Naefels - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] QE UEC: Add CMD_MII support, extend number of supported UECs to 4
> > David, I prefer to have two patch for this. > > One is the CMD_MII support > > The second is the extend UEC to 4. > No problem. Will split the patch. Merging is on you though :) > Regarding the MII support: This will include also a fix in the TSEC > driver to enable it to address all MII addresses on the bus, > regardless > of the port (as someone asked here). Thanks > Regarding the thread number: As each UEC requires 8+ threads (4 for > tx, > 4 for rx), extending the number of UECs to 4 will exceed the number of > QE threads. Now, 4 threads per TX/RX is only required for the GBE UEC. > FE only requires one thread. So I'll change the driver in a way that > it > will use 4+4 threads in case of GBE, and 1+1 in case of FE. I already > tested it here - and it worked fine. This way we won't need these CFG > options per UEC any more. Is this ok? It looks good to me. Thanks, Dave - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support
On Monday 14 January 2008, Matthias Fuchs wrote: > I will update the DU440 patch tonight and also update the sequoia > sources in the same manner. So Stefan can lean back :-) /me leans back and keeps busy with other high priority stuff. :) Thanks Matthias! Best regards, Stefan = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED] = - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] QE UEC: Add CMD_MII support, extend number of supported UECs to 4
> David, I prefer to have two patch for this. > One is the CMD_MII support > The second is the extend UEC to 4. No problem. Will split the patch. Merging is on you though :) Regarding the MII support: This will include also a fix in the TSEC driver to enable it to address all MII addresses on the bus, regardless of the port (as someone asked here). > I don't like so much CFG_ option for the driver, which cause too many > CFG_UEC[x]_NUM_TX_RX_THR in config.h. for every board. > > and I think the threads number is not belonged to board specific things. > The u-boot don't need to consider the UEC performance. > > The default 4 threads should work for you. > If it doesn't work for you, I suggest you keep the changes only for your > project. > > I don't know if you can agree it. > > So, please repost the UEC_ETH4 support patch. Regarding the thread number: As each UEC requires 8+ threads (4 for tx, 4 for rx), extending the number of UECs to 4 will exceed the number of QE threads. Now, 4 threads per TX/RX is only required for the GBE UEC. FE only requires one thread. So I'll change the driver in a way that it will use 4+4 threads in case of GBE, and 1+1 in case of FE. I already tested it here - and it worked fine. This way we won't need these CFG options per UEC any more. Is this ok? David. - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] ARM: cleanup duplicated exception handling code
On Mon, Jan 14, 2008 at 10:06:52AM +0100, Andreas Engel wrote: > Move duplicated exception handling code into lib_arm. Your patch is line wrapped, please fix it. Otherwise I'm happy with it. (we probably do not need special do_fiq version for ixp) ladis - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support
I will update the DU440 patch tonight and also update the sequoia sources in the same manner. So Stefan can lean back :-) Matthias On Monday 14 January 2008 10:45, Wolfgang Denk wrote: > Dear Matthias, > > in message <[EMAIL PROTECTED]> you wrote: > > > > as you might have noticed the DU440 board is havily based on seuqoia code. > > No, I wasn't aware of this. > > > Nearly all of your comments apply to that board as well. I thought of the > > sequoia code as exemplary reference code. And I prefer not to reformat > > comments > > when copy and pasting from one board to another. > > Hm. So I have to talk with the maintainer of this board - especially > how he managed to run this through the custodian without public > review. Stefan, how did he bribe you? :-) > > > But if you really insist of these changes I will change the patch. > > Please do. Ideally, please include the Sequoia in your cleanup, too. > > > > > +#if 0 > > > > +/* > > > > + * test commands for SM722 2D acceleration > > > > + */ > > > ... > > > > +U_BOOT_CMD( > > > > + gfxline,CFG_MAXARGS,1, do_gfxline, > > > > + "gfxline - draw line\n", > > > > + "[color] [x1] [y1] [x2] [y2]\n" > > > > + ); > > > > +#endif > > > > > > Please remove the dead code. > > Please not. The DU440 board will get an updated smi_lynxem driver with > > support for the > > SM722 soon. My current hack is to dirty for submission and I just got some > > more register > > dumps from SM to support more videomodes. I will need this commented out > > code to test it. > > I plan to remove it later. > > Please remove it. We use source code management systems to maintain > test code etc. If it's "#if 0" is has no place in the public code. > > > > You probably may want to adjust the (C) messages in some other files, > > > too. > > Ack. May I put my name on it? The source of this code has no copyright > > either. > > Stefan??? > > > > > + __bss_start = .; > > > > + .bss : > > > > > > NOLOAD attribute missing. Please fix. > > This is new to me. But I just noticed that all other boards have been > > updated according to this. So will I. > > Thanks. > > > I will update my patches. Perhaps you can comment on my comments above. > > Done :-) > > Best regards, > > Wolfgang Denk > -- - Dipl.-Ing. Matthias Fuchs SD4 esd electronic system design gmbh Vahrenwalder Str. 207 - 30165 Hannover - GERMANY Telefon: 0511-37298-0 - Fax: 0511-37298-68 Bitte besuchen Sie uns im Internet unter http://www.esd.eu Quality Products - Made in Germany - Geschäftsführer: Klaus Detering, Dr. Werner Schulze Amtsgericht Hannover HRB 51373 - VAT-ID DE 115672832 - - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [ppc4xx] Please pull git://www.denx.de/git/u-boot-ppc4xx.git
In message <[EMAIL PROTECTED]> you wrote: > The following changes since commit f43ad53908f1ea83a7c26c3505bbe84382e47aad: > Wolfgang Denk (1): > ARM: update mach-types.h from 2.6.24-rc7 Linux kernel tree > > are available in the git repository at: > > git://www.denx.de/git/u-boot-ppc4xx.git master > > Stefan Roese (1): > ppc4xx: Update Kilauea CPLD configuration with USB PHY reset bit > > board/amcc/kilauea/kilauea.c | 14 +++--- > 1 files changed, 7 insertions(+), 7 deletions(-) Done. Thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED] Time is an illusion perpetrated by the manufacturers of space. - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] ARM: cleanup duplicated exception handling code
Move duplicated exception handling code into lib_arm.
Signed-off-by: Andreas Engel <[EMAIL PROTECTED]>
---
cpu/arm1136/interrupts.c | 134 ---
cpu/arm720t/interrupts.c | 132 --
cpu/arm920t/interrupts.c | 134 ---
cpu/arm925t/interrupts.c | 135 ---
cpu/arm926ejs/interrupts.c | 134 ---
cpu/arm946es/interrupts.c | 134 ---
cpu/arm_intcm/Makefile |2
cpu/arm_intcm/interrupts.c | 192
-
cpu/ixp/interrupts.c | 128 +-
cpu/lh7a40x/interrupts.c | 135 ---
cpu/pxa/interrupts.c | 117 ---
cpu/s3c44b0/interrupts.c | 104
cpu/sa1100/interrupts.c| 137
lib_arm/Makefile |2
lib_arm/interrupts.c | 174
15 files changed, 189 insertions(+), 1605 deletions(-)
diff -urpN u-boot-1.3.1/cpu/arm1136/interrupts.c
u-boot-local/cpu/arm1136/interrupts.c
--- u-boot-1.3.1/cpu/arm1136/interrupts.c 2007-12-06
10:21:19.0 +0100
+++ u-boot-local/cpu/arm1136/interrupts.c 2008-01-14
08:49:18.306656000 +0100
@@ -37,145 +37,11 @@
# include
#endif
-#include
-
#define TIMER_LOAD_VAL 0
/* macro to read the 32 bit timer */
#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+TCRR))
-#ifdef CONFIG_USE_IRQ
-/* enable IRQ interrupts */
-void enable_interrupts (void)
-{
- unsigned long temp;
- __asm__ __volatile__("mrs %0, cpsr\n"
-"bic %0, %0, #0x80\n"
-"msr cpsr_c, %0"
-: "=r" (temp)
-:
-: "memory");
-}
-
-/*
- * disable IRQ/FIQ interrupts
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts (void)
-{
- unsigned long old,temp;
- __asm__ __volatile__("mrs %0, cpsr\n"
-"orr %1, %0, #0xc0\n"
-"msr cpsr_c, %1"
-: "=r" (old), "=r"
(temp)
-:
-: "memory");
- return(old & 0x80) == 0;
-}
-#else
-void enable_interrupts (void)
-{
- return;
-}
-int disable_interrupts (void)
-{
- return 0;
-}
-#endif
-
-
-void bad_mode (void)
-{
- panic ("Resetting CPU ...\n");
- reset_cpu (0);
-}
-
-void show_regs (struct pt_regs *regs)
-{
- unsigned long flags;
- const char *processor_modes[] = {
- "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
- "UK4_26", "UK5_26", "UK6_26", "UK7_26",
- "UK8_26", "UK9_26", "UK10_26", "UK11_26",
- "UK12_26", "UK13_26", "UK14_26", "UK15_26",
- "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
- "UK4_32", "UK5_32", "UK6_32", "ABT_32",
- "UK8_32", "UK9_32", "UK10_32", "UND_32",
- "UK12_32", "UK13_32", "UK14_32", "SYS_32",
- };
-
- flags = condition_codes (regs);
-
- printf ("pc : [<%08lx>]lr : [<%08lx>]\n"
- "sp : %08lx ip : %08lx fp : %08lx\n",
- instruction_pointer (regs),
- regs->ARM_lr, regs->ARM_sp, regs->ARM_ip,
regs->ARM_fp);
- printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
- regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
- printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
- regs->ARM_r7, regs->ARM_r6, regs->ARM_r5,
regs->ARM_r4);
- printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
- regs->ARM_r3, regs->ARM_r2, regs->ARM_r1,
regs->ARM_r0);
- printf ("Flags: %c%c%c%c",
- flags & CC_N_BIT ? 'N' : 'n',
- flags & CC_Z_BIT ? 'Z' : 'z',
- flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ?
'V' : 'v');
- printf (" IRQs %s FIQs %s Mode %s%s\n",
- interrupts_enabled (regs) ? "on" : "off",
- fast_interrupts_enabled (regs) ? "on" : "off",
- processor_modes[processor_mode (regs)],
- thumb_mode (regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction (struct pt_regs *pt_regs)
-{
- printf ("undefined instruction\n");
- show_regs (pt_regs);
- bad_mode ();
-}
-
-void do_software_interrupt (struct pt_regs *pt_regs)
-{
- printf ("software interrupt\n");
- show_regs
Re: [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support
Dear Matthias, in message <[EMAIL PROTECTED]> you wrote: > > as you might have noticed the DU440 board is havily based on seuqoia code. No, I wasn't aware of this. > Nearly all of your comments apply to that board as well. I thought of the > sequoia code as exemplary reference code. And I prefer not to reformat > comments > when copy and pasting from one board to another. Hm. So I have to talk with the maintainer of this board - especially how he managed to run this through the custodian without public review. Stefan, how did he bribe you? :-) > But if you really insist of these changes I will change the patch. Please do. Ideally, please include the Sequoia in your cleanup, too. > > > +#if 0 > > > +/* > > > + * test commands for SM722 2D acceleration > > > + */ > > ... > > > +U_BOOT_CMD( > > > + gfxline,CFG_MAXARGS,1, do_gfxline, > > > + "gfxline - draw line\n", > > > + "[color] [x1] [y1] [x2] [y2]\n" > > > + ); > > > +#endif > > > > Please remove the dead code. > Please not. The DU440 board will get an updated smi_lynxem driver with > support for the > SM722 soon. My current hack is to dirty for submission and I just got some > more register > dumps from SM to support more videomodes. I will need this commented out code > to test it. > I plan to remove it later. Please remove it. We use source code management systems to maintain test code etc. If it's "#if 0" is has no place in the public code. > > You probably may want to adjust the (C) messages in some other files, > > too. > Ack. May I put my name on it? The source of this code has no copyright either. Stefan??? > > > + __bss_start = .; > > > + .bss : > > > > NOLOAD attribute missing. Please fix. > This is new to me. But I just noticed that all other boards have been updated > according to this. So will I. Thanks. > I will update my patches. Perhaps you can comment on my comments above. Done :-) Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED] Ernest asks Frank how long he has been working for the company. "Ever since they threatened to fire me." - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] QE UEC: Add CMD_MII support, extend number of supported UECs to 4
> Description: QE UEC: Add CMD_MII support, extend number of supported
> UECs to 4
David, I prefer to have two patch for this.
One is the CMD_MII support
The second is the extend UEC to 4.
> > diff -purN net/eth.c.orig net/eth.c
> --- net/eth.c.origWed Jan 2 13:39:04 2008
> +++ net/eth.c Thu Jan 3 18:44:45 2008
> @@ -202,7 +202,12 @@ int eth_initialize(bd_t *bis)
> #if defined(CONFIG_UEC_ETH2)
> uec_initialize(1);
> #endif
> -
> +#if defined(CONFIG_UEC_ETH3)
> + uec_initialize(2);
> +#endif
The UEC_ETH3 is ready in the main tree.
> +#if defined(CONFIG_UEC_ETH4)
> + uec_initialize(3);
> +#endif
Could you have one patch to add the UEC_ETH4?
> > diff -purN drivers/qe/uec.c.orig drivers/qe/uec.c
> --- drivers/qe/uec.c.orig Wed Jan 2 13:39:04 2008
> +++ drivers/qe/uec.c Thu Jan 3 17:23:17 2008
> @@ -29,6 +29,7 @@
> #include "uccf.h"
> #include "uec.h"
> #include "uec_phy.h"
> +#include "miiphy.h"
>
> #if defined(CONFIG_QE)
>
> @@ -40,8 +41,13 @@ static uec_info_t eth1_uec_info = {
> .tx_clock = CFG_UEC1_TX_CLK,
> .eth_type = CFG_UEC1_ETH_TYPE,
> },
> +#ifdef CFG_UEC1_NUM_TX_RX_THR
> + .num_threads_tx = CFG_UEC1_NUM_TX_RX_THR,
> + .num_threads_rx = CFG_UEC1_NUM_TX_RX_THR,
> +#else
> .num_threads_tx = UEC_NUM_OF_THREADS_4,
> .num_threads_rx = UEC_NUM_OF_THREADS_4,
> +#endif
I don't like so much CFG_ option for the driver, which cause too many
CFG_UEC[x]_NUM_TX_RX_THR in config.h. for every board.
and I think the threads number is not belonged to board specific things.
The u-boot don't need to consider the UEC performance.
The default 4 threads should work for you.
If it doesn't work for you, I suggest you keep the changes only for your
project.
I don't know if you can agree it.
> +#define MAXCONTROLLERS (4)
> +
> +static uec_private_t *privlist[MAXCONTROLLERS];
> +
> +static int uec_miiphy_read(char *devname, unsigned char addr,
> + unsigned char reg, unsigned short *value);
> +static int uec_miiphy_write(char *devname, unsigned char addr,
> + unsigned char reg, unsigned short value);
> +u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
> +void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
>
> static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
> {
> @@ -1238,11 +1306,21 @@ int uec_initialize(int index)
> #ifdef CONFIG_UEC_ETH2
> uec_info = ð2_uec_info;
> #endif
> + } else if (index == 2) {
> +#ifdef CONFIG_UEC_ETH3
> + uec_info = ð3_uec_info;
> +#endif
> + } else if (index == 3) {
> +#ifdef CONFIG_UEC_ETH4
> + uec_info = ð4_uec_info;
> +#endif
So, please repost the UEC_ETH4 support patch.
Big thanks,
Dave
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Re: [U-Boot-Users] [PATCH] QE: fix compile warning
In message <[EMAIL PROTECTED]> you wrote: > qe.c: In function 'qe_upload_firmware': > qe.c:390: warning: pointer targets in passing argument 2 > uec.c: In function 'uec_initialize': > uec.c:1236: warning: 'uec_info' may be used uninitialized > > Signed-off-by: Dave Liu <[EMAIL PROTECTED]> Applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED] After a time, you may find that "having" is not so pleasing a thing, after all, as "wanting." It is not logical, but it is often true. -- Spock, "Amok Time", stardate 3372.7 - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] Add support for MS7720RP02 board
On Mon, 03 Dec 2007 22:58:50 +0900 Yoshihiro Shimoda <[EMAIL PROTECTED]> wrote: > Add support for MS7720RP02 board. > > Signed-off-by: Yoshihiro Shimoda <[EMAIL PROTECTED]> > CC: Nobuhiro Iwamatsu <[EMAIL PROTECTED]> > --- > Makefile |8 > board/ms7720se/Makefile| 51 + > board/ms7720se/config.mk | 35 > board/ms7720se/lowlevel_init.S | 269 +++ > board/ms7720se/ms7720se.c | 61 +++ > board/ms7720se/u-boot.lds | 109 > include/configs/ms7720se.h | 134 +++ > 7 files changed, 667 insertions(+) Applied, thanks. -- Nobuhiro Iwamatsu GPG ID : 3170EBE9 - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] serial_sh: Add support for SH7720
On Mon, 03 Dec 2007 22:58:47 +0900 Yoshihiro Shimoda <[EMAIL PROTECTED]> wrote: > Add support for SH7720 in serial_sh driver. > > Signed-off-by: Yoshihiro Shimoda <[EMAIL PROTECTED]> > CC: Nobuhiro Iwamatsu <[EMAIL PROTECTED]> > --- > drivers/serial_sh.c | 26 -- > 1 file changed, 24 insertions(+), 2 deletions(-) Applied, thanks. -- Nobuhiro Iwamatsu [EMAIL PROTECTED] [EMAIL PROTECTED] GPG ID : 3170EBE9 - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] sh: Add support SH3 and SH7720
On Mon, 03 Dec 2007 22:58:45 +0900 Yoshihiro Shimoda <[EMAIL PROTECTED]> wrote: > Add support Renesas SH3 and SH7720. > > Signed-off-by: Yoshihiro Shimoda <[EMAIL PROTECTED]> > CC: Nobuhiro Iwamatsu <[EMAIL PROTECTED]> > --- > cpu/sh3/Makefile| 49 > cpu/sh3/cache.c | 112 ++ > cpu/sh3/config.mk | 31 + > cpu/sh3/cpu.c | 84 + > cpu/sh3/interrupts.c| 43 +++ > cpu/sh3/start.S | 78 > cpu/sh3/time.c | 103 > cpu/sh3/watchdog.c | 34 + > include/asm-sh/cpu_sh3.h| 40 ++ > include/asm-sh/cpu_sh7720.h | 207 ++ > 10 files changed, 781 insertions(+) Applied, thanks. -- Nobuhiro Iwamatsu [EMAIL PROTECTED] [EMAIL PROTECTED] GPG ID : 3170EBE9 - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [ppc4xx] Please pull git://www.denx.de/git/u-boot-ppc4xx.git
The following changes since commit f43ad53908f1ea83a7c26c3505bbe84382e47aad: Wolfgang Denk (1): ARM: update mach-types.h from 2.6.24-rc7 Linux kernel tree are available in the git repository at: git://www.denx.de/git/u-boot-ppc4xx.git master Stefan Roese (1): ppc4xx: Update Kilauea CPLD configuration with USB PHY reset bit board/amcc/kilauea/kilauea.c | 14 +++--- 1 files changed, 7 insertions(+), 7 deletions(-) - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 1/2] ppc4xx: Add DU440 board support
Hi Wolfgang, as you might have noticed the DU440 board is havily based on seuqoia code. Nearly all of your comments apply to that board as well. I thought of the sequoia code as exemplary reference code. And I prefer not to reformat comments when copy and pasting from one board to another. But if you really insist of these changes I will change the patch. On Sunday 13 January 2008 23:08, Wolfgang Denk wrote: > > Ummm... > > #include > ... > size_val = ffs(gd->bd->bi_flashsize) - 21; > > seems more straigtforward to me... > Good idea. Thanks. > > +#if 1 > > Please remove the '#if 1' as it's redundant. Ack. > > ... > > +#if 0 > > +/* > > + * test commands for SM722 2D acceleration > > + */ > ... > > +U_BOOT_CMD( > > + gfxline,CFG_MAXARGS,1, do_gfxline, > > + "gfxline - draw line\n", > > + "[color] [x1] [y1] [x2] [y2]\n" > > + ); > > +#endif > > Please remove the dead code. Please not. The DU440 board will get an updated smi_lynxem driver with support for the SM722 soon. My current hack is to dirty for submission and I just got some more register dumps from SM to support more videomodes. I will need this commented out code to test it. I plan to remove it later. > > > > diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S > > new file mode 100644 > > index 000..1e15e72 > > --- /dev/null > > +++ b/board/esd/du440/init.S > > @@ -0,0 +1,80 @@ > > +/* > > + * > > + * See file CREDITS for list of people who contributed to this > > + * project. > > + * > > + * This program is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU General Public License as > > + * published by the Free Software Foundation; either version 2 of > > + * the License, or (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program; if not, write to the Free Software > > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > > + * MA 02111-1307 USA > > + */ > > Copyright missing. > > You probably may want to adjust the (C) messages in some other files, > too. Ack. May I put my name on it? The source of this code has no copyright either. > > > diff --git a/board/esd/du440/u-boot.lds b/board/esd/du440/u-boot.lds > > new file mode 100644 > > index 000..a423f98 > > --- /dev/null > > +++ b/board/esd/du440/u-boot.lds > ... > > + __bss_start = .; > > + .bss : > > NOLOAD attribute missing. Please fix. This is new to me. But I just noticed that all other boards have been updated according to this. So will I. I will update my patches. Perhaps you can comment on my comments above. Matthias - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] resend #2 [PATCH 5/5]: add AcTux-4 board support
This patch adds the AcTux-4 specific files.
Signed-off-by: Michael Schwingen <[EMAIL PROTECTED]>
diff --git a/board/actux4/Makefile b/board/actux4/Makefile
new file mode 100644
index 000..b5f16bb
--- /dev/null
+++ b/board/actux4/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS := actux4.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/actux4/actux4.c b/board/actux4/actux4.c
new file mode 100644
index 000..1771e59
--- /dev/null
+++ b/board/actux4/actux4.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, [EMAIL PROTECTED]
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, [EMAIL PROTECTED]
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. [EMAIL PROTECTED]
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH
+ * Marius Groeger <[EMAIL PROTECTED]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+
+#include "actux4_hw.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_post_init (void)
+{
+ return (0);
+}
+
+int board_init (void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_ACTUX4;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x0100;
+
+ GPIO_OUTPUT_CLEAR (CFG_GPIO_nPWRON);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_nPWRON);
+
+ GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
+
+ /* led not populated on board*/
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_LED3);
+ GPIO_OUTPUT_SET (CFG_GPIO_LED3);
+
+ /* middle LED */
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_LED2);
+ GPIO_OUTPUT_SET (CFG_GPIO_LED2);
+
+ /* right LED */
+ /* weak pulldown = LED weak on */
+ GPIO_OUTPUT_DISABLE (CFG_GPIO_LED1);
+ GPIO_OUTPUT_SET (CFG_GPIO_LED1);
+
+ /* Setup GPIO's for Interrupt inputs */
+ GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTA);
+ GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTB);
+ GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTC);
+ GPIO_OUTPUT_DISABLE (CFG_GPIO_RTCINT);
+ GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI_INTA);
+ GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI_INTB);
+
+ GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTA);
+ GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTB);
+ GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTC);
+ GPIO_INT_ACT_LOW_SET (CFG_GPIO_RTCINT);
+ GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI_INTA);
+ GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI_INTB);
+
+ /* Setup GPIO's for 33MHz clock output */
+ *IXP425_GPIO_GPCLKR = 0x011001FF;
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_EXT
[U-Boot-Users] resend #2 [PATCH 4/5]: add AcTux-3 board support
This patch adds the AcTux-3 specific files.
Signed-off-by: Michael Schwingen <[EMAIL PROTECTED]>
diff --git a/board/actux3/Makefile b/board/actux3/Makefile
new file mode 100644
index 000..f7a6091
--- /dev/null
+++ b/board/actux3/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS := actux3.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c
new file mode 100644
index 000..54167a5
--- /dev/null
+++ b/board/actux3/actux3.c
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, [EMAIL PROTECTED]
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, [EMAIL PROTECTED]
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. [EMAIL PROTECTED]
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH
+ * Marius Groeger <[EMAIL PROTECTED]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "actux3_hw.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_post_init (void)
+{
+ return (0);
+}
+
+int board_init (void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_ACTUX3;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x0100;
+
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_LED5_GN);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_LED6_RT);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_LED6_GN);
+
+ GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
+ GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST);
+
+ GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR);
+ GPIO_OUTPUT_SET (CFG_GPIO_DCD);
+
+ GPIO_OUTPUT_CLEAR (CFG_GPIO_LED5_GN);
+ GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_RT);
+ GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_GN);
+
+ /*
+* Setup GPIO's for Interrupt inputs
+*/
+ GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT);
+ GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT);
+
+ /*
+* Setup GPIO's for 33MHz clock output
+*/
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
+ *IXP425_GPIO_GPCLKR = 0x011001FF;
+
+ /* CS1: IPAC-X */
+ *IXP425_EXP_CS1 = 0x94d10013;
+ /* CS5: Debug port */
+ *IXP425_EXP_CS5 = 0x9d520003;
+ /* CS6: Release/Option register */
+ *IXP425_EXP_CS6 = 0x81860001;
+ /* CS7: LEDs */
+ *IXP425_EXP_CS7 = 0x8093;
+
+ udelay (533);
+ GPIO_OUTPUT_SET (
Re: [U-Boot-Users] CUSTODIANS: List of open issues / not applied patches
Haavard Skinnemoen wrote: > Hmm...I guess my compile tests didn't hit the CONFIG_CFI_FLASH_LEGACY > case. Are there any boards that are actually using this in mainline? > Not yet. AcTux-4 will be, as soon as it is fit for inclusion. cu Michael - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] resend #2 [PATCH 1/5]: add AcTux board support (common)
Hi, 2nd resend of the previous patch set with formatting fixed (hopefully). The patch adds 4 boards, called AcTux-1 .. AcTux-4. This patch contains the files that contain changes for multiple boards, the board-specific files follow as separate patches. I have kept the small version of the mach-types.h patch to fir the list size limit - the full version of the patch, with mach-types.h generated from the current ARM machine database, is at: http://www.schwingen.org/actux.diff cu Michael Signed-off-by: Michael Schwingen <[EMAIL PROTECTED]> diff --git a/MAINTAINERS b/MAINTAINERS index 2ef2f5c..9291f48 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -536,6 +536,13 @@ Alex Züpke <[EMAIL PROTECTED]> lartSA1100 dnp1110 SA1110 +Michael Schwingen <[EMAIL PROTECTED]> + + actux1 xscale + actux2 xscale + actux3 xscale + actux4 xscale + # # x86 Systems: # # # diff --git a/MAKEALL b/MAKEALL index ebc5a22..a058869 100755 --- a/MAKEALL +++ b/MAKEALL @@ -512,6 +512,10 @@ LIST_pxa=" \ " LIST_ixp=" \ + actux1 \ + actux2 \ + actux3 \ + actux4 \ ixdp425 \ ixdpg425\ pdnb3 \ diff --git a/Makefile b/Makefile index 1983ca0..9a4d5c9 100644 --- a/Makefile +++ b/Makefile @@ -2406,6 +2406,18 @@ SMN42_config : unconfig ## XScale Systems # +actux1_config : unconfig + @$(MKCONFIG) $(@:_config=) arm ixp actux1 + +actux2_config : unconfig + @$(MKCONFIG) $(@:_config=) arm ixp actux2 + +actux3_config : unconfig + @$(MKCONFIG) $(@:_config=) arm ixp actux3 + +actux4_config : unconfig + @$(MKCONFIG) $(@:_config=) arm ixp actux4 + adsvix_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa adsvix diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index ab19047..01bfecb 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -742,6 +742,10 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_AT91SAM9260EK 1099 #define MACH_TYPE_AT91RM9200DF1119 #define MACH_TYPE_AT91SAM9263EK 1202 +#define MACH_TYPE_ACTUX1 1479 +#define MACH_TYPE_ACTUX2 1480 +#define MACH_TYPE_ACTUX3 1481 +#define MACH_TYPE_ACTUX4 1532 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] resend #2 [PATCH 2/5]: add AcTux-1 board support
This patch adds the AcTux-1 specific files.
Signed-off-by: Michael Schwingen <[EMAIL PROTECTED]>
diff --git a/board/actux1/Makefile b/board/actux1/Makefile
new file mode 100644
index 000..a7e8322
--- /dev/null
+++ b/board/actux1/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS := actux1.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c
new file mode 100644
index 000..0ac9e41
--- /dev/null
+++ b/board/actux1/actux1.c
@@ -0,0 +1,169 @@
+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, [EMAIL PROTECTED]
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, [EMAIL PROTECTED]
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. [EMAIL PROTECTED]
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH
+ * Marius Groeger <[EMAIL PROTECTED]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "actux1_hw.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_post_init (void)
+{
+ return (0);
+}
+
+int board_init (void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_ACTUX1;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x0100;
+
+ GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
+
+ /* Setup GPIO's for PCI INTA */
+ GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI1_INTA);
+ GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI1_INTA);
+
+ /* Setup GPIO's for 33MHz clock output */
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
+ *IXP425_GPIO_GPCLKR = 0x011001FF;
+
+ /* CS5: Debug port */
+ *IXP425_EXP_CS5 = 0x9d520003;
+ /* CS6: HwRel */
+ *IXP425_EXP_CS6 = 0x81860001;
+ /* CS7: LEDs */
+ *IXP425_EXP_CS7 = 0x8093;
+
+ udelay (533);
+ GPIO_OUTPUT_SET (CFG_GPIO_IORST);
+
+ ACTUX1_LED1 (2);
+ ACTUX1_LED2 (2);
+ ACTUX1_LED3 (0);
+ ACTUX1_LED4 (0);
+ ACTUX1_LED5 (0);
+ ACTUX1_LED6 (0);
+ ACTUX1_LED7 (0);
+
+ ACTUX1_HS (ACTUX1_HS_DCD);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard (void)
+{
+ char revision;
+ char *s = getenv ("serial#");
+
+ puts ("Board: AcTux-1 rev.");
+ putc (ACTUX1_BOARDREL + 'A' - 1);
+
+ if (s != NULL) {
+ puts (", serial# ");
+ puts (s);
+ }
+ putc ('\n');
+
+ return (0);
+}
+
+/*
+ * get_board_rev() - setup to pass kernel board revision information
+ * 0 = reserved
+ * 1 = Rev. A
+ * 2 = Rev. B
+ *
[U-Boot-Users] resend #2 [PATCH 3/5]: add AcTux-2 board support
This patch adds the AcTux-2 specific files.
Signed-off-by: Michael Schwingen <[EMAIL PROTECTED]>
diff --git a/board/actux2/Makefile b/board/actux2/Makefile
new file mode 100644
index 000..1ff9785
--- /dev/null
+++ b/board/actux2/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS := actux2.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c
new file mode 100644
index 000..1b7a72e
--- /dev/null
+++ b/board/actux2/actux2.c
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, [EMAIL PROTECTED]
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, [EMAIL PROTECTED]
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. [EMAIL PROTECTED]
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH
+ * Marius Groeger <[EMAIL PROTECTED]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "actux2_hw.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_post_init (void)
+{
+ return (0);
+}
+
+int board_init (void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_ACTUX2;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x0100;
+
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD);
+
+ GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
+ GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST);
+
+ GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR);
+ GPIO_OUTPUT_SET (CFG_GPIO_DCD);
+
+ /* Setup GPIO's for Interrupt inputs */
+ GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT);
+ GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT);
+
+ /* Setup GPIO's for 33MHz clock output */
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
+ GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
+ *IXP425_GPIO_GPCLKR = 0x011001FF;
+
+ /* CS1: IPAC-X */
+ *IXP425_EXP_CS1 = 0x94d10013;
+ /* CS5: Debug port */
+ *IXP425_EXP_CS5 = 0x9d520003;
+ /* CS6: HW release register */
+ *IXP425_EXP_CS6 = 0x81860001;
+ /* CS7: LEDs */
+ *IXP425_EXP_CS7 = 0x8093;
+
+ udelay (533);
+ GPIO_OUTPUT_SET (CFG_GPIO_IORST);
+ GPIO_OUTPUT_SET (CFG_GPIO_ETHRST);
+
+ ACTUX2_LED1 (1);
+ ACTUX2_LED2 (0);
+ ACTUX2_LED3 (0);
+ ACTUX2_LED4 (0);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard (void)
+{
+ char revision;
+ char *s = getenv ("serial#");
+
+ puts ("
Re: [U-Boot-Users] CUSTODIANS: List of open issues / not applied patches
On Fri, 11 Jan 2008 22:06:30 +0100 [EMAIL PROTECTED] (Michael Schwingen) wrote: > Not sure about the source of the problem, but the > CONFIG_CFI_FLASH_LEGACY support seems to be broken - the code for > flash_read_jedec_ids_intel and flash_read_jedec_ids_amd which are > called in cfi_flash.c seems to be missing. I do not see any > missing/outstanding patches that seem relevant to this problem. Hmm...I guess my compile tests didn't hit the CONFIG_CFI_FLASH_LEGACY case. Are there any boards that are actually using this in mainline? Thanks for fixing it. Haavard - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] problems with CRC in fw_printenv and fw_setenv utility and use
u-boot user <[EMAIL PROTECTED]> writes: > I have built the binary fw_printenv by using mtd-user.h from mtd-utils on > the internet as it fw_printenv won't compile it without using that > file. So So you're obviously not using the newest version of U-Boot, what you should. Make sure to read the updated README in tools/env/. > I have used mtd-user.h and mtd-abi.h. The contents of my configuration file > are > # MTD device name Device offset Env. size Flash sector size > /dev/mtd1 0x 0x4000 0x4000 Is this in /etc/ ? > When I run fw_printenv it complained with error Warning : Bad CRC using > default environment in env_init function in fw_env.c source code. To gain a > better understanding I print the value crc1 calculated using > crc32(0,environment.data,ENV_SIZE). The value it prints is CRC > computed:FE641197 > If I print the environment.crc value it is D0CA8A0E. As the checksum values > are different crc1_ok is not set and I get the error. Any clue as to why > these values would be different? Probably some mismatch between the information in your config file and the real environment. Where is you're environment located in flash? Is your mtd partitioning right? What does $ cat /proc/mtd show? > When I use the fw_setenv utility to set an environment variable it gives the > following errors > Writing CRC value to flash: D0C78567 > Unlocking flash... > Other dev values are: 0 > Current dev value: 0 > Done > Erasing old environment... > MTD erase error on /dev/mtd1: Invalid argument > Error: can't write fw_env to flash Weird. I would guess your MTD partitioning is wrong. Best regards Markus Klotzbuecher -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED] - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
