Re: [U-Boot-Users] Problems with PCI-E Switch on 460EX

2008-10-15 Thread Stefan Roese
On Tuesday 14 October 2008, Ayman M. El-Khashab wrote:
 I hope somebody can shed some light on our problem.  The summary is
 that when we use a pci-e switch, we don't see anything on the downstream
 side of the switch in Linux.  U-Boot may or may not see the downstream
 side (details below).

 We are using the stock canyonlands (460EX) board with both original and
 new kernels.  We have the 1L port as an end-point and the 4L as a RC.
 We've purchased a PLX 8509 PCI-E Switch and PLX 8612 PCI-E Switch add-in
 cards.  Each of them fits into the 4 lane port.

So you are using the PCIe slot 1? I'm asking since slot 0 is known to have 
problems with some boards.

 We also have another 
 COTS pci-e sata controller (our control if you will).

 sata card to the canyonlands, everything works correctly.  This tells
 me that pci-e, discovery, etc are configured / working.

 sata to the 8509 and the 8509 to the canyonlands, u-boot will detect
 the sata card, but for whatever reason, Linux does not see it
 (via lspci or our own tool).

This is a Linux specific problem then. I suggest that you post this specific 
problem to linuxppc-dev.

BTW: Do you happen to have another non-406EX AMCC eval board with PCIe? 
Kilauea? Or Katmai? I know from another customer that using PCIe-switches on 
405EX works.

 sata to the 8612 and the 8612 to the canyonlands, u-boot does not see
 the card (and obviously linux does not see the card either).

 One more data point, we have an NI PCI-E GPIB controller.  It has a
 pci-e to pci bridge on board.  U-Boot sees the bridge, but again nothing
 on the downstream port.

Did you try to tune the pciscandelay environment variable? Setting 
pciscandelay to n will delay the PCI device scan by n seconds. Some 
endpoints seem to have problems with too early configuration, IIRC.

 We have looked at all of these cases using a lecroy pci-e analyzer.  In
 most cases the u-boot code looks to be doing the right thing.  The 8612
 being the only odd case.  We did notice the pci-e bus number change on
 the analyzer from 3 to (I think 129) -- I still cannot explain this.

Strange.

 1) Do I have to add anything to the device tree for the switch (I did
 not believe that it was required)

No.

 2) Since it appears no switch/bridge downstream device is visible, is
 something needed in Linux to make these go?  I checked both the u-boot
 and kernel config and saw nothing obvious other than enabling pci-e

No. I think this could be a timing issue. Or even a Canyonlands specific PCIe 
controller setup problem.

 3) Does u-boot require any special configuration to enable all these
 pci-e devices

No. But again its probably necessary to set pciscandelay.

 4) Anything else to try?

A good test would be with a different AMCC PCIe equipped board as mentioned 
above.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] cfi_flash: do not reset flash when probe fails

2008-10-04 Thread Stefan Roese
On Thursday 02 October 2008, Mike Frysinger wrote:
 The CFI flash driver starts at flash_init() which calls down into
 flash_get_size().  This starts by calling flash_detect_cfi().  If said
 function fails, flash_get_size() finishes by attempting to reset the
 flash.  Unfortunately, it does this with an info-portwidth set to 0x10
 which filters down into flash_make_cmd() and that happily smashes the
 stack by sticking info-portwidth bytes into a cfiword_t variable that
 lives on the stack.  On a 64bit system you probably won't notice, but
 killing the last 8 bytes on a 32bit system usually leads to a corrupt
 return address.  Which is what happens on a Blackfin system.

Applied to u-boot-cfi-flash repository. Thanks.

Best regards,
Stefan

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[U-Boot-Users] [cfi-flash] Please pull git://www.denx.de/git/u-boot-cfi-flash.git

2008-10-02 Thread Stefan Roese
The following changes since commit 8fd4166c467a46773f80208bda1ec3b4757747bc:
  Stefan Roese (1):
ppc4xx: Canyonlands: Remove unnecessary FDT warning upon DTB fixup

are available in the git repository at:

  git://www.denx.de/git/u-boot-cfi-flash.git master

Mike Frysinger (1):
  cfi_flash: do not reset flash when probe fails

 drivers/mtd/cfi_flash.c |3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

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Re: [U-Boot-Users] [PATCH] Add CFI_CMDSET_INTEL_EXTENDED to fix flash_real_protect()

2008-08-20 Thread Stefan Roese
On Wednesday 20 August 2008, Nick Spence wrote:
 This patch fixes a missing vendor code in the flash_real_protect()
 function.

Applied to u-boot-cfi-flash. Thanks.

Best regards,
Stefan

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[U-Boot-Users] [PATCH] hush: Fix printf debug macro in hush.c so that it usable in U-Boot

2008-08-19 Thread Stefan Roese
This patch changes the debug_printf() marco for U-Boot in hush.c and
moves the definition of DEBUG_SHELL to a place that is actually compiled
under U-Boot.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 common/hush.c |8 ++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/common/hush.c b/common/hush.c
index 75c18ce..a104a0d 100644
--- a/common/hush.c
+++ b/common/hush.c
@@ -115,7 +115,6 @@ extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, 
char *argv[]);  /
 #include signal.h
 
 /* #include dmalloc.h */
-/* #define DEBUG_SHELL */
 
 #if 1
 #include busybox.h
@@ -360,6 +359,11 @@ struct built_in_command {
 };
 #endif
 
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG_SHELL
+#endif
+
 /* This should be in utility.c */
 #ifdef DEBUG_SHELL
 #ifndef __U_BOOT__
@@ -371,7 +375,7 @@ static void debug_printf(const char *format, ...)
va_end(args);
 }
 #else
-#define debug_printf printf /* U-Boot debug flag */
+#define debug_printf(fmt,args...)  printf (fmt ,##args)
 #endif
 #else
 static inline void debug_printf(const char *format, ...) { }
-- 
1.5.6.5


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Re: [U-Boot-Users] [PATCH] hush: Fix printf debug macro in hush.c so that it usable in U-Boot

2008-08-19 Thread Stefan Roese
Hi Wolfgang,

On Tuesday 19 August 2008, Wolfgang Denk wrote:
  This patch changes the debug_printf() marco for U-Boot in hush.c and
  moves the definition of DEBUG_SHELL to a place that is actually compiled
  under U-Boot.

 ...

  +/* define DEBUG for debugging output (obviously ;-)) */
  +#if 0
  +#define DEBUG_SHELL
  +#endif

 So what do we have to #define - DEBUG or DEBUG_SHELL ?

DEBUG_SHELL! Sorry, I missed updating the comment. Will send an updated patch 
soon.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] Sequoia has two UARTs in 4-pin mode. Configure the GPIOs as per schematic.

2008-08-07 Thread Stefan Roese
On Wednesday 06 August 2008, Steven A. Falco wrote:
 The Sequoia board has two UARTs in 4-pin mode.  This patch modifies the
 GPIO configuration to match the schematic, and also sets the sdr0_pfc1
 register to select the corresponding mode for the UARTs.

  board/amcc/sequoia/sequoia.c |5 +
  include/configs/sequoia.h|   12 ++--
  2 files changed, 11 insertions(+), 6 deletions(-)

 Signed-off-by: Steven A. Falco [EMAIL PROTECTED]

Applied to u-boot-ppc4xx repository. Thanks.

Note that your s-o-b line should be *above* the patch statistics. Did you 
generate this patch using git-format-patch?

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] PPC4xx: Memory Queue Optimizations for PPC460EX/GT

2008-08-07 Thread Stefan Roese
On Thursday 07 August 2008, Prodyut Hazarika wrote:
 Set PL44 Arbiter Read pipeline depth to 4
 Optimize Memory Queue Configuration registers for PPC460EX/GT

 Signed-off-by: Prodyut Hazarika [EMAIL PROTECTED]

Thanks. Please find some comments below.

 ---
  board/amcc/canyonlands/canyonlands.c |9 +++
  cpu/ppc4xx/44x_spd_ddr2.c|4 +
  include/ppc440.h |  101
 ++ 3 files changed, 66 insertions(+), 48
 deletions(-)

 diff --git a/board/amcc/canyonlands/canyonlands.c
 b/board/amcc/canyonlands/canyonlands.c index e9eba49..dd285bc 100644
 --- a/board/amcc/canyonlands/canyonlands.c
 +++ b/board/amcc/canyonlands/canyonlands.c
 @@ -113,6 +113,15 @@ int board_early_init_f(void)
   mtdcr(AHB_TOP, 0x804B);
   mtdcr(AHB_BOT, 0x804B);

 + mtdcr(plb0_acr, plb0_acr_ppm_fair|
 + plb0_acr_hbu_enabled |
 + plb0_acr_rdp_4deep   |
 + plb0_acr_wrp_2deep);
 + mtdcr(plb1_acr, plb1_acr_ppm_fair|
 + plb1_acr_hbu_enabled |
 + plb1_acr_rdp_4deep   |
 + plb1_acr_wrp_2deep);
 +

Is this PLB0_ACR tuning Canyonlands specific? Or will all 460EX/GT boards 
profit from this configuration? Or even other 4xx PPC variants as well?

If this is the case then I suggest to move this code to a common place, 
perhaps in cpu_init_f(). What do you think?

   if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
   /*
* Configure USB-STP pins as alternate and not GPIO
 diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
 index e9940e8..c222507 100644
 --- a/cpu/ppc4xx/44x_spd_ddr2.c
 +++ b/cpu/ppc4xx/44x_spd_ddr2.c
 @@ -2251,6 +2251,10 @@ static void program_memory_queue(unsigned long
 *dimm_populated, */
   mtdcr(SDRAM_PLBADDULL, 0x); /* MQ0_BAUL */
   mtdcr(SDRAM_PLBADDUHB, 0x0008); /* MQ0_BAUH */
 +
 + mtdcr(SDRAM_CONF1HB, 0x80001c80);
 + mtdcr(SDRAM_CONF1LL, 0x80001c80);
 + mtdcr(SDRAM_CONFPATHB, 0x18a68000);

Could you please add a comment what exactly is configured with these magic 
numbers?

  #endif
  }

 diff --git a/include/ppc440.h b/include/ppc440.h
 index c581f1b..650ee4f 100644
 --- a/include/ppc440.h
 +++ b/include/ppc440.h
 @@ -422,53 +422,6 @@

  #define PLB4_ACR_WRP (0x8000  7)

 -/* Nebula PLB4 Arbiter - PowerPC440EP */
 -#define PLB_ARBITER_BASE   0x80
 -
 -#define plb0_revid(PLB_ARBITER_BASE+ 0x00)
 -#define plb0_acr  (PLB_ARBITER_BASE+ 0x01)
 -#define   plb0_acr_ppm_mask 0xF000
 -#define   plb0_acr_ppm_fixed0x
 -#define   plb0_acr_ppm_fair 0xD000
 -#define   plb0_acr_hbu_mask 0x0800
 -#define   plb0_acr_hbu_disabled 0x
 -#define   plb0_acr_hbu_enabled  0x0800
 -#define   plb0_acr_rdp_mask 0x0600
 -#define   plb0_acr_rdp_disabled 0x
 -#define   plb0_acr_rdp_2deep0x0200
 -#define   plb0_acr_rdp_3deep0x0400
 -#define   plb0_acr_rdp_4deep0x0600
 -#define   plb0_acr_wrp_mask 0x0100
 -#define   plb0_acr_wrp_disabled 0x
 -#define   plb0_acr_wrp_2deep0x0100
 -
 -#define plb0_besrl(PLB_ARBITER_BASE+ 0x02)
 -#define plb0_besrh(PLB_ARBITER_BASE+ 0x03)
 -#define plb0_bearl(PLB_ARBITER_BASE+ 0x04)
 -#define plb0_bearh(PLB_ARBITER_BASE+ 0x05)
 -#define plb0_ccr  (PLB_ARBITER_BASE+ 0x08)
 -
 -#define plb1_acr  (PLB_ARBITER_BASE+ 0x09)
 -#define   plb1_acr_ppm_mask 0xF000
 -#define   plb1_acr_ppm_fixed0x
 -#define   plb1_acr_ppm_fair 0xD000
 -#define   plb1_acr_hbu_mask 0x0800
 -#define   plb1_acr_hbu_disabled 0x
 -#define   plb1_acr_hbu_enabled  0x0800
 -#define   plb1_acr_rdp_mask 0x0600
 -#define   plb1_acr_rdp_disabled 0x
 -#define   plb1_acr_rdp_2deep0x0200
 -#define   plb1_acr_rdp_3deep0x0400
 -#define   plb1_acr_rdp_4deep0x0600
 -#define   plb1_acr_wrp_mask 0x0100
 -#define   plb1_acr_wrp_disabled 0x
 -#define   plb1_acr_wrp_2deep0x0100
 -
 -#define plb1_besrl(PLB_ARBITER_BASE+ 0x0A)
 -#define plb1_besrh(PLB_ARBITER_BASE+ 0x0B)
 -#define plb1_bearl(PLB_ARBITER_BASE+ 0x0C)
 -#define plb1_bearh(PLB_ARBITER_BASE+ 0x0D)
 -
  /* Pin Function Control Register 1 */
  #define SDR0_PFC10x4101
  #define   SDR0_PFC1_U1ME_MASK 0x0200/* UART1 Mode Enable
 */ @@ -742,7 +695,59 @@
  #define   SDR0_PFC1_PLB_PME_PLB4_SEL  0x1000  /* PLB3 Performance
 Monitor Enable */ 

Re: [U-Boot-Users] [PATCH] sequoia uarts

2008-08-06 Thread Stefan Roese
On Friday 01 August 2008, Wolfgang Denk wrote:
 In message [EMAIL PROTECTED] you wrote:
  I have verified that the Sequoia (440EPx) does not have its UARTs
  properly configured.  The attached patch corrects this by setting three
  bits in SDR0_PFC1 to enable 4-wire mode, and to select cts/rts
  functionality for the UARTs.  Also, I modified the GPIO settings for

 We definitely do NOT want any hardware handshake on the serial
 console. Never.

Ack, we don't want hardware handshake enabled in U-Boot. But if I understand 
this correctly, then this patch from Steven configures the RTS/CTS lines 
correctly (they are multiplexed with other signals), so that they *can* be 
used by the OS if needed. It doesn't enable hardware handshake in U-Boot.

Steven please correct me if I am wrong here.

Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH 1/7 v5] Add definition for the AM29LV800BB AMD NOR-flash

2008-08-06 Thread Stefan Roese
On Tuesday 05 August 2008, Guennadi Liakhovetski wrote:
 Signed-off-by: Guennadi Liakhovetski [EMAIL PROTECTED]

Applied to next brach of u-boot-cfi-flash repository.

Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] sequoia uarts

2008-08-06 Thread Stefan Roese
On Wednesday 06 August 2008, Steven A. Falco wrote:
  Ack, we don't want hardware handshake enabled in U-Boot. But if I
  understand this correctly, then this patch from Steven configures the
  RTS/CTS lines correctly (they are multiplexed with other signals), so
  that they *can* be used by the OS if needed. It doesn't enable hardware
  handshake in U-Boot.
 
  Steven please correct me if I am wrong here.

 You are correct.  The patch simply configures the lines to match the
 schematic - it does not activate hardware handshake within U-Boot.

Could you please send a git formatted patch (git-format-patch and 
git-send-email are your friends here :)) with a patch description and a 
signed-off-by line? This makes it easier for me to apply this patch.

Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] ppc4xx: ML507: U-Boot in flash and System ACE

2008-07-30 Thread Stefan Roese
On Monday 21 July 2008, Ricardo Ribalda Delgado wrote:
 This patch allows booting from FLASH the ML507 board
  by Xilinx.

 Previously, u-boot needed to be loaded from JTAG or a Sytem ACE
  CF

 Signed-off-by: Ricardo Ribalda Delgado [EMAIL PROTECTED]

Applied to next branch of u-boot-ppc4xx repository.

Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] ppc4xx: ML507: Environment in flash and MTD Support

2008-07-30 Thread Stefan Roese
On Wednesday 23 July 2008, Ricardo Ribalda Delgado wrote:
 -Relocate the location of u-boot in the flash
 -Save the environment in one sector of the flash memory
 -MTD Support

 Signed-off-by: Ricardo Ribalda Delgado [EMAIL PROTECTED]
 ---
  Makefile |2 +-
  board/xilinx/ml507/xparameters.h |2 +-
  common/cmd_load.c|2 +-

This must have slipped in here.

  include/configs/ml507.h  |   15 +++
  4 files changed, 14 insertions(+), 7 deletions(-)

NAK. Please remove this cmd_load.c change and resubmit.

Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] ppc4xx: ml507: Use of get_ram_size in board ml507

2008-07-30 Thread Stefan Roese
On Tuesday 29 July 2008, Ricardo Ribalda Delgado wrote:
 -Change suggested by WD

 Signed-off-by: Ricardo Ribalda Delgado [EMAIL PROTECTED]

Applied to next branch of u-boot-ppc4xx repository.

Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] bdinfo not showing correct info about memory size

2008-07-30 Thread Stefan Roese
Ricardo,

On Wednesday 30 July 2008, Ricardo Ribalda Delgado wrote:
   I don't think that it is a problem with my board config, otherwhise
 it won't show the correct size using print_num...
Maybe other users didn't have any problems because their memory
 size is smaller than 256MB.

Most likely you need to enable 64bit printf format (%ll) support:

#define CFG_64BIT_VSPRINTF
#define CFG_64BIT_STRTOUL

This is already done for all 440 PPC's (include/ppc4xx.h) in the current git 
head. I'll merge this soon into the next branch of my ppc4xx repository, then 
your problem should go away.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] bdinfo not showing correct info about memory size

2008-07-30 Thread Stefan Roese
On Wednesday 30 July 2008, Wolfgang Denk wrote:
 = bdi
 memstart= 0x
 memsize = 0x1
 ...

 As you can see, this board has 4 GB of RAM and everything works  just
 fine.

Yes. But unfortunately not for all boards. As it seems the patch 
b57ca3e128cc10a133ba79bc7ec3e7b50e7c8fbe [Change bd/gd memsize/ram_size to be 
phys_size_t.] introduced %llX unconditionally for all non-ARM boards. And 
many boards don't have support for 64bit printf formats enabled.

So what to do? Enable 64bit format on all boards? Or make this size printing 
conditionally somehow?

Best regards,
Stefan

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[U-Boot-Users] [PATCH 1/2] net/ppc4xx: Rework 4xx non NET_MULTI MII init code

2008-07-30 Thread Stefan Roese
This patch simplifies the 4xx MII PHY init code by introducing the define
CONFIG_PPC4xx_EMAC for EMAC enabled SoC's.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
This is post 1.3.4 material.

Ben, could you please queue this up and push it in the next merge
window? If nobody objects of course.

 net/eth.c |3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/net/eth.c b/net/eth.c
index 38979aa..77a8500 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -620,8 +620,7 @@ int eth_initialize(bd_t *bis)
 #if defined(CONFIG_AT91RM9200)
at91rm9200_miiphy_initialize(bis);
 #endif
-#if defined(CONFIG_4xx)  !defined(CONFIG_IOP480) \
-!defined(CONFIG_AP1000)  !defined(CONFIG_405)
+#if defined(CONFIG_PPC4xx_EMAC)
emac4xx_miiphy_initialize(bis);
 #endif
 #if defined(CONFIG_MCF52x2)
-- 
1.5.6.4


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[U-Boot-Users] [PATCH 2/2] net/ppc4xx: Rework 4xx non NET_MULTI MII init code

2008-07-30 Thread Stefan Roese
This patch simplifies the 4xx MII PHY init code by introducing the define
CONFIG_PPC4xx_EMAC for EMAC enabled SoC's.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
This is post 1.3.4 material.

 cpu/ppc4xx/4xx_enet.c |7 ++-
 include/ppc4xx.h  |8 
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 8a38335..62a3be8 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -1969,12 +1969,9 @@ int eth_rx(void)
return (ppc_4xx_eth_rx(emac0_dev));
 }
 
-int emac4xx_miiphy_initialize (bd_t * bis)
+int emac4xx_miiphy_initialize(bd_t * bis)
 {
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-   miiphy_register (ppc_4xx_eth0,
-emac4xx_miiphy_read, emac4xx_miiphy_write);
-#endif
+   miiphy_register(ppc_4xx_eth0, emac4xx_miiphy_read, 
emac4xx_miiphy_write);
 
return 0;
 }
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 5a6b855..732f4dd 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -46,6 +46,14 @@
 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2   /* IBM DDR(2) controller */
 #endif
 
+/*
+ * Configure if SoC is equipped with one or multiple EMAC's
+ */
+#if !defined(CONFIG_405)  !defined(CONFIG_405CR)  \
+!defined(CONFIG_IOP480)  !defined(CONFIG_XILINX_440)
+#define CONFIG_PPC4xx_EMAC
+#endif
+
 #if defined(CONFIG_440)
 #include ppc440.h
 #else
-- 
1.5.6.4


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Re: [U-Boot-Users] [PATCH] bdinfo not showing correct info about memory size

2008-07-30 Thread Stefan Roese
On Wednesday 30 July 2008, Wolfgang Denk wrote:
  Most likely you need to enable 64bit printf format (%ll) support:
 
  #define CFG_64BIT_VSPRINTF
  #define CFG_64BIT_STRTOUL
 
  This is already done for all 440 PPC's (include/ppc4xx.h) in the current
  git head. I'll merge this soon into the next branch of my ppc4xx
  repository, then your problem should go away.

 Given the fact that print_lnum() unconditionally takes a u64 arg  and
 unconditionally  uses  a  %llX  format,  I  thinkwe shoudl either fix
 print_lnum() for non-64bit cases, or drop  the  CFG_64BIT_VSPRINTF  /
 CFG_64BIT_STRTOUL options completely.

Personally, I'm voting for dropping the options completely and enabling the 
64bit support unconditionally. I took me some time a few days ago to figure 
out that this support was *not* enabled by default.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] (Re-re-submited) Ad ded support to flash_real_protect for Atmel f lash devices (tested with AT49BV6416)

2008-07-30 Thread Stefan Roese
Rafael,

On Wednesday 30 July 2008, Rafael Campos wrote:
 Some of the flash memories produced by ATMEL start in read-only mode. We
 need to unprotect it.
 This patch allows the AT49BV6416 to work with cfi_flash memories. Tested
 in the at91rm9200ek board.

Thanks. I finally find the time to review this patch. Sorry for the delay. But 
as Wolfgang already mentioned, resending the same patch over and over again 
is not the best way to handle things. Please find some nitpicking comments 
below.

 Signed-off-by: Rafael Campos Las Heras [EMAIL PROTECTED]
 ---
  drivers/mtd/cfi_flash.c |   40 ++--
  1 files changed, 34 insertions(+), 6 deletions(-)

 diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
 index 4340b1b..8d12eb8 100644
 --- a/drivers/mtd/cfi_flash.c
 +++ b/drivers/mtd/cfi_flash.c
 @@ -103,6 +103,10 @@
  #define AMD_STATUS_TOGGLE0x40
  #define AMD_STATUS_ERROR 0x20

 +#define ATM_CMD_UNLOCK_SECT  0x70
 +#define ATM_CMD_SOFTLOCK_START   0x80
 +#define ATM_CMD_LOCK_SECT0x40
 +
  #define FLASH_OFFSET_MANUFACTURER_ID 0x00
  #define FLASH_OFFSET_DEVICE_ID   0x01
  #define FLASH_OFFSET_DEVICE_ID2  0x0E
 @@ -1348,12 +1352,36 @@ int flash_real_protect (flash_info_t * info, long
 sector, int prot) {
   int retcode = 0;

 - flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
 - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
 - if (prot)
 - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
 - else
 - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
 + switch (info-vendor) {
 + case CFI_CMDSET_INTEL_PROG_REGIONS:
 + case CFI_CMDSET_INTEL_STANDARD:
 + flash_write_cmd (info, sector, 0, 
 FLASH_CMD_CLEAR_STATUS);
 + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
 + if (prot)
 + flash_write_cmd (info, sector, 0, 
 FLASH_CMD_PROTECT_SET);
 + else
 + flash_write_cmd (info, sector, 0, 
 FLASH_CMD_PROTECT_CLEAR);
 + break;
 + case CFI_CMDSET_AMD_EXTENDED:
 + case CFI_CMDSET_AMD_STANDARD:
 +#ifdef CONFIG_FLASH_CFI_LEGACY
 + case CFI_CMDSET_AMD_LEGACY:
 +#endif
 + /* U-Boot only checks the first byte */
 + if (info-manufacturer_id == (uchar)ATM_MANUFACT ) {

Drop the space before ')'.

 + if (prot) {
 + flash_unlock_seq(info, 0);
 + flash_write_cmd (info, 0, info-addr_unlock1, 
 ATM_CMD_SOFTLOCK_START);

This line gets pretty long. Please wrap this (and others) line that exceed the 
80 chars.

 + flash_unlock_seq(info, 0);
 + flash_write_cmd (info, sector, 0, 
 ATM_CMD_LOCK_SECT);

Decide for one coding style: func () or func(). As this file used the func () 
version, please use it all the time.

 + } else {
 + flash_write_cmd (info, 0, info-addr_unlock1, 
 AMD_CMD_UNLOCK_START);
 + if (info-device_id == ATM_ID_BV6416)
 + flash_write_cmd (info, sector, 0, 
 ATM_CMD_UNLOCK_SECT);
 + }
 + }
 + break;
 + }

   if ((retcode =
flash_full_status_check (info, sector, info-erase_blk_tout,

BTW: Did you test this patch with other FLASH chips too (Intel, Spansion ...)? 
Or only the Atmel one?

And please CC me directly on CFI related patches.

Thanks.

Best regards,
Stefan

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[U-Boot-Users] [PATCH] ppc4xx: Enable 64bit printf format on 440/460 platforms

2008-07-18 Thread Stefan Roese
This patch defines CFG_64BIT_VSPRINTF and CFG_64BIT_STRTOUL for all
440/460 platforms. This may be needed since those platforms support
36bit physical address space.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 include/ppc4xx.h |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 0a8479f..1d06da8 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -46,6 +46,12 @@
 #endif
 
 #if defined(CONFIG_440)
+/*
+ * Enable long long (%ll ...) printf format on 440 PPC's since most of
+ * them support 36bit physical addressing
+ */
+#define CFG_64BIT_VSPRINTF
+#define CFG_64BIT_STRTOUL
 #include ppc440.h
 #else
 #include ppc405.h
-- 
1.5.6.3


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[U-Boot-Users] [PATCH] ide: Use CFG_64BIT_LBA instead of CFG_64BIT_STRTOUL

2008-07-18 Thread Stefan Roese
This is needed for boards that define CFG_64BIT_STRTOUL but don't define
CFG_64BIT_LBA.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 common/cmd_ide.c |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index 97a873d..56db433 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -298,7 +298,7 @@ int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char 
*argv[])
ulong addr = simple_strtoul(argv[2], NULL, 16);
ulong cnt  = simple_strtoul(argv[4], NULL, 16);
ulong n;
-#ifdef CFG_64BIT_STRTOUL
+#ifdef CFG_64BIT_LBA
lbaint_t blk  = simple_strtoull(argv[3], NULL, 16);
 
printf (\nIDE read: device %d block # %qd, count %ld ... ,
@@ -327,7 +327,7 @@ int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char 
*argv[])
ulong addr = simple_strtoul(argv[2], NULL, 16);
ulong cnt  = simple_strtoul(argv[4], NULL, 16);
ulong n;
-#ifdef CFG_64BIT_STRTOUL
+#ifdef CFG_64BIT_LBA
lbaint_t blk  = simple_strtoull(argv[3], NULL, 16);
 
printf (\nIDE write: device %d block # %qd, count %ld ... ,
-- 
1.5.6.3


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[U-Boot-Users] [PATCH] POST: Add disable interrupts in some of the missing CPU POST tests

2008-07-18 Thread Stefan Roese
Some CPU POST tests did not disable the interrupts while running. This
seems to be necessary to protect this self modifying code.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 post/lib_ppc/b.c   |4 
 post/lib_ppc/cmp.c |4 
 post/lib_ppc/cmpi.c|4 
 post/lib_ppc/complex.c |4 
 post/lib_ppc/cr.c  |4 
 post/lib_ppc/load.c|4 
 post/lib_ppc/multi.c   |4 
 post/lib_ppc/store.c   |4 
 post/lib_ppc/string.c  |4 
 9 files changed, 36 insertions(+), 0 deletions(-)

diff --git a/post/lib_ppc/b.c b/post/lib_ppc/b.c
index 45b9ff2..7a2583d 100644
--- a/post/lib_ppc/b.c
+++ b/post/lib_ppc/b.c
@@ -95,6 +95,7 @@ int cpu_post_test_b (void)
 {
 int ret = 0;
 unsigned int i;
+int flag = disable_interrupts();
 
 if (ret == 0)
 {
@@ -188,6 +189,9 @@ int cpu_post_test_b (void)
}
 }
 
+if (flag)
+   enable_interrupts();
+
 return ret;
 }
 
diff --git a/post/lib_ppc/cmp.c b/post/lib_ppc/cmp.c
index 8d80f86..13809d4 100644
--- a/post/lib_ppc/cmp.c
+++ b/post/lib_ppc/cmp.c
@@ -102,6 +102,7 @@ int cpu_post_test_cmp (void)
 {
 int ret = 0;
 unsigned int i;
+int flag = disable_interrupts();
 
 for (i = 0; i  cpu_post_cmp_size  ret == 0; i++)
 {
@@ -124,6 +125,9 @@ int cpu_post_test_cmp (void)
}
 }
 
+if (flag)
+   enable_interrupts();
+
 return ret;
 }
 
diff --git a/post/lib_ppc/cmpi.c b/post/lib_ppc/cmpi.c
index 92b4d57..5ecfe87 100644
--- a/post/lib_ppc/cmpi.c
+++ b/post/lib_ppc/cmpi.c
@@ -102,6 +102,7 @@ int cpu_post_test_cmpi (void)
 {
 int ret = 0;
 unsigned int i;
+int flag = disable_interrupts();
 
 for (i = 0; i  cpu_post_cmpi_size  ret == 0; i++)
 {
@@ -124,6 +125,9 @@ int cpu_post_test_cmpi (void)
}
 }
 
+if (flag)
+   enable_interrupts();
+
 return ret;
 }
 
diff --git a/post/lib_ppc/complex.c b/post/lib_ppc/complex.c
index 271392a..4983c51 100644
--- a/post/lib_ppc/complex.c
+++ b/post/lib_ppc/complex.c
@@ -101,6 +101,7 @@ static int cpu_post_test_complex_2 (void)
 int cpu_post_test_complex (void)
 {
 int ret = 0;
+int flag = disable_interrupts();
 
 if (ret == 0)
 {
@@ -117,6 +118,9 @@ int cpu_post_test_complex (void)
post_log (Error at complex test !\n);
 }
 
+if (flag)
+   enable_interrupts();
+
 return ret;
 }
 
diff --git a/post/lib_ppc/cr.c b/post/lib_ppc/cr.c
index 0bd9e74..2c7976a 100644
--- a/post/lib_ppc/cr.c
+++ b/post/lib_ppc/cr.c
@@ -248,6 +248,7 @@ int cpu_post_test_cr (void)
 int ret = 0;
 unsigned int i;
 unsigned long cr_sav;
+int flag = disable_interrupts();
 
 asm ( mfcr %0 : =r (cr_sav) : );
 
@@ -347,6 +348,9 @@ int cpu_post_test_cr (void)
 
 asm ( mtcr %0 : : r (cr_sav));
 
+if (flag)
+   enable_interrupts();
+
 return ret;
 }
 
diff --git a/post/lib_ppc/load.c b/post/lib_ppc/load.c
index 86bc223..eccebb7 100644
--- a/post/lib_ppc/load.c
+++ b/post/lib_ppc/load.c
@@ -178,6 +178,7 @@ int cpu_post_test_load (void)
 {
 int ret = 0;
 unsigned int i;
+int flag = disable_interrupts();
 
 for (i = 0; i  cpu_post_load_size  ret == 0; i++)
 {
@@ -246,6 +247,9 @@ int cpu_post_test_load (void)
}
 }
 
+if (flag)
+   enable_interrupts();
+
 return ret;
 }
 
diff --git a/post/lib_ppc/multi.c b/post/lib_ppc/multi.c
index 5d3f584..47135ab 100644
--- a/post/lib_ppc/multi.c
+++ b/post/lib_ppc/multi.c
@@ -44,6 +44,7 @@ int cpu_post_test_multi (void)
 {
 int ret = 0;
 unsigned int i;
+int flag = disable_interrupts();
 
 if (ret == 0)
 {
@@ -72,6 +73,9 @@ int cpu_post_test_multi (void)
post_log (Error at multi test !\n);
 }
 
+if (flag)
+   enable_interrupts();
+
 return ret;
 }
 
diff --git a/post/lib_ppc/store.c b/post/lib_ppc/store.c
index 09ec485..c96f263 100644
--- a/post/lib_ppc/store.c
+++ b/post/lib_ppc/store.c
@@ -163,6 +163,7 @@ int cpu_post_test_store (void)
 {
 int ret = 0;
 unsigned int i;
+int flag = disable_interrupts();
 
 for (i = 0; i  cpu_post_store_size  ret == 0; i++)
 {
@@ -226,6 +227,9 @@ int cpu_post_test_store (void)
}
 }
 
+if (flag)
+   enable_interrupts();
+
 return ret;
 }
 
diff --git a/post/lib_ppc/string.c b/post/lib_ppc/string.c
index b2daa88..3683ac9 100644
--- a/post/lib_ppc/string.c
+++ b/post/lib_ppc/string.c
@@ -47,6 +47,7 @@ int cpu_post_test_string (void)
 {
 int ret = 0;
 unsigned int i;
+int flag = disable_interrupts();
 
 if (ret == 0)
 {
@@ -97,6 +98,9 @@ int cpu_post_test_string (void)
post_log (Error at string test !\n);
 }
 
+if (flag)
+   enable_interrupts();
+
 return ret;
 }
 
-- 
1.5.6.3


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Re: [U-Boot-Users] [PATCH 1/1] POST PPC4xx/spr IVPR only if PPC440

2008-07-18 Thread Stefan Roese
On Friday 18 July 2008, Niklaus Giger wrote:
 Signed-off-by: Niklaus Giger [EMAIL PROTECTED]

Acked-by: Stefan Roese [EMAIL PROTECTED]

Thanks.

Best regards,
Stefan

=
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: [EMAIL PROTECTED]
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Re: [U-Boot-Users] ppc4xx: [PATCH] CPU PPC440x5 on Virtex5 FX (resubmit)

2008-07-18 Thread Stefan Roese
On Thursday 17 July 2008, Ricardo Ribalda Delgado wrote:
 -This patchs gives support for the embbedded ppc440
 on the Virtex5 FPGAs

 -interrupts.c divided in uic.c and interrupts.c

 -xilinx_irq.c for xilinx interrupt controller

 -Include modifications propossed by  Stefan Roese

Applied to next branch of u-boot-ppc4xx after some minor cleanups.

Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] ppc4xx: [PATCH] ML507 Board Support (Resubmit)

2008-07-18 Thread Stefan Roese
On Thursday 17 July 2008, Ricardo Ribalda Delgado wrote:
 The Xilinx ML507 Board is a Virtex 5 prototyping board that includes,
   among others:
   -Virtex 5 FX FPGA (With a ppc440x5 in it)
   -256MB of SDRAM2
   -32MB of Flash
   -I2C Eeprom
   -System ACE chip
   -Serial ATA connectors
   -RS232 Level Conversors
   -Ethernet Transceiver

 This patch gives support to a standard design produced by EDK for this
 board: ppc440, uartlite, xilinx_int and flash

 - Includes Changes propossed by Stefan Roese and Michal Simek

Applied to next branch of u-boot-ppc4xx after some minor cleanups.

Thanks.

Best regards,
Stefan

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[U-Boot-Users] [PATCH] ppc4xx: Fix incorrect MODTx setup for some DIMM configurations

2008-07-18 Thread Stefan Roese
This patch fixes a problem with incorrect MODTx (On Die Termination)
setup for a configuration with multiple DIMM's and multiple ranks.
Without this change Katmai was unable to boot Linux with DDR2 frequency
= 533MHz and mem=3GB. With this patch Katmai successfully boots Linux
with DDR2 frequency = 640MHz and mem=4GB.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 cpu/ppc4xx/44x_spd_ddr2.c |   24 
 1 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index a27e276..e9940e8 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -1150,50 +1150,50 @@ static void program_codt(unsigned long *dimm_populated,
if (dimm_type == SDRAM_DDR2) {
codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
if ((total_dimm == 1)  (firstSlot == TRUE)) {
-   if (total_rank == 1) {
+   if (total_rank == 1) {  /* PUUU */
codt |= CALC_ODT_R(0);
modt0 = CALC_ODT_W(0);
modt1 = 0x;
modt2 = 0x;
modt3 = 0x;
}
-   if (total_rank == 2) {
+   if (total_rank == 2) {  /* PPUU */
codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
-   modt0 = CALC_ODT_W(0);
-   modt1 = CALC_ODT_W(0);
+   modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
+   modt1 = 0x;
modt2 = 0x;
modt3 = 0x;
}
} else if ((total_dimm == 1)  (firstSlot != TRUE)) {
-   if (total_rank == 1) {
+   if (total_rank == 1) {  /* UUPU */
codt |= CALC_ODT_R(2);
modt0 = 0x;
modt1 = 0x;
modt2 = CALC_ODT_W(2);
modt3 = 0x;
}
-   if (total_rank == 2) {
+   if (total_rank == 2) {  /* UUPP */
codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
modt0 = 0x;
modt1 = 0x;
-   modt2 = CALC_ODT_W(2);
-   modt3 = CALC_ODT_W(2);
+   modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
+   modt3 = 0x;
}
}
if (total_dimm == 2) {
-   if (total_rank == 2) {
+   if (total_rank == 2) {  /* PUPU */
codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
modt0 = CALC_ODT_RW(2);
modt1 = 0x;
modt2 = CALC_ODT_RW(0);
modt3 = 0x;
}
-   if (total_rank == 4) {
+   if (total_rank == 4) {  /*  */
codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
CALC_ODT_R(2) | CALC_ODT_R(3);
-   modt0 = CALC_ODT_RW(2);
+   modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
modt1 = 0x;
-   modt2 = CALC_ODT_RW(0);
+   modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
modt3 = 0x;
}
}
-- 
1.5.6.3


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[U-Boot-Users] [ppc4xx] Please pull git://www.denx.de/git/u-boot-ppc4xx.git

2008-07-18 Thread Stefan Roese
The following changes since commit 699f05125509249072a0b865c8d35520d97cd501:
  Wolfgang Denk (1):
Prepare v1.3.4-rc1: Code cleanup, update CHANGELOG, sort Makefile

are available in the git repository at:

  git://www.denx.de/git/u-boot-ppc4xx.git master

Stefan Roese (2):
  ppc4xx: Fix incorrect MODTx setup for some DIMM configurations
  ppc4xx: Enable 64bit printf format on 440/460 platforms

 cpu/ppc4xx/44x_spd_ddr2.c |   24 
 include/ppc4xx.h  |6 ++
 2 files changed, 18 insertions(+), 12 deletions(-)

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Re: [U-Boot-Users] ppc4xx: [PATCH] CPU PPC440x5 on Virtex5 FX (new version)

2008-07-17 Thread Stefan Roese
On Wednesday 16 July 2008, Ricardo Ribalda Delgado wrote:
 Previous patch did not compile on some boards


 Signed-off-by: Ricardo Ribalda Delgado [EMAIL PROTECTED]
 ---
 -This patchs gives support for the embbedded ppc440
 on the Virtex5 FPGAs

 -interrupts.c divided in uic.c and interrupts.c

 -xilinx_irq.c for xilinx interrupt controller

Jon already commented about the swapped commit text/comments issue. Apart from 
that please find some more comments below:

  cpu/ppc4xx/Makefile |   13 +++
  cpu/ppc4xx/cpu.c|8 ++
  cpu/ppc4xx/interrupts.c |  178 ++--
  cpu/ppc4xx/speed.c  |6 +-
  cpu/ppc4xx/uic.c|  210
 +++ cpu/ppc4xx/xilinx_irq.c | 
 111 +++
  include/asm-ppc/interrupt.h |   37 
  include/asm-ppc/processor.h |2 +
  8 files changed, 416 insertions(+), 149 deletions(-)
  create mode 100644 cpu/ppc4xx/uic.c
  create mode 100644 cpu/ppc4xx/xilinx_irq.c
  create mode 100644 include/asm-ppc/interrupt.h

 diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile
 index 800bb41..9d918c9 100644
 --- a/cpu/ppc4xx/Makefile
 +++ b/cpu/ppc4xx/Makefile
 @@ -35,10 +35,14 @@ SOBJS += kgdb.o
  COBJS:= 40x_spd_sdram.o
  COBJS+= 44x_spd_ddr.o
  COBJS+= 44x_spd_ddr2.o
 +ifndef CONFIG_XILINX_440
  COBJS+= 4xx_enet.o
 +endif
  COBJS+= 4xx_pci.o
  COBJS+= 4xx_pcie.o
 +ifndef CONFIG_XILINX_440
  COBJS+= 4xx_uart.o
 +endif
  COBJS+= bedbug_405.o
  COBJS+= commproc.o
  COBJS+= cpu.o
 @@ -47,11 +51,20 @@ COBJS += denali_data_eye.o
  COBJS+= denali_spd_ddr2.o
  COBJS+= ecc.o
  COBJS+= fdt.o
 +ifndef CONFIG_XILINX_440
  COBJS+= gpio.o
 +endif
  COBJS+= i2c.o
  COBJS+= interrupts.o
 +ifndef CONFIG_XILINX_440
 +COBJS+= uic.o
 +else
 +COBJS+= xilinx_irq.o
 +endif
  COBJS+= iop480_uart.o
 +ifndef CONFIG_XILINX_440
  COBJS+= miiphy.o
 +endif

Even though we usually sort the files alphabetically, these 
multiple ifndef's look very ugly. Perhaps we should change this here to a 
single ifndef with all the non-Xilinx files in it.

  COBJS+= ndfc.o
  COBJS+= sdram.o
  COBJS+= speed.o
 diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
 index ef32bc6..775ed01 100644
 --- a/cpu/ppc4xx/cpu.c
 +++ b/cpu/ppc4xx/cpu.c
 @@ -279,7 +279,11 @@ int checkcpu (void)

   get_sys_info(sys_info);

 +#if defined(CONFIG_XILINX_440)
 + puts(IBM PowerPC 4);
 +#else
   puts(AMCC PowerPC 4);
 +#endif

  #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
  defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
 @@ -541,6 +545,10 @@ int checkcpu (void)
   puts(GX Rev. A);
   strcpy(addstr, No Security support);
   break;
 +
 + case PVR_VIRTEX5:
 + puts( VIRTEX5);
 + break;

Is the CPU really a VIRTEX5 or a PPC440 variant? I think the latter. Perhaps 
something like PPC440x5?

   default:
   printf ( UNKNOWN (PVR=%08x), pvr);
 diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
 index 8215dc6..58d1d81 100644
 --- a/cpu/ppc4xx/interrupts.c
 +++ b/cpu/ppc4xx/interrupts.c
 @@ -8,6 +8,10 @@
   * (C) Copyright 2003 (440GX port)
   * Travis B. Sawyer, Sandburst Corporation, [EMAIL PROTECTED]
   *
 + * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
 + * Ricardo Ribalda-Universidad Autonoma de [EMAIL PROTECTED]
 + * Work supported by Qtechnology (htpp://qtec.com)
 + *
   * See file CREDITS for list of people who contributed to this
   * project.
   *
 @@ -31,23 +35,11 @@
  #include watchdog.h
  #include command.h
  #include asm/processor.h
 +#include asm/interrupt.h
  #include ppc4xx.h
  #include ppc_asm.tmpl
  #include commproc.h

 -#if (UIC_MAX  3)
 -#define UICB0_ALL(UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
 -  UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
 -  UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
 -#elif (UIC_MAX  2)
 -#define UICB0_ALL(UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
 -  UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
 -#elif (UIC_MAX  1)
 -#define UICB0_ALL(UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
 -#else
 -#define UICB0_ALL0
 -#endif
 -
  DECLARE_GLOBAL_DATA_PTR;

  /*
 @@ -58,11 +50,7 @@ struct irq_action {
   void *arg;
   int count;
  };
 -
 -static struct irq_action irq_vecs[UIC_MAX * 32];
 -
 -u32 get_dcr(u16);
 -void set_dcr(u16, u32);
 +static struct irq_action irq_vecs[IRQ_MAX];

  #if defined(CONFIG_440)

 @@ -103,7 +91,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
   /*
* Mark all irqs as free
*/
 - for (vec = 0; vec  (UIC_MAX * 32); vec++) {
 + for (vec = 0; vec  IRQ_MAX; vec++) {
   

Re: [U-Boot-Users] ppc4xx: [PATCH] ML507 Board Support

2008-07-17 Thread Stefan Roese
On Wednesday 16 July 2008, Ricardo Ribalda Delgado wrote:
 Added Flash Support

 Signed-off-by: Ricardo Ribalda Delgado [EMAIL PROTECTED]

Please add a small board description in the commit text.

 ---
  CREDITS  |5 ++
  MAINTAINERS  |4 +
  MAKEALL  |1 +
  Makefile |3 +
  board/xilinx/ml507/Makefile  |   58 +
  board/xilinx/ml507/config.mk |   24 +++
  board/xilinx/ml507/init.S|   47 ++
  board/xilinx/ml507/ml507.c   |   46 +
  board/xilinx/ml507/u-boot.lds|  130
 ++ board/xilinx/ml507/xparameters.h |  
 35 ++
  include/configs/ml507.h  |  116 +
  11 files changed, 469 insertions(+), 0 deletions(-)
  create mode 100644 board/xilinx/ml507/Makefile
  create mode 100644 board/xilinx/ml507/config.mk
  create mode 100644 board/xilinx/ml507/init.S
  create mode 100644 board/xilinx/ml507/ml507.c
  create mode 100644 board/xilinx/ml507/u-boot.lds
  create mode 100644 board/xilinx/ml507/xparameters.h
  create mode 100644 include/configs/ml507.h

 diff --git a/CREDITS b/CREDITS
 index 3b6e57d..06e78bf 100644
 --- a/CREDITS
 +++ b/CREDITS
 @@ -399,6 +399,11 @@ N: Stelian Pop
  E: [EMAIL PROTECTED]
  D: Atmel AT91CAP9ADK support

 +N: Ricardo Ribalda Delgado
 +E: [EMAIL PROTECTED]
 +D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460
 +W: http://www.ii.uam.es/~rribalda
 +
  N: Stefan Roese
  E: [EMAIL PROTECTED]
  D: AMCC PPC4xx Support
 diff --git a/MAINTAINERS b/MAINTAINERS
 index b667c8e..75b5b02 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
 @@ -311,6 +311,10 @@ Daniel Poirot [EMAIL PROTECTED]
   sbc8240 MPC8240
   sbc405  PPC405GP

 +Ricardo Ribalda [EMAIL PROTECTED]
 +
 + ml507   PPC440x5
 +
  Stefan Roese [EMAIL PROTECTED]

   P3M7448 MPC7448
 diff --git a/MAKEALL b/MAKEALL
 index a256e9a..5463a58 100755
 --- a/MAKEALL
 +++ b/MAKEALL
 @@ -239,6 +239,7 @@ LIST_4xx=\
   yosemite\
   yucca   \
   zeus\
 + ml507   \
  

  #
 diff --git a/Makefile b/Makefile
 index 10a3e06..40029e6 100644
 --- a/Makefile
 +++ b/Makefile
 @@ -1336,6 +1336,9 @@ ML2_config: unconfig
  ml300_config:unconfig
   @$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx

 +ml507_config:unconfig
 + @$(MKCONFIG) $(@:_config=) ppc ppc4xx ml507 xilinx
 +
  ocotea_config:   unconfig
   @$(MKCONFIG) $(@:_config=) ppc ppc4xx ocotea amcc

 diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile
 new file mode 100644
 index 000..b9bd737
 --- /dev/null
 +++ b/board/xilinx/ml507/Makefile
 @@ -0,0 +1,58 @@
 +#
 +# (C) Copyright 2000-2006
 +# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
 +#
 +# See file CREDITS for list of people who contributed to this
 +# project.
 +#
 +# This program is free software; you can redistribute it and/or
 +# modify it under the terms of the GNU General Public License as
 +# published by the Free Software Foundation; either version 2 of
 +# the License, or (at your option) any later version.
 +#
 +# This program is distributed in the hope that it will be useful,
 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 +# GNU General Public License for more details.
 +#
 +# You should have received a copy of the GNU General Public License
 +# along with this program; if not, write to the Free Software
 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 +# MA 02111-1307 USA
 +#
 +
 +include $(TOPDIR)/config.mk
 +ifneq ($(OBJTREE),$(SRCTREE))
 +endif
 +
 +INCS :=
 +CFLAGS   += $(INCS)
 +HOST_CFLAGS  += $(INCS)
 +
 +LIB  = $(obj)lib$(BOARD).a
 +
 +COBJS= $(BOARD).o \
 +
 +SOBJS= init.o
 +
 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 +OBJS := $(addprefix $(obj),$(COBJS))
 +SOBJS:= $(addprefix $(obj),$(SOBJS))
 +
 +$(LIB):  $(OBJS) $(SOBJS)
 + $(AR) $(ARFLAGS) $@ $^
 +
 +clean:
 + rm -f $(SOBJS) $(OBJS)
 +
 +distclean:   clean
 + rm -f $(LIB) core *.bak .depend
 +
 +#
 +
 +# defines $(obj).depend target
 +include $(SRCTREE)/rules.mk
 +
 +sinclude $(obj).depend
 +
 +#
 diff --git a/board/xilinx/ml507/config.mk b/board/xilinx/ml507/config.mk
 new file mode 100644
 index 000..35c52ad
 --- /dev/null
 +++ b/board/xilinx/ml507/config.mk
 @@ -0,0 +1,24 @@
 +#
 +# (C) Copyright 2000
 +# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
 +#
 +# See file CREDITS for list of people who contributed to this
 +# project.
 +#
 +# This program

Re: [U-Boot-Users] ppc4xx: [PATCH] ML507 Board Support

2008-07-17 Thread Stefan Roese
On Thursday 17 July 2008, Wolfgang Denk wrote:
 In message [EMAIL PROTECTED] you wrote:
   +phys_size_t initdram(int board_type)
   +{
   + return 256 * 1024 * 1024;
   +}
 
  How about at least defining this SDRAM size in the board header and using
  it here:
 
  board_foo.h:
  #define CFG_MBYTES_SDRAM256

 No. All boards, especially all PowerPC boards, should use dynamic
 memory size detection.

You are probably referring to calling get_ram_size() instead of just returning 
the configured fixed value. But what do we gain here. get_ram_size() also 
needs the ram-size as parameter. Not sure if this is an improvement on such 
fixed systems.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH v2] cfi_flash: fix flash on BE machines with CFG_WRITE_SWAPPED_DATA

2008-07-17 Thread Stefan Roese
On Wednesday 16 July 2008, Sebastian Siewior wrote:
 This got broken by commits 93c56f212c
  [cfi_flash: support of long cmd in U-boot.]

 That command needs to be in little endian format on BE machines
 with CFG_WRITE_SWAPPED_DATA. Without this patch, the command 0xf0
 gets saved on stack as 0x00 00 00 f0 and 0x00 gets written into
 the cmdbuf in case portwidth = chipwidth = 8bit.

 Cc: Alexey Korolev [EMAIL PROTECTED]
 Cc: Vasiliy Leonenko [EMAIL PROTECTED]
 Signed-off-by: Sebastian Siewior [EMAIL PROTECTED]
 ---
 I verified the results with
 http://download.breakpoint.cc/cfi-uboout-test.c
 and I get equal results with old / new method in four categories
 - BE  swapped data
 - BE  data now swapped
 - LE  swapped data
 - LE  data now swapped
 on x86  powerpc

Now this looks better and actually works again on my BE platform.

Applied to u-boot-cfi-flash. Thanks.

Best regards,
Stefan

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Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: [EMAIL PROTECTED]
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[U-Boot-Users] [cfi-flash] Please pull git://www.denx.de/git/u-boot-cfi-flash.git

2008-07-17 Thread Stefan Roese
The following changes since commit 699f05125509249072a0b865c8d35520d97cd501:
  Wolfgang Denk (1):
Prepare v1.3.4-rc1: Code cleanup, update CHANGELOG, sort Makefile

are available in the git repository at:

  git://www.denx.de/git/u-boot-cfi-flash.git master

Sebastian Siewior (1):
  cfi_flash: fix flash on BE machines with CFG_WRITE_SWAPPED_DATA

 drivers/mtd/cfi_flash.c |5 -
 1 files changed, 4 insertions(+), 1 deletions(-)

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Re: [U-Boot-Users] [PATCH] cfi_flash: fix flash on Big Endian machines.

2008-07-15 Thread Stefan Roese
Hi Sebastian,

On Monday 14 July 2008, Sebastian Siewior wrote:
 This got broken by commits 93c56f212c
  [cfi_flash: support of long cmd in U-boot.]

 That command seems to be access in a little endian way so
 wrappers are required.

Please explain why this is the case? Little endian wrappers on big endian 
machines for FLASH access? This sounds wrong to me.

 Long is the wrong type because it will behave differently on
 64bit machnines in a way that is probably not expected.
 int should be enough.

Yes. I suggest that you move this long/int issue to a separate patch. It isn't 
related to this endian issue.

And to you main patch:

NAK. After applying this, CFI support on kilauea (PPC405EX with 1* Spansion 
S29GL512N, 16bit wide) breaks:

U-Boot 1.3.3-02016-g3ed7287 (Jul 15 2008 - 10:37:58)

CPU:   AMCC PowerPC 405EX Rev. C at 533.333 MHz (PLB=177, OPB=88, EBC=88 MHz)
   Security support
   Bootstrap Option H - Boot ROM Location I2C (Addr 0x52)
   16 kB I-Cache 16 kB D-Cache
Board: Kilauea - AMCC PPC405EX Evaluation Board
I2C:   ready
DTT1:  34 C
DRAM:  256 MB
FLASH: CFI: Unknown command set 0x0
## Unknown FLASH on Bank 1 - Size = 0x = 0 MB
*** failed ***
### ERROR ### Please RESET the board ###

Please explain what exactly you need to fix, perhaps with an example. The 
current version breaks other boards.

/me fetches the BDI to reflash the kilauea...

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] cfi_flash: fix flash on Big Endian machines.

2008-07-15 Thread Stefan Roese
On Tuesday 15 July 2008, Sebastian Siewior wrote:
  That command seems to be access in a little endian way so
  wrappers are required.
 
 Please explain why this is the case? Little endian wrappers on big endian
 machines for FLASH access? This sounds wrong to me.

 Look at this snippet from flash_make_cmd (my case: big endian 

 CFG_WRITE_SWAPPED_DATA):
 | for (i = info-portwidth; i  0; i--){
 | cword_offset = (info-portwidth-i)%info-chipwidth;
 | cp_offset = info-portwidth - i;
 | val = *((uchar*)cmd + cword_offset);
 | cp[cp_offset] = (cword_offset = sizeof(uint)) ? 0x00 :
 | val; }

 Now, 8bit access, 8bit bus: portwidth = 1, chipwidth = 1. I am only once
 in this for loop and I get the MSB byte of cmd which is 0x00 instead of
 the command which is never touched.

  Long is the wrong type because it will behave differently on
  64bit machnines in a way that is probably not expected.
  int should be enough.
 
 Yes. I suggest that you move this long/int issue to a separate patch. It
  isn't related to this endian issue.

 Right.

OK, I'll await a separate patch for this.

 And to you main patch:
 
 NAK. After applying this, CFI support on kilauea (PPC405EX with 1*
  Spansion S29GL512N, 16bit wide) breaks:

 Is this big endian + CFG_WRITE_SWAPPED_DATA? Did it work before the
 patch?

This is big endian and CFG_WRITE_SWAPPED_DATA *not* defined. You can check 
this yourself, the port is officially available. And yes, of course it worked 
before the patch.

 FLASH: CFI: Unknown command set 0x0

 The command has not been sent but MSB which was 0x00.

 ## Unknown FLASH on Bank 1 - Size = 0x = 0 MB

 That's the message I got before my patch. There is probably still
 something wrong.

 Please explain what exactly you need to fix, perhaps with an example. The
 current version breaks other boards.

 I attached a file which can be used for testing. On your little endian
 machine you should have __LITTLE_ENDIAN

Little endian? Why should I have this defined on my PPC system. It's not.

 defined and your result should 
 be 0xf0 in the case i = 0. Right now, I get 0x00 on my BE machine while
 LE case is working fine.

I have to admit that I don't have the time to test anything right now. It 
seems that you have a problem with the #else path in flash_make_cmd(). Do you 
have access to a big endian platform which doesn't define 
CFG_WRITE_SWAPPED_DATA? If yes, you could test both cases.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] cfi_flash: fix flash on Big Endian machines.

2008-07-15 Thread Stefan Roese
On Tuesday 15 July 2008, Sebastian Siewior wrote:
 * Stefan Roese | 2008-07-15 11:48:11 [+0200]:
 OK, I'll await a separate patch for this.

 Could be in your inbox allready :)

Yes. :)

  And to you main patch:
  
  NAK. After applying this, CFI support on kilauea (PPC405EX with 1*
   Spansion S29GL512N, 16bit wide) breaks:
 
  Is this big endian + CFG_WRITE_SWAPPED_DATA? Did it work before the
  patch?
 
 This is big endian and CFG_WRITE_SWAPPED_DATA *not* defined. You can check
 this yourself, the port is officially available. And yes, of course it
  worked before the patch.

 So I might have an idea where the bug is.

Good.

snip

  defined and your result should
  be 0xf0 in the case i = 0. Right now, I get 0x00 on my BE machine while
  LE case is working fine.
 
 I have to admit that I don't have the time to test anything right now. It
 seems that you have a problem with the #else path in flash_make_cmd(). Do
  you have access to a big endian platform which doesn't define
 CFG_WRITE_SWAPPED_DATA? If yes, you could test both cases.

 No I don't, but I have an idea how I could test this assuming that it
 has work after the patch in question and didn't after mine.

Yes, it works on those kind of platforms (CFG_WRITE_SWAPPED_DATA not defined) 
on current top of git repository. And fails with your patch applied.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] CPU PPC440x5 on Virtex5 FX

2008-07-14 Thread Stefan Roese
Hi Racardo,

On Monday 14 July 2008, Ricardo Ribalda Delgado wrote:
   I'm back from short hollydays, so expect some patches in this week
 :). Some general questions:

 master or next:
 Shall I apply the patches to master or to next? Both have
 modifications from 2 days ago.

next please. master is only for bug fixes now, since the merge window is 
closed.

 interrupts:
 I have been thinking about the irq handler and I am going to create this
 files:

-interrupt.c (actual file) - common part
-uic.c (new file) - uic part (extracted from interrupt.c)
-xilinx_iic.c (new file) - Xilinx Irq handler

xilinx_iic.c ??? This really sounds like I2C. Please choose a different name.

 The Makefile will select among uic.c or xilinx_iic.c

Yes, this is possible. But IIRC then the microblaze CPU suport has the same or 
at least a similar interrupt handler. Isn't there a way to use some interrupt 
code on both CPU architectures?

 ml507:
 As you know I have been sending patches for the ml507 board. I will
 wait until this patch in accepted until I resend the ml507 patch. Is
 this ok?

To clarify: You will wait to send the ml507 board support patches until the 
CPU  interrupt stuff is accepted?

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] I2C Monitor Chip ADT7460 support

2008-07-11 Thread Stefan Roese
On Friday 11 July 2008, Ricardo Ribalda Delgado wrote:
 Signed-off-by: Ricardo Ribalda Delgado [EMAIL PROTECTED]

Please find some comments below (mostly nitpicking).

  drivers/hwmon/Makefile  |1 +
  drivers/hwmon/adt7460.c |   81
 +++ drivers/hwmon/adt7460.h |  
 49 
  include/dtt.h   |3 +-
  4 files changed, 133 insertions(+), 1 deletions(-)
  create mode 100644 drivers/hwmon/adt7460.c
  create mode 100644 drivers/hwmon/adt7460.h

 diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
 index 065433a..e301eaa 100644
 --- a/drivers/hwmon/Makefile
 +++ b/drivers/hwmon/Makefile
 @@ -37,6 +37,7 @@ COBJS-y += ds1775.o
  COBJS-$(CONFIG_DTT_LM73) += lm73.o
  COBJS-y += lm75.o
  COBJS-y += lm81.o
 +COBJS-$(CONFIG_DTT_ADT7460) += adt7460.o

  COBJS:= $(COBJS-y)
  SRCS := $(COBJS:.o=.c)
 diff --git a/drivers/hwmon/adt7460.c b/drivers/hwmon/adt7460.c
 new file mode 100644
 index 000..3fbd6fa
 --- /dev/null
 +++ b/drivers/hwmon/adt7460.c
 @@ -0,0 +1,81 @@
 +/*
 +(C) Copyright 2008
 +Ricado Ribalda-Universidad Autonoma de Madrid, [EMAIL PROTECTED]
 +This work has been supported by: Q-Technology  http://qtec.com/
 +
 +This program is free software: you can redistribute it and/or modify
 +it under the terms of the GNU General Public License as published by
 +the Free Software Foundation, either version 2 of the License, or
 +(at your option) any later version.
 +
 +This program is distributed in the hope that it will be useful,
 +but WITHOUT ANY WARRANTY; without even the implied warranty of
 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 +GNU General Public License for more details.
 +
 +You should have received a copy of the GNU General Public License
 +along with this program.  If not, see http://www.gnu.org/licenses/.
 +*/
 +
 +#include common.h
 +
 +#include i2c.h
 +#include dtt.h
 +#include adt7460.h
 +
 +#define ADT7460_ADDRESS 0x2c
 +int dtt_read(int sensor, int reg)
 +{
 + u8 dir=reg;

Codingstyle:

u8 dir = reg;

 + u8 data;
 +
 + if (i2c_read(ADT7460_ADDRESS,dir,1,data,1)==-1)

Spaces are sometimes nice too:

if (i2c_read(ADT7460_ADDRESS, dir, 1, data, 1) == -1)

 + return -1;
 +
 + if (data==ADT7460_INVALID)

Again spaces missing:

if (data == ADT7460_INVALID)

I'll stop here with it. Please fix all this codingstyle issues in this file.

snip

 diff --git a/drivers/hwmon/adt7460.h b/drivers/hwmon/adt7460.h
 new file mode 100644
 index 000..d915d1b
 --- /dev/null
 +++ b/drivers/hwmon/adt7460.h
 @@ -0,0 +1,49 @@
 +/*
 +(C) Copyright 2008
 +Ricado Ribalda-Universidad Autonoma de Madrid, [EMAIL PROTECTED]
 +This work has been supported by: Q-Technology  http://qtec.com/
 +
 +This program is free software: you can redistribute it and/or modify
 +it under the terms of the GNU General Public License as published by
 +the Free Software Foundation, either version 2 of the License, or
 +(at your option) any later version.
 +
 +This program is distributed in the hope that it will be useful,
 +but WITHOUT ANY WARRANTY; without even the implied warranty of
 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 +GNU General Public License for more details.
 +
 +You should have received a copy of the GNU General Public License
 +along with this program.  If not, see http://www.gnu.org/licenses/.
 +*/
 +#ifndef ADT7460
 +#define ADT7460
 +
 +
 +#define ADT7460_INVALID 128
 +
 +#define ADT7460_2_5V 0x20
 +#define ADT7460_VCCP 0x21
 +#define ADT7460_VCC  0x22
 +#define ADT7460_V5   0x23
 +#define ADT7460_V12  0x24
 +#define ADT7460_REM1_TEMP0x25
 +#define ADT7460_LOCAL_TEMP   0x26
 +#define ADT7460_REM2_TEMP0x27
 +#define ADT7460_TACH1L   0x28
 +#define ADT7460_TACH1H   0x29
 +#define ADT7460_TACH2L   0x2a
 +#define ADT7460_TACH2H   0x2b
 +#define ADT7460_TACH3L   0x2c
 +#define ADT7460_TACH3H   0x2d
 +#define ADT7460_TACH4L   0x2e
 +#define ADT7460_TACH4H   0x2f
 +#define ADT7460_TACH5L   0xa9
 +#define ADT7460_TACH5H   0xaa
 +#define ADT7460_TACH6L   0xab
 +#define ADT7460_TACH6H   0xac
 +#define ADT7460_REVISION 0x3f
 +#define ADT7460_CONFIG   0x40
 +
 +
 +#endif

Do you really think this header is necessary? I would prefer to move those 
defines into the C file instead and drop the header completely.

Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] New Dummy I2C Driver

2008-07-11 Thread Stefan Roese
On Friday 11 July 2008, Ricardo Ribalda Delgado wrote:
 I didn't add this to the description sorry:

  This driver provides access to a false i2c eeprom.
  This false eeprom could be very useful in boards with
  ddr2 memories and no i2c interfaces.
  Using this driver the user can simulate the spd interface
  of the ddr2 memory and use the ddr2 auto configuration

Problem is, that those SPD values in this driver are board specific. Other 
boards with other DIMM(s) would need other EEPROM values. So it doesn't make 
sense to add this in such a common file for me. And I really don't like the 
name dummy_i2c.c.

Which SDRAM controller is used on your 440/Virtex SoC? Is it an IBM compatible 
one? Or an IP core from Xilinx? I suggest you take a look at the similar 
implementation selectable via CFG_SIMULATE_SPD_EEPROM (used on bamboo).

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] I2C Monitor Chip ADT7460 support

2008-07-11 Thread Stefan Roese
On Friday 11 July 2008, Ricardo Ribalda Delgado wrote:
 Signed-off-by: Ricardo Ribalda Delgado [EMAIL PROTECTED]

Ricardo, please address my (nitpicking) comments below in the next version. 
You could also run Lindent if you don't want to do this coding style 
cleanup manually.

 ---
  drivers/hwmon/Makefile  |1 +
  drivers/hwmon/adt7460.c |   85
 +++ include/dtt.h   |  
  3 +-
  3 files changed, 88 insertions(+), 1 deletions(-)
  create mode 100644 drivers/hwmon/adt7460.c

 diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
 index 065433a..e301eaa 100644
 --- a/drivers/hwmon/Makefile
 +++ b/drivers/hwmon/Makefile
 @@ -37,6 +37,7 @@ COBJS-y += ds1775.o
  COBJS-$(CONFIG_DTT_LM73) += lm73.o
  COBJS-y += lm75.o
  COBJS-y += lm81.o
 +COBJS-$(CONFIG_DTT_ADT7460) += adt7460.o

  COBJS:= $(COBJS-y)
  SRCS := $(COBJS:.o=.c)
 diff --git a/drivers/hwmon/adt7460.c b/drivers/hwmon/adt7460.c
 new file mode 100644
 index 000..28b2eb7
 --- /dev/null
 +++ b/drivers/hwmon/adt7460.c
 @@ -0,0 +1,85 @@
 +/*
 +(C) Copyright 2008
 +Ricado Ribalda-Universidad Autonoma de Madrid, [EMAIL PROTECTED]
 +This work has been supported by: Q-Technology  http://qtec.com/
 +
 +This program is free software: you can redistribute it and/or modify
 +it under the terms of the GNU General Public License as published by
 +the Free Software Foundation, either version 2 of the License, or
 +(at your option) any later version.
 +
 +This program is distributed in the hope that it will be useful,
 +but WITHOUT ANY WARRANTY; without even the implied warranty of
 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 +GNU General Public License for more details.
 +
 +You should have received a copy of the GNU General Public License
 +along with this program.  If not, see http://www.gnu.org/licenses/.
 +*/
 +
 +#include common.h
 +#include i2c.h
 +#include dtt.h
 +
 +#define ADT7460_ADDRESS  0x2c
 +#define ADT7460_INVALID  128
 +#define ADT7460_CONFIG   0x40
 +#define ADT7460_REM1_TEMP0x25
 +#define ADT7460_LOCAL_TEMP   0x26
 +#define ADT7460_REM2_TEMP0x27
 +
 +int dtt_read(int sensor, int reg)
 +{
 + u8 dir=reg;

Spaces missing:

u8 dir = reg;

 + u8 data;
 +
 + if ( i2c_read(ADT7460_ADDRESS,dir,1,data,1) ==-1 )

This should be:

if (i2c_read(ADT7460_ADDRESS, dir, 1, data, 1) == -1)

 + return -1;
 + if (data==ADT7460_INVALID)

Again spaces. And more below...

I suggest you run Lindent over this file.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH 1/1] hwmon: Cleaning hwmon devices

2008-07-11 Thread Stefan Roese
On Friday 11 July 2008, [EMAIL PROTECTED] wrote:
 From: Michal Simek [EMAIL PROTECTED]

 Clean Makefile
 Move device specific values to driver for better reading

Thanks. One comment below though:

 Signed-off-by: Michal Simek [EMAIL PROTECTED]
 ---
  drivers/hwmon/Makefile  |   12 
  drivers/hwmon/adm1021.c |   35 +++--
  drivers/hwmon/ds1621.c  |   12 +--
  drivers/hwmon/ds1722.c  |5 ---
  drivers/hwmon/ds1775.c  |8 ++--
  drivers/hwmon/lm73.c|6 
  drivers/hwmon/lm75.c|8 ++--
  drivers/hwmon/lm81.c|8 +++--
  include/dtt.h   |   77
 +- 9 files changed, 66
 insertions(+), 105 deletions(-)

 diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
 index 065433a..61b028f 100644
 --- a/drivers/hwmon/Makefile
 +++ b/drivers/hwmon/Makefile
 @@ -30,13 +30,13 @@ include $(TOPDIR)/config.mk

  LIB  = $(obj)libhwmon.a

 -COBJS-y += adm1021.o
 -COBJS-y += ds1621.o
 -COBJS-y += ds1722.o
 -COBJS-y += ds1775.o
 +COBJS-$(CONFIG_DTT_ADM1021) += adm1021.o
 +COBJS-$(CONFIG_DTT_DS1621) += ds1621.o
 +COBJS-$(CONFIG_DS1722) += ds1722.o

CONFIG_DS1722 does not match the CONFIG_DTT_foo idea all other sensors are 
using. Perhaps you could fix this up too (CONFIG_DS1722 - CONFIG_DTT_DS1722) 
with another version of this patch?

Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH 1/1] hwmon: Cleaning hwmon devices

2008-07-11 Thread Stefan Roese
On Friday 11 July 2008, Michal Simek wrote:
  -COBJS-y += adm1021.o
  -COBJS-y += ds1621.o
  -COBJS-y += ds1722.o
  -COBJS-y += ds1775.o
  +COBJS-$(CONFIG_DTT_ADM1021) += adm1021.o
  +COBJS-$(CONFIG_DTT_DS1621) += ds1621.o
  +COBJS-$(CONFIG_DS1722) += ds1722.o
 
 CONFIG_DS1722 does not match the CONFIG_DTT_foo idea all other sensors
  are using. Perhaps you could fix this up too (CONFIG_DS1722 -
  CONFIG_DTT_DS1722) with another version of this patch?

 Second patch for it seems reasonable for me because there will be change in
 board config and it will be better to have full change in one commit. I'll
 do it and send it.

Great, that's what I meant.

Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] ppc4xx: Fix include sequence in 4xx_pcie.c

2008-07-11 Thread Stefan Roese
Hi Wolfgang,

On Thursday 10 July 2008, Stefan Roese wrote:
  Hm. I think we have a serious problem when the correctness of the code
  depends on the include order. It seems that include/asm-ppc/types.h
  depends on CONFIG_PHYS_64BIT, so include/asm-ppc/types.h must make
  sure this variable is set correctly, i. e. we should include common.h
  there.

 Yes, I though too that this problem might affect other files too. But
 unfortunately including common.h from within asm/types.h does not work
 since common.h includes (and needs) types.h itself.

 I have no elegant solution to handle this in a more generic way right now.
 Perhaps somebody else has? Ideas welcome. :)

Since nobody has come up with a better idea, I suggest we push the current fix 
for now. Same reason as the USB shutdown patch that you pulled even though it 
is not perfect.

Should I put it in my repo and send a pull request?

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] PPC4xx: Add MII mode support to the EMAC RGMII Bridge

2008-07-11 Thread Stefan Roese
On Tuesday 08 July 2008, Grant Erickson wrote:
 This patch adds support for placing the RGMII bridge on the
 PPC405EX(r) into MII/GMII mode and allows a board-specific
 configuration to specify the bridge mode at compile-time.

 Signed-off-by: Grant Erickson [EMAIL PROTECTED]

Applied to next branch in u-boot-ppc4xx repository. Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH 1/3] ppc4xx: Add initial 460SX defines for the cpu/ppc4xx directory.

2008-07-11 Thread Stefan Roese
On Wednesday 09 July 2008, [EMAIL PROTECTED] wrote:
 From: Feng Kan [EMAIL PROTECTED]

 Signed-off-by: Feng Kan [EMAIL PROTECTED]

Applied to next branch in u-boot-ppc4xx repository. Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH 3/3] ppc4xx: Initial framework of the AMCC PPC460SX redwood reference board.

2008-07-11 Thread Stefan Roese
On Wednesday 09 July 2008, [EMAIL PROTECTED] wrote:
 From: Feng Kan [EMAIL PROTECTED]

 Add AMCC Redwood reference board that uses the latest
 PPC 464 CPU processor combined with a rich mix of peripheral
 controllers. The board will support PCIe, mutiple Gig ethernet
 ports, advanced hardware RAID assistance and IEEE 1588.

 Signed-off-by: Feng Kan [EMAIL PROTECTED]

Applied to next branch in u-boot-ppc4xx repository. Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH v2] PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r)

2008-07-11 Thread Stefan Roese
On Wednesday 09 July 2008, Grant Erickson wrote:
 While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM
 controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in
 the 405EX(r), SDRAM_MCSTAT has a different DCR value.

 Its present value on the 405EX(r) causes a read back of 0x
 which causes SDRAM initialization to periodically fail since it can
 prematurely indicate SDRAM ready status.

 Signed-off-by: Grant Erickson [EMAIL PROTECTED]

Applied to next branch in u-boot-ppc4xx repository. Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] PPC4xx: Add SDR0_SRST Mnemonics for the 405EX(r)

2008-07-11 Thread Stefan Roese
On Thursday 10 July 2008, Grant Erickson wrote:
 This patch adds bit field mnemonics for the 405EX(r) SDR0_SRST soft reset
 register.

 Signed-off-by: Grant Erickson [EMAIL PROTECTED]

Applied to next branch in u-boot-ppc4xx repository. Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] PPC4xx: Add AMCC/IBM DDR2 SDRAM ECC Field Mnemonics

2008-07-11 Thread Stefan Roese
On Thursday 10 July 2008, Grant Erickson wrote:
 Add additional DDR2 SDRAM memory controller DCR mneomnics, condition
 revision ID DCR based on 405EX, and add field mnemonics for bus error
 status and ECC error status registers.

 Signed-off-by: Grant Erickson [EMAIL PROTECTED]

Applied to next branch in u-boot-ppc4xx repository. Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] CPU PPC440x5 on Virtex5 FX

2008-07-11 Thread Stefan Roese
Ricardo,

On Friday 11 July 2008, Ricardo Ribalda Delgado wrote:
 This patchs gives support for the embbedded ppc440
 on the Virtex5 FPGAs

Thanks.

Some general comments:

Please rebase your 4xx related patches on the next branch of my 
u-boot-ppc4xx repository. I just pushed some bigger rework/cleanup patchsets 
that are destined for the next merge window.

And please add ppc4xx:  to the beginning of the patch subject and add me to 
CC on 4xx related patches.

More comments below...

 ---
  cpu/ppc4xx/4xx_enet.c   |3 +-
  cpu/ppc4xx/4xx_uart.c   |3 +
  cpu/ppc4xx/cpu.c|4 +
  cpu/ppc4xx/gpio.c   |5 +
  cpu/ppc4xx/interrupts.c |  238
 --- cpu/ppc4xx/miiphy.c |  
  5 +
  cpu/ppc4xx/speed.c  |6 +-
  include/asm-ppc/processor.h |3 +-
  net/eth.c   |3 +-
  9 files changed, 228 insertions(+), 42 deletions(-)

 diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
 index 4e863dc..cf26237 100644
 --- a/cpu/ppc4xx/4xx_enet.c
 +++ b/cpu/ppc4xx/4xx_enet.c
 @@ -97,7 +97,8 @@
   * network support enabled.
   * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC
 controller! */
 -#if defined(CONFIG_CMD_NET)  !defined(CONFIG_405) 
 !defined(CONFIG_IOP480) +#if defined(CONFIG_CMD_NET) 
 !defined(CONFIG_405)  !defined(CONFIG_IOP480) \ +   
 !defined(CONFIG_440_VIRTEX5)

  #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
  #error CONFIG_MII has to be defined!
 diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c
 index a7587d4..37d3dbc 100644
 --- a/cpu/ppc4xx/4xx_uart.c
 +++ b/cpu/ppc4xx/4xx_uart.c
 @@ -48,6 +48,7 @@
  #include watchdog.h
  #include asm/ppc4xx-intvec.h

 +#if !defined(CONFIG_440_VIRTEX5)

You add this #if !defined(CONFIG_440_VIRTEX5) to many of the cpu/ppc4xx 
files with this patch. I don't like this. We should let the Makefile handle 
this. Perhaps something like this:

ifndef $(CONFIG_440_VIRTEX5)
COBJS   += 4xx_enet.o
...
endif

  #ifdef CONFIG_SERIAL_MULTI
  #include serial.h
  #endif
 @@ -873,3 +874,5 @@ int serial_tstc(void)
  #endif /* CONFIG_SERIAL_MULTI */

  #endif   /* CONFIG_405GP || CONFIG_405CR */
 +
 +#endif
 diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
 index 39f439d..f510cdd 100644
 --- a/cpu/ppc4xx/cpu.c
 +++ b/cpu/ppc4xx/cpu.c
 @@ -508,6 +508,10 @@ int checkcpu (void)
   puts(GT Rev. A);
   strcpy(addstr, Security/Kasumi support);
   break;
 +
 + case PVR_VIRTEX5:
 + printf( VIRTEX5);
 + break;

   default:
   printf ( UNKNOWN (PVR=%08x), pvr);
 diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c
 index df99f53..59159ee 100644
 --- a/cpu/ppc4xx/gpio.c
 +++ b/cpu/ppc4xx/gpio.c
 @@ -26,6 +26,9 @@
  #include asm/io.h
  #include asm/gpio.h

 +
 +#if !defined(CONFIG_440_VIRTEX5)
 +

Again, move this to the Makefile instead.

  #if defined(CFG_4xx_GPIO_TABLE)
  gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] =
 CFG_4xx_GPIO_TABLE; #endif
 @@ -253,3 +256,5 @@ void gpio_set_chip_configuration(void)
   }
  }
  #endif /* CFG_4xx_GPIO_TABLE */
 +
 +#endif
 diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
 index 8620e2b..4648f52 100644
 --- a/cpu/ppc4xx/interrupts.c
 +++ b/cpu/ppc4xx/interrupts.c
 @@ -8,6 +8,10 @@
   * (C) Copyright 2003 (440GX port)
   * Travis B. Sawyer, Sandburst Corporation, [EMAIL PROTECTED]
   *
 + * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
 + * Ricardo Ribalda, Universidad Autonoma de Madrid, [EMAIL PROTECTED]
 + * Work supported by Qtechnology (htpp://qtec.com)
 + *
   * See file CREDITS for list of people who contributed to this
   * project.
   *
 @@ -41,6 +45,7 @@ DECLARE_GLOBAL_DATA_PTR;
  /*
   * Define the number of UIC's
   */
 +#if !defined(CONFIG_440_VIRTEX5)
  #if defined(CONFIG_440SPE) || \
  defined(CONFIG_460EX) || defined(CONFIG_460GT)
  #define UIC_MAX  4
 @@ -54,17 +59,23 @@ DECLARE_GLOBAL_DATA_PTR;
  #else
  #define UIC_MAX  1
  #endif
 -
 +#else
 +void xilinx_pic_enable(void);
 +#endif
  /*
   * CPM interrupt vector functions.
   */
 -struct   irq_action {
 +struct irq_action {

You seem to have run Lindent on this file too, correct? Please don't do this 
when you also add and/or fix something. This makes it hard to see the real 
changes. Only run Lindent on newly created files.

   interrupt_handler_t *handler;
   void *arg;
   int count;
  };

 +#if !defined(CONFIG_440_VIRTEX5)
  static struct irq_action irq_vecs[UIC_MAX * 32];
 +#else
 +static struct irq_action irq_vecs[XPAR_INTC_MAX_NUM_INTR_INPUTS];
 +#endif

  u32 get_dcr(u16);
  void set_dcr(u16, u32);
 @@ -81,27 +92,25 @@ static __inline__ void set_evpr(unsigned long val)
   asm volatile(mtspr 0x03f,%0 : : r (val));
  }

 -#else /* !defined(CONFIG_440) */
 +#else/* !defined(CONFIG_440) */

  static __inline__ void set_pit(unsigned long val)
  {
 

Re: [U-Boot-Users] [PATCH] CPU PPC440x5 on Virtex5 FX

2008-07-11 Thread Stefan Roese
On Friday 11 July 2008, Michal Simek wrote:
 Some days ago a sent to mailing list patch (currently is in) where I rename
 CONFIG_XILINX_ML300 - CONFIG_XILINX_405.

 I would like to see if you can use the same style for 440 -
 CONFIG_XILINX_440. I have no detail information about ppc440 but IMHO only
 virtex5 fx (or whatever) support it - make no sense to me use virtex5 in
 name.

 SR: Do you agree with me?

Yes, renaming this to CONFIG_XILINX_440 is a good idea.

 There is big part of code relate with interrupt controller which is the
 same with microblaze. This should be handled in the same way. Any
 suggestion? (Do generic driver?)

Yes, I already mentioned in my review, that this code should go into a 
separate file. If the microblaze implementation is the same or very similar 
then please use the same code here and move to to a common directory. 
Perhaps:

drivers/interrupt/xilinx.c ?

Comments?

 M

 BTW: some comments in code.

Michal, your comments are very hard to spot since you don't quote the original 
code by  .

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] ML507: New board support

2008-07-11 Thread Stefan Roese
On Friday 11 July 2008, Ricardo Ribalda Delgado wrote:
 -Suport for the Xilinx ML507 Development Board

Comments below...

 Signed-off-by: Ricardo Ribalda Delgado [EMAIL PROTECTED]
 ---
  Makefile|3 +

You forgot to add youself to MAINTAINERS and the board to MAKEALL.

  board/xilinx/ml507/Makefile |   53 
  board/xilinx/ml507/config.mk|   18 
  board/xilinx/ml507/init.S   |   45 +++
  board/xilinx/ml507/ml507.c  |   57 +
  board/xilinx/ml507/u-boot.lds   |  149
 +++ board/xilinx/ml507/u-boot.lds.debug | 
 136  board/xilinx/ml507/xparameters.h| 
  33 
  include/configs/ml507.h |  108 +
  9 files changed, 602 insertions(+), 0 deletions(-)
  create mode 100644 board/xilinx/ml507/Makefile
  create mode 100644 board/xilinx/ml507/config.mk
  create mode 100644 board/xilinx/ml507/init.S
  create mode 100644 board/xilinx/ml507/ml507.c
  create mode 100644 board/xilinx/ml507/u-boot.lds
  create mode 100644 board/xilinx/ml507/u-boot.lds.debug
  create mode 100644 board/xilinx/ml507/xparameters.h
  create mode 100644 include/configs/ml507.h

snip

 diff --git a/board/xilinx/ml507/ml507.c b/board/xilinx/ml507/ml507.c
 new file mode 100644
 index 000..27c87cc
 --- /dev/null
 +++ b/board/xilinx/ml507/ml507.c
 @@ -0,0 +1,57 @@
 +/*
 +(C) Copyright 2008
 +Ricado Ribalda-Universidad Autonoma de [EMAIL PROTECTED]
 +This work has been supported by: QTechnology  http://qtec.com/
 +
 +This program is free software: you can redistribute it and/or modify
 +it under the terms of the GNU General Public License as published by
 +the Free Software Foundation, either version 2 of the License, or
 +(at your option) any later version.
 +
 +This program is distributed in the hope that it will be useful,
 +but WITHOUT ANY WARRANTY; without even the implied warranty of
 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 +GNU General Public License for more details.
 +
 +You should have received a copy of the GNU General Public License
 +along with this program.  If not, see http://www.gnu.org/licenses/.
 +*/
 +
 +#include config.h
 +#include common.h
 +#include asm/processor.h
 +
 +int board_pre_init(void)
 +{
 + return 0;
 +}
 +
 +int checkboard(void)
 +{
 +
 + printf
 + (ML507 Board ported by Ricardo Ribalda [EMAIL PROTECTED]
 (http://qtec.com) \n); + return (0);

Hmmm. Do you really need to print your name in the U-Boot log each time the 
board boots? I wouldn't do this.

 +}
 +
 +phys_size_t initdram(int board_type)
 +{
 + return 256 * 1024 * 1024;
 +}
 +
 +int testdram(void)
 +{
 + printf(test: xxx MB - ok\n);
 +
 + return (0);
 +}

Remove testdram() please.

 +void get_sys_info(sys_info_t * sysInfo)
 +{
 + sysInfo-freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
 + sysInfo-freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
 + sysInfo-freqPCI = 0;
 +
 + return;
 +
 +}
 diff --git a/board/xilinx/ml507/u-boot.lds b/board/xilinx/ml507/u-boot.lds
 new file mode 100644
 index 000..054661c
 --- /dev/null
 +++ b/board/xilinx/ml507/u-boot.lds
 @@ -0,0 +1,149 @@
 +/*
 + * (C) Copyright 2000
 + * Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
 + * Modified by: Ricardo Ribalda Delgado ricardo.ribaldaatgmail.com
 ricardo.ribaldaatuam.es + *
 + * See file CREDITS for list of people who contributed to this
 + * project.
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 of
 + * the License, or (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 + * MA 02111-1307 USA
 + */
 +
 +OUTPUT_ARCH(powerpc)
 +ENTRY(_start_440)
 +/* Do we need any of these for elf?
 +   __DYNAMIC = 0;*/
 +SECTIONS
 +{
 +  /* Read-only sections, merged into text segment: */
 +  . = + SIZEOF_HEADERS;
 +  .interp : { *(.interp) }
 +  .hash  : { *(.hash)}
 +  .dynsym: { *(.dynsym)  }
 +  .dynstr: { *(.dynstr)  }
 +  .rel.text  : { *(.rel.text)}
 +  .rela.text : { *(.rela.text)   }
 +  .rel.data  : { *(.rel.data)}
 +  .rela.data : { *(.rela.data)   }
 +  .rel.rodata: { *(.rel.rodata)  }
 +  .rela.rodata   : { *(.rela.rodata) }
 +  .rel.got   : { *(.rel.got)   

[U-Boot-Users] [ppc4xx] Please pull git://www.denx.de/git/u-boot-ppc4xx.git

2008-07-11 Thread Stefan Roese
The following changes since commit 9b55a2536919f4de1bb1044e6eb8262c2f53bc96:
  Wolfgang Denk (1):
Fix some more print() format errors.

are available in the git repository at:

  git://www.denx.de/git/u-boot-ppc4xx.git master

Stefan Roese (1):
  ppc4xx: Fix include sequence in 4xx_pcie.c

 cpu/ppc4xx/4xx_pcie.c |6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

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Re: [U-Boot-Users] [PATCH 1/1] hwmon: rename CONFIG_DS1722 to CONFIG_DTT_DS1722

2008-07-11 Thread Stefan Roese
On Friday 11 July 2008, [EMAIL PROTECTED] wrote:
 From: Michal Simek [EMAIL PROTECTED]


 Signed-off-by: Michal Simek [EMAIL PROTECTED]

Acked-by: Stefan Roese [EMAIL PROTECTED]

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH 1/1] hwmon: Cleaning hwmon devices

2008-07-11 Thread Stefan Roese
On Friday 11 July 2008, [EMAIL PROTECTED] wrote:
 From: Michal Simek [EMAIL PROTECTED]

 Clean Makefile
 Move device specific values to driver for better reading

 Signed-off-by: Michal Simek [EMAIL PROTECTED]

Acked-by: Stefan Roese [EMAIL PROTECTED]

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] CPU PPC440x5 on Virtex5 FX

2008-07-11 Thread Stefan Roese
On Friday 11 July 2008, Wolfgang Denk wrote:
 In message [EMAIL PROTECTED] you wrote:
  2. I don't know if is good idea to create drivers for interrupt
  controllers.

 I have to admit that such an idea surprises me a bit.

  If yes xilinx_intc.c, will be better.
  I will wait for WD comments.

 In my opinion an interrupt controller is fundamentally different from
 an device that is handled by a device driver. It therefore has no
 place in the drivers/ directory.

Yes, I was hesitating here too. Only other idea that comes to my mind is:

cpu/xilinx/interrupt.c

Better?

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] pci: Move PCI device configuration check into a separate weak function

2008-07-10 Thread Stefan Roese
On Thursday 10 July 2008, Wolfgang Denk wrote:
 In message [EMAIL PROTECTED] you wrote:
  Yes, I think we should put it into the repo now.
 
  Wolfgang, can you please pick my patch up directly?

 I can, if you tell me which one exactly.

The one from this email thread:

[PATCH] pci: Move PCI device configuration check into a separate weak function

From 08.07.2008

Thanks.

Best regards,
Stefan

=
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: [EMAIL PROTECTED]
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[U-Boot-Users] [PATCH] ppc4xx: Fix printf format warnings now visible with the updated format check

2008-07-10 Thread Stefan Roese
This patch fixes ppc4xx related printf format warning. Those warnings are
now visible since patch dc4b0b38d4aadf08826f6c31270f1eecd27964fd
[Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is
really helpful.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 board/amcc/katmai/cmd_katmai.c |4 ++--
 board/esd/du440/du440.c|4 ++--
 board/lwmon5/sdram.c   |2 +-
 board/zeus/zeus.c  |2 +-
 cpu/ppc4xx/44x_spd_ddr2.c  |   10 +-
 cpu/ppc4xx/4xx_enet.c  |2 +-
 cpu/ppc4xx/denali_spd_ddr2.c   |8 
 cpu/ppc4xx/tlb.c   |4 ++--
 cpu/ppc4xx/traps.c |   26 +-
 9 files changed, 31 insertions(+), 31 deletions(-)

diff --git a/board/amcc/katmai/cmd_katmai.c b/board/amcc/katmai/cmd_katmai.c
index 439be4f..703d225 100644
--- a/board/amcc/katmai/cmd_katmai.c
+++ b/board/amcc/katmai/cmd_katmai.c
@@ -176,7 +176,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int 
argc, char *argv[])
 #endif
}
 #ifdef DEBUG
-   printf( pin strap0 to write in i2c  = %x\n, data);
+   printf( pin strap0 to write in i2c  = %lx\n, data);
 #endif /* DEBUG */
 
if (i2c_write(chip, 0, 1, (uchar *)data, 4) != 0)
@@ -201,7 +201,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int 
argc, char *argv[])
data |= 0x05A5;
 
 #ifdef DEBUG
-   printf( pin strap1 to write in i2c  = %x\n, data);
+   printf( pin strap1 to write in i2c  = %lx\n, data);
 #endif /* DEBUG */
 
udelay(1000);
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
index 3dbb2e1..8765cc1 100644
--- a/board/esd/du440/du440.c
+++ b/board/esd/du440/du440.c
@@ -956,9 +956,9 @@ int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char 
*argv[])
ret = run_command (cmd, 0);
end = get_ticks();
 
-   printf(ticks=%d\n, (ulong)(end - start));
+   printf(ticks=%ld\n, (ulong)(end - start));
us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
-   printf(usec=%d\n, us);
+   printf(usec=%ld\n, us);
 
return ret;
 }
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index 0a13831..189e824 100644
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -84,7 +84,7 @@ void board_add_ram_info(int use_default)
puts( (ECC not);
 
get_sys_info(board_cfg);
-   printf( enabled, %d MHz, (board_cfg.freqPLB * 2) / 100);
+   printf( enabled, %ld MHz, (board_cfg.freqPLB * 2) / 100);
 
mfsdram(DDR0_03, val);
val = DDR0_03_CASLAT_DECODE(val);
diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c
index 0113d48..33d971a 100644
--- a/board/zeus/zeus.c
+++ b/board/zeus/zeus.c
@@ -280,7 +280,7 @@ static int restore_default(void)
} else {
crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4);
if (crc != *(u32 *)buf) {
-   printf(ERROR: crc mismatch %08lx %08lx\n, crc, *(u32 
*)buf);
+   printf(ERROR: crc mismatch %08x %08x\n, crc, *(u32 
*)buf);
return -1;
}
 
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 9a5340c..a27e276 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -378,7 +378,7 @@ static phys_size_t sdram_memsize(void)
mem_size+=4096;
break;
default:
-   printf(WARNING: Unsupported bank size 
(SDSZ=0x%x)!\n
+   printf(WARNING: Unsupported bank size 
(SDSZ=0x%lx)!\n
   , sdsz);
mem_size=0;
break;
@@ -860,8 +860,8 @@ static void check_rank_number(unsigned long *dimm_populated,
 
 
if (dimm_rank  MAXRANKS) {
-   printf(ERROR: DRAM DIMM detected with %d ranks 
in 
-  slot %d is not supported.\n, 
dimm_rank, dimm_num);
+   printf(ERROR: DRAM DIMM detected with %lu 
ranks in 
+  slot %lu is not supported.\n, 
dimm_rank, dimm_num);
printf(Only %d ranks are supported for all 
DIMM.\n, MAXRANKS);
printf(Replace the DIMM module with a 
supported DIMM.\n\n);
spd_ddr_init_hang ();
@@ -1062,7 +1062,7 @@ static void program_copt1(unsigned long *dimm_populated,
dimm_32bit = TRUE;
break;
default:
-   printf(WARNING: Detected a DIMM with a data 
width of %d bits.\n,
+   printf(WARNING: Detected a DIMM with a data 
width of %lu bits

[U-Boot-Users] [PATCH] rtc: Fix printf format warning in m41t60.c

2008-07-10 Thread Stefan Roese
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 drivers/rtc/m41t60.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/rtc/m41t60.c b/drivers/rtc/m41t60.c
index 8a32ea0..ef135ca 100644
--- a/drivers/rtc/m41t60.c
+++ b/drivers/rtc/m41t60.c
@@ -241,7 +241,7 @@ void rtc_reset(void)
 
if (l = 0x3F) {
if ((data[RTC_CTRL]  0x3F) != l) {
-   printf(Setting RTC calibration to 0x%02X\n,
+   printf(Setting RTC calibration to 0x%02lX\n,
   l);
data[RTC_CTRL] = 0xC0;
data[RTC_CTRL] |= (uchar) l;
-- 
1.5.6.2


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[U-Boot-Users] [PATCH] MTD/NAND: Fix printf format warning in nand code

2008-07-10 Thread Stefan Roese
This patch fixes NAND related printf format warning. Those warnings are
now visible since patch dc4b0b38d4aadf08826f6c31270f1eecd27964fd
[Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is
really helpful.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 common/cmd_nand.c|   12 ++--
 drivers/mtd/nand/nand.c  |2 +-
 drivers/mtd/nand/nand_util.c |6 +++---
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index e20c1af..cc7c5ba 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -55,11 +55,11 @@ static int nand_dump(nand_info_t *nand, ulong off)
off = ~(nand-oobblock - 1);
i = nand_read_raw(nand, buf, off, nand-oobblock, nand-oobsize);
if (i  0) {
-   printf(Error (%d) reading page %08x\n, i, off);
+   printf(Error (%d) reading page %08lx\n, i, off);
free(buf);
return 1;
}
-   printf(Page %08x dump:\n, off);
+   printf(Page %08lx dump:\n, off);
i = nand-oobblock  4; p = buf;
while (i--) {
printf( \t%02x %02x %02x %02x %02x %02x %02x %02x
@@ -149,7 +149,7 @@ out:
if (*size == nand-size)
puts(whole chip\n);
else
-   printf(offset 0x%x, size 0x%x\n, *off, *size);
+   printf(offset 0x%lx, size 0x%x\n, *off, *size);
return 0;
 }
 
@@ -181,7 +181,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char 
*argv[])
putc('\n');
for (i = 0; i  CFG_MAX_NAND_DEVICE; i++) {
if (nand_info[i].name)
-   printf(Device %d: %s, sector size %lu KiB\n,
+   printf(Device %d: %s, sector size %u KiB\n,
i, nand_info[i].name,
nand_info[i].erasesize  10);
}
@@ -238,7 +238,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char 
*argv[])
printf(\nDevice %d bad blocks:\n, nand_curr_device);
for (off = 0; off  nand-size; off += nand-erasesize)
if (nand_block_isbad(nand, off))
-   printf(  %08x\n, off);
+   printf(  %08lx\n, off);
return 0;
}
 
@@ -417,7 +417,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char 
*argv[])
if (off == nand-size - nand-oobblock
|| (s != last_status  off != 0))  {
 
-   printf(%08x - %08x: %8d pages 
%s%s%s\n,
+   printf(%08lx - %08lx: %8lu pages 
%s%s%s\n,
   block_start,
   off-1,
   (off-block_start)/nand-oobblock,
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index 27b5792..e44470e 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -70,7 +70,7 @@ void nand_init(void)
if (nand_curr_device == -1)
nand_curr_device = i;
}
-   printf(%lu MiB\n, size / (1024 * 1024));
+   printf(%u MiB\n, size / (1024 * 1024));
 
 #ifdef CFG_NAND_SELECT_DEVICE
/*
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index c82f77b..828cc33 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -154,7 +154,7 @@ int nand_erase_opts(nand_info_t *meminfo, const 
nand_erase_options_t *opts)
}
 
if (erase_length  meminfo-erasesize) {
-   printf(Warning: Erase size 0x%08x smaller than one\
+   printf(Warning: Erase size 0x%08lx smaller than one   \
   erase block 0x%08x\n,erase_length, meminfo-erasesize);
printf( Erasing 0x%08x instead\n, meminfo-erasesize);
erase_length = meminfo-erasesize;
@@ -498,7 +498,7 @@ int nand_write_opts(nand_info_t *meminfo, const 
nand_write_options_t *opts)
 * on (slow) serial consoles
 */
if (percent != percent_complete) {
-   printf(\rWriting data at 0x%x 
+   printf(\rWriting data at 0x%lx 
   -- %3d%% complete.,
   mtdoffset, percent);
percent_complete = percent;
@@ -678,7 +678,7 @@ int nand_read_opts(nand_info_t *meminfo, const 
nand_read_options_t *opts)
 */
if (percent != percent_complete) {
if (!opts-quiet)
-   printf(\rReading data from 0x%x 
+   printf(\rReading data from 0x%lx

[U-Boot-Users] [ppc4xx] Please pull git://www.denx.de/git/u-boot-ppc4xx.git

2008-07-10 Thread Stefan Roese
The following changes since commit ac5ba41c2234dd513ed2c879914e964cc05a0135:
  Stefan Roese (1):
Merge branch 'master' of /home/stefan/git/u-boot/u-boot

are available in the git repository at:

  git://www.denx.de/git/u-boot-ppc4xx.git master

Larry Johnson (2):
  ppc4xx: Update and add FDT to Korat board support
  ppc4xx: Remove implementation of testdram() from Korat board support

Stefan Roese (2):
  ppc4xx: Enable support for  2GB SDRAM on AMCC Katmai
  ppc4xx: Fix printf format warnings now visible with the updated format 
check

 board/amcc/katmai/cmd_katmai.c |4 +-
 board/esd/du440/du440.c|4 +-
 board/korat/korat.c|   74 
 board/lwmon5/sdram.c   |2 +-
 board/zeus/zeus.c  |2 +-
 cpu/ppc4xx/44x_spd_ddr2.c  |   64 ++
 cpu/ppc4xx/4xx_enet.c  |2 +-
 cpu/ppc4xx/denali_spd_ddr2.c   |8 ++--
 cpu/ppc4xx/tlb.c   |4 +-
 cpu/ppc4xx/traps.c |   26 +++---
 include/asm-ppc/ppc4xx-sdram.h |4 +-
 include/configs/katmai.h   |7 
 include/configs/korat.h|   11 --
 13 files changed, 128 insertions(+), 84 deletions(-)

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Re: [U-Boot-Users] usage of git to send patches to u-boot mailinglist

2008-07-10 Thread Stefan Roese
On Thursday 10 July 2008, Markus Klotzbücher wrote:
  So is this really the preferred workflow? How are others dealing with
  this?  How to avoid commitlog pollution?

 I never used quilt, but I believe stacked git (stgit) implements more or
 less the same behavior on top of git.

Yes, and guilt should be similar too. I'm looking forward to the guilt BOFS at 
OLS in a few weeks.

Best regards,
Stefan

=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: [EMAIL PROTECTED]
=

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[U-Boot-Users] [PATCH] ppc4xx: Fix include sequence in 4xx_pcie.c

2008-07-10 Thread Stefan Roese
This patch now moves common.h to the top of the inlcude list. This
is needed for boards with CONFIG_PHYS_64BIT set (e.g. katmai), so that
the phys_size_t/phys_addr_t are defined to the correct size in this
driver.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 cpu/ppc4xx/4xx_pcie.c |6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index d50a538..9803fcc 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -25,11 +25,11 @@
 #define DEBUG
 #endif
 
-#include asm/processor.h
-#include asm-ppc/io.h
-#include ppc4xx.h
 #include common.h
 #include pci.h
+#include ppc4xx.h
+#include asm/processor.h
+#include asm-ppc/io.h
 
 #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) ||\
 defined(CONFIG_460EX) || defined(CONFIG_460GT))  \
-- 
1.5.6.2


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Re: [U-Boot-Users] [PATCH] ppc4xx: Fix include sequence in 4xx_pcie.c

2008-07-10 Thread Stefan Roese
On Thursday 10 July 2008, Wolfgang Denk wrote:
 In message [EMAIL PROTECTED] you wrote:
  This patch now moves common.h to the top of the inlcude list. This
  is needed for boards with CONFIG_PHYS_64BIT set (e.g. katmai), so that
  the phys_size_t/phys_addr_t are defined to the correct size in this
  driver.
 
  Signed-off-by: Stefan Roese [EMAIL PROTECTED]
  ---
   cpu/ppc4xx/4xx_pcie.c |6 +++---
   1 files changed, 3 insertions(+), 3 deletions(-)

 Hm. I think we have a serious problem when the correctness of the code
 depends on the include order. It seems that include/asm-ppc/types.h
 depends on CONFIG_PHYS_64BIT, so include/asm-ppc/types.h must make
 sure this variable is set correctly, i. e. we should include common.h
 there.

Yes, I though too that this problem might affect other files too. But 
unfortunately including common.h from within asm/types.h does not work since 
common.h includes (and needs) types.h itself.

I have no elegant solution to handle this in a more generic way right now. 
Perhaps somebody else has? Ideas welcome. :)

Thanks.

Best regards,
Stefan

=
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: [EMAIL PROTECTED]
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Re: [U-Boot-Users] [PATCH] add 'license' command to u-boot?commandline

2008-07-10 Thread Stefan Roese
On Thursday 10 July 2008, Detlev Zundel wrote:
  IMHO, vim and xxd are essential programs so I'm OK with using
  xxd. OTOH, I understand some people actually prefer emacs and may have
  a problem with requiring vim to be installed.  ;-/

 Even though I'm an enthusiastic Emacs user, I have different reasons for
 my vote.  As far as build dependencies go, I'd like to restrict this to
 the LSB standard[1].  Xdd is not in there, so thats why I vote for the
 small C program (unless we can adapt the script and use 'od').

I would prefer this C program solution too.

Best regards,
Stefan

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[U-Boot-Users] [PATCH] ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boards

2008-07-10 Thread Stefan Roese
This patch removes some ft_board_setup() functions from some 4xx boards.
This can be done since we now have a default weak implementation for this
in cpu/ppc4xx/fdt.c. Only board in need for a different/custom
implementation like canyonlands need their own version.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 board/amcc/katmai/katmai.c |   21 -
 board/amcc/kilauea/kilauea.c   |   21 -
 board/amcc/makalu/makalu.c |   21 -
 board/amcc/sequoia/sequoia.c   |   21 -
 board/amcc/yosemite/yosemite.c |   21 -
 board/esd/pmc440/pmc440.c  |   21 -
 board/prodrive/alpr/alpr.c |   21 -
 cpu/ppc4xx/fdt.c   |   12 ++--
 8 files changed, 10 insertions(+), 149 deletions(-)

diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index 3a0b18f..f2bed5c 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -517,24 +517,3 @@ int post_hotkeys_pressed(void)
return (ctrlc());
 }
 #endif
-
-#if defined(CONFIG_OF_LIBFDT)  defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-   u32 val[4];
-   int rc;
-
-   ft_cpu_setup(blob, bd);
-
-   /* Fixup NOR mapping */
-   val[0] = 0; /* chip select number */
-   val[1] = 0; /* always 0 */
-   val[2] = gd-bd-bi_flashstart;
-   val[3] = gd-bd-bi_flashsize;
-   rc = fdt_find_and_setprop(blob, /plb/opb/ebc, ranges,
- val, sizeof(val), 1);
-   if (rc)
-   printf(Unable to update property NOR mapping, err=%s\n,
-  fdt_strerror(rc));
-}
-#endif /* defined(CONFIG_OF_LIBFDT)  defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index f30dc8f..7b10255 100644
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -374,24 +374,3 @@ int post_hotkeys_pressed(void)
return 0;   /* No hotkeys supported */
 }
 #endif /* CONFIG_POST */
-
-#if defined(CONFIG_OF_LIBFDT)  defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-   u32 val[4];
-   int rc;
-
-   ft_cpu_setup(blob, bd);
-
-   /* Fixup NOR mapping */
-   val[0] = 0; /* chip select number */
-   val[1] = 0; /* always 0 */
-   val[2] = gd-bd-bi_flashstart;
-   val[3] = gd-bd-bi_flashsize;
-   rc = fdt_find_and_setprop(blob, /plb/opb/ebc, ranges,
- val, sizeof(val), 1);
-   if (rc)
-   printf(Unable to update property NOR mapping, err=%s\n,
-  fdt_strerror(rc));
-}
-#endif /* defined(CONFIG_OF_LIBFDT)  defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
index 9baec9a..2b4d3d4 100644
--- a/board/amcc/makalu/makalu.c
+++ b/board/amcc/makalu/makalu.c
@@ -330,24 +330,3 @@ int post_hotkeys_pressed(void)
return 0;   /* No hotkeys supported */
 }
 #endif /* CONFIG_POST */
-
-#if defined(CONFIG_OF_LIBFDT)  defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-   u32 val[4];
-   int rc;
-
-   ft_cpu_setup(blob, bd);
-
-   /* Fixup NOR mapping */
-   val[0] = 0; /* chip select number */
-   val[1] = 0; /* always 0 */
-   val[2] = gd-bd-bi_flashstart;
-   val[3] = gd-bd-bi_flashsize;
-   rc = fdt_find_and_setprop(blob, /plb/opb/ebc, ranges,
- val, sizeof(val), 1);
-   if (rc)
-   printf(Unable to update property NOR mapping, err=%s\n,
-  fdt_strerror(rc));
-}
-#endif /* defined(CONFIG_OF_LIBFDT)  defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 5ff9787..b833092 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -509,24 +509,3 @@ int post_hotkeys_pressed(void)
return 0;   /* No hotkeys supported */
 }
 #endif /* CONFIG_POST */
-
-#if defined(CONFIG_OF_LIBFDT)  defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-   u32 val[4];
-   int rc;
-
-   ft_cpu_setup(blob, bd);
-
-   /* Fixup NOR mapping */
-   val[0] = 0; /* chip select number */
-   val[1] = 0; /* always 0 */
-   val[2] = gd-bd-bi_flashstart;
-   val[3] = gd-bd-bi_flashsize;
-   rc = fdt_find_and_setprop(blob, /plb/opb/ebc, ranges,
- val, sizeof(val), 1);
-   if (rc)
-   printf(Unable to update property NOR mapping, err=%s\n,
-  fdt_strerror(rc));
-}
-#endif /* defined(CONFIG_OF_LIBFDT)  defined

Re: [U-Boot-Users] [PATCH] USB: shutdown USB before booting

2008-07-10 Thread Stefan Roese
Hi Markus,

On Thursday 10 July 2008, Markus Klotzbücher wrote:
 This patch fixes a potentially serious issue related to USB which was
 discouvered by Martin Krause [EMAIL PROTECTED] and fixed for
 ARM920T. Martin wrote:

   Turn off USB to prevent the host controller from writing to the
   SDRAM while Linux is booting. This could happen, because the HCCA
   (Host Controller Communication Area) lies within the SDRAM and the
   host controller writes continously to this area (as busmaster!), for
   example to increase the HccaFrameNumber variable, which happens
   every 1 ms.

 This is a slightly modified version of the patch in order to shutdown
 USB when booting on all architectures.

Yes, I remember hearing of this problem. I thought it was already fixed. Seems 
not to be the case. Please find a comment below.

 Signed-off-by: Markus Klotzbuecher [EMAIL PROTECTED]
 ---
  common/cmd_bootm.c |   18 ++
  1 files changed, 18 insertions(+), 0 deletions(-)

 diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c

By implementing this usb_stop() in do_bootm() you prevent this problem in many 
cases (e.g. Linux booting). But unfortunately not in all cases. For 
example bootelf or bootvx are not fixed.

Can't this be solved in a different way. By calling usb_stop each time after 
an USB command completes. IIRC, this is how it is done in the U-Boot network 
implementation too.

What do you think?

Best regards,
Stefan

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Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: [EMAIL PROTECTED]
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[U-Boot-Users] [PATCH] print_size: Enable printing of = 4GB

2008-07-09 Thread Stefan Roese
Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 lib_generic/display_options.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/lib_generic/display_options.c b/lib_generic/display_options.c
index a52fa04..99aa443 100644
--- a/lib_generic/display_options.c
+++ b/lib_generic/display_options.c
@@ -45,7 +45,7 @@ int display_options (void)
 void print_size (phys_size_t size, const char *s)
 {
ulong m, n;
-   ulong d = 1  20;  /* 1 MB */
+   phys_size_t d = 1  20;/* 1 MB */
char  c = 'M';
 
if (size  d) { /* print in kB */
-- 
1.5.6.2


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[U-Boot-Users] [PATCH] ppc4xx: Enable support for 2GB SDRAM on AMCC Katmai

2008-07-09 Thread Stefan Roese
Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
To support such configurations, we only map the first 2GB via the TLB's. We
need some free virtual address space for the remaining peripherals like, SoC
devices, FLASH etc.

Note that ECC is currently not supported on configurations with more than 2GB
SDRAM. This is because we only map the first 2GB on such systems, and therefore
the ECC parity byte of the remaining area can't be written.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 cpu/ppc4xx/44x_spd_ddr2.c  |   58 +++
 include/asm-ppc/ppc4xx-sdram.h |4 +-
 include/configs/katmai.h   |7 +
 3 files changed, 55 insertions(+), 14 deletions(-)

diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index c28fc46..c70795d 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -138,6 +138,20 @@
 #endif
 
 /*
+ * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of 
SDRAM.
+ * To support such configurations, we only map the first 2GB via the TLB's. 
We
+ * need some free virtual address space for the remaining peripherals like, SoC
+ * devices, FLASH etc.
+ *
+ * Note that ECC is currently not supported on configurations with more than 
2GB
+ * SDRAM. This is because we only map the first 2GB on such systems, and 
therefore
+ * the ECC parity byte of the remaining area can't be written.
+ */
+#ifndef CONFIG_MAX_MEM_MAPPED
+#define CONFIG_MAX_MEM_MAPPED  ((phys_size_t)2  30)
+#endif
+
+/*
  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
  */
 void __spd_ddr_init_hang (void)
@@ -181,7 +195,7 @@ typedef enum ddr_cas_id {
 
/*-+
  * Prototypes
  
*-*/
-static unsigned long sdram_memsize(void);
+static phys_size_t sdram_memsize(void);
 static void get_spd_info(unsigned long *dimm_populated,
 unsigned char *iic0_dimm_addr,
 unsigned long num_dimm_banks);
@@ -306,9 +320,9 @@ static unsigned char spd_read(uchar chip, uint addr)
 
/*-+
  * sdram_memsize
  
*-*/
-static unsigned long sdram_memsize(void)
+static phys_size_t sdram_memsize(void)
 {
-   unsigned long mem_size;
+   phys_size_t mem_size;
unsigned long mcopt2;
unsigned long mcstat;
unsigned long mb0cf;
@@ -364,6 +378,8 @@ static unsigned long sdram_memsize(void)
mem_size+=4096;
break;
default:
+   printf(WARNING: Unsupported bank size 
(SDSZ=0x%x)!\n
+  , sdsz);
mem_size=0;
break;
}
@@ -371,8 +387,7 @@ static unsigned long sdram_memsize(void)
}
}
 
-   mem_size *= 1024 * 1024;
-   return(mem_size);
+   return mem_size  20;
 }
 
 
/*-+
@@ -400,7 +415,7 @@ phys_size_t initdram(int board_type)
unsigned long val;
ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
int write_recovery;
-   unsigned long dram_size = 0;
+   phys_size_t dram_size = 0;
 
num_dimm_banks = sizeof(iic0_dimm_addr);
 
@@ -558,6 +573,12 @@ phys_size_t initdram(int board_type)
/* get installed memory size */
dram_size = sdram_memsize();
 
+   /*
+* Limit size to 2GB
+*/
+   if (dram_size  CONFIG_MAX_MEM_MAPPED)
+   dram_size = CONFIG_MAX_MEM_MAPPED;
+
/* and program tlb entries for this size (dynamic) */
 
/*
@@ -595,7 +616,7 @@ phys_size_t initdram(int board_type)
 */
set_mcsr(get_mcsr());
 
-   return dram_size;
+   return sdram_memsize();
 }
 
 static void get_spd_info(unsigned long *dimm_populated,
@@ -2133,15 +2154,15 @@ static void program_memory_queue(unsigned long 
*dimm_populated,
 unsigned long num_dimm_banks)
 {
unsigned long dimm_num;
-   unsigned long rank_base_addr;
+   phys_size_t rank_base_addr;
unsigned long rank_reg;
-   unsigned long rank_size_bytes;
+   phys_size_t rank_size_bytes;
unsigned long rank_size_id;
unsigned long num_ranks;
unsigned long baseadd_size;
unsigned long i;
unsigned long bank_0_populated = 0;
-   unsigned long total_size = 0;
+   phys_size_t total_size = 0

Re: [U-Boot-Users] BDI3000 and PPC460GT board

2008-07-09 Thread Stefan Roese
Hi Vadim,

On Wednesday 09 July 2008, vb wrote:
 I am trying to control the amcc glacier (evkit460gt) eval board with a
 BDI3000, using the config file from
 ftp://78.31.64.234/bdigdb/config/powerpc/ppc4xx/ppc440/evkit460gt.cfg
 (modulo my local IP/tftp configuration).

I attached my local version for you. Perhaps this works better. It works here 
fine on my Glacier.

 The problem is that the board fails to run under the BDI control, and
 runs just fine without it.

 When looking closer I see that the bdi resets the board properly and
 takes it all the way to the point where the TLBs are set and the rfi
 instruction is executed to jump out of the original 4k window. At this
 point a TLB exception is thrown, that is it loos like TLB programming
 'did not take' while under BDI control. So, if I just reset the board
 and let it run, it keeps cycling through TLB error exception as no
 memory other than the top 4k bytes is accessible. Again, it works just
 fine without the BDI.

 Any hints and suggestions will be highly appreciated,

What command are you using to control the PPC? reset halt will run you 
initialization from the script and halt the PPC. reset run will skip this 
init and give just run the PPC (hopefully to the U-Boot prompt).

Best regards,
Stefan

=
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: [EMAIL PROTECTED]
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; bdiGDB configuration file for AMCC 460GT Evaluation Kit Glacier
; -
;
;
[INIT]
; Setup TLB
WTLB0xF095  0x4F3F  ;Boot Space 256MB
WTLB0x0094  0x003F  ;SDRAM 256MB @ 0x
WTLB0x9095  0x403F  ;ISRAM/OCM

; Setup Peripheral Bus
;
WDCR0x120x0010  ;Select EBC0_B0AP
WDCR0x130x10055e00
WDCR0x120x  ;Select EBC0_B0CR
WDCR0x130xfc0da000  ; 64MByte

; OCM
;WDCR0x20   0x40004580  ;16k


[TARGET]
JTAGCLOCK   1   ;use 8 MHz JTAG clock
CPUTYPE 440 ;the used target CPU type
WAKEUP  500 ;wakeup time after reset
BREAKMODE   HARD;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODEHWBP;JTAG or HWBP, HWBP uses one or two hardware 
breakpoints


[HOST]
IP  10.0.0.152
FILE/tftpboot/glacier/u-boot.bin
FORMAT  BIN
DUMP/tftpboot/glacier/dump.bin
PROMPT  460EX


[FLASH]
;WORKSPACE   0xe304  ;workspace in OCM
;WORKSPACE   0x7000  ;workspace in OCM
;WORKSPACE   0x9004  ;workspace in OCM
CHIPTYPEMIRRORX16;Flash type
CHIPSIZE0x100;The size of one flash chip in bytes
BUSWIDTH16  ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE/tftpboot/glacier/u-boot.bin
;FORMAT  BIN 0xFFF8
FORMAT  BIN 0xFFFA
;ERASE   0xFFF8  ;erase sector 4
ERASE   0xFFFA  ;erase sector 4
ERASE   0xFFFC  ;erase sector 4
ERASE   0xFFFE  ;erase sector 6


[REGS]
FILE/tftpboot/BDI2000/reg460ex.def

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Re: [U-Boot-Users] [PATCH][RFC] pci: Add check PCI bridge class (Re: [PATCH][RFC] pci: Remove CONFIG_PCI_SKIP_HOST_BRIDGE and Add check PCI class of host bridge)

2008-07-08 Thread Stefan Roese
Hi Nobuhiro,

On Tuesday 08 July 2008, Nobuhiro Iwamatsu wrote:
  c) CONFIG_PCI_CONFIG_HOST_BRIDGE is defined and the env variable
pciconfighost is defined too
 
  If I understand you correctly, then you have some PCI devices at BDF ==
  0,0,0 that need to be configured (and not skipped). Correct? If this is
  correct, wouldn't it be enough for you to use solution c) from above?

 Yes, Your indication is right. And there was the part which I did not
 understand.
 But, I think that there is still a problem only by these measures.

 For example, BDF == 0,0,0 are not displayed when I validated
 CONFIG_PCI_SCAN_SHOW.

Right, this is a problem.

 475 #ifdef CONFIG_PCI_SCAN_SHOW
 476 /* Skip our host bridge */
 477 if ( dev != PCI_BDF(hose-first_busno,0,0) ) {
 478 unsigned char int_line;
 479
 480 pci_hose_read_config_byte(hose, dev,
 PCI_INTERRUPT_LINE, 481   int_line);
 482 printf(%02x  %02x  %04x  %04x  %04x  %02x\n,
 483PCI_BUS(dev), PCI_DEV(dev), vendor, device, class,
 484int_line);
 485 }
 486 #endif

 I think that it is a problem to handle only  BDF == 0,0,0.
 I think that I had better check it in Class ID.
 (Of cource, I understand that my implementation is mean.)

Yes, switching to this class-ID check would be probably cleaner. The main 
problem I see with this is, that we could break backward compatibility. I 
really don't know if all boards currently using this Host-Bridge-Skipping 
implementation have the class-ID set to 0x0680 (Other bridge type).

So I suggest the following solution: I'll prepare a patch to move 
this Skip-device-check into a separate weak function with the current 
behavior. You (and others) can then define a custom Skip-device-check 
function in your platform code that overrides this default function.

I'll send this patch to the list in a short while. Please try it out and let 
me know if this works for you.

Best regards,
Stefan

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[U-Boot-Users] [PATCH] pci: Move PCI device configuration check into a separate weak function

2008-07-08 Thread Stefan Roese
This patch moves the check, if a device should be skipped in PCI PNP
configuration into the function pci_skip_dev(). This function is defined
as weak so that it can be overwritten by a platform specific one if
needed. The check if the device should get printed in the PCI summary upon
bootup (when CONFIG_PCI_SCAN_SHOW is defined) is moved to the function
pci_print_dev() which is also defined as weak too.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 drivers/pci/pci.c |   70 ++--
 1 files changed, 46 insertions(+), 24 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index b3ae3b1..16180cb 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -411,6 +411,40 @@ void pci_cfgfunc_do_nothing(struct pci_controller *hose,
 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 extern void pciauto_config_init(struct pci_controller *hose);
 
+int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
+{
+   /*
+* Check if pci device should be skipped in configuration
+*/
+   if (dev == PCI_BDF(hose-first_busno, 0, 0)) {
+#if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
+   /*
+* Only skip configuration if pciconfighost is not set
+*/
+   if (getenv(pciconfighost) == NULL)
+   return 1;
+#else
+   return 1;
+#endif
+   }
+
+   return 0;
+}
+int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
+   __attribute__((weak, alias(__pci_skip_dev)));
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
+{
+   if (dev == PCI_BDF(hose-first_busno, 0, 0))
+   return 0;
+
+   return 1;
+}
+int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
+   __attribute__((weak, alias(__pci_print_dev)));
+#endif /* CONFIG_PCI_SCAN_SHOW */
+
 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 {
unsigned int sub_bus, found_multi=0;
@@ -423,21 +457,10 @@ int pci_hose_scan_bus(struct pci_controller *hose, int 
bus)
 
for (dev =  PCI_BDF(bus,0,0);
 dev   PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
-dev += PCI_BDF(0,0,1))
-   {
-   /* Skip our host bridge */
-   if ( dev == PCI_BDF(hose-first_busno,0,0) ) {
-#if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE)  /* don't skip host 
bridge */
-   /*
-* Only skip hostbridge configuration if 
pciconfighost is not set
-*/
-   if (getenv(pciconfighost) == NULL) {
-   continue; /* Skip our host bridge */
-   }
-#else
-   continue; /* Skip our host bridge */
-#endif
-   }
+dev += PCI_BDF(0,0,1)) {
+
+   if (pci_skip_dev(hose, dev))
+   continue;
 
if (PCI_FUNC(dev)  !found_multi)
continue;
@@ -473,15 +496,14 @@ int pci_hose_scan_bus(struct pci_controller *hose, int 
bus)
hose-fixup_irq(hose, dev);
 
 #ifdef CONFIG_PCI_SCAN_SHOW
-   /* Skip our host bridge */
-   if ( dev != PCI_BDF(hose-first_busno,0,0) ) {
-   unsigned char int_line;
-
-   pci_hose_read_config_byte(hose, dev, 
PCI_INTERRUPT_LINE,
- int_line);
-   printf(%02x  %02x  %04x  %04x  %04x  
%02x\n,
-  PCI_BUS(dev), PCI_DEV(dev), vendor, device, 
class,
-  int_line);
+   if (pci_print_dev(hose, dev)) {
+   unsigned char int_line;
+
+   pci_hose_read_config_byte(hose, dev, 
PCI_INTERRUPT_LINE,
+ int_line);
+   printf(%02x  %02x  %04x  %04x  %04x  
%02x\n,
+  PCI_BUS(dev), PCI_DEV(dev), vendor, 
device, class,
+  int_line);
}
 #endif
}
-- 
1.5.6.2


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[U-Boot-Users] [PATCH] jedec_flash: Fix AM29DL800BB device ID

2008-07-08 Thread Stefan Roese
As pointed out by Jerry Hicks, this patch corrects the device ID of
the Spansion AM29DL800BB NOR device. Verified against latest Spansion
datasheet (rev C4 from Dezember 2006).

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 drivers/mtd/jedec_flash.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c
index b958d17..9845e93 100644
--- a/drivers/mtd/jedec_flash.c
+++ b/drivers/mtd/jedec_flash.c
@@ -42,7 +42,7 @@
 #define MANUFACTURER_SST   0x00BF
 
 /* AMD */
-#define AM29DL800BB0x22C8
+#define AM29DL800BB0x22CB
 #define AM29DL800BT0x224A
 
 #define AM29F800BB 0x2258
-- 
1.5.6.2


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Re: [U-Boot-Users] PATCH: drivers/mtd/jedec_flash.c (typo)

2008-07-08 Thread Stefan Roese
On Monday 07 July 2008, Jerry Hicks wrote:
 We were using a custom driver written by Andy Lowe of Montavista.
 He had a #define local to our flash.c implementation when I noticed
 the discrepancy between his local definition and the one in the u-boot
 header.

 On our hardware it works with 0x22CB but not with 0x22C8.

 The current documentation from Spansion also shows it as 0x22CB.

 http://www.spansion.com/datasheets/21519c4.pdf

I created an official patch for this and applied it to the cfi_flash 
repository. I'll send the pull request soon.

Thanks.

Best regards,
Stefan

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[U-Boot-Users] [cfi-flash] Please pull git://www.denx.de/git/u-boot-cfi-flash.git

2008-07-08 Thread Stefan Roese
The following changes since commit c956717ab25c962ef49d49064dfc73f4edcba1fb:
  Wolfgang Denk (1):
Merge branch 'master' of /home/wd/git/u-boot/custodians

are available in the git repository at:

  git://www.denx.de/git/u-boot-cfi-flash.git master

Stefan Roese (1):
  jedec_flash: Fix AM29DL800BB device ID

 drivers/mtd/jedec_flash.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

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Re: [U-Boot-Users] [PATCH] Fix a missing include for the lwmon5 dspic init POST.

2008-07-07 Thread Stefan Roese
On Friday 30 May 2008, Wolfgang Denk wrote:
 In message [EMAIL PROTECTED] you
 wrote: ...

  -   while (!gpio_read_in_bit(CFG_GPIO_DSPIC_READY)  reg++  1000) {
  +   while (gpio_read_in_bit(CFG_GPIO_DSPIC_READY)  reg++  1000) {
  udelay(1000);
  }
  -   gpio_write_bit(CFG_GPIO_HIGHSIDE, 0);
  if (gpio_read_in_bit(CFG_GPIO_DSPIC_READY)) {
  /* set boot error flag */
  out_be32((void *)CFG_DSPIC_TEST_ADDR,
  in_be32((void *)CFG_DSPIC_TEST_ADDR) |
  CFG_DSPIC_TEST_MASK);
  +   } else {
  +   /* dspic ready - disable LSB transmitter */
  +   gpio_write_bit(CFG_GPIO_HIGHSIDE, 0);

 Description and patch don't match. Please fix.

Sascha, any updates here?

Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] Change GPIO to control the LSB transmitter on lwmon5 board.

2008-07-07 Thread Stefan Roese
On Friday 30 May 2008, [EMAIL PROTECTED] wrote:
 From: Sascha Laue [EMAIL PROTECTED]


 Signed-off-by: Sascha Laue [EMAIL PROTECTED]

Patch does not apply. Seems to depend on other patches from you that are not 
applied yet. Please number such dependant patches next time using the -n 
option in git-format-patch.

So, please fix and resubmit. Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] Fix lwmon5 dsp POST sequence.

2008-07-07 Thread Stefan Roese
On Friday 30 May 2008, Wolfgang Denk wrote:
 In message [EMAIL PROTECTED] you 
wrote:
  +   /* momorize fpga status */

 momorize ?

Sascha, please fix and resubmit. Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] Release status - things to be done

2008-07-07 Thread Stefan Roese
Hi Wolfgang,

On Sunday 06 July 2008, Wolfgang Denk wrote:
 Open question:

snip

  2994  05/30 [EMAIL PROTECTED]  [U-Boot-Users] [PATCH] Change GPIO to
 control the LSB transmitter on lwmon5 board. - for ppc_4xx custodian

Forgot about that, sorry. I checked and it doesn't apply. Seems to be depend 
on other non-applied patches. I asked Sascha to resubmit.

snip

  3766  06/12 Brian S. ParkRe: [U-Boot-Users] U-Boot and Linux on
 Walnut based board - problem confirmed, to be taken care of by PPC4xx
 custodian.

I just tested with current TOT U-Boot (c956717a) and it works (again). Not 
sure what caused this problem though.

  3828  06/14 Larry Johnson  [U-Boot-Users] [PATCH] ppc4xx: Update and
 add FDT to Korat board support 3829  06/14 Larry Johnson 
 [U-Boot-Users] [PATCH] pp44xx: Remove implementation of testdram() from
 Korat board support - for ppc4xx custodian

This was submitted *after* the merge window closed. So I staged it into my 
internal next branch. Or should I apply those patches to master and ask you 
to pull them now?

  3871  06/16 Stefan Roese   [U-Boot-Users] [PATCH] cfi-flash: Fix
 problem in flash_toggle(), busy was not detected reliably - for CFI-Flash
 custodian

Already applied:

fb8c061ea05fc68d37e2a8b9f8c949d76c8d71a8

  3905  06/17 Nobuhiro Iwamats  Re: [U-Boot-Users] [PATCH][RFC] pci: Remove
 CONFIG_PCI_SKIP_HOST_BRIDGE and Add check PCI class 3908  06/17 Nobuhiro
 Iwamatsu  [PATCH][RFC] pci: Add check PCI bridge class (Re: [U-Boot-Users]
 [PATCH][RFC] pci: Remove CONFI - asked other users (Stefan Roese) for
 feedback

Will review and test today/tomorrow.

  4026  06/18 Jason McMullan [U-Boot-Users] [PATCH] mtd: SPI Flash:
 Winbond W25X16/WX2532/WX2564 support 4027  06/19 Jason McMullan
 [U-Boot-Users] [PATCH] mtd: SPI Flash: Support the ST Microelectronics
 M25P80 and M25P40 4028  06/19 McMullan, Jason  [U-Boot-Users] MTD Winbond
 and MTD STMicro SPI Flash Support - for MTD custodian

MTD custodian? We don't have one. Should I put those patches in my cfi-flash 
custodian repository?

Again, those patches were submitted *after* the merge windows closed. So I 
would normally queue them for the next merge window. Please let me know if 
you want to merge them now.

Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] Release status - things to be done

2008-07-07 Thread Stefan Roese
On Monday 07 July 2008, Wolfgang Denk wrote:
 In message [EMAIL PROTECTED] you wrote:
3766  06/12 Brian S. ParkRe: [U-Boot-Users] U-Boot and Linux on
   Walnut based board - problem confirmed, to be taken care of by PPC4xx
   custodian.
 
  I just tested with current TOT U-Boot (c956717a) and it works (again).
  Not sure what caused this problem though.

 Well, the bug is bisectable, IIRC.

 I would like to be sure that the bug ius really fixed now, and will
 not show up in the next version again.

 Could you please check?

OK, I'll try to find some time today to do this too.

3828  06/14 Larry Johnson  [U-Boot-Users] [PATCH] ppc4xx: Update
   and add FDT to Korat board support 3829  06/14 Larry Johnson
   [U-Boot-Users] [PATCH] pp44xx: Remove implementation of testdram() from
   Korat board support - for ppc4xx custodian
 
  This was submitted *after* the merge window closed. So I staged it into
  my internal next branch. Or should I apply those patches to master and
  ask you to pull them now?

 Your decision. I was asking because I didn't see any feedback.

I would like to get those patches pushed upstream now. I'll pull them into my 
custodian repo and ask for a pull soon.

4026  06/18 Jason McMullan [U-Boot-Users] [PATCH] mtd: SPI Flash:
   Winbond W25X16/WX2532/WX2564 support 4027  06/19 Jason McMullan
   [U-Boot-Users] [PATCH] mtd: SPI Flash: Support the ST Microelectronics
   M25P80 and M25P40 4028  06/19 McMullan, Jason  [U-Boot-Users] MTD
   Winbond and MTD STMicro SPI Flash Support - for MTD custodian
 
  MTD custodian? We don't have one. Should I put those patches in my
  cfi-flash custodian repository?

 s/MTD/NAND/. I think SPI flash code should be  handled  by  the  NAND
 custodian - Scott?

Ufff. :)

Best regards,
Stefan

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Re: [U-Boot-Users] Release status - things to be done

2008-07-07 Thread Stefan Roese
On Monday 07 July 2008, Stefan Roese wrote:
 3766  06/12 Brian S. ParkRe: [U-Boot-Users] U-Boot and Linux
on Walnut based board - problem confirmed, to be taken care of by
PPC4xx custodian.
  
   I just tested with current TOT U-Boot (c956717a) and it works (again).
   Not sure what caused this problem though.
 
  Well, the bug is bisectable, IIRC.
 
  I would like to be sure that the bug ius really fixed now, and will
  not show up in the next version again.
 
  Could you please check?

 OK, I'll try to find some time today to do this too.

I found the time. Unfortunately it was not easy to bisect since 4xx was not 
buildable for quite some time. So I had to manually bisect. The commit that 
fixes this issue is:

c821b5f120bedf73867513466412587c6912a8f8

ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling

This patch (Part 1 of 2):

* Rolls up a suite of changes to enable correct primordial stack and
  global data handling when the data cache is used for such a purpose
  for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).

* Related to the first, unifies DDR2 SDRAM and ECC initialization by
  eliminating redundant ECC initialization implementations and moving
  redundant SDRAM initialization out of board code into shared 4xx
  code.

* Enables MCSR visibility on the 405EX(r).

* Enables the use of the data cache for initial RAM on
  both AMCC's Kilauea and Makalu and removes a redundant
  CFG_POST_MEMORY flag from each board's CONFIG_POST value.

  - Removed, per Stefan Roese's request, defunct memory.c file for
Makalu and rolled sdram_init from it into makalu.c.

With respect to the 4xx DDR initialization and ECC unification, there
is certainly more work that can and should be done (file renaming,
etc.). However, that can be handled at a later date on a second or
third pass. As it stands, this patch moves things forward in an
incremental yet positive way for those platforms that utilize this
code and the features associated with it.

Signed-off-by: Grant Erickson [EMAIL PROTECTED]
Signed-off-by: Stefan Roese [EMAIL PROTECTED]


So it seems to have been a problem with the INIT RAM in D-cache which got 
fixed by Grant's patch here. Thanks again to Grant for all his great work.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH] add 'license' comma nd to u-boot commandline

2008-07-07 Thread Stefan Roese
On Monday 07 July 2008, Detlev Zundel wrote:
 Hi,

   [PATCH] add 'license' command to u-boot command line
  
   The 'license' command includes the u-boot license (GPLv2) into the
   actual bootloader binary.  The license text can be shown interactively
   at the u-boot commandline.

 I second such an addition.

Ack from me too.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH][RFC] pci: Add che ck PCI bridge class (Re: [PATCH][RFC] pci: Remove CONFIG_PCI_SKIP_HOST_BRIDGE and Add check PCI class of host bridge)

2008-07-07 Thread Stefan Roese
Hi Nobuhiro,

sorry about the late reply.

On Tuesday 17 June 2008, Nobuhiro Iwamatsu wrote:
 In current source code, when the device number of PCI is 0, process PCI
 bridge without fail. However, when the device number is 0, it is not PCI
 always bridge. There are times when device of PCI allocates.

 This patch add check PCI bridge class.

   - 0x0604 PCI to AGP bridge / PCI to PCI bridge
   - 0x0605 PCI to PCMCIA bridge
   - 0x0606 Nu Bus bridge
   - 0x0607 PCMCIA CardBus controller
   - 0x0608 RACEWay bridge

I now finally took the time to take a closer look at this issue. Your approach 
doesn't look clean to me. To be honsest, the original code isn't clean 
either. But with your addition it really get confusing. At least for me.

So let me summarize what the current code (without your patch) does and 
perhaps you could write again what exactly you want to fix/change. And please 
correct me if I am wrong.

Currently, the configuration of the PCI device at BDF == 0,0,0 will be skipped 
if:

a) CONFIG_PCI_CONFIG_HOST_BRIDGE is not defined

or

b) CONFIG_PCI_CONFIG_HOST_BRIDGE is defined but the env variable
   pciconfighost is not defined

So this PCI device will get configured if:

c) CONFIG_PCI_CONFIG_HOST_BRIDGE is defined and the env variable
   pciconfighost is defined too

If I understand you correctly, then you have some PCI devices at BDF == 0,0,0 
that need to be configured (and not skipped). Correct? If this is correct, 
wouldn't it be enough for you to use solution c) from above?

If this is not the case, then please explain again exactly what you need to 
achieve.

Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] [PATCH 2/3] Add initial PPC460SX reference board (redwood) config file and defines.

2008-07-04 Thread Stefan Roese
On Friday 04 July 2008, [EMAIL PROTECTED] wrote:
 From: Feng Kan [EMAIL PROTECTED]

 Add config file for AMCC redwood reference board for PPC460SX.
 Also include defines for PPC460SX processor.

Thanks. Please find some review comments below.

 Signed-off-by: Feng Kan [EMAIL PROTECTED]
 ---
  include/asm-ppc/ppc4xx-sdram.h |3 +-
  include/asm-ppc/processor.h|4 +
  include/configs/redwood.h  |  211
  include/ppc440.h   |  
 20 +++--
  include/ppc4xx.h   |3 +-
  5 files changed, 232 insertions(+), 9 deletions(-)
  create mode 100644 include/configs/redwood.h

 diff --git a/include/asm-ppc/ppc4xx-sdram.h
 b/include/asm-ppc/ppc4xx-sdram.h index 83931f1..6eb8209 100644
 --- a/include/asm-ppc/ppc4xx-sdram.h
 +++ b/include/asm-ppc/ppc4xx-sdram.h
 @@ -282,7 +282,8 @@
   * Memory Bank 0-7 configuration
   */
  #if defined(CONFIG_440SPE) || \
 -defined(CONFIG_460EX) || defined(CONFIG_460GT)
 +defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
 +defined(CONFIG_460SX)
  #define SDRAM_RXBAS_SDBA_MASK0xFFE0  /* Base address 
 */
  #define SDRAM_RXBAS_SDBA_ENCODE(n)   u32)(n))0xFFE0)2)
  #define SDRAM_RXBAS_SDBA_DECODE(n)   u32)(n))0xFFE0)2)
 diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
 index 5b50679..7f1e34f 100644
 --- a/include/asm-ppc/processor.h
 +++ b/include/asm-ppc/processor.h
 @@ -810,6 +810,10 @@
  #define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
  #define PVR_460GT_SE_RA  0x130218A0 /* 460GT rev A with Security Engine  
  
 */ #define PVR_460GT_RA   0x130218A1 /* 460GT rev A without Security 
 Engine
 */ +#define PVR_460SX_RA0x13541800 /* 460SX rev A   */
 +#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security
 disabled */ +#define PVR_460GX_RA0x13541802 /* 460GX rev A 
  */ +#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1
 Security disabled */ #define PVR_601  0x0001
  #define PVR_602  0x0005
  #define PVR_603  0x0003
 diff --git a/include/configs/redwood.h b/include/configs/redwood.h
 new file mode 100644
 index 000..bf4468b
 --- /dev/null
 +++ b/include/configs/redwood.h
 @@ -0,0 +1,211 @@
 +/*
 + * Configuration for AMCC 460SX Ref (redwood)
 + *
 + * (C) Copyright 2008
 + * Feng Kan, Applied Micro Circuits Corp., [EMAIL PROTECTED]
 + *
 + * See file CREDITS for list of people who contributed to this
 + * project.
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 of
 + * the License, or (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 + * MA 02111-1307 USA
 + */
 +#ifndef __CONFIG_H
 +#define __CONFIG_H
 +
 +/*---
 + * High Level Configuration Options
 + *--*/
 +#define CONFIG_4xx   1   /* ... PPC4xx family*/
 +#define CONFIG_440   1   /* ... PPC460 family*/
 +#define CONFIG_460SX 1   /* ... PPC460 family*/
 +#define CONFIG_BOARD_EARLY_INIT_F1   /* Call board_pre_init  */
 +
 +/*---
 + * Include common defines/options for all AMCC boards
 + *--*/
 +#define CONFIG_HOSTNAME  redwood
 +
 +#include amcc-common.h
 +
 +#define CONFIG_SYS_CLK_FREQ  /* external freq to pll */
 +
 +/*---
 + * Base addresses -- Note these are effective addresses where the
 + * actual resources get mapped (not physical addresses)
 + *--*/
 +#define CFG_FLASH_BASE   0xfff0  /* start of FLASH   
 */
 +#define CFG_PERIPHERAL_BASE  0xa000  /* internal peripherals */
 +#define CFG_ISRAM_BASE   0x9000  /* internal SRAM
 */
 +
 +#define CFG_PCI_BASE 0xd000  /* internal PCI regs*/
 +
 +#define CFG_PCIE_MEMBASE0x9000  /* mapped PCIe memory   */
 +#define CFG_PCIE0_MEMBASE   0x9000  /* mapped PCIe memory   */
 +#define CFG_PCIE1_MEMBASE 

Re: [U-Boot-Users] [PATCH 3/3] Initial framework of the AMCC PPC460SX redwood reference board.

2008-07-04 Thread Stefan Roese
On Friday 04 July 2008, [EMAIL PROTECTED] wrote:
 From: Feng Kan [EMAIL PROTECTED]

 Add AMCC Redwood reference board that uses the latest
 PPC 464 CPU processor combined with a rich mix of peripheral
 controllers. The board will support PCIe, mutiple Gig ethernet
 ports, advanced hardware RAID assistance and IEEE 1588.

Please find some review comments below.

 Signed-off-by: Feng Kan [EMAIL PROTECTED]
 ---
  MAINTAINERS   |3 +
  MAKEALL   |1 +
  Makefile  |3 +
  board/amcc/redwood/Makefile   |   50 
  board/amcc/redwood/config.mk  |   42 
  board/amcc/redwood/init.S |   77 +++
  board/amcc/redwood/redwood.c  |  496
 + board/amcc/redwood/redwood.h  |  
 50 
  board/amcc/redwood/u-boot.lds |  147 
  9 files changed, 869 insertions(+), 0 deletions(-)
  create mode 100644 board/amcc/redwood/Makefile
  create mode 100644 board/amcc/redwood/config.mk
  create mode 100644 board/amcc/redwood/init.S
  create mode 100644 board/amcc/redwood/redwood.c
  create mode 100644 board/amcc/redwood/redwood.h
  create mode 100644 board/amcc/redwood/u-boot.lds

snip

 diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c
 new file mode 100644
 index 000..0587e39
 --- /dev/null
 +++ b/board/amcc/redwood/redwood.c
 @@ -0,0 +1,496 @@
 +/*
 + * This is the main board level file for the Redwood AMCC board.
 + *
 + * (C) Copyright 2008
 + * Feng Kan, Applied Micro Circuits Corp., [EMAIL PROTECTED]
 + *
 + * See file CREDITS for list of people who contributed to this
 + * project.
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 of
 + * the License, or (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 + * MA 02111-1307 USA
 + *
 + */
 +
 +#include common.h
 +#include redwood.h
 +#include ppc4xx.h
 +#include asm/processor.h
 +#include i2c.h
 +#include asm-ppc/io.h
 +
 +int compare_to_true(char *str);
 +char *remove_l_w_space(char *in_str);
 +char *remove_t_w_space(char *in_str);
 +int get_console_port(void);
 +
 +static void early_init_EBC(void);
 +static int bootdevice_selected(void);
 +static void early_reinit_EBC(int);
 +static void early_init_UIC(void);
 +
 +/*
+ +| Define Boot devices
 ++-
---*/ +#define BOOT_FROM_8BIT_SRAM 0x00
 +#define BOOT_FROM_16BIT_SRAM 0x01
 +#define BOOT_FROM_32BIT_SRAM 0x02
 +#define BOOT_FROM_8BIT_NAND  0x03
 +#define BOOT_FROM_16BIT_NOR  0x04
 +#define BOOT_DEVICE_UNKNOWN  0xff
 +
 +/*
+ +| EBC Devices Characteristics
 +|   Peripheral Bank Access Parameters   -   EBC_BxAP
 +|   Peripheral Bank Configuration Register  -   EBC_BxCR
 ++-
---*/ +
 +/*
 + * 8 bit width SRAM
 + * BU Value
 + * BxAP : 0x0380  - 0 0111 0 00 00 00 00 00 000 0 0 0 0 0
 + * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0
 + * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0
 + */
 +#define EBC_BXAP_8BIT_SRAM  EBC_BXAP_BME_DISABLED   | \
 +EBC_BXAP_TWT_ENCODE(7)  | \
 +EBC_BXAP_BCE_DISABLE| \
 +EBC_BXAP_BCT_2TRANS | \
 +EBC_BXAP_CSN_ENCODE(0)  | \
 +EBC_BXAP_OEN_ENCODE(0)  | \
 +EBC_BXAP_WBN_ENCODE(0)  | \
 +EBC_BXAP_WBF_ENCODE(0)  | \
 +EBC_BXAP_TH_ENCODE(0)   | \
 +EBC_BXAP_RE_DISABLED| \
 +EBC_BXAP_SOR_DELAYED| \
 +EBC_BXAP_BEM_WRITEONLY  | \
 +EBC_BXAP_PEN_DISABLED
 +
 +#define EBC_BXAP_16BIT_SRAM  EBC_BXAP_8BIT_SRAM
 +#define EBC_BXAP_32BIT_SRAM  EBC_BXAP_8BIT_SRAM
 +
 +/*
 + * NAND flash
 + * BU Value
 + * BxAP : 0x048ff240  - 0 0111 0 00 00 00 00 00 

Re: [U-Boot-Users] [PATCH 1/3] Add initial PPC460SX defines for the cpu/ppc4xx directory.

2008-07-04 Thread Stefan Roese
Hi Feng,

On Friday 04 July 2008, [EMAIL PROTECTED] wrote:
 From: Feng Kan [EMAIL PROTECTED]

 Add AMCC PPC460SX defines to prep for new 460SX boards.

Thanks.

One general comment:

Could you please add ppc4xx:  as the first word in your patch 
description/subject? For all 4xx related patches. This way the patches are 
easier to differentiate from other subsystem patches.

Example:

ppc4xx: Add initial PPC460SX defines for the cpu/ppc4xx directory

Thanks.

Best regards,
Stefan

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Re: [U-Boot-Users] Problem with the prompt

2008-07-02 Thread Stefan Roese
On Wednesday 02 July 2008, navin karnam wrote:
 When u-boot is loaded on board following messages come on my board.

 U-Boot 1.3.3 (Jul  2 2008 - 10:34:34)

 DRAM:  256 MB
 ERROR: too many flash sectors



 Flash: 64 MB
 *** Warning - bad CRC, using default environment


 In:serial
 Out:   serial
 Err:   serial

 $

I suggest that you first solve the problem above with the too many flash 
sectors. Most like you only need to increase CFG_MAX_FLASH_SECT in your 
board config file.

Best regards,
Stefan

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Re: [U-Boot-Users] CPU (405ep) clock upgrade..

2008-07-02 Thread Stefan Roese
On Wednesday 02 July 2008, Yi-Neng Lin wrote:
  This arises another question. Assume that both configurations (CPU and
 SDRAM) are obtained from the EEPROM, how can C program/function be adopted
 to use these parameters before CPU/memory is initiated? C
 programs/functions need memory space to setup the stacks, which means
 CPU/memory initialization should be done (via assembly) before any C
 programs/functions can be used.

All this is already taken care of. U-Boot uses a small area for initial RAM. 
Sometimes in D-cache, sometimes in onboard SRAM (SoC). IIRC, the 405EP has 
OCM, so this could be used here. You just need to configure this correctly in 
your board config file. Again I suggest you take a look at the zeus board as 
an example.

Best regards,
Stefan

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Re: [U-Boot-Users] Using DDR1 in AMCC 460EX custom design

2008-07-01 Thread Stefan Roese
Felix,

On Tuesday 01 July 2008, Felix Radensky wrote:
 Thanks a lot for a very useful info. I'll ask hardware designers to be
 in contact
 with AMCC. Did you have a chance to test ECC enabled DDR2 on Canyonlands ?

No. I don't have SODIMM with ECC. But I don't expect bigger problems here, 
since this code is tested with ECC enabled on other 4xx platforms like the 
AMCC Katmai 440SPe eval board.

Best regards,
Stefan

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[U-Boot-Users] [PATCH] ppc4xx: Fix 460EX/GT PCIe port initialization

2008-07-01 Thread Stefan Roese
This patch fixes a bug where the 460EX/GT PCIe UTLSET1 register was
configured incorrectly. Thanks to Olga Buchonina from AMCC for pointing
this out.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 cpu/ppc4xx/4xx_pcie.c |   12 +---
 1 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 503facc..d50a538 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -615,22 +615,20 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
 {
-   u32 val = 1  24;
+   u32 val;
u32 utlset1;
 
-   if (rootport) {
+   if (rootport)
val = PTYPE_ROOT_PORT  20;
-   utlset1 = 0x2122;
-   } else {
+   else
val = PTYPE_LEGACY_ENDPOINT  20;
-   utlset1 = 0x2022;
-   }
 
if (port == 0) {
val |= LNKW_X1  12;
+   utlset1 = 0x2000;
} else {
val |= LNKW_X4  12;
-   utlset1 |= 0x00101101;
+   utlset1 = 0x20101101;
}
 
SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
-- 
1.5.6.1


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Re: [U-Boot-Users] CPU (405ep) clock upgrade..

2008-06-30 Thread Stefan Roese
On Monday 30 June 2008, Yi-Neng Lin (林義能) wrote:
 We've got a board powered by 405ep running at 266MHz. Now we want to
 upgrade the clock rate to 333MHz (model: 3LB333C), can anyone give us
 some pointers doing this? I've tried to search the mailing list but
 found nothing quite related. Also there seems to exist very limited
 ports, if not none, of this model to which I may reference.

There are quite a big number of 405EP board ports. I suspect that some of them 
are capable of running with 333MHz. The frequencies are usually configured 
via the I2C bootstrap EEPROM.

 Below are questions that are more specific:
 1. For CPU clock rate configuration, exactly what parameters should I
 modify? The suspected ones are FWDV (Feedback Divide) and FBDVB (Forward
 Divide B) which according to the processor user manual determines the
 PLLOUT A.

Sure. You need to configure the PLL parameters accordingly. The 405EP users 
manual should give you all the infos you need.

 2. SDRAM clocking. I guess the clocking should be adapted to something
 like 111MHz (given the 333MHz CPU clock); however, the manual shows
 there there seems to be only two options, namely 100MHz and 133MHz.

Which SDRAM init code are you using? I suggest that you take a look at 
cpu/ppc4xx/sdram.c and use this file on your system too. You only need to 
configure some SDRAM chip parameters (for example include/configs/zeus.h):

/*
 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
 */
#define CONFIG_SDRAM_BANK0  1   /* init onboard SDRAM bank 0 */
#define CONFIG_SDRAM_BANK1  1   /* init onboard SDRAM bank 1 */

/* SDRAM timings used in datasheet */
#define CFG_SDRAM_CL3   /* CAS latency */
#define CFG_SDRAM_tRP   20  /* PRECHARGE command period */
#define CFG_SDRAM_tRC   66  /* ACTIVE-to-ACTIVE command period */
#define CFG_SDRAM_tRCD  20  /* ACTIVE-to-READ delay */
#define CFG_SDRAM_tRFC  66  /* Auto refresh period */

 3. Clocking of others such as PCI (on-chip PLB clock, sync/async PCI
 clock) and serial port. Are they supposed to be modified accordingly?
 4. Any other parameters?

You need to make sure that all frequencies are in range.

Best regards,
Stefan

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[U-Boot-Users] [PATCH] ppc4xx: Cleanup Katmai Yucca PCIe register usage

2008-06-30 Thread Stefan Roese
This patch cleans up the 440SPe PCIe register usage. Now only defines
from the include/asm-ppc/4xx_pcie.h are used.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 board/amcc/katmai/katmai.c |   72 +---
 board/amcc/yucca/yucca.c   |   62 -
 include/configs/katmai.h   |1 -
 3 files changed, 8 insertions(+), 127 deletions(-)

diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index 3a0b18f..42f0514 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -349,7 +349,7 @@ int is_pci_host(struct pci_controller *hose)
return 1;
 }
 
-int katmai_pcie_card_present(int port)
+static int katmai_pcie_card_present(int port)
 {
u32 val;
 
@@ -437,76 +437,6 @@ void pcie_setup_hoses(int busno)
 }
 #endif /* defined(CONFIG_PCI) */
 
-int misc_init_f (void)
-{
-   uint reg;
-#if defined(CONFIG_STRESS)
-   uint i ;
-   uint disp;
-#endif
-
-   /* minimal init for PCIe */
-#if 0 /* test-only: test endpoint at some time, for now rootpoint only */
-   /* pci express 0 Endpoint Mode */
-   mfsdr(SDR0_PE0DLPSET, reg);
-   reg = (~0x0040);
-   mtsdr(SDR0_PE0DLPSET, reg);
-#else
-   /* pci express 0 Rootpoint  Mode */
-   mfsdr(SDR0_PE0DLPSET, reg);
-   reg |= 0x0040;
-   mtsdr(SDR0_PE0DLPSET, reg);
-#endif
-   /* pci express 1 Rootpoint  Mode */
-   mfsdr(SDR0_PE1DLPSET, reg);
-   reg |= 0x0040;
-   mtsdr(SDR0_PE1DLPSET, reg);
-   /* pci express 2 Rootpoint  Mode */
-   mfsdr(SDR0_PE2DLPSET, reg);
-   reg |= 0x0040;
-   mtsdr(SDR0_PE2DLPSET, reg);
-
-#if defined(CONFIG_STRESS)
-   /*
-* All this setting done by linux only needed by stress an charac. test
-* procedure
-* PCIe 1 Rootpoint PCIe2 Endpoint
-* PCIe 0 FIR Pre-emphasis Filter Coefficients  Transmit Driver Power 
Level
-*/
-   for (i=0,disp=0; i8; i++,disp+=3) {
-   mfsdr(SDR0_PE0HSSSET1L0+disp, reg);
-   reg |= 0x3300;
-   mtsdr(SDR0_PE0HSSSET1L0+disp, reg);
-   }
-
-   /*PCIe 1 FIR Pre-emphasis Filter Coefficients  Transmit Driver Power 
Level */
-   for (i=0,disp=0; i4; i++,disp+=3) {
-   mfsdr(SDR0_PE1HSSSET1L0+disp, reg);
-   reg |= 0x3300;
-   mtsdr(SDR0_PE1HSSSET1L0+disp, reg);
-   }
-
-   /*PCIE 2 FIR Pre-emphasis Filter Coefficients  Transmit Driver Power 
Level */
-   for (i=0,disp=0; i4; i++,disp+=3) {
-   mfsdr(SDR0_PE2HSSSET1L0+disp, reg);
-   reg |= 0x3300;
-   mtsdr(SDR0_PE2HSSSET1L0+disp, reg);
-   }
-
-   reg = 0x2124;
-   mtsdr(SDR0_PE2UTLSET1, reg);
-   reg = 0x1100;
-   mtsdr(SDR0_PE2UTLSET2, reg);
-   /* pci express 1 Endpoint  Mode */
-   reg = 0x4000;
-   mtsdr(SDR0_PE2DLPSET, reg);
-
-   mtsdr(SDR0_UART1, 0x2080005a);  /* patch for TG */
-#endif
-
-   return 0;
-}
-
 #ifdef CONFIG_POST
 /*
  * Returns 1 if keys pressed to start the power-on long-running tests
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 6608893..84c3938 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -677,7 +677,7 @@ int is_pci_host(struct pci_controller *hose)
return 1;
 }
 
-int yucca_pcie_card_present(int port)
+static int yucca_pcie_card_present(int port)
 {
u16 reg;
 
@@ -879,10 +879,6 @@ void pcie_setup_hoses(int busno)
 int misc_init_f (void)
 {
uint reg;
-#if defined(CONFIG_STRESS)
-   uint i ;
-   uint disp;
-#endif
 
out16(FPGA_REG10, (in16(FPGA_REG10) 
~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
@@ -897,67 +893,23 @@ int misc_init_f (void)
 
/* minimal init for PCIe */
/* pci express 0 Endpoint Mode */
-   mfsdr(SDR0_PE0DLPSET, reg);
+   mfsdr(SDRN_PESDR_DLPSET(0), reg);
reg = (~0x0040);
-   mtsdr(SDR0_PE0DLPSET, reg);
+   mtsdr(SDRN_PESDR_DLPSET(0), reg);
/* pci express 1 Rootpoint  Mode */
-   mfsdr(SDR0_PE1DLPSET, reg);
+   mfsdr(SDRN_PESDR_DLPSET(1), reg);
reg |= 0x0040;
-   mtsdr(SDR0_PE1DLPSET, reg);
+   mtsdr(SDRN_PESDR_DLPSET(1), reg);
/* pci express 2 Rootpoint  Mode */
-   mfsdr(SDR0_PE2DLPSET, reg);
+   mfsdr(SDRN_PESDR_DLPSET(2), reg);
reg |= 0x0040;
-   mtsdr(SDR0_PE2DLPSET, reg);
+   mtsdr(SDRN_PESDR_DLPSET(2), reg);
 
out16(FPGA_REG1C,(in16 (FPGA_REG1C) 
~FPGA_REG1C_PE0_ROOTPOINT 
~FPGA_REG1C_PE1_ENDPOINT  
~FPGA_REG1C_PE2_ENDPOINT));
 
-#if defined(CONFIG_STRESS)
-   /*
-* all this setting done by linux only needed by stress an charac. test
-* procedure
-* PCIe 1 Rootpoint PCIe2 Endpoint
-* PCIe 0 FIR Pre-emphasis

[U-Boot-Users] [PATCH] ppc4xx: Continue cleanup of ppc440.h

2008-06-30 Thread Stefan Roese
This patch continues the ppc440.h cleanup by removing some of the unused
defines.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 include/ppc440.h |  305 +-
 1 files changed, 3 insertions(+), 302 deletions(-)

diff --git a/include/ppc440.h b/include/ppc440.h
index dd7a64c..2a4526e 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -77,7 +77,6 @@
 #define tbl0x11c   /* time base lower (supervisor)*/
 #define tbu0x11d   /* time base upper (supervisor)*/
 #define pir0x11e   /* processor id register */
-/*#define  pvr 0x11fprocessor version register */
 #define dbsr   0x130   /* debug status register */
 #define dbcr0  0x134   /* debug control register 0 */
 #define dbcr1  0x135   /* debug control register 1 */
@@ -268,86 +267,6 @@
 #define sdr_sdstp6 0x4005
 #define sdr_sdstp7 0x4007
 
-/**
- * PCI express defines
- 
**/
-#define SDR0_PE0UTLSET10x0300  /* PE0 Upper 
transaction layer conf setting */
-#define SDR0_PE0UTLSET20x0301  /* PE0 Upper 
transaction layer conf setting 2 */
-#define SDR0_PE0DLPSET 0x0302  /* PE0 Data link  logical 
physical configuration */
-#define SDR0_PE0LOOP   0x0303  /* PE0 Loopback interface 
status */
-#define SDR0_PE0RCSSET 0x0304  /* PE0 Reset, clock  shutdown 
setting */
-#define SDR0_PE0RCSSTS 0x0305  /* PE0 Reset, clock  shutdown 
status */
-#define SDR0_PE0HSSSET1L0  0x0306  /* PE0 HSS Control Setting 1: 
Lane 0 */
-#define SDR0_PE0HSSSET2L0  0x0307  /* PE0 HSS Control Setting 2: 
Lane 0 */
-#define SDR0_PE0HSSSTSL0   0x0308  /* PE0 HSS Control Status : 
Lane 0 */
-#define SDR0_PE0HSSSET1L1  0x0309  /* PE0 HSS Control Setting 1: 
Lane 1 */
-#define SDR0_PE0HSSSET2L1  0x030A  /* PE0 HSS Control Setting 2: 
Lane 1 */
-#define SDR0_PE0HSSSTSL1   0x030B  /* PE0 HSS Control Status : 
Lane 1 */
-#define SDR0_PE0HSSSET1L2  0x030C  /* PE0 HSS Control Setting 1: 
Lane 2 */
-#define SDR0_PE0HSSSET2L2  0x030D  /* PE0 HSS Control Setting 2: 
Lane 2 */
-#define SDR0_PE0HSSSTSL2   0x030E  /* PE0 HSS Control Status : 
Lane 2 */
-#define SDR0_PE0HSSSET1L3  0x030F  /* PE0 HSS Control Setting 1: 
Lane 3 */
-#define SDR0_PE0HSSSET2L3  0x0310  /* PE0 HSS Control Setting 2: 
Lane 3 */
-#define SDR0_PE0HSSSTSL3   0x0311  /* PE0 HSS Control Status : 
Lane 3 */
-#define SDR0_PE0HSSSET1L4  0x0312  /* PE0 HSS Control Setting 1: 
Lane 4 */
-#define SDR0_PE0HSSSET2L4  0x0313  /* PE0 HSS Control Setting 2: 
Lane 4 */
-#define SDR0_PE0HSSSTSL4   0x0314  /* PE0 HSS Control Status : 
Lane 4 */
-#define SDR0_PE0HSSSET1L5  0x0315  /* PE0 HSS Control Setting 1: 
Lane 5 */
-#define SDR0_PE0HSSSET2L5  0x0316  /* PE0 HSS Control Setting 2: 
Lane 5 */
-#define SDR0_PE0HSSSTSL5   0x0317  /* PE0 HSS Control Status : 
Lane 5 */
-#define SDR0_PE0HSSSET1L6  0x0318  /* PE0 HSS Control Setting 1: 
Lane 6 */
-#define SDR0_PE0HSSSET2L6  0x0319  /* PE0 HSS Control Setting 2: 
Lane 6 */
-#define SDR0_PE0HSSSTSL6   0x031A  /* PE0 HSS Control Status : 
Lane 6 */
-#define SDR0_PE0HSSSET1L7  0x031B  /* PE0 HSS Control Setting 1: 
Lane 7 */
-#define SDR0_PE0HSSSET2L7  0x031C  /* PE0 HSS Control Setting 2: 
Lane 7 */
-#define SDR0_PE0HSSSTSL7   0x031D  /* PE0 HSS Control Status : 
Lane 7 */
-#define SDR0_PE0HSSSEREN   0x031E  /* PE0 Serdes Transmitter 
Enable */
-#define SDR0_PE0LANEABCD   0x031F  /* PE0 Lanes ABCD affectation */
-#define SDR0_PE0LANEEFGH   0x0320  /* PE0 Lanes EFGH affectation */
-
-#define SDR0_PE1UTLSET10x0340  /* PE1 Upper 
transaction layer conf setting */
-#define SDR0_PE1UTLSET20x0341  /* PE1 Upper 
transaction layer conf setting 2 */
-#define SDR0_PE1DLPSET 0x0342  /* PE1 Data link  logical 
physical configuration */
-#define SDR0_PE1LOOP   0x0343  /* PE1 Loopback interface 
status */
-#define SDR0_PE1RCSSET 0x0344  /* PE1 Reset, clock  shutdown 
setting */
-#define SDR0_PE1RCSSTS 0x0345  /* PE1 Reset, clock  shutdown 
status */
-#define SDR0_PE1HSSSET1L0  0x0346  /* PE1 HSS Control Setting 1: 
Lane 0 */
-#define SDR0_PE1HSSSET2L0  0x0347  /* PE1 HSS Control Setting 2: 
Lane 0 */
-#define SDR0_PE1HSSSTSL0   0x0348  /* PE1 HSS Control Status : 
Lane 0 */
-#define SDR0_PE1HSSSET1L1  0x0349  /* PE1 HSS Control Setting 1: 
Lane 1 */
-#define

Re: [U-Boot-Users] CPU (405ep) clock upgrade..

2008-06-30 Thread Stefan Roese
On Monday 30 June 2008, Yi-Neng Lin (林義能) wrote:
  Thanks a lot for your reply, Stefan. However, in my understanding, only
 memory-related info is stored in the EEPROM in the memory module, isn't it?

Yes, the I2C EEPROM on the DIMM has of course only memory module related 
stuff. But I was referring to the 405EX bootstrap EEPROM (see chapter 9.2 IIC 
serial EPROM controller (IEC) Operation in the 405EP users manual).

 The CPU and bus related info is hard-coded in the code. This is what I saw
 from my code. Not very sure of it, though.

Yes, could be that you are using the fixed, compiled-in speed configuration.

    I think it's the spd_sdram() [cpu/ppc4xx] who does the job, which could
 have been an outdated method.

It was renamed and is now called 40x_spd_sdram.c. For board with DIMM modules 
on 405EP this is the way to go.

 The timing info is read from the SPD (Serial 
 Presence Detect) EEPROM on the SDRAM module. My question is, with the
 upgraded CPU clock (333MHz), ordinary SDRAMs (PC100 and PC133) may not be
 able to support it, which means I may have to use PC2700 (333MHz; too
 fast?) or PC66(66MHz; too slow?). Am I correct? Any other comment or
 solution for this?

I'm pretty sure that you still can use the ordinary DIMMs. The driver should 
configure the needed parameters like CAS latency accordingly.

Best regards,
Stefan

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[U-Boot-Users] [ppc4xx] Please pull git://www.denx.de/git/u-boot-ppc4xx.git

2008-06-30 Thread Stefan Roese
The following changes since commit 914f58c5766860373a7d232e961cee5a4b54a55b:
  Wolfgang Denk (1):
Merge branch 'master' of git://www.denx.de/git/u-boot-cfi-flash

are available in the git repository at:

  git://www.denx.de/git/u-boot-ppc4xx.git master

Stefan Roese (3):
  ppc4xx: Fix problem in gpio_config()
  ppc4xx: Fix compilation problems with phys_size_t
  ppc4xx: Fix 460EX errata with CPU lockup upon high AHB traffic

 board/amirix/ap1000/serial.c |1 +
 board/exbitgen/exbitgen.c|1 +
 board/exbitgen/flash.c   |1 +
 board/ml2/serial.c   |1 +
 board/xilinx/ml300/serial.c  |1 +
 cpu/ppc4xx/cpu_init.c|   20 ++--
 cpu/ppc4xx/gpio.c|4 ++--
 include/ppc440.h |2 ++
 8 files changed, 27 insertions(+), 4 deletions(-)

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Re: [U-Boot-Users] [PATCH 1/3] ppc4xx: Consolidate PPC4xx UIC defines

2008-06-30 Thread Stefan Roese
On Monday 30 June 2008, Scott Wood wrote:
 On Sat, Jun 28, 2008 at 02:02:47PM +0200, Stefan Roese wrote:
  This patch is the first step to consolidate the UIC related defines in
  the 4xx headers. Move header from asm-ppc/ppc4xx-intvec.h to
  asm-ppc/ppc4xx-uic.h as it will hold all UIC related defines in the next
  steps.
 
  Signed-off-by: Stefan Roese [EMAIL PROTECTED]
  ---
   board/amcc/sequoia/sequoia.c|3 +-
   cpu/ppc4xx/4xx_enet.c   |1 -
   cpu/ppc4xx/4xx_uart.c   |2 +-
   cpu/ppc4xx/interrupts.c |1 -
   cpu/ppc4xx/iop480_uart.c|1 -
   cpu/ppc4xx/usbdev.c |2 +-
   include/asm-ppc/ppc4xx-intvec.h |  474
  --- include/asm-ppc/ppc4xx-uic.h|
   469 ++ include/ppc4xx.h 
|1 +
   9 files changed, 473 insertions(+), 481 deletions(-)
   delete mode 100644 include/asm-ppc/ppc4xx-intvec.h
   create mode 100644 include/asm-ppc/ppc4xx-uic.h
 
  Unfortunately this patch is too big for the (soft) list limit and
  Wolfgang is on vacation. So this patch will not hit the list for another
  few days. Because of this please find the patch at this location for
  review:
 
  http://pastebin.com/m28342307

 If you pass -M -C to git-format-patch, it'll detect renames (even with
 some editing), and make the patch small enough to post.

Right, I forgot. But it would not have helped with the 2nd patch of this 
series.

But thanks for reminding.

Best regards,
Stefan

=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: [EMAIL PROTECTED]
=

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[U-Boot-Users] [PATCH 1/3] ppc4xx: Consolidate PPC4xx UIC defines

2008-06-28 Thread Stefan Roese
This patch is the first step to consolidate the UIC related defines in the
4xx headers. Move header from asm-ppc/ppc4xx-intvec.h to
asm-ppc/ppc4xx-uic.h as it will hold all UIC related defines in the next
steps.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 board/amcc/sequoia/sequoia.c|3 +-
 cpu/ppc4xx/4xx_enet.c   |1 -
 cpu/ppc4xx/4xx_uart.c   |2 +-
 cpu/ppc4xx/interrupts.c |1 -
 cpu/ppc4xx/iop480_uart.c|1 -
 cpu/ppc4xx/usbdev.c |2 +-
 include/asm-ppc/ppc4xx-intvec.h |  474 ---
 include/asm-ppc/ppc4xx-uic.h|  469 ++
 include/ppc4xx.h|1 +
 9 files changed, 473 insertions(+), 481 deletions(-)
 delete mode 100644 include/asm-ppc/ppc4xx-intvec.h
 create mode 100644 include/asm-ppc/ppc4xx-uic.h

Unfortunately this patch is too big for the (soft) list limit and Wolfgang
is on vacation. So this patch will not hit the list for another few days.
Because of this please find the patch at this location for review:

http://pastebin.com/m28342307

Best regards,
Stefan

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[U-Boot-Users] [PATCH 2/3] ppc4xx: Consolidate PPC4xx UIC defines

2008-06-28 Thread Stefan Roese
This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.

Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.

Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 board/amcc/sequoia/sequoia.c |2 +-
 common/cmd_reginfo.c |5 +-
 cpu/ppc4xx/4xx_enet.c|  408 +++-
 cpu/ppc4xx/interrupts.c  |   75 +++--
 cpu/ppc4xx/usbdev.c  |2 +-
 include/asm-ppc/ppc4xx-uic.h |  648 ++
 include/configs/HH405.h  |2 +-
 include/ppc405.h |  247 ---
 include/ppc440.h |  706 --
 9 files changed, 397 insertions(+), 1698 deletions(-)

Unfortunately this patch is too big for the list limit and its nearly
impossible to split this into smaller pieces by leaving the repo
git-bisectable.
Because of this please find the patch at this location for review:

http://pastebin.com/m122589f4

Best regards,
Stefan

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[U-Boot-Users] [PATCH 3/3] ppc4xx: Rework 440GX UIC handling

2008-06-28 Thread Stefan Roese
This patch reworks the 440GX interrupt handling so that the common 4xx
code can be used. The 440GX is an exception to all other 4xx variants
by having the cascading interrupt vectors not on UIC0 but on a special
UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references
the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt
handling is simpler without any 440GX special cases.

Also some additional cleanup to cpu/ppc4xx/interrupt.c is done.

Signed-off-by: Stefan Roese [EMAIL PROTECTED]
---
 board/amcc/ocotea/ocotea.c  |   50 +++---
 board/amcc/taishan/taishan.c|   50 +++---
 board/prodrive/alpr/alpr.c  |   50 +++---
 board/sandburst/karef/karef.c   |   50 +++---
 board/sandburst/metrobox/metrobox.c |   50 +++---
 board/xpedite1k/xpedite1k.c |   50 +++---
 cpu/ppc4xx/4xx_enet.c   |9 ++-
 cpu/ppc4xx/cpu_init.c   |   17 +-
 cpu/ppc4xx/interrupts.c |   97 ++-
 include/asm-ppc/ppc4xx-uic.h|   93 +
 10 files changed, 270 insertions(+), 246 deletions(-)

diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index eea1e1e..4d1d093 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -147,36 +147,48 @@ int board_early_init_f (void)
/*
 * Setup the interrupt controller polarities, triggers, etc.
 *---*/
-   mtdcr (uic0sr, 0x); /* clear all */
-   mtdcr (uic0er, 0x); /* disable all */
-   mtdcr (uic0cr, 0x0009); /* SMI  UIC1 crit are critical */
-   mtdcr (uic0pr, 0xfe13); /* per ref-board manual */
-   mtdcr (uic0tr, 0x01c8); /* per ref-board manual */
-   mtdcr (uic0vr, 0x0001); /* int31 highest, base=0x000 */
-   mtdcr (uic0sr, 0x); /* clear all */
-
+   /*
+* Because of the interrupt handling rework to handle 440GX interrupts
+* with the common code, we needed to change names of the UIC registers.
+* Here the new relationship:
+*
+* U-Boot name  440GX name
+* ---
+* UIC0 UICB0
+* UIC1 UIC0
+* UIC2 UIC1
+* UIC3 UIC2
+*/
mtdcr (uic1sr, 0x); /* clear all */
mtdcr (uic1er, 0x); /* disable all */
-   mtdcr (uic1cr, 0x); /* all non-critical */
-   mtdcr (uic1pr, 0xe0ff); /* per ref-board manual */
-   mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
+   mtdcr (uic1cr, 0x0009); /* SMI  UIC1 crit are critical */
+   mtdcr (uic1pr, 0xfe13); /* per ref-board manual */
+   mtdcr (uic1tr, 0x01c8); /* per ref-board manual */
mtdcr (uic1vr, 0x0001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0x); /* clear all */
 
mtdcr (uic2sr, 0x); /* clear all */
mtdcr (uic2er, 0x); /* disable all */
mtdcr (uic2cr, 0x); /* all non-critical */
-   mtdcr (uic2pr, 0x); /* per ref-board manual */
-   mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
+   mtdcr (uic2pr, 0xe0ff); /* per ref-board manual */
+   mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x0001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0x); /* clear all */
 
-   mtdcr (uicb0sr, 0xfc00); /* clear all */
-   mtdcr (uicb0er, 0x); /* disable all */
-   mtdcr (uicb0cr, 0x); /* all non-critical */
-   mtdcr (uicb0pr, 0xfc00); /* */
-   mtdcr (uicb0tr, 0x); /* */
-   mtdcr (uicb0vr, 0x0001); /* */
+   mtdcr (uic3sr, 0x); /* clear all */
+   mtdcr (uic3er, 0x); /* disable all */
+   mtdcr (uic3cr, 0x); /* all non-critical */
+   mtdcr (uic3pr, 0x); /* per ref-board manual */
+   mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
+   mtdcr (uic3vr, 0x0001); /* int31 highest, base=0x000 */
+   mtdcr (uic3sr, 0x); /* clear all */
+
+   mtdcr (uic0sr, 0xfc00); /* clear all */
+   mtdcr (uic0er, 0x); /* disable all */
+   mtdcr (uic0cr, 0x); /* all non-critical */
+   mtdcr (uic0pr, 0xfc00); /* */
+   mtdcr (uic0tr, 0x); /* */
+   mtdcr (uic0vr, 0x0001); /* */
mfsdr (sdr_mfr, mfr);
mfr = ~SDR0_MFR_ECS_MASK;
 /* mtsdr(sdr_mfr, mfr); */
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index b6c3065..fdd82e7 100644
--- a/board/amcc

[U-Boot-Users] [ppc4xx] Please pull git://www.denx.de/git/u-boot-ppc4xx.git

2008-06-28 Thread Stefan Roese
The following changes since commit 914f58c5766860373a7d232e961cee5a4b54a55b:
  Wolfgang Denk (1):
Merge branch 'master' of git://www.denx.de/git/u-boot-cfi-flash

are available in the git repository at:

  git://www.denx.de/git/u-boot-ppc4xx.git master

Stefan Roese (2):
  ppc4xx: Fix problem in gpio_config()
  ppc4xx: Fix compilation problems with phys_size_t

 board/amirix/ap1000/serial.c |1 +
 board/exbitgen/exbitgen.c|1 +
 board/exbitgen/flash.c   |1 +
 board/ml2/serial.c   |1 +
 board/xilinx/ml300/serial.c  |1 +
 cpu/ppc4xx/gpio.c|4 ++--
 6 files changed, 7 insertions(+), 2 deletions(-)

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