l
Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I83841654cee74b940f967b3a37b99d87c01bd92c
Gerrit-Change-Number: 70732
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Richard Cooper
Segments=2)
+# LD1RO{B,H,W,D} (scalar plus scalar)
+emitSveLoadAndReplMulti(offsetIsImm=False, numQwordSegments=2)
# LD{2,3,4}{B,H,W,D} (scalar plus immediate)
# ST{2,3,4}{B,H,W,D} (scalar plus immediate)
--
To view, visit
https://gem5-review.googlesource.com/c/public/gem5/+/7
0;
isar0_el1.atomic = release->has(ArmExtension::FEAT_LSE) ? 0x2 :
0x0;
isar0_el1.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
isar0_el1.tme = release->has(ArmExtension::TME) ? 0x1 : 0x0;
--
To view, visit
https://gem5-review.googl
cture Reference
Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A"
(https://developer.arm.com/architectures/cpu-architecture/a-profile/
docs/arm-architecture-reference-manual-supplement-armv8-a)
Additional Contributors: Giacomo Travaglini
AdvSIMD *scalar* three same Extra" in the Arm arm. The
encoding space reserved to the pool bears the
"Advanced SIMD three-register extension" name; we
therefore rename the function to decodeNeon3RegExtension
Change-Id: I056da8f0c7808935d12a4b05490d30654178071f
Signed-off-by
)
..
arch-arm: Implement FEAT_FLAGM(2)
Change-Id: I21f1eb91ad9acb019a776a7d5edd38754571a62e
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/insts/misc64.cc
M
: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/regs/cc.hh
1 file changed, 23 insertions(+), 11 deletions(-)
diff --git a/src/arch/arm/regs/cc.hh b/src/arch/arm/regs/cc.hh
index ba75527..474e48e 100644
--- a/src/arch/arm/regs/cc.hh
+++ b/src
..
arch-arm: Implement trapping of SME registers
Change-Id: Ic5bcc79a535c928265fbc1db1cd0c85ba1a1b152
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/regs/misc.cc
1 file changed, 80 insertions
)
Change-Id: Ifa03a93cb73de0b2dc93d7784f9011e0e55dfc1e
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa/formats/aarch64.isa
1 file changed, 361 insertions(+), 309 deletions(-)
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats
..
arch-arm: Define a AA64ZFR0 data type
Change-Id: I6b0dcf0c1882f356783934f625c2bc3a25fbb885
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 13 insertions(+), 0
..
arch-arm: Implement FEAT_RNG
Change-Id: I9d60d249172ef4bbaf5d9b38ef279eff344b80d8
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
M src/arch/arm
..
arch-arm: Implement FEAT_IDST
Change-Id: I3cabcfdb10f4eefaf2ab039376d840cc4c54609a
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/regs/misc.cc
2 files changed, 59 insertions(+), 17
..
arch-arm: Extend SCR to be 64-bit wide
Change-Id: I9928de3db61957404269d189a15a951fd6707c8a
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 1 insertion(+), 1
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/70697?usp=email )
Change subject: arch-arm: Fix printing of VecElemClass registers
..
arch-arm: Fix printing
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70567?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Implement FEAT_TLBIOS
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70557?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Add UNSERIALIZE flag
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70563?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Implement RES0/RES1
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70561?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Update MISCREG_DBGDIDR
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70560?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Implement RAZ/WI
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70559?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Provide default mask
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70565?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Simplify FPSCR writes
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70566?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Extend SCTLR to be 64
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70558?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Move RO values from
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70562?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Group self hosted
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70564?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Remove unnecessary
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70637?usp=email )
Change subject: arch-arm: Fix position of AA64ISAR0.AES bitfield
..
arch-arm: Fix position of AA64ISAR0
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/70637?usp=email )
Change subject: arch-arm: Fix position of AA64ISAR0.AES bitfield
..
arch-arm: Fix position
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/insts/misc64.cc
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
4 files changed, 151 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
specifiers
..
arch-arm: Implement RES0/RES1 with miscreg specifiers
Change-Id: Ic2caea121e02f63f069f1576760c849bcbdac894
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
M src/arch/arm/regs
is
raz/rao. This won't be probably used by rao but I
am striving for symmetry and providing a default won't
probably hurt
Change-Id: I309e345fc8336df3a74474f8f9202bf7e2095b41
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/regs/misc.hh
1 file changed, 2 insertions
to Armv8 debug
arch
..
arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch
Change-Id: I20691ecdaedde6740c706782635b1f9a4491dc51
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/regs
arm/isa.cc#L1019
Change-Id: Icea6563ee5816b14a097926b5734f2fce10530c7
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.hh
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
ind
..
arch-arm: Extend SCTLR to be 64-bit wide
In AArch64 SCTLR_EL1/_EL2/_EL3 is 64-bit wide
Change-Id: I80931f9dd1a57f3132229b84d32a8ab08eee3371
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/regs
: I62270cdb59f39b8a143e9554c8beaa8cd15824aa
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 49 insertions(+), 66 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f55235d..14349b1 100644
--- a/src
this by explicitly marking them as RES0 at construction
time
Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 2 insertions(+), 32 deletions(-)
diff --git a/src/arch/arm
::readMiscReg
..
arch-arm: Remove unnecessary case in ISA::readMiscReg
Change-Id: I8b95a75fbfec2626fbe8b455ae9b3f30acda538f
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
1 file changed, 0
..
arch-arm: Implement RAZ/WI with raz specifier
Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files
switch
..
arch-arm: Group self hosted debug writes in ISA switch
Change-Id: If9c0675743856b603e7b5ec1898f5cdd650f3ce6
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
1 file changed, 8
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70470?usp=email )
Change subject: arch-arm: Remove clear32/64 methods
..
arch-arm: Remove clear32/64 methods
Change-Id
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70469?usp=email )
Change subject: arch-arm: Remove ISA::initID64
..
arch-arm: Remove ISA::initID64
Signed-off-by: Giacomo
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70468?usp=email )
Change subject: arch-arm: Rewrite ISA::initID64 using BitUnions
..
arch-arm: Rewrite ISA::initID64 using
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70471?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: VMPIDR_EL2 can
esentata l'anno scorso
> > ma non ritrovo l'articolo accademico che ne parlava.
>
> Grazie ancora per l'articolo e per lo scambio.
Grazie a te!
Spero solo che non siamo stati troppo "opachi" per chi non conosce il tema.
Giacomo
___
nexa mailing list
nexa@server-nexa.polito.it
https://server-nexa.polito.it/cgi-bin/mailman/listinfo/nexa
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70467?usp=email )
Change subject: arch-arm: Remove ISA::initID32
..
arch-arm: Remove ISA::initID32
Signed-off-by: Giacomo
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70458?usp=email )
Change subject: arch-arm: Make MISCREGs reset value configurable
..
arch-arm: Make MISCREGs reset value
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70466?usp=email )
Change subject: arch-arm: Rewrite ISA::initID32 using BitUnions
..
arch-arm: Rewrite ISA::initID32 using
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70463?usp=email )
Change subject: arch-arm: Map CTR_EL0 to AArch32 version
..
arch-arm: Map CTR_EL0 to AArch32 version
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70457?usp=email )
Change subject: arch-arm: Replace 0ing of miscRegs with assignment of reset
value
..
arch-arm: Replace
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70464?usp=email )
Change subject: arch-arm: Fix read redirection for MIDR register
..
arch-arm: Fix read redirection
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70461?usp=email )
Change subject: arch-arm: Map MIDR_EL1 to AArch32 version
..
arch-arm: Map MIDR_EL1 to AArch32 version
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70465?usp=email )
Change subject: arch-arm: Move MISCREG init logic from ISA to reset field
..
arch-arm: Move MISCREG init
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70462?usp=email )
Change subject: arch-arm: Map MPIDR_EL1 to AArch32 version
..
arch-arm: Map MPIDR_EL1 to AArch32 version
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70459?usp=email )
Change subject: arch-arm: Generalize SCTLR_RST behaviour
..
arch-arm: Generalize SCTLR_RST behaviour
On Wed, May 10, 2023 at 04:56:19PM +0200, Giacomo Tesio wrote:
>
> Ho un vaghissimo ricordo di una tecnica simile presentata l'anno scorso
> ma non ritrovo l'articolo accademico che ne parlava.
era questo: https://eprint.iacr.org/2022/204.pdf
(ovviamente non potevo che trovarlo
a e misurando i tempi di risposta può
dedurre il valore del primo bit del testo in chiaro.
Ho un vaghissimo ricordo di una tecnica simile presentata l'anno scorso
ma non ritrovo l'articolo accademico che ne parlava.
Giacomo
___
nexa mailing list
nexa@server-nexa.polito.it
https://server-nexa.polito.it/cgi-bin/mailman/listinfo/nexa
..
arch-arm: Remove clear32/64 methods
Change-Id: I62d2dc0612298fdb4cdc3bf368e080c8ebebe23a
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/regs/misc.cc
3 files
..
arch-arm: Rewrite ISA::initID64 using BitUnions
Signed-off-by: Giacomo Travaglini
Change-Id: I3e8c7bdcf86c01eccbd90fccaa2d4306a501ed13
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
M src
: Ie7e112a83e64f33a98885e88504c2d6bc5070218
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/utility.cc
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 6764569..05d1cab 100644
--- a/src/arch/arm/utility.cc
+++ b
..
arch-arm: Remove ISA::initID64
Signed-off-by: Giacomo Travaglini
Change-Id: I3d03ee15df46fa7d9a9ec439b26e99baf33cbb5e
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/regs/misc.cc
3 files changed
..
arch-arm: Remove ISA::initID32
Signed-off-by: Giacomo Travaglini
Change-Id: I70cce0b9d99ed5fe146e64c6ee55fa8cedf98ac6
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/regs/misc.cc
3 files changed, 46
..
arch-arm: Map MIDR_EL1 to AArch32 version
Signed-off-by: Giacomo Travaglini
Change-Id: Id3ddc18ebfc296389bed6dc7615899bef83178ea
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 2
with FEAT_SEL2)
2) Is extending this logic to the AArch64 version (MIDR_EL1)
It is also rewriting the base logic using Armv8 terminology
(checking the EL rather than the mode as an example).
Signed-off-by: Giacomo Travaglini
Change-Id: I5cf09240206287cab877ea7ff6e46cf823aa8c35
Reviewed-by: Richard
.
We when simply apply the pre-computed reset value to the miscReg
storage, as implemented by a previous patch [1]
[1]: Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79
Signed-off-by: Giacomo Travaglini
Change-Id: Iec4878217c38707be4ce7d4746ff95a208b4
Reviewed-by: Richard Cooper
---
M
in the
AArch32 version without the need to re-calculate the fix affinity
numbers
Change-Id: Id42d1994cdd1722f07874ffa7364154cf011e00a
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/regs/misc.cc
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/regs
version
..
arch-arm: Map MVFR0_EL1/MVFR1_EL1 to AArch32 version
Signed-off-by: Giacomo Travaglini
Change-Id: I28753de7b437be58e5ac891ac2e549bbab6b53b0
Reviewed-by: Richard Cooper
---
M src/arch/arm/regs/misc.cc
1 file changed, 4
..
arch-arm: Map CTR_EL0 to AArch32 version
Change-Id: Ia3e0cafa1bd2a3054b286e79ac378c895d6910e8
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/regs/misc.cc
1 file changed, 2 insertions(+), 1 deletion
register.
Signed-off-by: Giacomo Travaglini
Change-Id: Ib61019ec499b35382289fe18740c90eee5de4907
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
4 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/src/arch
..
arch-arm: Rewrite ISA::initID32 using BitUnions
Signed-off-by: Giacomo Travaglini
Change-Id: I38460766bb5ed363b176bc6faca8e770a8a5e4c6
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc_types.hh
2
configurable
..
arch-arm: Make MISCREGs reset value configurable
Signed-off-by: Giacomo Travaglini
Change-Id: I536065a2de5faeb8ab64391f8ca2aa83fb2cc82f
Reviewed-by: Richard Cooper
---
M src/arch/arm/regs/misc.hh
1 file changed, 7
should
assign them their reset value when clearing them.
As of now the reset variable is unused so using it is functionally
equivalent of calling memset. This will however change once we start
using the reset field
Signed-off-by: Giacomo Travaglini
Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79
nte da rete aziendale e
tramite
utenze pseudonimiche, i servizi cloud dei GAFAM sono solo cari, ma non violano
il GDPR.
(forse però la PA che li adotta continua a violare il CAD)
Giacomo
___
nexa mailing list
nexa@server-nexa.polito.it
https://server-nexa.polito.it/cgi-bin/mailman/listinfo/nexa
voli dati personali contenuti in quelli
impropriamente detti "metadati".
Pensa ad esempio agli header SMTP delle email, agli header HTTP inviati
dalle richieste web etc...
Non è possibile criptare i destinatari di una email.
O l'ora in cui è inviata.
Giacomo
___
i... tace.
I regolatori sono molto facile da controllare.
Giacomo
___
nexa mailing list
nexa@server-nexa.polito.it
https://server-nexa.polito.it/cgi-bin/mailman/listinfo/nexa
persino risposto
spiegandoci che le alternative devono essere identiche a quelle di Google,
gratuite e non
richiedere competenze tecniche all'ateneo.
Tutto firmato o sottoscritto da Data PROTECTION Officer.
Giacomo
___
nexa mailing list
nexa
sempre state gratis, per gli schiavi.
Giacomo
Il 6 Maggio 2023 08:28:13 UTC, Federico Guerrini via nexa
ha scritto:
>Ciao, mi sono imbattuto in questo articolo del New Yorker che, secondo
>me, meriterebbe di essere copi-incollato tutto;non necessariamente
>perché sia d'accordo
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/70277?usp=email )
Change subject: arch-arm: Partial SVE2 Implementation
..
arch-arm: Partial SVE2 Implementation
.numWorkItemsCompleted0
# Number of work items this cpu completed (Count)
So you should be able to match stats with the correct cpu type…
Is this what you meant?
Kind Regards
Giacomo
From: inderjitsingh.davu--- via gem5-users
Date: Monday, 1 May 2023 at 04:41
To: gem5-users@gem5
è un database)
E giova ripetere che un LLM viene programmato a partire da un enorme database.
Si può tranquillamente rimuovere i dati relativi al richiedente da quel
database: è solo costoso.
Poi per ulteriore sicurezza si può mettere un filtro a valle che impedisce al
software di inviare
Hi Iana,
In theory it shouldn't be a problem to run a dynamically linked binary on a Arm
host... Could you run the application with GDB and check why the mmap is
failing?
Kind Regards
Giacomo
From: Iana Chertkova via gem5-users
Sent: 28 April 2023 03:24
richiama alla mente
un'esperienza umana (il decidere) e produce analoghe aberrazioni
(seppur su scala minore)
"Programmazione statistica" è al momento la mia locuzione preferita
non solo perché fredda e tecnica, ma perché presuppone la pr
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/70117?usp=email )
Change subject: mem: Fix SW prefetch asynchronous handling
..
mem: Fix SW prefetch asynchronous
e le funzioni erotiche.
Autorevoli giuristi che giustificano le violazioni dei diritti umani
fatte da Open AI tramite Chat GPT perché... "è solo una povera AI!"
E così via.
Io sono CERTO della buona fede di Giuseppe nell'uso della locuzione
"intelligenza artificiale".
Co
command line (for example /bin/bash)
Kind Regards
Giacomo
On 26/04/2023 08:59, 李强 via gem5-users wrote:
Hi:
I am currently trying to boot ubuntu-18.04-arm64-docker.img using QEMU. The
image file was extracted from aarch-system-20220707.tar.bz2, which I downloaded
from https://www.gem5.org
Come si diventa "vetted researcher"?
Sembra davvero divertente!
Giacomo
___
nexa mailing list
nexa@server-nexa.polito.it
https://server-nexa.polito.it/cgi-bin/mailman/listinfo/nexa
@Adolfo, thanks!
I suspected a packaging issue, but I didn't know that Draw and Impress can't be
installed independently at all.
--
You received this bug notification because you are a member of Desktop
Packages, which is subscribed to libreoffice in Ubuntu.
Public bug reported:
Draw fails to open, unless I install also libreoffice Impress.
It only shows the splash screen for 1/2 second, and then dies.
I tried to find a useful error message, but I couldn't find any.
I randomly discovered that if I install libreoffice-impress, then Draw starts
Ragion per cui è FONDAMENTALE trattare gli automatismi come cose prive
di identità o dignità alcuna, ma estensioni della volontà di chi li
costruisce e li mette in opera.
SEMPRE.
Che si chiamino Google Chrome, Office 365, Android, Classroom o ChatGPT.
Ricordando sempre la domanda fondamentale della cibernetica: cui
prodest?
Giacomo
___
nexa mailing list
nexa@server-nexa.polito.it
https://server-nexa.polito.it/cgi-bin/mailman/listinfo/nexa
] (from your program)
with the PR_SVE_SET_VL flag.
Let me know if this works...
Kind Regards
Giacomo
[1]:
https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/ZCR-EL1--SVE-Control-Register--EL1-?lang=en
[2]:
https://developer.arm.com/documentation/ddi0601/2020-12/AArch64
enormemente, ma etichettare le critiche di Giacomo (critiche
>che non
>condivido completamente - ma non ho tempo di farne l'analisi) come
>"oscurantiste" non
>fa bene al dibattito.
Per la verità non sono le mie critiche che Giuseppe ha etichettato come
"oscurantiste, be
o aver deciso quale società vogliamo per i nostri figli, potremo
iniziare a pensare quale infrastruttura tecnologica gli servirà.
E potremo così anche realizzarla.
Invece, inseguire l'elisir della AI significa accettare proni un modello
di società deciso altrove, nell'interesse di altri.
o, ma sarebbe l’uso sbagliato.
Giusto o sbagliato che sia, l'importante è che qualcuno ne risponda.
Giacomo
___
nexa mailing list
nexa@server-nexa.polito.it
https://server-nexa.polito.it/cgi-bin/mailman/listinfo/nexa
sentire una chiara argomentazione a favore
dell'immunità dalla Legge per coloro che la violano tramite automatismi.
Magari mi convinci pure!
In fondo a me basta che valga per tutti.
Hacker inclusi! ;-)
Ciò che però ti chiederei è di evitare argomenti fantoccio.
Discutiamo nel merito.
Giacomo
___
?
Quello che si fa con qualsiasi altra azienda che pubblichi su un sito web lo
stesso contenuto.
Dov'è il problema?
Giacomo
___
nexa mailing list
nexa@server-nexa.polito.it
https://server-nexa.polito.it/cgi-bin/mailman/listinfo/nexa
Beh, però se l'output di ChatGPT attribuisse la maggior età alla nipote di
Mubarak all'epoca
dei loro rapporti, Berlusconi avrebbe diritto a chiedere una rettifica.
Al contempo si porrebbe un problema di disinformazione da parte di OpenAI
(tramite ChatGPT)
Giacomo
Il 16 Aprile 2023 06:55:40
usare ad esempio solo testi provenienti dalla letteratura.
> niente dati personali, giusto?
Non è detto: anche le biografie sono letteratura. ;-)
Giacomo
___
nexa mailing list
nexa@server-nexa.polito.it
https://server-nexa.polito.it/cgi-bin/mailman/listinfo/nexa
i diritti umani.
ChatGPT è solo un software che qualcuno ha programmato ed esegue.
Fa esattamente ciò per cui è programmato.
E' Open AI che deve rispondere di tali violazioni.
E deve farlo perché la legge deve restare uguale per tutti.
Giacomo
[1]: ad esempio https:/
On Fri, 14 Apr 2023 11:34:14 +0200 Giuseppe Attardi wrote:
> > On 14 Apr 2023, at 10:20, Giacomo Tesio wrote:
> >
> > Beh, è facile concordare sui finanziamenti alla ricerca.
>
> Talmente facile che non viene fatto.
>
> La voce “Intelligenza Artificiale
Marine Protected Area.
Cheers,
Giacomo
___
MARMAM mailing list
MARMAM@lists.uvic.ca
https://lists.uvic.ca/mailman/listinfo/marmam
di lontanamente paragonabile a quello che ha fatto Databricks,
insomma.
Purtuttavia qualcosa di perfettamente fattibile da un punto di vista
tecnico, sebbene estremamente costoso.
Giacomo
On Fri, 14 Apr 2023 09:36:30 +0200 D. Davide Lamanna wrote:
> On 4/13/23 12:49, Giacomo Tesio wrote:
iva che la costruzione di macchine che non possano
tecnicamente garantire il rispetto dei diritti umani va
semplicemente vietata.
Il che non limita in alcun modo la ricerca! Anzi! La incoraggia!
E la orienta verso soluzioni... "degne di fiducia" ;-)
Giacomo
On Thu, 13 Apr 2023 16:34:08 -070
301 - 400 of 12300 matches
Mail list logo
