On 2017年05月23日 23:16, Christian König wrote:
Am 23.05.2017 um 17:08 schrieb Deucher, Alexander:
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Chunming Zhou
Sent: Tuesday, May 16, 2017 5:26 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou,
From: Michel Dänzer
* Point to the amd-gfx mailing list
* Specify the component in all bugzilla URLs
* Use https:// for all HTML URLs
(Ported from radeon commit d80d01a73c2eaba2e3649b7bc0a3541b3ff782f6)
Signed-off-by: Michel Dänzer
---
README
On 23/05/17 10:37 PM, Harry Wentland wrote:
> On 2017-05-20 04:13 AM, Christian König wrote:
>> Am 19.05.2017 um 22:28 schrieb Harry Wentland:
>>>
>>> I realize this is raising a lot of concern. I was concerned myself
>>> when I first saw this. Beside calling kernel_fpu_begin() and
>>>
I don't have any test for KCQ , but KFD use the KIQ to invalidate_tlbs , I
try to add some print message in the code to prove it go through the new code
path , but seems I don't see any messages I added. I tried pr_info , pr_err
and printk , DRM_ERROR and nothing works , anything
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Tuesday, May 23, 2017 11:59 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH] drm/amd/amdgpu: Return error if initiating read out of
> range on
On Tue, May 23, 2017 at 5:31 PM, Alex Deucher wrote:
> On Fri, May 12, 2017 at 7:11 AM, Tom St Denis wrote:
>> On 11/05/17 07:33 PM, Tom St Denis wrote:
>>>
>>> On 11/05/17 02:35 PM, Alex Deucher wrote:
These are the laste of the gfx9 KIQ
On Fri, May 12, 2017 at 7:11 AM, Tom St Denis wrote:
> On 11/05/17 07:33 PM, Tom St Denis wrote:
>>
>> On 11/05/17 02:35 PM, Alex Deucher wrote:
>>>
>>> These are the laste of the gfx9 KIQ patches that haven't landed yet. Can
>>> someone with gfx9 capable hw test this
Check to make sure the vblank period is long enough to support
mclk switching.
v2: drop needless initial assignment (Nils)
bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 31
Even if the vblank period would allow it, it still seems to
be problematic on some cards.
bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 ++-
1 file changed, 2
On Tue, May 23, 2017 at 6:43 PM, Christian König
wrote:
> From: Christian König
>
> BOs larger than the minimum fragment size should have their VA
> alignet to at least the fragment size for optimal performance.
>
> Signed-off-by: Christian
Do you need something in amdgpu_vm_update_level to stop it from
overwriting huge page PTEs?
Regards,
Felix
On 17-05-23 12:52 PM, Christian König wrote:
> From: Christian König
>
> The hardware can use huge pages to map 2MB of address space with only one PDE.
>
> v2:
On 17-05-23 12:52 PM, Christian König wrote:
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -395,7 +395,13 @@
> static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
> return pte_flag;
> }
> +static uint64_t
Signed-off-by: Tom St Denis
---
src/lib/read_vram.c | 27 ++-
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c
index deb958dc4c88..80ef4a5664de 100644
--- a/src/lib/read_vram.c
+++
> -Original Message-
> From: Lukas Wunner [mailto:lu...@wunner.de]
> Sent: Monday, May 22, 2017 11:51 PM
> To: Michel Dänzer
> Cc: Nicolai Stange; Sean Paul; Deucher, Alexander; dri-
> de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Koenig,
> Christian
> Subject: Re: [PATCH]
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Monday, May 22, 2017 5:10 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 1/2] drm/amdgpu: fix null point error when rmmod amdgpu.
>
> this bug
> -Original Message-
> From: Koenig, Christian
> Sent: Monday, May 22, 2017 4:12 AM
> To: Christian König; Masahiro Yamada; dri-de...@lists.freedesktop.org;
> Daniel Vetter; Deucher, Alexander; Daenzer, Michel; linux-
> ker...@vger.kernel.org; amd-gfx@lists.freedesktop.org
> Subject: Re:
> -Original Message-
> From: Arindam Nath [mailto:anath@gmail.com] On Behalf Of
> arindam.n...@amd.com
> Sent: Monday, May 22, 2017 3:48 AM
> To: io...@lists.linux-foundation.org
> Cc: amd-gfx@lists.freedesktop.org; Joerg Roedel; Deucher, Alexander;
> Bridgman, John;
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Flora Cui
> Sent: Thursday, May 18, 2017 11:37 PM
> To: Christian K�nig
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: fix ocl test performance drop
>
> btw, what's
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Wednesday, May 17, 2017 10:17 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH xf86-video-ati] Update URLs
>
> From: Michel Dänzer
>
>
From: Christian König
If updating the PDs fails we now invalidate all entries to try again later.
Signed-off-by: Christian König
Reviewed-by: Chunming Zhou
Reviewed-by: Junwei Zhang
---
From: Christian König
The fragment bits work differently for Vega10 compared to previous generations.
Increase the fragment size to 2MB for now to better handle that.
Signed-off-by: Christian König
---
From: Christian König
Rename adjust_mc_addr to get_vm_pde and check the address bits in one place.
v2: handle vcn as well, keep setting the valid bit manually,
add a BUG_ON() for GMC v6, v7 and v8 as well.
v3: handle vcn_v1_0_enc_ring_emit_vm_flush as well.
From: Christian König
Makes it easier to update the PDE with huge pages.
Signed-off-by: Christian König
Reviewed-by: Junwei Zhang
Reviewed-by: Chunming Zhou
---
From: Christian König
This isn't beneficial any more since VRAM allocations are now split
so that they fits into a single page table.
Signed-off-by: Christian König
Reviewed-by: Junwei Zhang
Reviewed-by: Chunming Zhou
From: Harish Kasiviswanathan
This change is also useful for the upcoming changes where page tables
can be updated by CPU.
Change-Id: I07510ed60c94cf1944ee96bb4b16c40ec88ea17c
Signed-off-by: Harish Kasiviswanathan
Reviewed-by:
Am 23.05.2017 um 17:59 schrieb Tom St Denis:
If you initiate a read that is out of the VRAM address space return
ENXIO instead of 0.
Reads that begin below that point will read upto the VRAM limit as
before.
Signed-off-by: Tom St Denis
Reviewed-by: Christian König
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Marek Olšák
> Sent: Wednesday, May 17, 2017 2:06 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: add an INFO query for monitoring VRAM
> CPU page faults
>
> From: Marek
> -Original Message-
> From: Koenig, Christian
> Sent: Wednesday, May 17, 2017 4:23 AM
> To: Gustavo A. R. Silva; Deucher, Alexander; David Airlie
> Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH] gpu: drm: radeon:
On 17-05-23 09:37 AM, Harry Wentland wrote:
>
>
> On 2017-05-20 04:13 AM, Christian König wrote:
>> Are you aware of anyone using our GPUs on non-X86 architectures? If
>> so, I never heard of it.
>>
>> Yeah, there are actually quite a number of people. That's one of the
>> reasons why we still
Am 23.05.2017 um 17:08 schrieb Deucher, Alexander:
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Chunming Zhou
Sent: Tuesday, May 16, 2017 5:26 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou, David(ChunMing)
Subject: [PATCH 2/4] drm/amdgpu:
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Chunming Zhou
> Sent: Tuesday, May 16, 2017 5:26 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou, David(ChunMing)
> Subject: [PATCH 2/4] drm/amdgpu: return -ENODEV to user space when
> vram
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Monday, May 15, 2017 2:26 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH 2/2] drm/amd/amdgpu: Clean up gmc6 wait_for_idle
>
> Signed-off-by:
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Monday, May 15, 2017 10:58 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH 2/2] drm/amd/amdgpu: Tidy up static int
> dce_v6_0_get_num_crtc()
>
On 23/05/17 10:28 AM, Deucher, Alexander wrote:
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Tom St Denis
Sent: Monday, May 15, 2017 9:49 AM
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom
Subject: [PATCH 5/5] drm/amd/amdgpu: Use modern
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Monday, May 15, 2017 9:49 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH 1/5] drm/amd/amdgpu: Clean up GFX6 tilemode
> programming
>
>
From: Tony Cheng
need to program DCSURF_PRIMARY_SURFACE_ADDRESS last as HW automatically
latch rest of addr regs on write when SURFACE_UPDATE_LOCK is not used
Change-Id: I9284f3cebd02ed3c25c844bc14a95ecc45b1d123
Signed-off-by: Tony Cheng
Reviewed-by:
From: Tom St Denis
Change-Id: I8f7cb2a366d112414fe4058affe36b14b38e7105
Signed-off-by: Tom St Denis
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 6 +++---
1 file changed, 3
Change-Id: I3a2032942816f66fc8a89ea0911d3cac3d187d19
Signed-off-by: Harry Wentland
Reviewed-by: Sun peng Li
Reviewed-by: Roman Li
Acked-by: Harry Wentland
---
From: Andrey Grodzovsky
Use DC interface to query for plane update type
so in case of FULL update you flush any outstanding
commits.
Change-Id: If9104ba3072f115a2fe2fe1e86882b1a8b07bb5e
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Harry
From: Andrey Grodzovsky
You cannot have modeset and flip in the same call for
same CRTC, in such case it will be set mode and set plane,
not a flip.
Change-Id: If7e7ef4a62dfc1c62b2a3fef63a4a6316d0155d3
Signed-off-by: Andrey Grodzovsky
This will be NULL on a new stream. DC handles it gracefully.
Signed-off-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
From: Tom St Denis
Change-Id: Ib2f7b1a4c55033028b88351e8d278cfb77b71c4d
Signed-off-by: Tom St Denis
Reviewed-by: Harry Wentland
---
.../drm/amd/display/dc/dce120/dce120_timing_generator.c | 16 +---
1 file changed,
From: Dmytro Laktyushkin
This is causing asserts for dce 8 and 10 since they do not contain this
field. It is also unnecessary for later DCEs as it is left in it's
default state of 0
Change-Id: Icdc977f8f1990065d3762efda5dd85224d9c534b
Signed-off-by: Dmytro
From: Tom St Denis
Simplify the function by removing identical looking code blocks.
Change-Id: Ibaad41529f5657189599328493d12d951de1e304
Signed-off-by: Tom St Denis
Reviewed-by: Harry Wentland
---
From: Tony Cheng
instead of GC, as after GFX off, GC can be power gated any time
Change-Id: Ia40d341ffd06fb1928bd8d95a4b3ef7eca4f73d1
Signed-off-by: Tony Cheng
Reviewed-by: Dmytro Laktyushkin
Acked-by: Harry Wentland
From: Dmytro Laktyushkin
Change-Id: I0a1b924f5a9e66b3e24f8ac2ca1b6597da919305
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
From: Ayyappa Chandolu
ASSR mode is not enable when we connect eDP panel via DP to eDP converter.
connector_signal is coming as SIGNAL_TYPE_DISPLAY_PORT. Present code
ignoring panel_mode_edp for SIGNAL_TYPE_DISPLAY_PORT. Added checking
panel_mode_edp for all signals.
From: Tom St Denis
Change-Id: I0f893a9abad76da9b403da6103b192af39174088
Signed-off-by: Tom St Denis
Reviewed-by: Harry Wentland
Reviewed-by: Tony Cheng
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
From: Andrey Grodzovsky
Change-Id: Ie5f33497e8ab22da8ae3549028023e0e5837867f
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 1 +
1 file
From: Andrey Grodzovsky
Remove extra loop we have for page flips and do flips in same loop we do
for surface create/update.
Add documentation for synchronization between commits on different crtcs.
Rename function to have DM prefix.
Change-Id:
From: Dmytro Laktyushkin
Change-Id: Ib270db25b4bcb14226f740aa5a8926d0f9c736ca
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
From: Dmytro Laktyushkin
Change-Id: Ie24528a1e8e70a94eb4f029289ea1c4e8f8722b7
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
From: Dmytro Laktyushkin
Apply dc_get_validate_context re-entrancy fix to dc_validate_resources instead
Change-Id: I8502010ff24f6b3b4ea932e1042fdca1a02a5a0c
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Dmytro Laktyushkin
From: Tom St Denis
Change-Id: I0a0cb44a5224a74dd4f0a819c3e8c38c2afca8a1
Signed-off-by: Tom St Denis
Reviewed-by: Harry Wentland
---
.../drm/amd/display/dc/dce120/dce120_timing_generator.c | 17 -
1 file changed,
From: Roman Li
- fixing bug in calculation of reg offset for D5VGA_CONTROL
Change-Id: I0e08d59d03c8daaaf4848a71fac38c37eba492c5
Signed-off-by: Roman Li
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
From: "Leo (Sunpeng) Li"
use_lut() checks if the input surface's pixel format is compatible with
a 256 entry LUT. This function can be used across different versions and
not just dce11.
Change-Id: Ia2813007c91f39939e0ceef65e2f68af0a5e235c
Signed-off-by: Leo (Sunpeng) Li
From: Andrey Grodzovsky
Today we use special interface for flip because of fear of cuncurency issues
over dc->current_ctx. This should be no longer an issue when flipping on
multiple CRTCs concurently since for fast update (as flip is) no new context
is created and the
From: Andrey Grodzovsky
Change-Id: Icf443def80e33f255d2d4c151a36c06951d275d2
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
From: Amy Zhang
- Add immediate ABM disable when eDP is disabled
- Fix purple screen when ABM is mistakenly enabled
on non eDP display
Change-Id: Iff09807f7051126ba95b043061a2f7b1600b34a2
Signed-off-by: Amy Zhang
Reviewed-by: Tony Cheng
From: Andrey Grodzovsky
Typo in expresion.
Change-Id: I156388e19ccfa40996a16383c1532ffde687427e
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Andrey Grodzovsky
Acked-by: Harry Wentland
* Use update_surfaces for stream instead of special casing it
* Fix wrong scanline reporting
* Bunch of other bug fixes for Raven, Vega, and others
* Some small cleanups and a large cleanup in memory interface
Amy Zhang (2):
drm/amd/display: Program CSC Mode For BT2020
drm/amd/display:
On Thu, May 18, 2017 at 8:24 AM, Christian König
wrote:
> From: Christian König
>
> The DPB must be in VRAM, but not in the first segment.
>
> Signed-off-by: Christian König
> Tested-by: Arthur Marsh
On Mon, May 15, 2017 at 6:16 AM, Hawking Zhang wrote:
> only mmhub will be invalidated during vcn dec/enc vm flush
>
> Change-Id: Ide47c892c98a12c6a50918237595135fd7bf208b
> Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
On Mon, May 15, 2017 at 5:06 AM, Hawking Zhang wrote:
> Change-Id: I63002c95c25cc3e2df3931d7d0e6b886b1b7e373
> Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 ++
On 2017-05-20 04:13 AM, Christian König wrote:
Am 19.05.2017 um 22:28 schrieb Harry Wentland:
On 2017-05-19 04:18 PM, Dave Airlie wrote:
On 20 May 2017 at 05:36, Harry Wentland wrote:
On 2017-05-19 11:02 AM, Christian König wrote:
Am 19.05.2017 um 16:01 schrieb
On Tue, May 23, 2017 at 12:00:16PM +0200, Lukas Wunner wrote:
> On Mon, May 22, 2017 at 09:24:34PM +0200, Daniel Vetter wrote:
> > On Thu, May 18, 2017 at 09:33:44PM +0200, Lukas Wunner wrote:
> > > Nicolai Stange reports the following oops which is caused by
> > > dereferencing rdev->pdev before
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Friday, May 12, 2017 6:11 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH xf86-video-amdgpu] Simplify tracking of PRIME scanout
> pixmap
>
> From: Michel
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Thursday, May 11, 2017 8:50 PM
> To: Li, Samuel
> Cc: amd-gfx@lists.freedesktop.org; Yuan, Xiaojie
> Subject: Re: [PATCH 1/1] amdgpu: move asic id table to a separate
On Tue, May 23, 2017 at 2:45 AM, Michel Dänzer wrote:
> On 22/05/17 07:09 PM, Marek Olšák wrote:
>> On Mon, May 22, 2017 at 12:00 PM, Michel Dänzer wrote:
>>> On 20/05/17 06:26 PM, Marek Olšák wrote:
On May 20, 2017 3:26 AM, "Michel Dänzer"
Am 23.05.2017 um 12:14 schrieb Lukas Wunner:
On Tue, May 23, 2017 at 09:32:38AM +0200, Christian König wrote:
Am 23.05.2017 um 05:55 schrieb Michel Dänzer:
On 23/05/17 12:50 PM, Lukas Wunner wrote:
On Tue, May 23, 2017 at 12:09:49PM +0900, Michel Dänzer wrote:
On 22/05/17 11:04 PM, Lukas
On Tue, May 23, 2017 at 09:32:38AM +0200, Christian König wrote:
> Am 23.05.2017 um 05:55 schrieb Michel Dänzer:
> >On 23/05/17 12:50 PM, Lukas Wunner wrote:
> >>On Tue, May 23, 2017 at 12:09:49PM +0900, Michel Dänzer wrote:
> >>>On 22/05/17 11:04 PM, Lukas Wunner wrote:
> On Sun, May 21, 2017
On Mon, May 22, 2017 at 03:35:48PM -0400, Sean Paul wrote:
> On Mon, May 22, 2017 at 04:04:07PM +0200, Lukas Wunner wrote:
> > On Sun, May 21, 2017 at 09:31:09AM +0200, Nicolai Stange wrote:
> > > On Thu, May 18 2017, Lukas Wunner wrote:
> > [snip]
> > > > Reported-by: Nicolai Stange
Am 23.05.2017 um 09:36 schrieb Daniel Vetter:
On Tue, May 23, 2017 at 09:32:38AM +0200, Christian König wrote:
Am 23.05.2017 um 05:55 schrieb Michel Dänzer:
On 23/05/17 12:50 PM, Lukas Wunner wrote:
On Tue, May 23, 2017 at 12:09:49PM +0900, Michel Dänzer wrote:
On 22/05/17 11:04 PM, Lukas
On Tue, May 23, 2017 at 09:36:44AM +0200, Daniel Vetter wrote:
> On Tue, May 23, 2017 at 09:32:38AM +0200, Christian König wrote:
> > Am 23.05.2017 um 05:55 schrieb Michel Dänzer:
> > > On 23/05/17 12:50 PM, Lukas Wunner wrote:
> > > > On Tue, May 23, 2017 at 12:09:49PM +0900, Michel Dänzer wrote:
On Tue, May 23, 2017 at 09:32:38AM +0200, Christian König wrote:
> Am 23.05.2017 um 05:55 schrieb Michel Dänzer:
> > On 23/05/17 12:50 PM, Lukas Wunner wrote:
> > > On Tue, May 23, 2017 at 12:09:49PM +0900, Michel Dänzer wrote:
> > > > On 22/05/17 11:04 PM, Lukas Wunner wrote:
> > > > > On Sun,
Am 23.05.2017 um 05:55 schrieb Michel Dänzer:
On 23/05/17 12:50 PM, Lukas Wunner wrote:
On Tue, May 23, 2017 at 12:09:49PM +0900, Michel Dänzer wrote:
On 22/05/17 11:04 PM, Lukas Wunner wrote:
On Sun, May 21, 2017 at 09:31:09AM +0200, Nicolai Stange wrote:
On Thu, May 18 2017, Lukas Wunner
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