Got it, I will make a v2 patch.
Thanks.
-Original Message-
From: Zhang, Hawking
Sent: Tuesday, August 20, 2019 2:52 PM
To: Feng, Kenneth ; amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth
Subject: RE: [PATCH] drm/amd/powerplay: disable MMHUB PG on navi10/14
Hi Kenneth,
We should contro
Hi Kenneth,
We should control PG feature on/off from nv_common_early_init by setting
initial value of pg_flag, instead of hard-code it from SMU side.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Kenneth Feng
Sent: 2019年8月20日 14:34
To: amd-gfx@lists.freedesktop.org
Cc:
Hi Kevin,
smu11_thermal_policy provides the default thermal policy if the ASIC does not
provide its own(e.g. Navi10). It's not ASIC specific.
Btw I think we should have enough information to provide Navi10's own
settings(for temp2/3) in navi10_get_thermal_temperature_range().
Can you help to ad
Disable MMHUB PG on navi10 and navi14 according to the
production requirement.
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
Hi Alex/Christian,
I have update the previous patch. Would you please help to review it?
Here is the updated part compared with last patch
The change here is to adapt vega10 sriov need to use the mc base from 0,
instead of read the config from mmhub.
- if (!amdgpu_sriov_vf(adev)) {
-
sriov would not use agp, so seperate the fb aperture setting.
Change-Id: I1372cd355326731a31361bff13d79e12121b8651
Signed-off-by: Frank.Min
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 39
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 12 +-
drivers/gpu/dr
I don't recommend it.
each asic maybe has different thermal policy, you can custom this value in asic
file .
and your patch define a new array in smu_v11_0.h header file.
it's never done that before, and the code looks is not clearly.
Best Regards,
Kevin
From: F
> -Original Message-
> From: Wang, Kevin(Yang)
> Sent: Tuesday, August 20, 2019 1:36 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, Ray ; Wang, Kevin(Yang)
>
> Subject: [PATCH] drm/amd/powerplay: remove duplicate macro
> smu_get_uclk_dpm_states in amdgpu_smu.h
>
> remove duplicate m
remove duplicate macro smu_get_uclk_dpm_states in amdgpu_smu.h
"
#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
((smu)->ppt_funcs->get_uclk_dpm_states ?
(smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
#define smu_get_max_sustainable_c
Reviewed-by: Kevin Wang
Best Regards,
Kevin
From: amd-gfx on behalf of Evan Quan
Sent: Tuesday, August 20, 2019 12:23 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH] drm/amd/powerplay: correct typo
"COMPUTE" was wrongly spelled as "CUST
"COMPUTE" was wrongly spelled as "CUSTOM".
Change-Id: I11693c0e55c2ce5c889d57bb7411fdf9795a8739
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gp
Consider amdgpu_ras_error_query < 0 and !con are almost impossible, the patch
is:
Reviewed-by: Tao Zhou
> -Original Message-
> From: amd-gfx On Behalf Of
> Guchun Chen
> Sent: 2019年8月20日 10:25
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Li, Dennis ; Pan, Xinhui
> ; Zhou1, T
Reviewed-by: Kenneth Feng mailto:kenneth.f...@amd.com>>
From: Quan, Evan
Sent: Tuesday, August 20, 2019 10:10 AM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Wang, Kevin(Yang)
Subject: RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings
Ping..
From: Quan, Evan
Sent
From: Alex Deucher
Sent: Monday, August 19, 2019 11:33 PM
To: Wang, Kevin(Yang)
Cc: amd-gfx@lists.freedesktop.org ; Feng,
Kenneth ; Quan, Evan ; Huang, Ray
Subject: Re: [PATCH] drm/amd/powerplay: add smu_smc_read_sensor support for
arcturus
On Fri, Aug 16, 2
Reviewed-by: Kevin Wang
Best Regards,
Kevin
From: Quan, Evan
Sent: Tuesday, August 20, 2019 10:09 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Kevin(Yang)
Subject: RE: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value
Ping..
From: Quan, Evan
Sent: Fri
Use unsigned long type for the same ras count variable.
This will avoid overflow on 64 bit system.
Change-Id: I011406d81bad69a65433b63960e1691c4959bbc5
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 4 ++--
drivers/gpu/drm
Ping..
From: Quan, Evan
Sent: Monday, August 19, 2019 1:27 PM
To: Feng, Kenneth ; Wang, Kevin(Yang)
; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings
Yes, the lowest settings for thermal controller is 0.
Regards
Evan
From: Feng, Kenn
Ping..
From: Quan, Evan
Sent: Friday, August 16, 2019 4:00 PM
To: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value
Since smu_get_atom_data_table() was already used in
smu_v11_0_get_vbios_bootup_values(). We should get all our nee
Please add the followings to the description part. With that added, the patch
is Reviewed-by: Evan Quan
"
This fixes the following static checker warning.
drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:390
smu_v11_0_setup_pptable()
warn: passing casted pointer '&size' to 'sm
Hi all,
On Mon, 19 Aug 2019 18:34:41 -0700 Randy Dunlap wrote:
>
> On 8/19/19 2:18 AM, Stephen Rothwell wrote:
> > Hi all,
> >
> > Changes since 20190816:
> >
>
> on x86_64:
>
> ../drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c: In function ‘amdgpu_exit’:
> ../drivers/gpu/drm/amd/amdgpu/amdgpu_drv
>> Whenever a connector on an MST network is attached, detached, or
>> undergoes a modeset, the DSC configs for each stream on that
>> topology will be recalculated. This can change their required
>> bandwidth, requiring a full reprogramming, as though a modeset
>> was performed, even if that strea
On 8/19/19 11:50 AM, David Francis wrote:
> For DSC MST, sometimes monitors would break out
> in full-screen static. The issue traced back to the
> PPS generation code, where these variables were being used
> uninitialized and were picking up garbage.
>
> memset to 0 to avoid this
>
> Signed-off-
On 8/19/19 11:50 AM, David Francis wrote:
>> We were using drm helpers to convert a timing into its
>> bandwidth, its bandwidth into pbn, and its pbn into timeslots
>>
>> These helpers
>> -Did not take DSC timings into account
>> -Used the link rate and lane count of the link's aux device,
>> whi
On 8/19/19 11:50 AM, David Francis wrote:
> Whenever a connector on an MST network is attached, detached, or
> undergoes a modeset, the DSC configs for each stream on that
> topology will be recalculated. This can change their required
> bandwidth, requiring a full reprogramming, as though a modese
On 8/19/19 11:50 AM, David Francis wrote:
> We were using drm helpers to convert a timing into its
> bandwidth, its bandwidth into pbn, and its pbn into timeslots
>
> These helpers
> -Did not take DSC timings into account
> -Used the link rate and lane count of the link's aux device,
> which are
Tested-by: Mikita Lipski
Mikita Lipski
On 2019-08-19 11:50 a.m., David Francis wrote:
> In create_stream_for_sink, check for SST DP connectors
>
> Parse DSC caps to DC format, then, if DSC is supported,
> compute the config
>
> DSC hardware will be programmed by dc_commit_state
>
> Cc: Mikita
If there is limited link bandwidth on a MST network,
it must be divided fairly between the streams on that network
Implement an algorithm to determine the correct DSC config
for each stream
The algorithm:
This
[ ] ( )
represents the range of bandwidths possible for
Whenever a connector on an MST network is attached, detached, or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if that stream did not chang
Rework the dm_helpers_write_dsc_enable callback to
handle the MST case
Depending on how DSC is done, the DP_DSC_ENABLE bit
needs to be set on a different point
For SST, use the link aux
For endpoint DSC over DP-to-DP peer devices,
use the output port
For peer device DSC over DP-to-DP peer devic
This patchset enables Display Stream Compression (DSC) on DP
connectors on Navi ASICs, both SST and DSC.
8k60 and 4k144 support requires ODM combine, an AMD internal
feature that may be a bit buggy right now.
Patches 1 through 5 enable DSC for SST. Most of the work was
already done in the Navi p
This field on drm_dp_mst_branch was never filled
Initialize it to zero when the list of ports is created.
When a port is added to the list, increment num_ports
Signed-off-by: David Francis
---
drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gp
The first step in MST DSC is checking MST endpoints
to see how DSC can be enabled
Case 1: DP-to-DP peer device
if the branch immediately upstream has
- PDT = DP_PEER_DEVICE_DP_MST_BRANCHING (2)
- DPCD rev. >= DP 1.4
- Exactly one input and one output
- The output has PDT = DP_PEER_DEVICE_SST_S
This reverts commit 5f2fd347eeff7d4ce271920efd47baaa18fe968c.
Re-enable enc2_dp_set_dsc_config. This function caused warnings
due to missing register definitions. With the registers added,
this now works
Signed-off-by: David Francis
Reviewed-by: Roman Li
Reviewed-by: Harry Wentland
---
.../gp
We were using drm helpers to convert a timing into its
bandwidth, its bandwidth into pbn, and its pbn into timeslots
These helpers
-Did not take DSC timings into account
-Used the link rate and lane count of the link's aux device,
which are not the same as the link's current cap
-Did not take FEC
To use these functions in drm driver directories, they must be
exported
Signed-off-by: David Francis
---
drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 53a0ad16e37b..
As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating
if FEC can be supported up to that point in the MST network.
The bit is the first byte of the ENUM_PATH_RESOURCES ack reply,
bottom-most bit (refer to section 2.11.9.4 of DP standard,
v1.4)
That value is needed for FEC and DSC support
Sto
In create_stream_for_sink, check for SST DP connectors
Parse DSC caps to DC format, then, if DSC is supported,
compute the config
DSC hardware will be programmed by dc_commit_state
Cc: Mikita Lipski
Signed-off-by: David Francis
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 ++
This reverts commit 80e80ec817f161560b4159608fb41bd289abede3.
This commit fixed an issue with underscan commits not updating all
needed timing values, but through various refactors it is no longer
necessary. It causes corruption on odm combine by
overwriting the halved h_active in the stream timin
For DSC MST, sometimes monitors would break out
in full-screen static. The issue traced back to the
PPS generation code, where these variables were being used
uninitialized and were picking up garbage.
memset to 0 to avoid this
Signed-off-by: David Francis
---
drivers/gpu/drm/amd/display/dc/cor
This reverts commit 55a6f5bbcf00a49565946c0a9b8c716313dc6c05.
This commit was accidentally promoted twice
Signed-off-by: David Francis
Reviewed-by: Roman Li
Reviewed-by: Harry Wentland
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 4 --
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 6
This reverts commit 55ad81f3510ec1a1c19e6a4d8a6319812d07d256.
optc dsc config was causing warnings due to missing register
definitions. With the registers restored, the function can
be re-enabled
The reverted commit also disabled sanity checks and dsc
power gating. The sanity check warnings are n
fix size type errors, from uint32_t to uint16_t.
it will cause only initializes the highest 16 bits in
smu_get_atom_data_table function.
Signed-off-by: Kevin Wang
Reported-by: Dan Carpenter
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
d
On Mon, Aug 19, 2019 at 5:39 PM Will Deacon wrote:
>
> On Mon, Aug 19, 2019 at 05:16:37PM +0200, Andrey Konovalov wrote:
> > On Mon, Aug 19, 2019 at 5:03 PM Will Deacon wrote:
> > >
> > > On Mon, Aug 19, 2019 at 03:14:42PM +0200, Andrey Konovalov wrote:
> > > > Fix tagged_ptr not being initialize
On Mon, Aug 19, 2019 at 05:16:37PM +0200, Andrey Konovalov wrote:
> On Mon, Aug 19, 2019 at 5:03 PM Will Deacon wrote:
> >
> > On Mon, Aug 19, 2019 at 03:14:42PM +0200, Andrey Konovalov wrote:
> > > Fix tagged_ptr not being initialized when TBI is not enabled.
> > >
> > > Dan Carpenter
> >
> > Gu
On Fri, Aug 16, 2019 at 3:22 AM Wang, Kevin(Yang) wrote:
>
> the bellow patch refine the sensor read sequence,
> but missed to add arcuturs support. (arcuturs_ppt.c)
>
> drm/amd/powerplay: change smu_read_sensor sequence in smu
>
> Signed-off-by: Kevin Wang
> ---
> drivers/gpu/drm/amd/powerplay/
Hi Dan,
Thank you for reporting this bug to me,
I will make a fix patch as soon as possible, when patch ready after I send
copies to you review,
thank you.
Best Regards,
Kevin
From: Dan Carpenter
Sent: Monday, August 19, 2019 9:03 PM
To: Wang, Kevin(Yang)
Cc:
On Mon, Aug 19, 2019 at 5:03 PM Will Deacon wrote:
>
> On Mon, Aug 19, 2019 at 03:14:42PM +0200, Andrey Konovalov wrote:
> > Fix tagged_ptr not being initialized when TBI is not enabled.
> >
> > Dan Carpenter
>
> Guessing this was Reported-by, or has Dan introduced his own tag now? ;)
Oops, yes,
On 8/19/19 4:48 PM, Neil Armstrong wrote:
> Hi Dariusz, Hans,
>
> I can apply the dw-hdmi patches if necessary.
I'd appreciate it if you can do that.
Thanks,
Hans
>
> Neil
>
> On 19/08/2019 11:38, Hans Verkuil wrote:
>> Hi all,
>>
>> The patches in this series can be applied independ
On Mon, Aug 19, 2019 at 03:14:42PM +0200, Andrey Konovalov wrote:
> Fix tagged_ptr not being initialized when TBI is not enabled.
>
> Dan Carpenter
Guessing this was Reported-by, or has Dan introduced his own tag now? ;)
Got a link to the report?
Will
__
Hi Dariusz, Hans,
I can apply the dw-hdmi patches if necessary.
Neil
On 19/08/2019 11:38, Hans Verkuil wrote:
> Hi all,
>
> The patches in this series can be applied independently from each other.
>
> If you maintain one of these drivers and you want to merge it for v5.4
> yourself, then pleas
From: Dmytro Laktyushkin
Need to memset all odm pipes when calling dc_remove_stream_from_ctx
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 65 +--
1 file changed, 32 insertions(+), 3
From: Jaehyun Chung
[Why] HW rotation is not enabled. Calculations for cursor rotation
are wrong for the values passed to set_cursor_position.
[How] Swap Src rect and height and vertically mirror surface for
the correct surface rotation direction. Cursor position is rotated
according to angle. O
From: Joshua Aberback
[Why]
The register LVTMA_PWRSEQ_CNTL is used to determine the power state of the
embedded display. Currently we do not actually read this register's values,
so during power down we think that this display is already off, so we skip
calling into VBIOS to actually turn it off.
From: Derek Lai
[Why]
We should be using the ddc_num from res_caps. As the
pipe count != number of i2c resources.
[How]
Use ddc_num from res_cap instead of pipe count.
Signed-off-by: Derek Lai
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dce/dce_i
From: Jun Lei
[why]
Calculating DCFCLK DS time requires calculating
delivery time for luma/chroma, but this value is
not calculated in DMLv2, it was inadvertently
removed when porting DMLv2
[how]
Add the calculation back
Signed-off-by: Jun Lei
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanp
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 239cb0
From: Jun Lei
[why]
Previous workaround to prevent a vsync flip to be converted
to immediate flip is no longer needed, and is risky because
there are cases where it can result in infinite loop.
[how]
Remove wait loop (which is potentially infinite) before locking
pipe
Signed-off-by: Jun Lei
Re
From: hersen wu
[WHY] value of dchub_ref_clock is decided by dchubbub global timer
settings which is programmed by vbios command table disp_init.
for multi-GPU case, vbios is posted only for primary GPU. without
vbios posted for the secondary GPU, value of dchub_ref_clock is not
set properly. thi
From: David Francis
DRM provides drm_dp_mst_dump_topology, which prints
useful information about MST devices
Hook this up to a debugfs file named amdgpu_mst_topology
Signed-off-by: David Francis
Acked-by: Bhawanpreet Lakha
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 24 ++
From: Dmytro Laktyushkin
Update bw validation to use prev and next odm pipe pointers
for populating dml inputs.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 40 +--
1 file changed,
From: Charlene Liu
[Description]
OS will reserve HW state in UEFI mode.
Driver init_hw reset to RGB which caused HDMI green in YCbCr mode.
read HW blank_color based on acc_mode.
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../amd/display/dc/dcn
From: Jaehyun Chung
[How] Allocate memory for default page and program memory block addr
into default page addr register.
Signed-off-by: Jaehyun Chung
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/d
From: Bayan Zabihiyan
[Why]
We need to have the ability to to tell us set degamma on the cursor.
[How]
Pass a flag down to register programming that tells us if the
current surface format needs cursor degamma.
Signed-off-by: Bayan Zabihiyan
Reviewed-by: Krunoslav Kovac
Acked-by: Bhawanpreet L
From: Wyatt Wood
[Why]
A recent bug showed that logging would be useful in debugging
various gamma issues.
[How]
Add logging in dc.
Fix formatting for easier graphing.
Signed-off-by: Wyatt Wood
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn10/dcn10_hw_se
From: Dmytro Laktyushkin
dcn20 requires special casing for odm.
This change treats odm as alternative to mpc tree on dcn20.
This is planned to be fixed in a future refactor
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/displa
From: Yogesh Mohan Marimuthu
[Why]
In newer hardware MANUAL_FLOW_CONTROL is not a trigger bit. Due to this
front porch is fixed and in these hardware freesync does not work.
[How]
Change the programming to generate a pulse so that the event will be
triggered, front porch will be cut short and fr
From: Bayan Zabihiyan
[Why]
Existing HW Features, HW Diags test requested that the
registers be exposed.
[How]
Add V_TOTAL_MID to existing DC structures.
Make sure values are passed down throughout DC
Add Register definition.
Program the additional registers
Add additional Logic for V_TOTAL_CONT
From: Nikola Cornij
[why]
num_slices_h was not being checked
[How]
Fix the typo and check num_slices_h
Signed-off-by: Nikola Cornij
Reviewed-by: Harry Wentland
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
From: Charlene Liu
[Description]
port spdif fix to staging:
spdif hardwired to afmt inst 1.
spdif func pointer
spdif resource allocation (reserve last audio endpoint for spdif only)
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd
From: Martin Leung
[why]
during a refactor a redundant code that has unknown behaviour was added.
[how]
removed old bad code
Fixes: 7b0b6ee982ab018ecce70f661e676d059bfe8270
drm/amd/display: Make init_hw and init_pipes generic for seamless boot
Signed-off-by: Martin Leung
Reviewed-by:
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 6ee82e
From: Qingqing Zhuo
[Why]
This function is not being used, it was left in
when introducing DCN2
[How]
Remove the function
Signed-off-by: Qingqing Zhuo
Reviewed-by: Eric Bernstein
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c | 1 -
drivers/gpu/drm/amd/disp
From: Zi Yu Liao
[why]
With visual confirm enabled, displays where ODM combine is enabled
has a test pattern stuck on the right half of the display even
though the display is unblanked.
[how]
Add a condition to not show the colour ramp test pattern when the
display is unblanked.
Signed-off-by:
From: Dmytro Laktyushkin
ODM next and prev pipe were missing from dc_copy_state
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Nikola Cornij
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
2
From: Nikola Cornij
[why]
Before a statically allocated PPS data structure, that did
get zeroed-out at startup, had been re-used for making packed PPS
SDP. With S3 fix, using a non-initialized PPS data structure was
introduced, while wrongly assuming it'd get initialized before it's
populated. As
From: Qingqing Zhuo
IEEE OUI will now be used while referring to certain vendors.
instead of normal index
Signed-off-by: Qingqing Zhuo
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 2 +-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c
From: Ahmad Othman
[Why]
Video Timing Extended Metadata packet (VTEM) is not
specific to freesync. So move it out of freesync module
[How]
- Moved VTEM from freesync module to info_packet module
- Created new structure for VTEM parameters that can be used for VRR
and FVA
Signed-off-by: Ahmad Ot
From: Ilya Bakoulin
Set the writeback Hratio and Vratio in dml.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/
From: Joseph Gravenor
add new function to get the voltage at the end of
dcn_validate_bandwidth, to check against the
highest voltage we allow.
Created a stub to allow for optimizations
Signed-off-by: Joseph Gravenor
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet Lakha
Acked-by: Sun peng Li
--
From: Josip Pavic
[Why]
ABM 2.3 firmware expects information in iRAM that differs from previous
versions of ABM, so a mechanism is required to provide it with that
information.
[How]
Extend the existing iRAM definition to include parameters added by
ABM 2.3, and load it if DMCU is running ABM 2.
From: Dmytro Laktyushkin
A previous odm change broke stream enable by always setting
n_multiply as if odm was on.
This fixes the check for odm by making sure opp count is >1
rather than not 0.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
driver
From: Wyatt Wood
Adding NULL checks to various parameters in log_tf, to avoid
nullptr errors
Signed-off-by: Wyatt Wood
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
Acked-by: Nikola Cornij
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c| 9 ++---
1 file changed, 6 i
From: Su Sung Chung
[Why]
Disable_audio_stream gets enum option as a paramenter which will decide
if we free acquired resources or not. However checks for the option is
guarded by the other condition which check if audio stream is getting
diabled more than once. With both conditions combined, if
Summary Of Changes
*ODM fixes
*Gamma logging
*DSC fixes
Ahmad Othman (1):
drm/amd/display: Refactoring VTEM
Anthony Koo (2):
drm/amd/display: 3.2.47
drm/amd/display: 3.2.48
Bayan Zabihiyan (2):
drm/amd/display: add Cursor Degamma logic for DCN2
drm/amd/display: Expose OTG_V_TOTAL_MID f
From: Zi Yu Liao
[why]
With Scatter Gather enabled, HUBP underflows during MPO enabled video
playback. hubp_init has a register write that fixes this problem, but
the register is cleared when HUBP gets power gated.
[how]
Make a call to hubp_init during enable_plane, so that the fix can
be applie
From: Dmytro Laktyushkin
Currently odm is handled using top_bottom pipe by special casing
the differing opps to differentiate from mpc combine.
Since top/bottom pipe list was made to track mpc muxing this creates
difficulties in adding a 4 pipe odm case support.
Rather than continue using mpc c
From: Julian Parkin
[Why]
dig_encoder_sel_to_atom will always return zero on any ASIC version
past DCE80 since programming of the FE selection is handled by
driver, but the translation code was left in the function, making
it look like a coding error.
[How]
Remove code that has no effect, and re
On Mon, Aug 19, 2019 at 3:14 PM Andrey Konovalov wrote:
>
> Fix tagged_ptr not being initialized when TBI is not enabled.
>
> Dan Carpenter
> Signed-off-by: Andrey Konovalov
> ---
> tools/testing/selftests/arm64/tags_test.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> dif
Fix tagged_ptr not being initialized when TBI is not enabled.
Dan Carpenter
Signed-off-by: Andrey Konovalov
---
tools/testing/selftests/arm64/tags_test.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/tools/testing/selftests/arm64/tags_test.c
b/tools/testing/selfte
Applied. thanks!
Alex
On Sun, Aug 18, 2019 at 9:33 PM Yuan, Xiaojie wrote:
>
> Reviewed-by: Xiaojie Yuan
>
> Xiaojie
>
> > On Aug 19, 2019, at 12:00 AM, Christophe JAILLET
> > wrote:
> >
> > '_navi10_ip_offset_HEADER' is already used in 'navi10_ip_offset.h', so use
> > '_navi12_ip_offset_HEA
Hello Kevin Wang,
The patch b55c83a7438d: "drm/amd/powerplay: implement smc firmware
v2.1 for smu11" from Jun 21, 2019, leads to the following static
checker warning:
drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:390
smu_v11_0_setup_pptable()
warn: passing casted pointer '&
On Mon, Aug 19, 2019 at 11:38 AM Hans Verkuil wrote:
>
> Hi all,
>
Hi Hans.
> The patches in this series can be applied independently from each other.
>
> If you maintain one of these drivers and you want to merge it for v5.4
> yourself, then please do so and let me know. If you prefer I commit it
On 8/19/19 1:28 PM, Dariusz Marcinkiewicz wrote:
> On Mon, Aug 19, 2019 at 11:38 AM Hans Verkuil
> wrote:
>>
>> Hi all,
>>
> Hi Hans.
>> The patches in this series can be applied independently from each other.
>>
>> If you maintain one of these drivers and you want to merge it for v5.4
>> yoursel
Hello Charlene Liu,
This is a semi-automatic email about new static checker warnings.
The patch 925f566cb7ae: "drm/amd/display: add set and get clock for
testing purposes" from Jun 27, 2019, leads to the following Smatch
complaint:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequ
Am 16.08.19 um 10:59 schrieb Frank.Min:
Change-Id: I7153153785fdd54a10ebc47e778e06982edc79d7
Signed-off-by: Frank.Min
Can't judge if the values are correct, but feel free to add an Acked-by:
Christian König to the first two patches.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
1
> As I point out. For SRIOV, amdgpu_gmc_agp_location() would not be called, so
> the value calculation would not be valid.
Yeah, that is a good point. The values are zero initialized, but that is
probably not correct in this moment.
agp_start should be set to 0x and agp_end to 0x0, that
Hi Christian,
As I point out. For SRIOV, amdgpu_gmc_agp_location() would not be called, so
the value calculation would not be valid. Would you please give more info why
we need the AGP except for the zfb?
For another, whether you review the other patches?
Best Regards,
Frank
-邮件原件-
发件人
Hi all,
The patches in this series can be applied independently from each other.
If you maintain one of these drivers and you want to merge it for v5.4
yourself, then please do so and let me know. If you prefer I commit it
to drm-misc, then please review and (hopefully) Ack the patch.
I would re
Hi Christian,
Appreciate your concern and suggestion!
I am fine to remove the external file and move all test configurations into C
code.
I will prepare patches to address this later.
Regards,
Guchun
-Original Message-
From: Koenig, Christian
Sent: Monday, August 19, 2019 4:42 PM
To:
OH, STOP! Good that we talked about that because that would have caused quite
a bunch of trouble.
The case in amdgpu_ttm_init() would break, we intentionally reserve memory at
the beginning of the visible space here to avoid problem switching between
VBIOS and KMS.
I suggest to first add a du
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