I think we should do it differently because this interface will be mostly
unused by open source userspace in its current form.
Let's set the workload hint in drm_amdgpu_ctx_in::flags, and that will be
immutable for the lifetime of the context. No other interface is needed.
Marek
On Mon, Sep 26,
Reinit mes ip block during reset on SRIOV.
Signed-off-by: YiPeng Chai
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index
Gfx v11_0_3 supports ras on SRIOV, so need to resume ras
during reset.
Signed-off-by: YiPeng Chai
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
Enable ras for mp0 v13_0_10 on SRIOV.
Signed-off-by: YiPeng Chai
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index
[AMD Official Use Only - General]
OK, I see. Thanks for the explanations.
BR
Evan
> -Original Message-
> From: Koenig, Christian
> Sent: Tuesday, March 21, 2023 1:32 AM
> To: Kim, Jonathan ; Christian König
> ; Quan, Evan ;
> amd-gfx@lists.freedesktop.org
> Cc: Kuehling, Felix
>
On Mon, Mar 20, 2023 at 1:38 PM Alex Deucher
wrote:
> Add UAPI to query the GFX shadow buffer requirements
> for preemption on GFX11. UMDs need to specify the shadow
> areas for preemption.
>
> Signed-off-by: Alex Deucher
> ---
> include/uapi/drm/amdgpu_drm.h | 10 ++
> 1 file
On 2023-01-25 14:53, Jonathan Kim wrote:
The debugger can attach to a process prior to HSA enablement (i.e.
inferior is spawned by the debugger and attached to immediately before
target process has been enabled for HSA dispatches) or it
can attach to a running target that is already HSA
On Mon, Mar 20, 2023 at 1:38 PM Alex Deucher
wrote:
> Add UAPI to query the GFX shadow buffer requirements
> for preemption on GFX11. UMDs need to specify the shadow
> areas for preemption.
>
> Signed-off-by: Alex Deucher
> ---
> include/uapi/drm/amdgpu_drm.h | 10 ++
> 1 file
On 2023-01-25 14:53, Jonathan Kim wrote:
Add a debug operation that allows the debugger to send an exception
directly to runtime through a payload address.
For memory violations, normal vmfault signals will be applied to
notify runtime instead after passing in the saved exception data
when a
On 2023-01-25 14:53, Jonathan Kim wrote:
Exception events can be generated from interrupts or queue activitity.
The raise event function will save exception status of a queue, device
or process then notify the debugger of the status change by writing to
a debugger polled file descriptor that
On 2023-01-25 14:53, Jonathan Kim wrote:
To enable HW debug mode per process, all devices must be debug enabled
successfully. If a failure occures, rewind the enablement of debug mode
on the enabled devices.
A power management scenario that needs to be considered is HW
debug mode setting
On 2023-01-25 14:53, Jonathan Kim wrote:
Due to a HW bug, waves in only half the shader arrays can enter trap.
When starting a debug session, relocate all waves to the first shader
array of each shader engine and mask off the 2nd shader array as
unavailable.
When ending a debug session,
[Public]
> -Original Message-
> From: Kai-Heng Feng
> Sent: Wednesday, March 15, 2023 07:07
> To: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Kai-Heng Feng ; David Airlie
> ; Daniel Vetter ; Zhang, Hawking
> ; Gao, Likun ; Kuehling,
> Felix ; Zhao, Victor ;
> Xiao,
On 2023-01-25 14:53, Jonathan Kim wrote:
Similar to the F32 HWS, the RS64 HWS for GFX11 now supports a multi-process
debug API.
The skip_process_ctx_clear ADD_QUEUE requirement is to prevent the MES
from clearing the process context when the first queue is added to the
scheduler in order to
On 3/10/23 12:51, Ville Syrjälä wrote:
> On Fri, Mar 10, 2023 at 07:48:04PM +0200, Ville Syrjälä wrote:
>> On Thu, Mar 09, 2023 at 04:30:27PM -0500, Hamza Mahfooz wrote:
>>> We should be checking if drm_dp_dpcd_read() returns the size that we are
>>> asking it to read instead of just checking
On 3/10/23 13:42, Hamza Mahfooz wrote:
> We should be checking if drm_dp_dpcd_read() returns the size that we are
> asking it to read instead of just checking if it is greater than zero.
> So, compare the return value of drm_dp_dpcd_read() to the requested
> read size.
>
> Signed-off-by: Hamza
On 2023-01-25 14:53, Jonathan Kim wrote:
Unlike single process debug devices, multi-process debug devices allow
debug mode setting per-VMID (non-device-global).
Because the HWS manages PASID-VMID mapping, the new MAP_PROCESS API allows
the KFD to forward the required SPI debug register write
On 2023-01-25 14:53, Jonathan Kim wrote:
Older HW only supports debugging on a single process because the
SPI debug mode setting registers are device global.
The HWS has supplied a single pinned VMID (0xf) for MAP_PROCESS
for debug purposes. To pin the VMID, the KFD will remove the VMID from
On 2023-01-25 14:53, Jonathan Kim wrote:
The HWS schedule allows a grace period for wave completion prior to
preemption for better performance by avoiding CWSR on waves that can
potentially complete quickly. The debugger, on the other hand, will
want to inspect wave status immediately after it
Only set the supported flag if we have new enough CP FW.
XXX: don't commit this until the CP FW versions are finalized!
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
Add UAPI to query the GFX shadow buffer requirements
for preemption on GFX11. UMDs need to specify the shadow
areas for preemption.
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h
We need to reset the shadow state every time we submit an
IB and there needs to be a COND_EXEC packet after the
SET_Q_PREEMPTION_MODE packet for it to work properly, so
we should emit both of these packets regardless of whether
there is a job present or not.
Reviewed-by: Christian König
To provide IP specific shadow sizes. UMDs will use
this to query the kernel driver for the size of the
shadow buffers.
v2: make callback return an int (Alex)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 12
1 file changed, 12 insertions(+)
diff --git
So UMDs can determine whether the kernel supports this.
Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
Use the new callback to fetch the data. Return an error if
not supported. UMDs should use this query to check whether
shadow buffers are supported and if so what size they
should be.
v2: return an error rather than a zerod structure.
Signed-off-by: Alex Deucher
---
Used to get the size and alignment requirements for
the gfx shadow buffer for preemption.
v2: use FW version check to determine whether to
return a valid size here
return an error if not supported (Alex)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 27
From: Christian König
Add ring callback for gfx to update the CP firmware
with the new shadow information before we process the
IB.
v2: add implementation for new packet (Alex)
v3: add current FW version checks (Alex)
v4: only initialize shadow on first use
Only set IB_VMID when a valid
From: Christian König
Add support for submitting the shadow update packet
when submitting an IB. Needed for MCBP on GFX11.
v2: update API for CSA (Alex)
v3: fix ordering; SET_Q_PREEMPTION_MODE most come before COND_EXEC
Add missing check for AMDGPU_CHUNK_ID_CP_GFX_SHADOW in
Use this to determine if we support the new SET_Q_PREEMPTION_MODE
packet.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 ++
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 13 +
2 files changed, 15 insertions(+)
diff --git
For GFX11, the UMD needs to allocate some shadow buffers
to be used for preemption. The UMD allocates the buffers
and passes the GPU virtual address to the kernel since the
kernel will program the packet that specified these
addresses as part of its IB submission frame.
v2: UMD passes shadow
This patch set allows for FW assisted shadowing on supported
platforms. A new enough CP FW is required. This feature is
required for mid command buffer preemption and proper SR-IOV
support. This also simplifies the UMDs by allowing persistent
hardware state when the command submission executes.
Ah, yes! GART doesn't need to be read to make a GTT allocation.
When GART becomes ready it will be filled with all the buffers which
were allocated before it was ready.
So this is perfectly fine.
Thanks,
Christian.
Am 20.03.23 um 18:24 schrieb Kim, Jonathan:
[Public]
This was a long time
[Public]
This was a long time ago but I think we agreed allocation was ok before GART
was ready.
IIRC, there was also some mentioned related scenario where APUs needed to work
without VRAM but allocations were required (but I don't know the details
regarding that).
I vaguely remember the
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 73f2c2a7e1d2b31fdd5faa6dfa151c437a6c0a5a Add linux-next specific
files for 20230320
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202303081807.lblwkmpx-...@intel.com
https
I don't think so. Have we recently re-ordered something here?
Christian.
Am 20.03.23 um 08:05 schrieb Quan, Evan:
[AMD Official Use Only - General]
I happened to find the sdma_access_bo allocation from GTT seems performing
before gart is ready.
That makes the "amdgpu_gart_map" is skipped
On 2023-03-20 10:08, Graham Sider wrote:
Add log to display whether RAM is direct vs DMA mapped.
Signed-off-by: Graham Sider
Acked-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git
On Mon, Mar 20, 2023 at 11:49 AM Christian König
wrote:
>
> Am 17.03.23 um 18:17 schrieb Alex Deucher:
> > From: Christian König
> >
> > Add ring callback for gfx to update the CP firmware
> > with the new shadow information before we process the
> > IB.
> >
> > v2: add implementation for new
Am 20.03.23 um 17:01 schrieb Alex Deucher:
On Mon, Mar 20, 2023 at 11:55 AM Christian König
wrote:
Am 20.03.23 um 16:49 schrieb Alex Deucher:
On Mon, Mar 20, 2023 at 11:46 AM Christian König
wrote:
Am 17.03.23 um 18:17 schrieb Alex Deucher:
From: Christian König
Add support for
On Mon, Mar 20, 2023 at 11:58 AM Christian König
wrote:
>
> Am 17.03.23 um 18:17 schrieb Alex Deucher:
> > To provide IP specific shadow sizes. UMDs will use
> > this to query the kernel driver for the size of the
> > shadow buffers.
> >
> > v2: make callback return an int (Alex)
> >
> >
On Mon, Mar 20, 2023 at 11:55 AM Christian König
wrote:
>
> Am 20.03.23 um 16:49 schrieb Alex Deucher:
> > On Mon, Mar 20, 2023 at 11:46 AM Christian König
> > wrote:
> >> Am 17.03.23 um 18:17 schrieb Alex Deucher:
> >>> From: Christian König
> >>>
> >>> Add support for submitting the shadow
Am 17.03.23 um 18:17 schrieb Alex Deucher:
To provide IP specific shadow sizes. UMDs will use
this to query the kernel driver for the size of the
shadow buffers.
v2: make callback return an int (Alex)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 12
Am 20.03.23 um 16:49 schrieb Alex Deucher:
On Mon, Mar 20, 2023 at 11:46 AM Christian König
wrote:
Am 17.03.23 um 18:17 schrieb Alex Deucher:
From: Christian König
Add support for submitting the shadow update packet
when submitting an IB. Needed for MCBP on GFX11.
v2: update API for CSA
On Mon, Mar 20, 2023 at 11:46 AM Christian König
wrote:
>
> Am 17.03.23 um 18:17 schrieb Alex Deucher:
> > From: Christian König
> >
> > Add support for submitting the shadow update packet
> > when submitting an IB. Needed for MCBP on GFX11.
> >
> > v2: update API for CSA (Alex)
> > v3: fix
Am 17.03.23 um 18:17 schrieb Alex Deucher:
We need to reset the shadow state every time we submit an
IB and there needs to be a COND_EXEC packet after the
SET_Q_PREEMPTION_MODE packet for it to work properly, so
we should emit both of these packets regardless of whether
there is a job present or
On Mon, Mar 20, 2023 at 11:46 AM Christian König
wrote:
>
> Am 17.03.23 um 18:17 schrieb Alex Deucher:
> > From: Christian König
> >
> > Add support for submitting the shadow update packet
> > when submitting an IB. Needed for MCBP on GFX11.
> >
> > v2: update API for CSA (Alex)
> > v3: fix
Am 17.03.23 um 18:17 schrieb Alex Deucher:
From: Christian König
Add ring callback for gfx to update the CP firmware
with the new shadow information before we process the
IB.
v2: add implementation for new packet (Alex)
v3: add current FW version checks (Alex)
v4: only initialize shadow on
Am 17.03.23 um 18:17 schrieb Alex Deucher:
From: Christian König
Add support for submitting the shadow update packet
when submitting an IB. Needed for MCBP on GFX11.
v2: update API for CSA (Alex)
v3: fix ordering; SET_Q_PREEMPTION_MODE most come before COND_EXEC
Add missing check for
On Mon, Mar 20, 2023 at 11:19 AM Thomas Zimmermann wrote:
>
> Hi
>
> Am 20.03.23 um 16:11 schrieb Christian König:
> > Am 17.03.23 um 10:20 schrieb Thomas Zimmermann:
> >> Hi Christian
> >>
> >> Am 17.03.23 um 09:53 schrieb Christian König:
> >>> Am 16.03.23 um 10:37 schrieb Thomas Zimmermann:
>
Hi
Am 20.03.23 um 16:11 schrieb Christian König:
Am 17.03.23 um 10:20 schrieb Thomas Zimmermann:
Hi Christian
Am 17.03.23 um 09:53 schrieb Christian König:
Am 16.03.23 um 10:37 schrieb Thomas Zimmermann:
Convert radeon's fbdev code to drm_client. Replaces the current
ad-hoc integration. The
Am 17.03.23 um 10:20 schrieb Thomas Zimmermann:
Hi Christian
Am 17.03.23 um 09:53 schrieb Christian König:
Am 16.03.23 um 10:37 schrieb Thomas Zimmermann:
Convert radeon's fbdev code to drm_client. Replaces the current
ad-hoc integration. The conversion includes a number of cleanups.
Only
Add log to display whether RAM is direct vs DMA mapped.
Signed-off-by: Graham Sider
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
On 3/17/23 04:17, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stat.c:38: warning: Cannot
understand
*
[Public]
> -Original Message-
> From: Kuehling, Felix
> Sent: Friday, March 17, 2023 5:16 PM
> To: Sider, Graham ; Russell, Kent
> ; Mahfooz, Hamza ;
> amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: add print for iommu translation mode
>
> On 2023-03-17 16:04, Sider,
On Mon, 20 Mar 2023, Harry Wentland wrote:
>
>
> On 3/20/23 04:19, Lee Jones wrote:
> > On Fri, 17 Mar 2023, Alex Deucher wrote:
> >
> >> On Fri, Mar 17, 2023 at 4:23 AM Lee Jones wrote:
> >>>
> >>> Fixes the following W=1 kernel build warning(s):
> >>>
> >>>
[AMD Official Use Only - General]
Thanks Evan! Will do.
Thanks,
Lillian
-Original Message-
From: Quan, Evan
Sent: Monday, March 20, 2023 4:26 AM
To: Zhuo, Qingqing (Lillian) ;
amd-gfx@lists.freedesktop.org
Cc: Wang, Chao-kai (Stylon) ; Li, Sun peng (Leo)
; Wentland, Harry ; Zhuo,
On 3/20/23 04:19, Lee Jones wrote:
> On Fri, 17 Mar 2023, Alex Deucher wrote:
>
>> On Fri, Mar 17, 2023 at 4:23 AM Lee Jones wrote:
>>>
>>> Fixes the following W=1 kernel build warning(s):
>>>
>>> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stat.c:38: warning:
>>> Cannot understand
Hello
How can i verify the driver is engageing both phases in a mobile RX460 system?
I see there are PSI0_VID, PSI0_EN and PSI1 bits defined for use,
according to VRM specs they are active low and the VBIOS voltageobject
table is not setting any of these bits. Does that mean my system is
running
Final reminder that the nomination period for the X.Org Board of
Director elections finishes today, March 19th.
Please send your nominations or self-nominations as soon as possible
following the instructions below.
Thanks again for your attention.
On Mon, 2023-03-13 at 16:27 +0100, Ricardo
[AMD Official Use Only - General]
Reviewed-by: Stanley Yang
Regards,
Stanley
> -Original Message-
> From: amd-gfx On Behalf Of
> Hawking Zhang
> Sent: Monday, March 20, 2023 5:37 PM
> To: amd-gfx@lists.freedesktop.org; Zhou1, Tao
> Cc: Zhang, Hawking
> Subject: [PATCH] drm/amdgpu:
Fix a coding error which results to null interrupt
handler for umc ras.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
[AMD Official Use Only - General]
Better to update the subject with prefix as "drm/amd/pm" to align with other
power changes.
Either way the patch is
Reviewed-by: Evan Quan
BR
Evan
> -Original Message-
> From: amd-gfx On Behalf Of
> Qingqing Zhuo
> Sent: Saturday, March 18, 2023 3:56
On Fri, 17 Mar 2023, Alex Deucher wrote:
> Applied. Thanks!
>
> Alex
Awesome as ever Alex. Thank you.
> On Fri, Mar 17, 2023 at 4:24 AM Lee Jones wrote:
> >
> > Fixes the following W=1 kernel build warning(s):
> >
> > drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_detection.c:877:
> >
On Fri, 17 Mar 2023, Alex Deucher wrote:
> On Fri, Mar 17, 2023 at 4:23 AM Lee Jones wrote:
> >
> > Fixes the following W=1 kernel build warning(s):
> >
> > drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stat.c:38: warning:
> > Cannot understand
> >
[AMD Official Use Only - General]
I happened to find the sdma_access_bo allocation from GTT seems performing
before gart is ready.
That makes the "amdgpu_gart_map" is skipped since adev->gart.ptr is still NULL.
Is that done intentionally ?
Evan
> -Original Message-
> From: amd-gfx On
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