Hi Ilpo,
Apologies for the long delay.
On 10/18/2023 2:30 PM, Ilpo Järvinen wrote:
> On Wed, 18 Oct 2023, Shyam Sundar S K wrote:
>
>> PMF driver sends constant inputs to TA which its gets via the other
>> subsystems in the kernel. To debug certain TA issues knowing what inputs
>> being sent to
On 11/17/2023 10:50 AM, David Yat Sin wrote:
Fixes issue where user events of type KFD_EVENT_TYPE_HW_EXCEPTION do not
have valid data
Signed-off-by: David Yat Sin
Reviewed-by: Lijo Lazar
Thanks,
Lijo
---
drivers/gpu/drm/amd/amdkfd/kfd_events.c | 4
1 file changed, 4
No functional modification involved.
drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dpms.c:2461
link_set_dpms_on() warn: if statement not indented.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=7579
Signed-off-by: Jiapeng Chong
---
Hi Dave, Sima,
Fixes for 6.7.
The following changes since commit b85ea95d086471afb4ad062012a4d73cd328fa86:
Linux 6.7-rc1 (2023-11-12 16:19:07 -0800)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.7-2023-11-17
for you to fetch
Fixes issue where user events of type KFD_EVENT_TYPE_HW_EXCEPTION do not
have valid data
Signed-off-by: David Yat Sin
---
drivers/gpu/drm/amd/amdkfd/kfd_events.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
[AMD Official Use Only - General]
Reviewed-by: Alex Deucher
From: Liang, Prike
Sent: Thursday, November 16, 2023 10:35 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Li, Sun peng (Leo)
; Wentland, Harry ; Feng, Kenneth
; Liang, Prike
Subject:
Fix the amdgpu runpm dereference usage count.
Signed-off-by: Prike Liang
---
v2: remove goto clause and return directly(Alex)
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
On Mon, Nov 13, 2023 at 10:02 PM Liang, Prike wrote:
>
> [Public]
>
> > -Original Message-
> > From: Deucher, Alexander
> > Sent: Friday, November 10, 2023 5:46 AM
> > To: Liang, Prike ; amd-gfx@lists.freedesktop.org
> > Subject: RE: [PATCH 1/2] drm/amdgpu: correct the amdgpu runtime
> >
Add a module parameter for enabling LSDMA, defalt disable it until
proven stable. The module parameter is used to enable LSDMA ring
mode, and switch paging, system buffer management from SDMA to LSDMA.
Signed-off-by: Yifan Zhang
Reviewed-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h
LSDMA ring mode doesn't support doorbell.
Signed-off-by: Yifan Zhang
Reviewed-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index
This patch is to add ring mode support for lsdma.
Signed-off-by: Yifan Zhang
Reviewed-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 20 +
drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.c | 40 +
drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.h | 33 +-
This patch is to update lsdma headers.
Signed-off-by: Yifan Zhang
Reviewed-by: Tim Huang
---
.../drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_offset.h| 2 ++
.../drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_sh_mask.h | 7 +++
2 files changed, 9 insertions(+)
diff --git
This patch is to add lsdma interrupt src id.
Signed-off-by: Yifan Zhang
Reviewed-by: Tim Huang
---
drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_11_0_0.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_11_0_0.h
This patch is to add lsdma hw ip definition.
Signed-off-by: Yifan Zhang
Reviewed-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 15 +++
This series implements LSDMA ring mode, creates LSDMA ring and implement
amdgpu ring related functions. Introduce a new module parameter amdgpu_lsdma
to enable LSDMA, switch buffer and paging funcs from SDMA to LSDMA. It changes
amdgpu driver buffer operations to LSDMA, changes default page table
[AMD Official Use Only - General]
Reviewed-by: Kenneth Feng
-Original Message-
From: amd-gfx On Behalf Of Liang, Prike
Sent: Friday, November 17, 2023 9:37 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Li, Sun peng (Leo)
; Wentland, Harry
Subject: RE: [PATCH]
[AMD Official Use Only - General]
Ping for the review.
Regards,
--Prike
> -Original Message-
> From: Liang, Prike
> Sent: Tuesday, November 14, 2023 10:41 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liang, Prike
>
> Subject: [PATCH] drm/amdgpu: correct the amdgpu
On 2023-11-16 06:11, Christian König wrote:
Am 16.11.23 um 03:47 schrieb Ramesh Errabolu:
Tag VRAM BOs that do not have a VA with a unique Id, a 128-bit
UUID. This unique Id is used to distinguish BOs that might
otherwise be of same size. Checkpoint and restore assumes
that these BOs are
On 11/16/2023 11:57 AM, Melissa Wen wrote:
DRM_OBJECT_MAX_PROPERTY limits the number of properties to be attached
and we are increasing that value all time we add a new property (generic
or driver-specific).
In this series, we are adding 13 new KMS driver-specific properties for
AMD color
On 2023-11-07 11:58, Felix Kuehling wrote:
Create GEM handles for exporting DMABufs using GEM-Prime APIs. The GEM
handles are created in a drm_client_dev context to avoid exposing them
in user mode contexts through a DMABuf import.
This patch (and the next one) won't apply upstream because
On 11/9/2023 14:51, Alex Deucher wrote:
Should be && rather than ||.
Fixes: b2e1cbe6281f ("drm/amdgpu/gmc11: disable AGP on GC 11.5")
Signed-off-by: Alex Deucher
---
For the series:
Reviewed-by: Mario Limonciello
Tested-by: Mario Limonciello # PHX & Navi33
On Thu, Nov 16, 2023 at 02:34:50PM -0500, Alex Deucher wrote:
> I think this series should fix it:
> https://patchwork.freedesktop.org/series/126220/
This patch does not fix the issue for me but the patch [1] that you
mentioned in another thread does fix it (errors are no longer printed).
[1] -
On 11/16/23 20:34, Alex Deucher wrote:
> On Thu, Nov 16, 2023 at 11:42 AM Vlastimil Babka wrote:
>>
>> On 11/14/23 05:51, Abhinav Praveen wrote:
>> > Hi,
>> >
>> > When I start X/i3 on a 7900xtx with Linux 6.7-rc1 and Mesa 23.3_rc3, my
>> > log is filled with errors like:
>>
>> I have same kind
On 11/16/2023 13:22, Alex Deucher wrote:
On Thu, Nov 16, 2023 at 2:02 PM Mario Limonciello
wrote:
On 11/16/2023 09:00, Alex Deucher wrote:
This will break other things. The proper fix is either:
https://patchwork.freedesktop.org/patch/567101/
Drop this patch.
Alex
Yes; confirmed with
On Fri, Nov 10, 2023 at 12:23 PM André Almeida wrote:
>
> Document what each amdgpu driver reset method does.
>
> Signed-off-by: André Almeida
Applied with Randy's suggestion. Thanks!
Alex
> ---
> v2: Add more details and small correction (Alex)
>
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 25
Map the plane CTM driver-specific property to DC plane, instead of DC
stream. The remaining steps to program DPP block are already implemented
on DC shared-code.
v3:
- fix comment about plane and CRTC CTMs priorities (Harry)
Reviewed-by: Harry Wentland
Signed-off-by: Melissa Wen
---
From: Joshua Ashton
Need to funnel the color caps through to these functions so it can check
that the hardware is capable.
v2:
- remove redundant color caps assignment on plane degamma map (Harry)
- pass color caps to degamma params
v3:
- remove unused color_caps parameter from
From: Joshua Ashton
When commiting planes, we copy color mgmt resources to the stream state.
Do the same for shaper and 3D LUTs.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
From: Joshua Ashton
Detach value translation from CTM to reuse it for programming HDR
multiplier property.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 8 +---
Enable usage of predefined transfer func in addition to shaper 1D LUT.
That means we can save some complexity by just setting a predefined
curve, instead of programming a custom curve when preparing color space
for applying 3D LUT.
Reviewed-by: Harry Wentland
Signed-off-by: Melissa Wen
---
From: Joshua Ashton
Create drm_color_ctm_3x4 to support 3x4-dimension plane CTM matrix and
convert DRM CTM to DC CSC float matrix.
v3:
- rename ctm2 to ctm_3x4 (Harry)
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 28
From: Joshua Ashton
Map plane blend properties to DPP blend gamma. Plane blend is a
post-3D LUT curve that linearizes color space for blending. It may be
defined by a user-blob LUT and/or predefined transfer function. As
hardcoded curve (ROM) is not supported on blend gamma, we use AMD color
Plane CTM for pre-blending color space conversion. Only enable
driver-specific plane CTM property on drivers that support both pre- and
post-blending gamut remap matrix, i.e., DCN3+ family. Otherwise it
conflits with DRM CRTC CTM property.
Reviewed-by: Harry Wentland
Signed-off-by: Melissa Wen
Wire up DC 3D LUT to DM plane color management (pre-blending). On AMD
display HW, 3D LUT comes after a shaper curve and we always have to
program a shaper curve to delinearize or normalize the color space
before applying a 3D LUT (since we have a reduced number of LUT
entries).
In this version,
From: Joshua Ashton
Set DC plane with user degamma LUT or predefined TF from driver-specific
plane color properties. If plane and CRTC degamma are set in the same
time, plane degamma has priority. That means, we only set CRTC degamma
if we don't have plane degamma LUT or TF to configure. We
Map DC shaper LUT to DM plane color management. Shaper LUT can be used
to delinearize and/or normalize the color space for computational
efficiency and achiving specific visual styles. If a plane degamma is
apply to linearize the color space, a custom shaper 1D LUT can be used
just before applying
From: Joshua Ashton
Unlike degamma, blend gamma doesn't support hardcoded curve
(predefined/ROM), but we can use AMD color module to fill blend gamma
parameters when we have non-linear plane gamma TF without plane gamma
LUT. The regular degamma path doesn't hit this.
Reviewed-by: Harry Wentland
From: Joshua Ashton
With `dc_fixpt_from_s3132()` translation, we can just use it to set
hdr_mult.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
The next patch adds pre-blending degamma to AMD color mgmt pipeline, but
pre-blending degamma caps (DPP) is currently in use to provide DRM CRTC
atomic degamma or implict degamma on legacy gamma. Detach degamma usage
regarging CRTC color properties to manage plane and CRTC color
correction
DC only has pre-blending degamma caps (plane/DPP) that is currently in
use for CRTC/post-blending degamma, so that we don't have HW caps to
perform plane and CRTC degamma at the same time. Reject atomic updates
when serspace sets both plane and CRTC degamma properties.
Reviewed-by: Harry Wentland
Describe some expected behavior of the AMD DM color mgmt programming.
Reviewed-by: Harry Wentland
Signed-off-by: Melissa Wen
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git
From: Joshua Ashton
Otherwise this is just initialized to 0. This needs to actually have a
value so that compute_curve can work for PQ EOTF.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
From: Joshua Ashton
We should reset a plane state if at least one of the color management
properties differs from old and new state.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
From: Joshua Ashton
Add predefined transfer function programming. There is no post-blending
out gamma ROM for hardcoded curves, but we can use AMD color modules to
program LUT parameters from pre-defined coefficients and an empty
regamma LUT (or bump up LUT parameters with pre-defined TF
Brief documentation about pre-defined transfer function usage on AMD
display driver and standardized EOTFs and inverse EOTFs.
v3:
- Document BT709 OETF (Pekka)
- Fix description of sRGB and pure power funcs (Pekka)
v4:
- Add description of linear and non-linear forms (Harry)
Reviewed-by: Harry
Add 3D LUT property for plane color transformations using a 3D lookup
table. 3D LUT allows for highly accurate and complex color
transformations and is suitable to adjust the balance between color
channels. It's also more complex to manage and require more
computational resources.
Since a 3D LUT
Add AMD pre-defined transfer function property to default DRM CRTC gamma
to convert to wire encoding with or without a user gamma LUT. There is
no post-blending regamma ROM for pre-defined TF. When setting Gamma TF
(!= Identity) and LUT at the same time, the color module will combine
the
We will wire up MPC 3D LUT to DM CRTC color pipeline in the next patch,
but so far, only for atomic interface. By checking
set_output_transfer_func in DC drivers with MPC 3D LUT support, we can
verify that regamma is only programmed when 3D LUT programming fails. As
a groundwork to introduce 3D
From: Joshua Ashton
Blend 1D LUT or a pre-defined transfer function (TF) can be set to
linearize content before blending, so that it's positioned just before
blending planes in the AMD color mgmt pipeline, and after 3D LUT
(non-linear space). Shaper and Blend LUTs are 1D LUTs that sandwich 3D
From: Joshua Ashton
Multiplier to 'gain' the plane. When PQ is decoded using the fixed func
transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at
least) When sRGB is decoded, 1.0 -> 1.0. Therefore, 1.0 multiplier = 80
nits for SDR content. So if you want, 203 nits for SDR
We will add color mgmt properties to DRM planes in the next patches and
we want to track when one of this properties change to define atomic
commit behaviors. Using a similar approach from CRTC color props, we set
a color_mgmt_changed boolean whenever a plane color prop changes.
Reviewed-by:
Instead of relying on color block names to get the transfer function
intention regarding encoding pixel's luminance, define supported
Electro-Optical Transfer Functions (EOTFs) and inverse EOTFs, that
includes pure gamma or standardized transfer functions.
v3:
- squash linear and unity TFs to
On AMD HW, 3D LUT always assumes a preceding shaper 1D LUT used for
delinearizing and/or normalizing the color space before applying a 3D
LUT. Add pre-defined transfer function to enable delinearizing content
with or without shaper LUT, where AMD color module calculates the
resulted shaper curve.
From: Joshua Ashton
Allow userspace to tell the kernel driver the input space and,
therefore, uses correct predefined transfer function (TF) to go from
encoded values to linear values.
v2:
- rename TF enum prefix from DRM_ to AMDGPU_ (Harry)
- remove HLG TF
Reviewed-by: Harry Wentland
Hook up driver-specific atomic operations for managing AMD color
properties. Create AMD driver-specific color management properties
and attach them according to HW capabilities defined by `struct
dc_color_caps`.
First add plane degamma LUT properties that means user-blob and its
size. We will add
Place it in drm_property where drm_property_replace_blob and
drm_property_lookup_blob live. Then we can use the DRM helper for
driver-specific KMS properties too.
Reviewed-by: Harry Wentland
Reviewed-by: Liviu Dudau
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/arm/malidp_crtc.c | 2 +-
Hello,
This series extends the current KMS color management API with AMD
driver-specific properties to enhance the color management support on
AMD Steam Deck. The key additions to the color pipeline include:
- plane degamma LUT and pre-defined TF;
- plane HDR multiplier;
- plane CTM 3x4;
- plane
DRM_OBJECT_MAX_PROPERTY limits the number of properties to be attached
and we are increasing that value all time we add a new property (generic
or driver-specific).
In this series, we are adding 13 new KMS driver-specific properties for
AMD color manage:
- CRTC Gamma enumerated Transfer Function
On Thu, Nov 16, 2023 at 11:42 AM Vlastimil Babka wrote:
>
> On 11/14/23 05:51, Abhinav Praveen wrote:
> > Hi,
> >
> > When I start X/i3 on a 7900xtx with Linux 6.7-rc1 and Mesa 23.3_rc3, my
> > log is filled with errors like:
>
> I have same kind of errors filling my dmesg with 6.7-rc1 with
On Thu, Nov 16, 2023 at 2:02 PM Mario Limonciello
wrote:
>
> On 11/16/2023 09:00, Alex Deucher wrote:
> > This will break other things. The proper fix is either:
> > https://patchwork.freedesktop.org/patch/567101/
Drop this patch.
Alex
> > and/or:
> >
On Mon, Nov 13, 2023 at 12:50 PM Harry Wentland wrote:
>
> Please just use "drm/amd/display:" as tag in the commit subject.
>
> With that fixed, this is
> Acked-by: Harry Wentland
>
Acked-by: Alex Deucher
Feel free to take this via the i2c tree if you prefer.
Alex
> Harry
>
> On 2023-11-13
On Mon, Nov 13, 2023 at 3:55 PM Wolfram Sang wrote:
>
>
> > We're not in a hurry. It's just my experience with patch series' affecting
> > multiple subsystems that typically the decision was to apply the full
> > series via one tree. Also to avoid inquires from maintainers like:
> > Shall I take
On Mon, Nov 13, 2023 at 6:24 AM Heiner Kallweit wrote:
>
> After removal of the legacy EEPROM driver and I2C_CLASS_DDC support in
> olpc_dcon there's no i2c client driver left supporting I2C_CLASS_DDC.
> Class-based device auto-detection is a legacy mechanism and shouldn't
> be used in new code.
On Mon, Nov 13, 2023 at 6:37 AM Heiner Kallweit wrote:
>
> I2C_CLASS_SPD was used to expose the EEPROM content to user space,
> via the legacy eeprom driver. Now that this driver has been removed,
> we can remove I2C_CLASS_SPD support. at24 driver with explicit
> instantiation should be used
On 11/16/2023 09:00, Alex Deucher wrote:
This will break other things. The proper fix is either:
https://patchwork.freedesktop.org/patch/567101/
and/or:
https://patchwork.freedesktop.org/series/126220/
I applied the both of these series on 6.7-rc1
e5e258131973 (HEAD) drm/amdgpu/gmc9:
On Wed, Nov 15, 2023 at 4:15 AM Jan Hendrik Farr wrote:
>
> Hi all,
>
> just took out 6.7.0-rc1 for a spin (including latest upstream linux-firmware).
> GPU is an RX 7800 XT. I'm getting a constant flood of errors in dmesg.
>
> Otherwise I don't observe any out of place behavior on linux.
On Wed, Nov 15, 2023 at 1:14 PM Mikhail Gavrilov
wrote:
>
> On Wed, Nov 8, 2023 at 4:24 AM Mikhail Gavrilov
> wrote:
> >
> > Tested-by: Mikhail Gavrilov
> > Thanks, after applying the patch GPU loading meets expectations.
> > Games are working so overall all looking good for now.
> >
>
>
On 2023-11-15 11:15, Srinivasan Shanmugam wrote:
Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1373: warning: Function parameter or
member 'xcc_mask' not described in 'amdgpu_vm_flush_compute_tlb'
Cc: Felix Kuehling
Cc: Christian König
Cc: Alex Deucher
Cc: "Pan, Xinhui"
Ping on this series.
Alex
On Fri, Nov 10, 2023 at 1:37 PM Alex Deucher wrote:
>
> We've had misc reports of random IOMMU page faults when
> this is used. It's just a rarely used optimization anyway, so
> let's just disable it. It can still be toggled via the
> module parameter for testing.
>
[AMD Official Use Only - General]
Yes, it fixes regressions in KFDTest introduced by this commit ("b93ed51c32ca
drm/amdgpu: fix AGP init order"),
e.g. KFDMemoryTest.MemoryRegister failure:
fault addr 0x8084575a6000 is calculated by (gart_start + AGP aperture mc
addr) wrongly.
[
This will break other things. The proper fix is either:
https://patchwork.freedesktop.org/patch/567101/
and/or:
https://patchwork.freedesktop.org/series/126220/
Alex
On Thu, Nov 16, 2023 at 7:27 AM wrote:
>
> From: Ivan Lipski
>
> This commit caused a page fault issue on RX7000 series GPU.
>
Ping ...
On 2023-11-03 09:11, James Zhu wrote:
PC sampling is a form of software profiling, where the threads of an application
are periodically interrupted and the program counter that the thread is
currently
attempting to execute is saved out for profiling.
David Yat Sin (5):
On Tue, 14 Nov 2023, Mario Limonciello wrote:
> pci_is_thunderbolt_attached() looks at the hierarchy of the PCIe device
> to determine if any bridge along the way has the is_thunderbolt bit set.
> This bit will only be set when one of the devices in the hierarchy is an
> Intel Thunderbolt device.
On Tue, 14 Nov 2023, Mario Limonciello wrote:
> All callers have switched to dev_is_removable() for detecting
> hotpluggable PCIe devices.
>
> Signed-off-by: Mario Limonciello
> ---
> v2->v3:
> * No changes
> ---
> include/linux/pci.h | 22 --
> 1 file changed, 22
On Tue, 14 Nov 2023, Mario Limonciello wrote:
> The logic to calculate bandwidth limits may be used at multiple call sites
> so split it up into its own static function instead.
>
> No intended functional changes.
>
> Suggested-by: Ilpo Järvinen
> Signed-off-by: Mario Limonciello
> ---
>
On Tue, 14 Nov 2023, Mario Limonciello wrote:
> commit 493fb50e958c ("PCI: pciehp: Assume NoCompl+ for Thunderbolt
> ports") added a check into pciehp code to explicitly set NoCompl+
> for all Intel Thunderbolt controllers, including those that don't
> need it.
>
> This overloaded the purpose of
On Thu, Nov 16, 2023 at 4:37 AM Zhang, Yifan wrote:
>
> [AMD Official Use Only - General]
>
> Ping... this patch seems still not merged.
>
Can you confirm it fixes the AGP issues you saw?
Alex
> Best Regards,
> Yifan
>
> -Original Message-
> From: Alex Deucher
> Sent: Monday, November
On UHBR links the PBN divider is a fractional number, accordingly store
it in fixed point format. For now drm_dp_get_vc_payload_bw() always
returns a whole number and all callers will use only the integer part of
it which should preserve the current behavior. The next patch will fix
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Lazar, Lijo
Sent: Friday, November 10, 2023 15:56
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Wang, Yang(Kevin)
Subject: [PATCH v3] drm/amdgpu: Move
On 11/10/2023 1:25 PM, Lijo Lazar wrote:
Refactor code such that ras block decides the default mca debug mode,
and not swsmu block.
By default mca debug mode is set to false.
Signed-off-by: Lijo Lazar
---
v3: Default mca debug mode is set to false
v2: Set mca debug mode early before ras
Am 16.11.23 um 03:47 schrieb Ramesh Errabolu:
Tag VRAM BOs that do not have a VA with a unique Id, a 128-bit
UUID. This unique Id is used to distinguish BOs that might
otherwise be of same size. Checkpoint and restore assumes
that these BOs are not imported into a DRM device that is
Am 15.11.23 um 17:15 schrieb Srinivasan Shanmugam:
Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1373: warning: Function parameter or
member 'xcc_mask' not described in 'amdgpu_vm_flush_compute_tlb'
Cc: Felix Kuehling
Cc: Christian König
Cc: Alex Deucher
Cc: "Pan, Xinhui"
Am 15.11.23 um 21:08 schrieb Mikhail Gavrilov:
On Wed, Nov 15, 2023 at 11:39 PM Lee, Alvin wrote:
This change has a DMCUB dependency - are you able to update your DMCUB version
as well?
I can confirm this issue was gone after updating firmware.
❯ dmesg | grep DMUB
[ 11.496679] [drm]
[AMD Official Use Only - General]
Ping... this patch seems still not merged.
Best Regards,
Yifan
-Original Message-
From: Alex Deucher
Sent: Monday, November 13, 2023 2:13 AM
To: Koenig, Christian
Cc: Deucher, Alexander ;
amd-gfx@lists.freedesktop.org; Zhang, Yifan ; Zhang,
On 11/14/23 05:51, Abhinav Praveen wrote:
> Hi,
>
> When I start X/i3 on a 7900xtx with Linux 6.7-rc1 and Mesa 23.3_rc3, my
> log is filled with errors like:
I have same kind of errors filling my dmesg with 6.7-rc1 with Radeon RX 7600
using KDE on Wayland. I don't notice any other issues than
Hi Mario,
On Tue, Nov 14, 2023 at 02:07:53PM -0600, Mario Limonciello wrote:
> USB4 routers support a feature called "PCIe tunneling". This
> allows PCIe traffic to be transmitted over USB4 fabric.
>
> PCIe root ports that are used in this fashion can be discovered
> by device specific data that
Hi Mario,
On Wed, Nov 15, 2023 at 11:08:43AM -0600, Mario Limonciello wrote:
> On 11/15/2023 04:40, Mika Westerberg wrote:
> > Hi Mario,
> >
> > On Tue, Nov 14, 2023 at 02:07:53PM -0600, Mario Limonciello wrote:
> > > USB4 routers support a feature called "PCIe tunneling". This
> > > allows PCIe
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