,
+ int pipe_cnt);
+
void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
void dcn31_calculate_wm_and_dlg_fp(
Reviewed-by: Rodrigo Siqueira
This commit moves phanton FPU stream to dcn32_fpu file.
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 89 +--
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 84
From: Wayne Lin
[Why & How]
Correct few problems below to have debugfs trigger_hotplug entry
supports mst case
* Adjust the place for acquiring the hpd_lock. We'll also access
dc_link when simulate unplug
* When detect the connector is a mst root, call
reset_cur_dp_mst_topology() to
by moving the calculation after the DSC check.
Signed-off-by: Rodrigo Siqueira
---
.../dc/dml/dcn32/display_mode_vba_util_32.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
b
From: Chris Park
[Why]
Cursor size can update without MALL cache update.
Update the register on cursor attribute as well.
[How]
Update cursor MALL cache on cursor attribute update.
Reviewed-by: Alvin Lee
Acked-by: Alan Liu
Signed-off-by: Chris Park
---
From: Wenjing Liu
[why]
Number of DSC slices is an input to DML with high dependency
on display specific capability. This isn't something DML can decide
on its own. DML has to use the original number of DSC slices input
to DML during validation without modification. Otherwise the
computed DSC
From: Taimur Hassan
[Why]
For certain MPO configurations, DML will split a pipe after DET buffer has
already been allocated by driver, resulting in allocation of more DET
segments than the configurable return buffer has, causing underflow.
[How]
Determine during DET override calculation whether
From: Vladimir Stempen
[Why]
VM enabled in IP configuration causes UCLK not
reaching DPM0. The expectation for VM enable should
be that KMD will indicate to DAL when VM is enabled,
then DAL will set the bit accordingly
[How]
Set gpuvm_enable to zero in DCN3_20 and DCN3_21 resource.
From: Alvin Lee
Update DML to configure drr_display in vba struct.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Alan Liu
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 1 +
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 1 +
2 files
Move get_optimal_ntuple to the FPU code and call it inside
insert_entry_into_table_sorted.
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 28 ---
.../drm/amd/display/dc/dml/dcn32
The function dcn32_helper_populate_phantom_dlg_params uses FPU
operations. For this reason, this commit moves this function to the
dcn32_fpu file, and we ensure that we only invoke it under the
kernel_fpu protection.
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Rodrigo
From: Alvin Lee
[Description]
In general cases we want to keep the dram clock change requirement (we
prefer configs that support MCLK switch). Only override to false for
SubVP.
Acked-by: Alan Liu
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 10
From: Wayne Lin
[Why & How]
In order to leverage igt tool to maintain mst feature, expose new
debugfs entry "mst_progress_status".
In our dm flow, record down the result of each phase of mst and user
can examine the mst result by checking whether each phase get completed
successfully.
moving code from one part to another.
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 25
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 81 +
drivers/gpu/drm/amd/display/dc/dml/Makefile
From: Aric Cyr
This version brings along following fixes:
- Isolate FPU operation for DCN32/321 under the DML folder
- Create a specific file for CRTC and plane based on amdgpu_dm
- Fix DSC issues
- Update DML logic
Acked-by: Alan Liu
Signed-off-by: Aric Cyr
---
DML logic for unbounded req handling
Rodrigo Siqueira (16):
drm/amd/display: Create a file dedicated to planes
drm/amd/display: Create a file dedicated for CRTC
drm/amd/display: Fix hard hang if DSC is disabled
drm/amd/display: Drop FPU flags from dcn32_clk_mgr
drm/amd/display: Move
From: Wayne Lin
[Why & How]
Add "is_mst_connector" debugfs entry to help distinguish whether
a connector is in a mst topology or not.
Access it with the following command:
cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector
Result:
- "root" stands for the root connector of the topology
-
Move dcn32_calculate_wm_and_dlg from dcn32 resources to the FPU code.
Additionally, this commit adds an interface to it.
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 196 +-
.../drm
This commit fully move the missing FPU operations from dcn321 resource
to dcn321 fpu. It also remove those FPU flags from the Makefile.
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dcn321/Makefile| 25 -
.../amd
functions.
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 597 +-
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 2 +
.../display/dc/dcn32/dcn32_resource_helpers.c | 11 +
.../drm/amd
The final part of the DCN32 code that uses FPU is the bounding box code,
and this commit move it to dcn32_fpu.
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 460 +
.../drm/amd/display
The file dcn321_resource has a lot of FPU operations that should be
inside the dml folder. This commit introduces the dcn321_fpu file and
moves some of the FPU operation functions to this new file.
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
The function dcn32_predict_pipe_split uses FPU operations. This commit
moves this function to the dcn32_fpu file, and we ensure that we only
invoke it under the kernel_fpu protection.
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd
. This change does not change anything inside the
functions; the only exception is converting some static functions to a
global function.
Reviewed-by: Harry Wentland
Acked-by: Alan Liu
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/amdgpu_dm/Makefile| 1 +
.../gpu/drm/amd
according to
unbounded req enablement output from DML, as opposed to DML input.
Second, port in DML update which disables unbounded req in some
scenarios to fix an issue with poor stutter performance
Signed-off-by: Jun Lei
Reviewed-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn32
From: Jun Lei
Remove an unused variable "remove_disconnect_edp" which was a workaround
bit.
Acked-by: Alan Liu
Signed-off-by: Jun Lei
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
From: Taimur Hassan
[Why & How]
There are cases where the pipes populated are not all at the top
of the pipes list under context. Loop through all pipes for DET
allocation instead of just the number of populated ones, even if
some unpopulated pipes are iterated through unnecessarily.
This is the final commit from the FPU isolation for DCN32 and for this
reason we can finally remove flags related to FPU.
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn32/Makefile | 28 ---
1 file
From: Wayne Lin
[Why & How]
Need to leverage this function out of dc_link.c. Change it to public.
Reviewed-by: Hersen Wu
Acked-by: Alan Liu
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
drivers/gpu/drm/amd/display/dc/dc_link.h | 3 +++
2 files
Move dlg params calculation to the FPU folder and make it static.
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 485 +
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 6 -
.../drm
. This change does not change anything inside the
functions; the only exception is converting some static functions to a
global function.
Reviewed-by: Harry Wentland
Acked-by: Alan Liu
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/amdgpu_dm/Makefile|7 +-
.../gpu/drm/amd
From: Wayne Lin
[Why]
When CONFIG_DRM_AMD_SECURE_DISPLAY is enabled, it will try
to register vertical interrupt 0 for specific task.
Currently, only dcn10 have defined relevant info for vertical interrupt
0. If we enable CONFIG_DRM_AMD_SECURE_DISPLAY for other dcn ASIC, will
get
The insert_entry_into_table_sorted function uses FPU operation and calls
other static functions support. This commit moves the insert entry
function with all the required struct and static functions to the FPU
file.
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Rodrigo
On 12/07/2022 12:02, Limonciello, Mario wrote:
On 7/12/2022 10:59, Rodrigo Siqueira wrote:
We had an MST fix for some DELL devices that got merged, but we missed
other products. This commit adds the other missing Precision devices.
Cc: Mario Limonciello
Cc: Jerry Zuo
Cc: Qian Fu
Cc: Alex
Error")
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e203d75834de..96a0be850
From: Fangzhi Zuo
[why]
The first MST sideband message returns AUX_RET_ERROR_HPD_DISCON on
a certain Intel platform. Aux transaction is considered a failure if HPD
unexpectedly pulled low. The actual aux transaction success in such
case, hence do not return an error. Several Dell Intel-based
From: Fangzhi Zuo
[why]
The first MST sideband message returns AUX_RET_ERROR_HPD_DISCON on
a certain Intel platform. Aux transaction is considered a failure if HPD
unexpectedly pulled low. The actual aux transaction success in such
case, hence do not return an error. Several Dell Intel-based
MaximumMPCCombine = 0;
+ } else {
+ MaximumMPCCombine = 1;
}
}
}
LGTM,
Reviewed-by: Rodrigo Siqueira
"DMUB interface failed to initialize: status=%d\n",
r);
Series LGTM,
Reviewed-by: Rodrigo Siqueira
Kernel test robot reported this GCC error:
warning: no previous prototype for 'dc_reset_state' [-Wmissing-prototypes]
2720 | void dc_reset_state(struct dc *dc, struct dc_state *context)
This commit adds the missing prototype.
Reported-by: kernel test robot
Signed-off-by: Rodrigo Siqueira
On 2022-06-18 19:27, Guenter Roeck wrote:
ppc:allmodconfig builds fail with the following error.
powerpc64-linux-ld:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o
uses hard float,
ms);
+ DC_FP_END();
}
static bool dcn32_are_clock_states_equal(struct dc_clocks *a,
Hi Alex,
Reviewed-by: Rodrigo Siqueira
Btw, I already start to work on the FPU isolation for DCN32/321.
Thanks
Siqueira
-by: Rodrigo Siqueira
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index a9c59669dd1d..02bbc90a2c80 100644
--- a/drivers/gpu/drm/amd/display/dc
From: Chris Park
[Why]
Integrate OVT timing from DM to DC logic to update info frame
and mode management to report the resolution to the OS.
[How]
Reflect RID and Frame Rate to AVI InfoFrame Version 5.
Define new Timing Standard for OVT timing.
Reviewed-by: Charlene Liu
Acked-by: Alan Liu
From: Alvin Lee
[Description]
Program audio DTO before wall dto for audio
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git
From: Michael Strauss
[WHY]
lt_settings' pointers remain uninitialized but nonzero if display fails
to light up with no DPCD/EDID info populated, leading to a hang on access
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alan Liu
Signed-off-by: Michael Strauss
---
From: Hamza Mahfooz
Generic PCON SST support already exists and works for newer ASICs. So,
enable it by default.
Acked-by: Rodrigo Siqueira
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
From: Hamza Mahfooz
hdmi_frl_pcon_support has been the source of confusion. So, rename it to
dp_hdmi21_pcon_support.
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c| 2 +-
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
From: Jimmy Kizito
[Why]
Some TBT3 docks have DPOAs which report USB4 capability and are expected
to support USB4 DPOA features such as FEC/DSC.
[How]
By default, do not override FEC/DSC capabilities reported by TBT3 docks.
Reviewed-by: Meenakshikumar Somasundaram
Acked-by: Rodrigo Siqueira
From: Alvin Lee
[Description]
In general cases we want to keep the dram clock change requirement (we
prefer configs that support MCLK switch). Only override to false for
SubVP.
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml
From: Nicholas Kazlauskas
[Why & How]
Check lenc is not NULL since dynamic link encoder assignment could
end up assigning a NULL link encoder.
Reviewed-by: Michael Strauss
Acked-by: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/d
From: Meenakshikumar Somasundaram
[Why]
DC debug option to configure dpia hpd processing delay is not required.
[How]
Remove dc debug option for dpia hpd delay and also added log for
querying dpia hpd state.
Reviewed-by: Mustapha Ghaddar
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
From: Alan Liu
- Setup the shift and mask of HDMI_ACP_SEND register
- Program the register in hdmi stream encoder
- Also update ACP register in azalia configuration
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Alan Liu
---
drivers/gpu/drm/amd/display/dc/dce
From: Eric Bernstein
[Why]
For some customer blending transition cases, the
available pipe for second stream is a pipe index that is
greater than the number of timing generators, which
can cause a problem in acquire_first_free_pipe since it
assumes same index for pipe and timing generator
[How]
Jayamohanan Pillai
Acked-by: Rodrigo Siqueira
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm
From: Duncan Ma
[Why]
Some panels may require more MST delay on discovery
[How]
Add panel patch and debug mst delay flag
Reviewed-by: Charlene Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Duncan Ma
---
drivers/gpu/drm/amd/display/dc/dc.h | 3 ++-
drivers/gpu/drm/amd/display/dc
for ODM.
[How]
Set ODM flag in stream and commit stream when change
in ODM has been detected due to policy change.
Reviewed-by: Samson Tam
Acked-by: Rodrigo Siqueira
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +++
drivers/gpu/drm/amd/display/dc/dc_stream.h
From: Jimmy Kizito
[Why]
Uninitialized variable causes diag compilation build failure.
[How]
- Ensure that variable in question is always initialized before being
used.
- The variable in question is the USB4 DP training pattern. In case an
unsupported training pattern has been requested, update
From: Evgenii Krasnikov
[HOW/WHY]
Add an option to skip edp_wait_for_hpd_ready when necessary
Reviewed-by: Jayendran Ramani
Acked-by: Rodrigo Siqueira
Signed-off-by: Evgenii Krasnikov
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 5 +++--
drivers/gpu/drm/amd/display/dc/inc
ut bw check")
Reviewed-by: Hersen Wu
Acked-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/a
From: Dmytro Laktyushkin
This w/a has a bad interaction with seamless boot toggling an
active stream. Most panels recover, however some fail leading
to display corruption.
Reviewed-by: Charlene Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Dmytro Laktyushkin
---
.../gpu/drm/amd/display/dc
engine acquire.
Reviewed-by: Michael Strauss
Acked-by: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
b/drivers/gpu/drm/amd/display/dc/dce
From: Harry Wentland
Move all linux includes into OS types.
Acked-by: Alan Liu
Signed-off-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/basics/vector.c | 2 --
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2 --
drivers/gpu/drm/amd/display/dc/core/dc.c
From: Jun Lei
[why]
Some parts are consuming dangerously close to maximum number of states
supported when updating the BB (i.e. 8).
[how]
Change maximum stages from 9 to 20.
Acked-by: Rodrigo Siqueira
Signed-off-by: Jun Lei
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 508
From: Dmytro Laktyushkin
Fix for a bug where we would try to timing sync 2 odm halves.
Acked-by: Rodrigo Siqueira
Signed-off-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display
From: Martin Leung
[Why]:
On power down, virtual dal may try to delete link_encoders by
referencing uninitialized res_pool.
[How]:
Added guard against empty res_pool.
Acked-by: Rodrigo Siqueira
Signed-off-by: Martin Leung
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 --
1 file
the ASSERTION. We already guard against NULL link_enc.
Reviewed-by: Michael Strauss
Acked-by: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc
-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 277 +
drivers/gpu/drm/amd/display/dc/dc_stream.h | 18 ++
2 files changed, 295 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index
the mode
of operation of the link encoder assignment module.
- Add additional checks for encoder assignment defects.
- Explicitly reset the mode of operation if application of state
to hardware ends prematurely.
Acked-by: Rodrigo Siqueira
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc
We want to enable Firmware Assisted Memory (FAMS) Switching, but first,
we need to add the required code infrastructure in DC before allowing it
in amdgpu_dm.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +
drivers/gpu/drm/amd/display/dc/dc.h
From: Eric Bernstein
After some experimental tests, we noticed that we need to set
gpuvm_max_page_table_levels to '4' to meet the hardware requirements.
Signed-off-by: Eric Bernstein
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index db02f071c949..05c2e178ca99 100644
--- a/drivers
From: Chris Park
[Why]
For Pixel Rate control, when on HDMI, HDMI DTO should be selected
instead of DP DTO.
[How]
Pass HDMI parameter for HDMI stream, and select correct DTO.
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 ++
From: Alvin Lee
[Why]
Newer DCN should use optc3
[How]
Declare optc3 vmin/vmax function in header.
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 5 +
From: Alvin Lee
For MPO we want to allocate less than maximum DET for MPO pipes because
we need enogh buffer to move DET back to toher pipes when removing an
MPO plane. Also update regular DET allocation to use DET override (DCN32
has an internal policy which driver does not want to use)
From: Nicholas Kazlauskas
[Why]
Found when running igt@kms_atomic.
Userspace attempts to do a TEST_COMMIT when 0 streams which calls
dc_remove_stream_from_ctx. This in turn calls link_enc_unassign which
ends up modifying stream->link = NULL directly, causing the global
link_enc to be removed
From: Martin Leung
[WHY]:
Lut pipeline will be hooked up differently in some asics
need to add new interfaces and missing registers.
[HOW]:
Add missing registers and hook up programming from DPP for pre-blend
lut.
Acked-by: Rodrigo Siqueira
Signed-off-by: Martin Leung
---
.../gpu/drm/amd
From: Eric Bernstein
Add function to set pixels per cycle in DIG stream encoder
Acked-by: Rodrigo Siqueira
Signed-off-by: Eric Bernstein
---
.../amd/display/dc/dcn10/dcn10_stream_encoder.h | 1 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 5 ++---
.../display/dc/dcn32
Currently, we check if pixel_encoding is equal to
PIXEL_ENCODING_YCBCR422 to get the k1/k2 div parameters. This commit
changes this logic slightly by checking if two pixels per container are
used.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 8
PIXEL_RATE_DIVK2
- DP_PIXEL_PER_CYCLE_PROCESSING_MODE
- DIG_FIFO_OUTPUT_PIXEL_MODE
- DP_VID_N_MUL
Acked-by: Rodrigo Siqueira
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +++
.../dc/dcn32/dcn32_dio_stream_encoder.c
We are missing some ACP registers/mask value for some specific ASICs.
This commit includes it to those ASICs that support it.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h | 2 ++
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h | 2
nst ddc_pin being NULL for AUX
drm/amd/display: Remove incorrect ASSERT check for link_enc
drm/amd/display: Guard against NULL link encoder in log hw state
Rodrigo Siqueira (6):
drm/amd/display: Add missing registers for ACP
drm/amd/display: Use two pixel per container for k1/k2 div
drm/
chitecture. This issue can
be fixed by changing the value type.
Cc: Aurabindo Pillai
Cc: Harry Wentland
Cc: Alex Deucher
Cc: Randy Dunlap
Fixes: 9b79abf79c414 ("drm/amd/display: add CLKMGR changes for DCN32/321")
Reported-by: Stephen Rothwell
Signed-off-by: Rodrigo Siqueira
---
y Wentland
Cc: Alex Deucher
Cc: Randy Dunlap
Fixes: 9b79abf79c414 ("drm/amd/display: add CLKMGR changes for DCN32/321")
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --g
Randy Dunlap
Fixes: 9b79abf79c414 ("drm/amd/display: add CLKMGR changes for DCN32/321")
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/cl
you still see compilation issues,
please, report:
- GCC version
- Config file
- Branch
Thanks
Siqueira
Rodrigo Siqueira (4):
drm/amd/display: Fix __umoddi3 undefined for 32 bit compilation
drm/amd/display: Fix __floatunsidf undefined for 32 bit compilation
drm/amd/display: Fix __muldf3 un
Cc: Randy Dunlap
Fixes: 9b0e0d433f74 ("drm/amd/display: Add dependant changes for DCN32/321")
Reported-by: Stephen Rothwell
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a
c: Stephen Rothwell
Cc: Aurabindo Pillai
Cc: Rodrigo Siqueira Jordao
Signed-off-by: Alex Deucher
---
.../dc/dml/dcn32/display_mode_vba_32.c| 77 ---
.../drm/amd/display/dc/dml/display_mode_vba.h | 3 +-
2 files changed, 36 insertions(+), 44 deletions(-)
diff --git a/d
Hi,
First of all, thanks a lot for exploring the introduction of kunit
inside amdgpu.
See my inline comments
On 2022-06-18 05:08, David Gow wrote:
On Sat, Jun 18, 2022 at 4:24 AM Maíra Canal wrote:
On 6/17/22 04:55, David Gow wrote:
On Fri, Jun 17, 2022 at 6:41 AM Maíra Canal wrote:
On 2022-06-17 15:51, Nathan Chancellor wrote:
Hi Rodrigo,
On Fri, Jun 17, 2022 at 03:34:57PM -0400, Rodrigo Siqueira wrote:
From: Nicholas Choi
[Why & How]
Since we only need transmitter value in function transmitter_to_phy_id().
Replace argument struct dc_link with enum transmi
In DCN32 clk hook functions, we are using the wrong reference for
get_dp_ref_clk_frequency and missing the get_dtb_ref_clk_frequency
reference. This commit adds those references.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32
We already have DALSMC_MSG_TransferTableDram2Smu in the file dalsmc.h;
for this reason, we don't need this definition in the smu msg file.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c| 2 --
1 file changed, 2
DPP DTO to match exactly with the
exact DPP refclk).
Acked-by: Rodrigo Siqueira
Signed-off-by: Alvin Lee
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 25 ++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32
system
behaviour. There is a clash with FCLK message due to inconsitent PMFW
headers.
[How]
Implement a new BacoAudio function to workaround the problem of
inconsistent PMFW headers in order to avoid BacoAudio message clasing
with FCLK Enable message.
Acked-by: Rodrigo Siqueira
Signed-off
with a check to make sure clocks are not
zero.
Acked-by: Rodrigo Siqueira
Signed-off-by: George Shen
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32
Add support to get VCO frequency from registers.
Signed-off-by: Rodrigo Siqueira
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 94 ++-
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 3 +
2 files changed, 96 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
From: Alvin Lee
FCLK not supported for DCN321, but still need to update the software
state accordingly to prevent unneeded full updates in driver
Acked-by: Rodrigo Siqueira
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c| 6 +++---
1 file changed, 3
From: George Shen
[Why & How]
Old vendor specific w/a are no longer needed
and unused. Clean up codebase by removing them.
Reviewed-by: Wenjing Liu
Acked-by: Alan Liu
Signed-off-by: George Shen
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 133 +-
From: Aric Cyr
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Remove unnecessary code;
- Small fixes (compilation warnings, typos, etc);
- Improvements in the DPMS code;
- Fix eDP issues
- Improvements in the MST code
Acked-by: Rodrigo Siqueira
Signed-off
From: Nicholas Choi
[Why & How]
Since we only need transmitter value in function transmitter_to_phy_id().
Replace argument struct dc_link with enum transmitter.
Reviewed-by: Chao-kai Wang
Acked-by: Alan Liu
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Nathan Chancellor
Signed-off-by:
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