Hi Marcelo,
First of all, thanks a lot for your patch! Please check some of my
inline comments.
On 4/27/24 10:05 AM, Marcelo Mendes Spessoto Junior wrote:
Fix most of the display documentation compile warnings by
documenting struct mpc_funcs functions in dc/inc/hw/mpc.h file.
Could you add
On 2/13/24 3:43 PM, Joao Paulo Pereira da Silva wrote:
From: jppaulo
Clean some wrong indenting that throw errors in checkpatch.
Signed-off-by: Joao Paulo Pereira da Silva
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
*dccg_mask);
-
#endif //__DCN301_DCCG_H__
Hi David,
Thanks a lot for your patch.
Reviewed-by: Rodrigo Siqueira
I already merged your patch into the asdn.
Thanks
Siqueira
for (i = 0; i < pool->mpcc_count; i++) {
struct mpcc_state s = {0};
pool->mpc->funcs->read_mpcc_state(pool->mpc, i, );
Hi Melissa,
Thanks a lot for your patch.
Reviewed-by: Rodrigo Siqueira
I already merged this change to asdn.
Thanks
Siqueira
for your patch.
Your patch looks good; I just added {} in the if and spaces around '/'
before merging your patch.
Anyway,
Reviewed-by: Rodrigo Siqueira
Thanks
Siqueira
+ else {
+ is_dsc_possible = false;
+ goto done;
+ }
if (target_bandwidth
This reverts commit 5ea4581611d14a6a0e8df40965802ec7bee9c671.
This change must be reverted since it caused soft hangs when changing
the refresh rate to 122 & 144Hz when using a 7000 series GPU.
Reported-by: Mark Broadworth
Cc: Daniel Wheeler
Cc: Harry Wentland
Signed-off-by: Rodrigo Siqu
This reverts commit 5aba567a2988400d4e01d44493c84bed92820d8d.
The original patch introduces cursor gamma issue to multiple
Linux compositors. For this reason this commit reverts this change.
Cc: Melissa Wen
Cc: Harry Wentland
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc
Fill ring buffer before offload.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn20
From: Aric Cyr
This version brings along following fixes:
* Expand dmub_cmd operations.
* Update DVI configuration.
* Modify power sequence.
* Enable Z10 flag for IPS.
* Multiple code cleanups.
Acked-by: Rodrigo Siqueira
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2
Add some missing registers expansion in the dcn201_link_encoder file.
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/dc/dcn201/dcn201_link_encoder.h| 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201
From: Sung Joon Kim
Rework part of the modifications made to the power sequence and resource
allocation logic.
Reviewed-by: Xi (Alex) Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Sung Joon Kim
---
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 8 ++---
.../dc/resource/dcn351
From: Eric Bernstein
[Why] Update FMT_CONTROL settings based on HW spec
[How] Update FMT settings for 4:2:0
Signed-off-by: Eric Bernstein
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 9 -
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 2
This commit remove some unused code and also rename one of the define.
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn10/dcn10_stream_encoder.h| 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 614d7c27c759..0f66d00ef80f 100644
--- a/drivers/gpu/drm/amd/display/dc
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index ee6493a9a79c..5c7e4884cac2 100644
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
index a046664e2031..c1959672df50 100644
This commit groups many parts of the code that are redundant or not used
and drops all of them.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h| 1 -
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c| 3 ---
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 6
From: Anthony Koo
Update dmub_cmd to manipulate SDP control in replay FSM, add command
for panel_cntl, expand link rate enum, and increase the reserve byte.
Acked-by: Rodrigo Siqueira
Signed-off-by: Anthony Koo
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 53 ++-
1
This commit updates some comments to be more precise and adds another
small comment to some other parts to improve the code readability.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h | 10 +-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
.
Signed-off-by: Mikita Lipski
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 01c75b66e8f1..8eefba757da4 100644
--- a/drivers
From: "Bitnun, Ethan"
The previous assumption that there will be an optimize_bandwidth call
following every prepare_bandwidth call was incorrect and caused small
inaccuracies in logging, as some info was only updated in later prepare
calls.
Signed-off-by: Ethan Bitnun
Reviewed-b
The chip ID DEVICE_ID_NV_13FE is not meaningful and represents a legacy
way of dealing with chip ID. This commit uses dc_version instead of
chip_id and also DCN_VERSION_2_01 instead of DEVICE_ID_NV_13FE.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2
Move the scl_data.format to be close to other similar parts.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd
From: Sung Joon Kim
[why]
IPS FSM requires Z10 flag to be enabled to do save and restore the
registers properly.
[how]
Enable Z10 and use the correct function to determine Z10 capability
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
Signed-off-by: Sung Joon Kim
---
.../gpu
Update headers by removing two unecessary headers and include a new one.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c| 3 ---
.../gpu/drm/amd/display/dc/dcn30
with correct derefrence
operations.
Reviewed-by: Aurabindo Pillai
Acked-by: Rodrigo Siqueira
Signed-off-by: Chaitanya Dhere
---
drivers/gpu/drm/amd/display/dc/core/dc_state.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core
From: Nicholas Kazlauskas
[Why]
IPS ono sequence ordering differs based on the ASIC.
[How]
Detect the ASIC ID revision and set the boot option accordingly. Feed
it through the DCN35 DMUB functions.
Reviewed-by: Sung joon Kim
Acked-by: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
From: Charlene Liu
Limit the code change for ips enable to reduce the impact for now. Also
exit_ips first before dc_power_down to avoid 0x9f.
Reviewed-by: Chris Park
Acked-by: Rodrigo Siqueira
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++-
1 file
default to TOPLEFT to maintain same
behaviour as without offset support.
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/dc.h | 3 +++
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 +++
2 files changed, 10 insertions
From: Chris Park
[Why]
DVI is TMDS signal like HDMI but without audio. Current signal check
does not correctly reflect DVI clock programming.
[How]
Define a new signal check for TMDS that includes DVI to HDMI TMDS
programming.
Reviewed-by: Dillon Varone
Acked-by: Rodrigo Siqueira
Signed-off
From: Sung Joon Kim
To reduce the complexity of pipe resource allocation for different
use-cases, now we search for any free pipe sequentially rather than from
bottom up.
Reviewed-by: Wenjing Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Sung Joon Kim
---
.../dc/resource/dcn32
From: Sung Joon Kim
Need to update the power sequence to help prevent potential issues like
multi-display or multi-plane.
Reviewed-by: Duncan Ma
Acked-by: Rodrigo Siqueira
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc/hwss/Makefile | 2 +-
.../drm/amd/display/dc/hwss
):
drm/amd/display: Add a function for checking tmds mode
Eric Bernstein (1):
drm/amd/display: Update FMT settings for 4:2:0
Mikita Lipski (1):
drm/amd/display: Fix PSR command version passed
Nicholas Kazlauskas (1):
drm/amd/display: Pass sequential ONO bit to DMCUB boot options
Rodrigo
vsc_packet_revision = vsc_packet_rev2;
/* Update to revision 5 for extended colorimetry support */
if (stream->use_vsc_sdp_for_colorimetry)
Reviewed-by: Rodrigo Siqueira
pipe_ctx->plane_res.mpcc_inst >= 0)
+ if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp)
update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] =
false;
if (pipe_ctx->stream_res.dsc)
Reviewed-by: Rodrigo Siqueira
before this line.
Fixes the below:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:1680
dml32_TruncToValidBPP() warn: ignoring unreachable code.
Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321")
Cc: Rodrigo Siqueira
Cc: Roman Li
Cc:
'
Cc: Wenjing Liu
Cc: Alex Hung
Cc: Rodrigo Siqueira
Cc: Roman Li
Cc: Aurabindo Pillai
Cc: Tom Chung
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core
On 2/26/24 04:12, Jani Nikula wrote:
On Thu, 22 Feb 2024, Rodrigo Siqueira wrote:
diff --git a/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
b/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
index eb6f81601757..4c5861ad58bd 100644
--- a/drivers/gpu/drm/amd/display/test/kunit
caps(HDR,OLED...etc)
Cc: sta...@vger.kernel.org # 6.5.x
Cc: Hamza Mahfooz
Cc: Tsung-hua Lin
Cc: Chris Chi
Cc: Harry Wentland
Tested-by: Daniel Wheeler
Reviewed-by: Sun peng Li
Acked-by: Rodrigo Siqueira
Signed-off-by: Ivan Lipski
---
drivers/gpu/drm/amd/display/amdgpu_dm
From: Maíra Canal
Explain how to run the KUnit tests present in the AMDGPU's Display
Core and clarify which architectures and tools can be used to run
the tests. Moreover, explains how to add new tests to the existing
tests.
Signed-off-by: Maíra Canal
---
From: Magali Lemes
This commit adds unit tests to the functions dcn20_cap_soc_clocks and
dcn21_update_bw_bounding_box from dcn20/dcn20_fpu.
Signed-off-by: Magali Lemes
Signed-off-by: Maíra Canal
---
.../gpu/drm/amd/display/test/kunit/Makefile | 3 +-
From: Maíra Canal
Add a unit test to the SubVP feature in order to avoid possible
regressions and ensure code robustness. In particular, this new test
validates the expected parameters when using 4k144 and 4k240 displays.
Signed-off-by: Maíra Canal
Co-developed-by: Rodrigo Siqueira
Reported
From: Maíra Canal
The display_mode_vba_20 deals with hundreds of display parameters for
the DCN20 and sometimes does it in odd ways. The addition of unit tests
intends to assure the quality of the code delivered by HW engineers and,
also make it possible to refactor the code decreasing concerns
From: Maíra Canal
The display_mode_vba library deals with hundreds of display parameters
and sometimes does it in odd ways. The addition of unit tests intends to
assure the quality of the code delivered by HW engineers and, also make
it possible to refactor the code decreasing concerns about
From: Maíra Canal
KUnit unifies the test structure and provides helper tools that simplify
the development of tests. Basic use case allows running tests as regular
processes, which makes easier to run unit tests on a development machine
and to integrate the tests in a CI system.
This commit
From: Isabella Basso
This adds tests to the bit encoding format verification functions on the
file. They're meant to be simpler so as to provide a proof of concept on
testing DML code.
Change since v4:
- Use DRM_AMD_DC_FP guard for FPU tests
Signed-off-by: Isabella Basso
Signed-off-by: Maíra
From: Tales Aparecida
The fixed31_32 library performs a lot of the mathematical operations
involving fixed-point arithmetic and the conversion of integers to
fixed-point representation.
This unit tests intend to assure the proper functioning of the basic
mathematical operations of fixed-point
In 2022, we got a great patchset from a GSoC project introducing unit
tests to the amdgpu display. Since version 3, this effort was put on
hold, and now I'm attempting to revive it. I'll add part of the original
cover letter at the bottom of this cover letter, but you can read all
the original
,
new_addr_range.end);
- *out_data = kzalloc(*out_size * sizeof(**out_data), GFP_KERNEL);
+ *out_data = kcalloc(*out_size, sizeof(**out_data), GFP_KERNEL);
}
}
lgtm,
Reviewed-by: Rodrigo Siqueira
Hi Túlio,
First of all thanks for your patch. See my comments inline.
On 2/17/24 13:20, Túlio Fernandes wrote:
Clean unnecessary braces in dc/dcn32/dcn32_resource_helpers.c and
dc/dcn32/dcn201_link_encoder.c
Did you identify this issue with checkpatch? If so, I recommend you
paste the
pport configurable")
Cc: sta...@vger.kernel.org
Cc: Hamza Mahfooz
Cc: Mario Limonciello
Cc: Rodrigo Siqueira
Cc: Aurabindo Pillai
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/g
From: Aric Cyr
[Why]
Nanosec stats can overflow on long running systems potentially causing
statistic logging issues.
[How]
Use 64bit types for nanosec stats to ensure no overflow.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
A long time ago, the slab header was added to multiple files in DC. We
also included it in the os_types.h, which is included in many of those
DC files. At this point, there is no need to insert the slab.h header in
multiple files, so this commit drops those includes.
Signed-off-by: Rodrigo
From: Aric Cyr
This version brings along the following:
- Re-enable windowed MPO support for DCN32/321
- Improvements in the subvp feature
- Code clean up
- USB4 fixes
Acked-by: Rodrigo Siqueira
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1
these pipe transitions happen
automatically and quietly when the conditions are met without any visual
impacts to the user.
Reviewed-by: Martin Leung
Acked-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 1 +
.../gpu/drm/amd
From: Ethan Bitnun
Prevent logs during a prepare_bandwidth call to ensure log accuracy.
Reviewed-by: Alvin Lee
Acked-by: Rodrigo Siqueira
Signed-off-by: Ethan Bitnun
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Acked-by: Rodrigo Siqueira
Signed-off-by: Swapnil Patel
---
.../drm/amd/display/dc/dml2/dml2_translation_helper.c| 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
b/drivers/gpu/drm/amd/display/dc/dml2
From: Alvin Lee
Subvp bugs related to 8K60 have been fixed, so remove the limit that
blocks 8K60 timings from enabling SubVP.
Reviewed-by: Nevenko Stupar
Reviewed-by: Chaitanya Dhere
Acked-by: Rodrigo Siqueira
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32
add pointers in the plane state, stream, and
pointers in the stream state to the dc_scratch state and backup and
restore these so the minimal transition can take place successfully.
Reviewed-by: Wenjing Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/d
From: Nicholas Kazlauskas
[Why]
VBIOS DMCUB firmware doesn't set the dal_fw bit and we end up hanging
waiting for HW power up done because of it.
[How]
Simplify the path and allow mailbox_rdy to be a functional check when
we detect VBIOS firmware.
Reviewed-by: Charlene Liu
Acked-by: Rodrigo
://gitlab.freedesktop.org/drm/amd/-/issues/3122
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
Signed-off-by: Lewis Huang
---
.../drm/amd/display/dc/dce/dce_panel_cntl.c | 1 +
.../amd/display/dc/dcn301/dcn301_panel_cntl.c | 1 +
.../amd/display/dc/dcn31/dcn31_panel_cntl.c | 18
drm_device()
Cc: Stable
Reviewed-by: Aurabindo Pillai
Acked-by: Rodrigo Siqueira
Signed-off-by: Wayne Lin
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 37 +--
1 file changed, 18 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdg
is entered, and also to check for 2-lane versuse 4-lane
mode.
Reviewed-by: Charlene Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: George Shen
---
.../display/dc/dcn32/dcn32_dio_link_encoder.c | 85 ++-
.../display/dc/dcn32/dcn32_dio_link_encoder.h | 5 ++
2 files changed, 71
The function dcn32_build_wm_range_table call DC_FP_START/END. Drop the
unnecessary FPU guard.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32
Set a default value for target_div.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc
The file rv1_clk_mgr_clk.c is not used and for this reason useless. Drop
the unnecessary file.
Signed-off-by: Rodrigo Siqueira
---
.../dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c| 79 ---
1 file changed, 79 deletions(-)
delete mode 100644
drivers/gpu/drm/amd/display/dc/clk_mgr
via DMUB
Lewis Huang (1):
drm/amd/display: Only allow dig mapping to pwrseq in new asic
Nicholas Kazlauskas (1):
drm/amd/display: Fix S4 hang polling on HW power up done for VBIOS
DMCUB
Rodrigo Siqueira (6):
drm/amd/display: Remove break after return
drm/amd/display: Initialize variable
Remove break after return since it will never be reached.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
Instead of only asserting in the case of the SMU wait time is not what
we expect, add the SMU timeout check and try again.
Signed-off-by: Rodrigo Siqueira
---
.../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 11 ---
.../drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c| 6
From: Magali Lemes
This commit adds unit tests to the functions dcn20_cap_soc_clocks and
dcn21_update_bw_bounding_box from dcn20/dcn20_fpu.
Signed-off-by: Magali Lemes
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/amd/display/tests/Makefile| 3 +-
From: Maíra Canal
Explain how to run the KUnit tests present in the AMDGPU's Display
Core and clarify which architectures and tools can be used to run
the tests. Moreover, explains how to add new tests to the existing
tests.
Signed-off-by: Maíra Canal
---
From: Maíra Canal
The display_mode_vba_20 deals with hundreds of display parameters for
the DCN20 and sometimes does it in odd ways. The addition of unit tests
intends to assure the quality of the code delivered by HW engineers and,
also make it possible to refactor the code decreasing concerns
From: Maíra Canal
Add a unit test to the SubVP feature in order to avoid possible
regressions and ensure code robustness. In particular, this new test
validates the expected parameters when using 4k144 and 4k240 displays.
Signed-off-by: Maíra Canal
Signed-off-by: Rodrigo Siqueira
Reported
From: Maíra Canal
The display_mode_vba library deals with hundreds of display parameters
and sometimes does it in odd ways. The addition of unit tests intends to
assure the quality of the code delivered by HW engineers and, also make
it possible to refactor the code decreasing concerns about
From: Isabella Basso
This adds tests to the bit encoding format verification functions on the
file. They're meant to be simpler so as to provide a proof of concept on
testing DML code.
Signed-off-by: Isabella Basso
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/amd/display/Kconfig
From: Maíra Canal
KUnit unifies the test structure and provides helper tools that simplify
the development of tests. Basic use case allows running tests as regular
processes, which makes easier to run unit tests on a development machine
and to integrate the tests in a CI system.
This commit
From: Tales Aparecida
The fixed31_32 library performs a lot of the mathematical operations
involving fixed-point arithmetic and the conversion of integers to
fixed-point representation.
This unit tests intend to assure the proper functioning of the basic
mathematical operations of fixed-point
In 2022, we got a great patchset from a GSoC project introducing unit
tests to the amdgpu display. Since version 3, this effort was put on
hold, and now I'm attempting to revive it. I'll add part of the original
cover letter at the bottom of this cover letter, but you can read all
the original
On 1/23/24 09:19, Hamza Mahfooz wrote:
On 1/22/24 16:24, Rodrigo Siqueira wrote:
This patchset improves how the AMDGPU display documentation is
organized, expands the kernel-doc to extract information from the
source, and adds more context about DC workflow. Finally, at the end
Cc: Jun Lei
Cc: Aurabindo Pillai
Cc: Hamza Mahfooz
Cc: Harry Wentland
Cc: Alex Deucher
Signed-off-by: Rodrigo Siqueira
---
.../include/asic_reg/dcn/dcn_3_1_6_offset.h | 4 ++
.../include/asic_reg/dcn/dcn_3_1_6_sh_mask.h | 10 +++
.../include/asic_reg/dcn/dcn_3_5_0_offset.h | 24
This commit introduces basic DPP information and the struct scan for
code documentation.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: Harry Wentland
Cc: Hamza Mahfooz
Cc: Christian König
Cc: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../gpu/amdgpu/display/dcn-blocks.rst
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: Harry Wentland
Cc: Hamza Mahfooz
Cc: Christian König
Cc: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
Documentation/gpu/amdgpu/display/dcn-blocks.rst | 12
.../gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h | 10
König
Cc: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
Documentation/gpu/amdgpu/display/index.rst | 76 --
1 file changed, 69 insertions(+), 7 deletions(-)
diff --git a/Documentation/gpu/amdgpu/display/index.rst
b/Documentation/gpu/amdgpu/display/index.rst
index
Pillai
Signed-off-by: Rodrigo Siqueira
---
.../gpu/amdgpu/display/dcn-blocks.rst | 12 +
.../gpu/amdgpu/display/display-manager.rst| 3 -
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 250 --
3 files changed, 185 insertions(+), 80 deletions(-)
diff --git
-off-by: Rodrigo Siqueira
---
.../amdgpu/display/display-contributing.rst | 168 ++
Documentation/gpu/amdgpu/display/index.rst| 1 +
drivers/gpu/drm/amd/display/TODO | 110
3 files changed, 169 insertions(+), 110 deletions(-)
create mode 100644
Enable the documentation to extract code documentation from dchubbub.h
file.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: Harry Wentland
Cc: Hamza Mahfooz
Cc: Christian König
Cc: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
Documentation/gpu/amdgpu/display/dcn-blocks.rst | 12
Introduce OPP as part of the kernel documentation.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: Harry Wentland
Cc: Hamza Mahfooz
Cc: Christian König
Cc: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
Documentation/gpu/amdgpu/display/dcn-blocks.rst | 12
drivers/gpu/drm
Create the HUBP documentation page and add the doc references to extract
the HUBP code documentation.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: Harry Wentland
Cc: Hamza Mahfooz
Cc: Christian König
Cc: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../gpu/amdgpu/display/dcn
to the display code.
Changes since V1:
- Remove unprecise information about the DC process.
- Expand the contribution list.
- Rebase.
Thanks
Siqueira
Rodrigo Siqueira (8):
Documentation/gpu: Add basic page for HUBP
Documentation/gpu: Add simple doc page for DCHUBBUB
Documentation/gpu: Add kernel
Cc: Aurabindo Pillai
Cc: Rodrigo Siqueira
Cc: Hamza Mahfooz
Signed-off-by: Srinivasan Shanmugam
This change lgtm.
Btw, avoid to send new patches as a reply of the previous one.
Reviewed-by: Rodrigo Siqueira
Thanks
Siqueira
---
v2:
- Initialized status variable to 'DC_ERROR_UNEXPECTED' def
e.crtc->dev,
"doesn't support plane and CRTC degamma at the same
time\n");
- return -EINVAL;
+ return -EINVAL;
}
/* If we are here, it means we don't have plane degamma settings, check
Reviewed-by: Rodrigo Siqueira
Change also
nd
3.0.1.
Yeah... I totally agree with you. I'll try to get one DCN 316 device to
validate this issue. For now, let's revert this change since it causes a
large regression in our CI.
Reviewed-by: Rodrigo Siqueira
Also applied to asdn.
Thanks
Siqueira
Unfortunately, I don't have a DCN 3.1
From: Aric Cyr
This version brings along following fixes:
- Improve z8/z10 support
- Revert some of the VRR optimization
- Improve usb4 when using MST
Acked-by: Rodrigo Siqueira
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1
From: Meenakshikumar Somasundaram
[Why]
Dpia hpd status not in sync causing driver not enabling BW Alloc after
S4.
[How]
Update hpd_status of the link when querying hpd state from dmub in
dpia_query_hpd_status().
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
Signed-off
From: Daniel Miess
This reverts commit 058d7bea47e9d9fd43dc0503b6403071c3429d91.
The previous commit causes failure to light up for 1080p
eDP + 8k HDMI panel combo.
Reviewed-by: Charlene Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Daniel Miess
---
.../amd/display/dc/dml2
From: Charlene Liu
Adjust z8 latency for performance.
Reviewed-by: Muhammad Ahmed
Acked-by: Rodrigo Siqueira
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd
streams bandwidth added with dp MTPH overhead.
- Allocate/deallcate usb4 bandwidth when setting dpms on/off.
- When doing display mode validation, driver also need to consider total
bandwidth of all mst streams for mst link.
Reviewed-by: Cruise Hung
Acked-by: Rodrigo Siqueira
Signed-off
From: Martin Leung
This reverts commit 64d446649677255bc6b4e1fc757d8b772b6166b1.
The original commit causes regression in corner case with HDMI at
specific timings. reverting from staging to get the full suite to
retest
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Martin Leung
---
drivers
From: Martin Leung
This reverts commit 4b70dc8c46fc6e89dd1ce90d5ab7b620b25374f0.
The original commit causes issues with certain features when DRR is
disabled, need to revisit this change later after resolving issues with
new DRR policy.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Martin
From: Martin Tsai
[Why]
Panels show corruption with high refresh rate timings when ssc is
enabled.
[How]
Read down-spread percentage from lut to adjust dprefclk. Issues come
from S0i3 with this commit has been fixed by SMU.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
Signed
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