In the platform extension file, when I specify the SPI buses, there is a
clock subsignal "clk." If I want to have multiple SPI buses that share the
same clock, I'm going to need to reference the same clock subsignal in each
bus, which means that that specific pin will appear multiple times in the
f
On Friday, October 28, 2016 08:49 PM, Jonathan Mizrahi wrote:
In the platform extension file, when I specify the SPI buses, there is a
clock subsignal "clk." If I want to have multiple SPI buses that share
the same clock, I'm going to need to reference the same clock subsignal
in each bus, which
OK, thanks for confirming.
I have a two channel DDS board in which the DDSs have separate signal lines
but a common clock line. I am OK with only talking to one of them at a
time. What is the easiest way to implement the mux/demux you suggest? When
I declare the SPI bus I need the mosi/miso subsign
on Sayma RTM FPGA we have enough pins to do p2p connections for all SPI
chips, and so I did.
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I have a two channel DDS board in which the DDSs have separate signal lines but
a common clock line. I am OK with only talking to one of them at a time. What
is the easiest way to implement the mux/demux you suggest? When I declare the
SPI bus I need the mosi/miso subsignals to not be specific p
On Fri, Oct 28, 2016 at 3:31 PM, Jonathan Mizrahi wrote:
> OK, thanks for confirming.
> I have a two channel DDS board in which the DDSs have separate signal lines
> but a common clock line. I am OK with only talking to one of them at a time.
> What is the easiest way to implement the mux/demux yo
> > OK, thanks for confirming.
> > I have a two channel DDS board in which the DDSs have separate signal
> > lines but a common clock line. I am OK with only talking to one of them at a
> time.
> > What is the easiest way to implement the mux/demux you suggest? When
> I
> > declare the SPI bus I ne
Yes, I know how SPI and chip select lines work. The fact remains that I
have sitting in front of me a board with two chips on it, which have
separate data lines and a common clock line. This was done because the
board designer wanted to preserve the ability to write to both chips at the
same time.
Are there no chip select lines on these DDS chips? If there are, use them. If
there are not, use a mux/demux chip instead of trying to hack up something
atrocious in the gateware.
From: Jonathan Mizrahi [mailto:jmizr...@umd.edu]
Sent: Friday, October 28, 2016 9:30 AM
To: Slichter, Daniel H. (F
Yes, there are CS lines, and I can use them, if I physically short the data
lines. As it appears I have to short them to avoid having to make a bunch
of changes, I would rather virtually short them in software. How do you
recommend I do that?
Jonathan Mizrahi
Research Scientist
Joint Quantum Insti
On Friday, October 28, 2016 11:55 PM, Jonathan Mizrahi wrote:
How do you recommend I do that?
Something like:
self.comb += [
mosi_dev1.eq(mosi_spi_core),
mosi_dev2.eq(mosi_spi_core),
miso_spi_core.eq(miso_dev_1 | miso_dev_2)
]
The last line assumes that a non-transmitting device (weakly)
On Saturday, October 29, 2016 12:00 AM, Sébastien Bourdeauducq wrote:
The last line assumes that a non-transmitting device (weakly) pulls down
MISO.
You can enable a pull-down resistor inside the FPGA.
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