In situations where reentrancy is not necessary, maintaining code and
data in separate adjacent areas each on cache boundaries and sizes a
multiple of cache line length, these instructions may be very useful.
And perhaps there are enough critical kernel code paths protected by
locks for which
On 4/14/2022 10:35 AM, David Cole wrote:
Note, "dual path'ing" your code applies to TX, not to CTX.
That's true if your minimum supported z/OS release is z/OS 2.4. Not even
IBM is that aggressive!
If your product still supports z/OS 2.3 or less, you must dual-path CTX
as well.
--
On Apr 14, 2022, at 14:50:46, Tom Harper wrote:
>
> I did not propose any such instruction.
>
> Sent from my iPhone
>
>> On Apr 14, 2022, at 4:42 PM, Seymour J Metz wrote:
>>
>> You asked for an instruction to clear a page to zeros. I proposed an
>> instruction to clear a page to zeros
I did not propose any such instruction.
Sent from my iPhone
> On Apr 14, 2022, at 4:42 PM, Seymour J Metz wrote:
>
> You asked for an instruction to clear a page to zeros. I proposed an
> instruction to clear a page to zeros without causing an extraneous page-in if
> the page was
You asked for an instruction to clear a page to zeros. I proposed an
instruction to clear a page to zeros without causing an extraneous page-in if
the page was previously paged out and without causing an unnecessary page out
if the page was stolen after being cleared but before you wrote
Yes and no. A service exists, with the attendant overhead. An instruction to
do it without invoking the OS does not exist.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on
I like that: A significant improvement.
Sent from my iPhone
> On Apr 14, 2022, at 3:59 PM, Schmitt, Michael wrote:
>
> Fill Immediate:
>
> FILLI field,x'FF' set field to high-values
>
> Where machine sets field to the immediate value: space, zeros, whatever
>
>
> -Original
On Thu, 14 Apr 2022 at 12:29, Ngan, Robert (DXC Luxoft)
wrote:
>
> STRL/STGRLl?
> Is the GCC compiler generating non-reentrant code?
I've wondered why these relatively (heh...) recent instructions exist
in the architecture at all. (There is also STHRL.)
Certainly they appeared long after it
This already exists in the OS: PGSER RELEASE.
Keith Moe
BMC Software
Soon retired
On Thursday, April 14, 2022, 12:41:27 PM PDT, Seymour J Metz
wrote:
How about something a bit more complicated that let's the OS know that it can
do a page steal without having to page it out to
Fill Immediate:
FILLI field,x'FF' set field to high-values
Where machine sets field to the immediate value: space, zeros, whatever
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Tom Harper
Sent: Thursday, April 14, 2022 12:06 PM
To:
I don’t see what this has to do with what I’m proposing.
Sent from my iPhone
> On Apr 14, 2022, at 3:39 PM, Seymour J Metz wrote:
>
> Not directly, but it also wouldn't prevent unnecessary page outs after page
> steals. A better new instruction would be an unpriviled instruction similar
>
How about something a bit more complicated that let's the OS know that it can
do a page steal without having to page it out to DASD?
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Assembler List
Not directly, but it also wouldn't prevent unnecessary page outs after page
steals. A better new instruction would be an unpriviled instruction similar to
IPTE; mark the page as invalid only if write is permitted, otherwise protection
exception. Maybe even a version that also clears the page
I don’t believe the paging implications would be any different from an XC.
Sent from my iPhone
> On Apr 14, 2022, at 1:26 PM, Paul Gilmartin
> <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote:
>
> On Apr 14, 2022, at 11:06:09, Tom Harper wrote:
>>
>> IMHO, the next instruction to add
I was at a meeting IBM had with several ISVs at
which removal of TX and CTX was discussed. The
consensus in the room seemed to be that no one
particularly cared about TX, but many cared rather strongly about CTX!
It turned out that several ISVs were using CTX
and that they realized
Xlnt idea! And hopefully execution when target is page aligned would behave as
MVCL* does and not pollute caches.
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Tom Harper
Sent: Thursday, April 14, 2022 1:06 PM
To:
On Apr 14, 2022, at 11:06:09, Tom Harper wrote:
>
> IMHO, the next instruction to add to z/Architecture would be an instruction
> to clear storage to zeros.
>
Would that cause a Lot of paging I/O? Would it be better to mark all pages as
invalid, to be cleared automatically when referenced,
IMHO, the next instruction to add to z/Architecture would be an instruction to
clear storage to zeros.
Right now a number of methods are in widespread use, none of which are clean
and simple. I mean, it’s been almost sixty years.
MVCL takes three registers to set up beforehand; XC sets the
Yikes! What are the gcc default options?
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Ngan, Robert (DXC Luxoft) [robert.n...@dxc.com]
Sent: Thursday, April 14,
STRL/STGRLl?
Is the GCC compiler generating non-reentrant code?
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Ian Worthington
Sent: Thursday, April 14, 2022 08:05
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Signed/unsigned operations
I
On Apr 14, 2022, at 09:21:28, Robin Vowels wrote:
>
> On 2022-04-15 00:31, Seymour J Metz wrote:
>> The S/360 architecture uses two's complement arithmetic, and that
>> remains the case through z. Accordingly, signed and unsigned
>> arithmetic are the same except for the condition code, except
Yes, anything depending on the CC will be affected. I wonder whether there are
any new variations of LAT on the Z16.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
On 2022-04-15 00:31, Seymour J Metz wrote:
The S/360 architecture uses two's complement arithmetic, and that
remains the case through z. Accordingly, signed and unsigned
arithmetic are the same except for the condition code, except when
sign extension is an issue, e.g., adding a word to a grande
The S/360 architecture uses two's complement arithmetic, and that remains the
case through z. Accordingly, signed and unsigned arithmetic are the same except
for the condition code, except when sign extension is an issue, e.g., adding a
word to a grande register..
--
Shmuel (Seymour J.) Metz
I noticed today that GCC generates for:
static __uint32_t sumu32; // unsigned int
static __uint64_t sumu64; // unsigned long
void addStuff(__uint64_t a64, __uint64_t b64, __uint32_t a32, __uint32_t b32 ) {
sumu32 = a32 + b32;
sumu64 = a64 + b64;
}
the following:
117: sumu32 =
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