Abe,
This is documented in APAR PI62275.
Please see http://www-01.ibm.com/support/docview.wss?uid=swg22001988.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Abe Kornelis
Sent: Saturday, September 23, 2017 10
Gary,
Do you have a storage dump available?
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Gary Weinhold
Sent: Tuesday, December 15, 2015 6:05 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: BSA (Branch and Set
I am looking for any pointers to documentation describing how to structure a
multitasking assembler program where multiple subtasks are concurrently
accessing DB2.
No two (2) subtasks will be accessing the same DB2 table concurrently.
Any assistance will be most welcome.
John P. Baker
Martin,
I believe that these are new extended mnemonics rather than new hardware
instructions.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of mar...@pi-sysprog.de
Sent: Tuesday, March 10, 2015 5:07 AM
To
TGT(L'SRC-1),SRC+1
MVN TGT,SRC
NI TGT+L'SRC-1,X'0F'
Please note that is this instruction sequence, both of the source and target
areas must be of the same length.
In both of the instruction sequences provided, the maximum field length is
256 characters.
Binyamin,
The JC instruction would work fine in those cases where bits 8-15 of the
executed instruction are not to be modified by the contents of the low-order
byte of R1 (R1<>0).
However, where (R1<>0), your example fails to address John's scenario.
John P. Baker
Pre
ction, this operation occurs in the instruction processor
and does not affect the memory containing the instruction specified by the
I3 operand.
This instruction will not set a condition code. However, the EX(ecuted)
instruction may set the condition code.
John P. Baker
President
NGSSA
code. However, the EX(ecuted)
instruction may set the condition code.
John P. Baker
President
NGSSA, LLC
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of McKown, John
Sent: Monday, November 26, 2012 4:39 PM
To: ASSEMBLER
I can see many uses for transactional processing.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of David Cole
Sent: Tuesday, September 18, 2012 3:09 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: The Transaction
mal character string returned in R1 will equate to the absolute
value of the original binary content of R1 modulo 1.
John P. Baker
President
NGSSA, LLC
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of Bauer, Bobby (NIH/CIT)
R5,R4 Populate the low-order portion of
the mask
SLLGR5,0(R3)Discard the unneeded portion of the
mask
L10 DC 0H'0'
STMGR4,R5, Save the mask
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [m
Y instruction if the operand is specified as '(SL,{"symbol" |
"expression"})' and SYSSTATE ASCENV=ASC is in effect ;
LARL instruction of the operand is specified as '(SRL,{"symbol" |
"expression"})'; in this case, the SYSSTATE ASCEN
Tony,
On my system it appeared as "lacunae", which is a term used to indicate a
cavity or depression, or in this context, an omission in the design.
Code set differences?
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.U
ruction design could well be the cause.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of Edward Jaffe
Sent: Saturday, January 07, 2012 1:48 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: z/Arch design question.
John,
Since you have seen fit to reference APL2, can you please tell me if there
are any APL[2] mailing lists here about?
I was also confused. I would guess he was talking about redoing some
assembler into Metal/C. Or maybe it was my joking comment that we could
consider redoing assembler into CO
NG (label-1,label-2,label-3),register-list", the USING
statement will have an explicit range of label-2 thru label-3, where the 1st
register addresses label-1, which must lie between label-2 and label-3.
Please tell me what you think.
John P. Baker
t the code failure resulted from a missing DROP
R15 instruction.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Martin Trübner
Sent: Thursday, December 30, 2010 11:08 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re:
USING of the form USING (from,thru),register-list is issued.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Martin Trübner
Sent: Thursday, December 30, 2010 10:36 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: A
Martin,
My PTF level is UK48077.
R3 points to BASE at offset 590.
R15 points to an unlabeled instruction at offset 562.
Both LAY instructions address the same instruction, but use different
offsets, as one would expect.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler
Martin,
There is no overlap on the base registers, so no warning message is issued.
The code generated is correct.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Martin Trübner
Sent: Thursday, December 30, 2010
Tom,
In some cases, I can and do use R0, R1, R14, and R15.
At other times, this is not an option available to me.
Run baseless just makes the job easier.
What would really make things easier would be baseless macros.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List
Tom,
Running baseless just frees up additional registers, so that I can avoid the
overhead of repeated stores and loads.
It does NOT eliminate any need for a CLCL, MVCL, or PLO machine instruction.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l
se of the register changes, the first two cases will
permit NO parallel processing to occur in the pipeline.
My thought is that the proposed BRUX and EXRX instructions would be much
more pipeline friendly.
Am I somehow misinterpreting the impact of the various instructions on the
pipeline?
J
argument that writing baseless code is a waste of time, a
position that may be fine for his applications, but is anything but for my
development efforts.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Gerhard Adam
Edward,
No doubt about it. PLO is a great instruction!
Difficult to understand at first, and the operand mapping could drive a
troll to fits, but it is very fast.
My point was that some of the PLO variants use "lots" of registers.
John P. Baker
-Original Message-
From: IBM
, can
have its inefficiencies show up on the bill at the end of the month. To my
mind, that would not make for a good bullet point on a sales presentation.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Binyamin
procedures down. The code size grew dramatically. At
the same time, performance went to hell in a handbasket. MVCL and PLO
instructions tend to do that to you.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Savor
tells me a wholly different story.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Chris Craddock
Sent: Monday, December 20, 2010 12:38 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Baseless vs Based
wow what a
Edward,
I have to disagree.
What is the problem with using LARL to reference static data significantly
offset within a large CSECT/RSECT?
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Edward Jaffe
Sent: Monday
Binyamin,
I am currently using a BASR/B approach for the BRUX case.
I just question whether it is the best approach. Since BRUX would not
change any registers, I would think that it would be more efficient in the
pipeline.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler
serves to enhance
code bloat. I see far too much of that in Windows. I don't want to
encourage it on the mainframe.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Martin Trübner
Sent: Monday, December 20, 20
Martin,
Except that the "L" instruction requires a base register.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Martin Trübner
Sent: Monday, December 20, 2010 11:40 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.E
struction, I would say that it is highly desirable,
but not essential.
I welcome any comments you may have.
John P. Baker
Walt,
There seems to be some belief here that 2G thru 4G-1 is unavailable for some
reason other than that specifically addressed by the undocumented
USE2GTO32G={NO|YES} operand.
I do not believe that to be case. Am I correct?
John P. Baker
-Original Message-
From: IBM Mainframe
.
512T thru 16E-1 is available for private memory objects.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Bill Fairchild
Sent: Thursday, December 09, 2010 11:13 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: z
begins
at 4G. Is this correct?
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Bill Fairchild
Sent: Thursday, December 09, 2010 7:34 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: z/OS IARV64
Mostly correct
Tony,
Corrected text by removing extraneous word.
Also, see chapter 4 of publication SA22-7614-07 MVS Programming: Extended
Addressability Guide.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of John P. Baker
Sent
Tony,
A 64-bit user private area begins at 2G and extends up to 2T.
A 64-bit shared private area begins at 2T and extends up to 512T.
A second 64-bit user private area begins at 512T and extend to 16X
(Exabyte).
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List
functions which would
permit macro coder to example sublibrary and namespace definitions.
I will leave it to the z/OS and z/VM gurus to make suggestions as to how
these extensions could be implemented on their respective platforms.
Significant changes will be required in all of the various us
Keven,
Have you taken a look at the CSRSI service?
I believe that it can retrieve everything you require.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Hall, Keven
Sent: Friday, September 10, 2010 1:09 PM
To
ot; provided by HLASM, but that does not
change the underlying instruction.
I prefer to go by what the "Principles of Operation" publication documents
as distinct instructions.
John P. Baker
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Da
that multiple instructions may be implemented
by a single microcode/millicode routine. That is really not relevant to the
"number of instructions", since that is hidden from the programmer.
As far as we are concerned, every instruction could well be hardwired.
John P. Baker
-Origin
Tony,
Not quite.
You are correct about ISK/SSK.
HDV and SIOF were NOT part of the S/360 instruction set, but rather arrived
with the S/370.
The remaining S/360 privileged instruction were DIAG, LPSW, and SSM, all of
which remain available.
John P. Baker
-Original Message-
From: IBM
4 comprising the S/360 I/O feature and of 2 comprising
the S/360 Direct Control feature.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Gary L Peskin
Sent: Tuesday, August 31, 2010 12:38 AM
To: ASSEMBLER-LIST
Bernd,
The problem I am seeking to address is limited to instructions making use of
relative addressing that make reference to a literal whose representation
consists of an odd number of bytes.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l
NOT using CICS. Can you tell us
what the environment is?
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu] On
Behalf Of Patrick Roehl
Sent: Monday, August 23, 2010 10:46 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Efficient
All,
IBM has assigned MR0823102220 as the requirement number.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of John P. Baker
Sent: Saturday, August 21, 2010 4:20 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject
Paul,
I don't see a problem here.
In the case you cite, the program expects R4 to point to an AL3 constant.
The fact that when properly aligned, the AL3 constant may start at X'1002'
for a length of three (3), followed by one (1) bye of padding should be of
no concern to the p
operating system
level n.
So be it. I can live with that.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Keith E. Moe
Sent: Sunday, August 22, 2010 5:34 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Suggestion for
Edward,
I don't see it as being a major issue.
A little padding is not going to hurt anyone.
Memory is cheap. Programmer time is expensive.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Edward Jaffe
programming will
not be widely adopted until mechanisms are put in place to limit the cost of
re-engineering code to make use of baseless programming.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of john gilmore
Sent: Sunday
o not feel that it is the best solution.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of john gilmore
Sent: Sunday, August 22, 2010 11:14 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: LARL vs. literal alignme
Martin,
The requirement was submitted thru the z/VSE homepage, so yes, z/VSE is
prominent.
However, the requirement is operating system independent.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Martin Trübner
data.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Bohn, Dale
Sent: Sunday, August 22, 2010 2:01 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: LARL vs. Literal Alignment
This whole discussion seems to miss
1-Bits instruction.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Don Higgins
Sent: Tuesday, August 03, 2010 7:55 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: OF what use are one-bit counts for a bit string?
All
I thou
Tony,
A non-literal constant, if improperly aligned by the programmer, should be
flagged in error.
On the other hand, the placement of a literal constant is determined by the
assembler. That being the case, I believe that it is reasonable for the
assembler to provide correct alignment.
John P
f bytes.
However, a halfword aligned literal whose representation consists of an odd
number of bytes will cause the following literal to start on an odd address,
which is not addressable by an instruction using relative addressing.
It is not reasonable to tell a customer that they cannot use lite
will post that number for anyone who
may be interested.
John P. Baker
requesting that, at a minimum, an HLASM option be provided to enable
relative addressing literal alignment.
John P. Baker
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Paul Gilmartin
Sent: Saturday, August 21, 2010 2:55 PM
To
otherwise unaligned literal to be aligned in
order to meet the requirements of the relative instruction.
Has anyone else run into this problem?
Is there any known method by which to force an otherwise unaligned literal
to be aligned.
John P. Baker
27;N', and for T'&X(2) I receive 'U'.
If I code T'&X, and X=(,B), then for T'&X I receive 'O' (unexpected), for
T'&X(1) I receive 'O', and for T'&X(2) I receive 'U'.
It appears the T'&X is the same as T'&X(1), which makes it difficult to
determine if a sublisted operand has been wholly omitted.
Am I missing something here?
John P. Baker
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