My bad! The current edition is SA22-7832-12.
I had the latest z15 model on my mind, hence the -15 typo.
List On Behalf
Of Dan Greiner
Sent: Friday, June 5, 2020 13:57
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD instructions
Although it does actually access multiple data items, PERFORM LOCK OPERATION
(PLO) really doesn't qualify as a SIMD
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Martin Ward [mar...@gkc.org.uk]
Sent: Monday, June 8, 2020 3:52 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD instructions
On 07/06/2020 21:57
On 07/06/2020 21:57, Seymour J Metz wrote:
I will admit that the UNPK/TR technique won;t work so well with
Unicode, but then neither will TROT.
For the sixteen hex characters, Unicode UTF-8 encoding
is the same as ASCII :-)
--
Martin
Dr Martin Ward | Email:
Truebner [mar...@pi-sysprog.de]
Sent: Monday, June 8, 2020 8:22 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD instructions
>> F1F2F3F3 to 0001 0010 0011 0100
you ment
F1F2F3F3 to 00010010 00110100
or?
--
Martin T
>> F1F2F3F3 to 0001 0010 0011 0100
you ment
F1F2F3F3 to 00010010 00110100
or?
--
Martin Trübner; everything around "PoOps of z/arch"
Teichstraße 39E
D-63225 Langen
F: +49 6103 71254
M: +49 171 850 7132
E: mar...@pi-sysprog.de
IST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD
instructions
I might believe hex to binary, with the 16 symbols in an 8 bit encoding.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Assembler L
...@mweb.co.za]
Sent: Monday, June 8, 2020 2:33 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD
instructions
I did create a macro to build the table -- and one for TRTO, to convert
display to hex.
-Original Message-
From: IBM Mainframe
: Monday, June 8, 2020 2:33 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD instructions
I did create a macro to build the table -- and one for TRTO, to convert
display to hex.
-Original Message-
From: IBM Mainframe Assembler List
Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on
behalf of Pieter Wiid [pw...@mweb.co.za]
Sent: Sunday, June 7, 2020 1:39 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD
instructions
Do you mean conversion to printable hex, e.g. convert x
Mainframe Assembler List On Behalf
Of Ed Jaffe
Sent: Sunday, June 7, 2020 6:24 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD instructions
On 6/7/2020 9:23 AM, Farley, Peter x23353 wrote:
> Is there any chance you could provide (maybe eventua
, June 7, 2020 9:57 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD instructions
Ed, I too would be interested in your presentation from March 2017 SHARE ...
I can only imagine the barrage of knee-jerk responses you likely
encountered.
Sad
Ed, I too would be interested in your presentation from March 2017 SHARE ...
I can only imagine the barrage of knee-jerk responses you likely
encountered.
Sad but unfortunately predictable.
regards,
Kerry Liles
On Sun, 7 Jun 2020 at 18:23, Ed Jaffe wrote:
> On 6/7/2020 9:23 AM, Farley,
On 6/7/2020 9:23 AM, Farley, Peter x23353 wrote:
Is there any chance you could provide (maybe eventually in a SHARE session
presentation?) a set of good examples of using the vector instructions as you
say you do?
Peter,
There was a thread called "Count Words" into which at one time I
] on behalf
of Pieter Wiid [pw...@mweb.co.za]
Sent: Sunday, June 7, 2020 1:39 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD instructions
Do you mean conversion to printable hex, e.g. convert x'1234' to
x'f1f2f3f4'? These days, I use the TROT
/~smetz3
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Steve Smith [sasd...@gmail.com]
Sent: Sunday, June 7, 2020 1:40 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like
Something that I'd like to see inPoOps is an example of using UNPK
and TR to convert binary to hexadecimal.
You can't "convert" binary to hexadecimal, their bit patterns are the
same. If you're referring to displaying bytes' hexadecimal representation
in EBCDIC, then I'd say it's a bit late for
@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD
instructions
I thought that the descriptions of the vector instructions were a much
easier read than the, e.g., sort, transaction, instructions.
Something that I'd like to see inPoOps is an example of using UNPK and TR
7, 2020 10:48 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD instructions
On 6/7/2020 7:11 AM, Peter Relson wrote:
> That limitation is not the case for z/Architecture vector operations.
>
>
> I erred in writing that. Shmuel w
-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD instructions
On 6/7/2020 7:11 AM, Peter Relson wrote:
> That limitation is not the case for z/Architecture vector operations.
>
>
> I erred in writing that. Shmuel was of course correct.
On 6/7/2020 7:11 AM, Peter Relson wrote:
That limitation is not the case for z/Architecture vector operations.
I erred in writing that. Shmuel was of course correct. The "vector
register" is 128 bits (one quadword).
The extent of the "vectorization" depends on the size of the operands.
We
>>IBM has "Vector" instructions, but the size of a vector is limited to
one
>>quadword.
>That limitation is not the case for z/Architecture vector operations.
I erred in writing that. Shmuel was of course correct. The "vector
register" is 128 bits (one quadword).
The extent of the
ecture have something like the SIMD instructions
Caution! This message was sent from outside your organization.
Hi allI followed some advice her and yes, IBM has a pretty advanced SIMD
architecture from z13 onward. I am not sure about previous attempts, but the
current architecture seems to be
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Ze'ev Atlas [01774d97d104-dmarc-requ...@listserv.uga.edu]
Sent: Saturday, June 6, 2020 10:30 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like
Hi allI followed some advice her and yes, IBM has a pretty advanced SIMD
architecture from z13 onward. I am not sure about previous attempts, but the
current architecture seems to be pretty advanced.
BTW IBM claims that with 'arch(12)' COBOL. PL/I, C, Java will use that facility
at least
Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Peter Relson [rel...@us.ibm.com]
Sent: Saturday, June 6, 2020 9:06 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD instructions
IBM has "Vector" in
IBM has "Vector" instructions, but the size of a vector is limited to one
quadword.
That limitation is not the case for z/Architecture vector operations.
To the question of the subject, simply, yes. There are SIMD instructions.
Whether they are "the" SIMD instructions I don't know.
Peter
20 4:15 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD instructions
On 6/5/2020 12:15 PM, Seymour J Metz wrote:
> The S/370 PoOps mentions the vector facility and says "Vector operations are
> described in the publication
On 6/5/2020 12:15 PM, Seymour J Metz wrote:
The S/370 PoOps mentions the vector facility and says "Vector operations are
described in the publication IBM System/370 Vector Operations, SA22-7125."
You can download it from
r J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Dan Greiner [dan_grei...@att.net]
Sent: Friday, June 5, 2020 2:56 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z archite
Although it does actually access multiple data items, PERFORM LOCK OPERATION
(PLO) really doesn't qualify as a SIMD instruction (see my PLO screed below).
Seymour's reference to the Wikipedia page (https://en.wikipedia.org/wiki/SIMD)
is about as adequate a definition as any I've seen. As I
du/~smetz3
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Binyamin Dissen [bdis...@dissensoftware.com]
Sent: Friday, June 5, 2020 11:20 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something lik
Well, PLO is certainly an example.
But the relatively recent Transaction instructions greatly expand this.
On Fri, 5 Jun 2020 04:56:53 + Ze'ev Atlas
<01774d97d104-dmarc-requ...@listserv.uga.edu> wrote:
:>I admit being away from the mainframe for long time. Most of my work is on
z architecture have something like the SIMD instructions
I admit being away from the mainframe for long time. Most of my work is on
Solaris and Linux servers and therefore I do not code in Assembler. However, I
was active in porting a C library into classic z/OS.I was looking to do another
por
MBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Ze'ev Atlas [01774d97d104-dmarc-requ...@listserv.uga.edu]
Sent: Friday, June 5, 2020 12:56 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Does the z architecture have something like the SIMD instructions
I admit being away from the mainframe for long time.
List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Keven [k...@k3n.us]
Sent: Friday, June 5, 2020 1:42 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD instructions
Yes, z/Architecture has a number of SIMD instructions that operate
Yes, z/Architecture has a number of SIMD instructions that operate on
distinct data types. They are called vector instructions in mainframeze and
accordingly have mnemonics that all begin with V.
On Thu, Jun 4, 2020 at 11:57 PM
I admit being away from the mainframe for long time. Most of my work is on
Solaris and Linux servers and therefore I do not code in Assembler. However, I
was active in porting a C library into classic z/OS.I was looking to do another
port and stumbled upon the fact that that library has
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