Seymour is, of course, correct. 63 is the maximum valid characteristic.
I added this characteristic check at the last minute, and never bothered to
validate it. But for most current programming environments, a valid
characteristic limit will likely be much lower (unless you're actually dealing
h 5, 2022 5:03 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Fun with RXSBG
To paraphrase the Great and Powerful Oz, "Pay no attention to that man behind
the macro."
I had made a bunch of clean-up to this macro, renaming operands to be more
meaningful, and mistakenly sent out a part
To paraphrase the Great and Powerful Oz, "Pay no attention to that man behind
the macro."
I had made a bunch of clean-up to this macro, renaming operands to be more
meaningful, and mistakenly sent out a partially-updated copy. A fully-updated
copy is attached. I cleaned up the MEXIT and
The long-displacement facility has been part of the z/OS architecture level set
since z/OS 2.1 (including the "high performance" variant).
Mark B wrote:
If you need to test a facility bit in the range of 0-31 then use the list of
bits stored by the STORE FACILITY LIST instruction, which should
Hi Dan. I believe you have run into a couple of glitches in the
z390 assembler.
There is another issue with your WIF macro. The line:
LAY ,-1(,)
references variable symbol "" which is not defined.
The HLASM Language Reference states:
: Use the MEND statement to indicate the end of a
>> IHAFACL
uops - I spoke too soon
Am 04.03.22 um 19:44 schrieb Philippe Leite:
Macro IHAFACL
Regards,
Philippe Leite
LAB Services - IBM
and for the VSE people around
z/VSE stores facility indications beginning at V=R location 200 (C8 hex), so
you don't have to issue these instructions yourself.)
and to IBM people supporting this:
wouldn't it be nice to have a copy book such that you can simply code:
TM
VERY curious!
Of course, what Keith indicates is correct.
However, I'm currently limited to using the z390 assembler which produces the
expected code in the form I supplied. I don't know what HLASM would do with
this. Perhaps the MEND on the .SKIP_NFG label is only recognized if the macro
Should this:
.SKIP_NFG MEND
.BAD_C MNOTE 8,'C must be between 0 and 63.'
MEND
Be:
.SKIP_NFG MEXIT <==
.BAD_C MNOTE 8,'C must be between 0 and 63.'
MEND
Keith Moe
BMC Software (until May 31st)
On Friday, March 4, 2022, 03:10:53 PM PST, Dan Greiner
wrote:
More than one
More than one reader has contacted me requesting a copy of the "will it fit"
macro. It's pretty simple, as follows:
MACRO
WIF =1,=,=,=0,=,=
.*
.* Will It Fit?
.*
.* Given the following:
.* 1. Register "P" pointing to the next available location in an
.* integral buffer
On 3/4/2022 12:38 PM, Charles Mills wrote:
https://www-03.ibm.com/services/supline/products/ExtendedSupport/SystemZ_EOS.pdf
would seem to support my assertion that V2R2 is still in extended support,
until September 2023.
Haha! We don't count the three-year service extensions. We code to
] On
Behalf Of Ed Jaffe
Sent: Friday, March 4, 2022 12:28 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Long Displacement Facility (was: Fun with RXSBG)
On 3/4/2022 11:24 AM, Charles Mills wrote:
>
> ... My rule is to support the
> oldest version of z/OS still in extended support, which
On 3/4/2022 11:24 AM, Charles Mills wrote:
... My rule is to support the
oldest version of z/OS still in extended support, which I believe is
currently V2R2, and the oldest hardware that it supports, which is the z10.
The oldest supported OS is currently z/OS 2.3 and the oldest hardware it
customer surfaces who
is still running a z9? Do a custom build with ARCH(7).
Charles
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of Dave Clark
Sent: Friday, March 4, 2022 9:01 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Long Displa
> What is the macro to generate facility bit EQUs?
In TPF, it's IZARCH. For the z/OS macro, I'd have to phone a friend.
Actually I just did a Google search and found IHAPSAE, which itself points you
to IHAFACL.
- mb
Macro IHAFACL
Regards,
Philippe Leite
LAB Services - IBM
PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Long Displacement Facility (was: Fun with RXSBG)
> I went back and checked:
>
>
> o Long-displacement facility was first documented in SA22-7832-02
>
> o STFLE was first documented in SA22-7832-04
If you need to test a facilit
Yes, the R*SBG instructions are implemented in hardware. As I recall, they do
all the rotation, AND/XOR/OR/INSERT operation, and bit selection in a single
cycle.
Yes, it may cause a brief headache or spell of vertigo to get used to them.
Just remember that the second operand is first rotated,
- mb
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Ed Jaffe
Sent: Friday, March 4, 2022 12:53 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: [EXTERNAL] Re: Long Displacement Facility (was: Fun with RXSBG)
On 3/4/2022 9:31 AM, Dave Clark wrote:
> "IBM Mai
The long-displacement facility wasn't in the first z/Architecture machine, but
it followed soon thereafter. The first implementation was done in firmware —
primarily to allow IBM internal testing of new software. It was implemented in
hardware in any z/Architecture machine shipped after June
On 3/4/2022 9:31 AM, Dave Clark wrote:
"IBM Mainframe Assembler List" wrote on
03/04/2022 12:19:51 PM:
IIRC, STFLE is newer than the Long Displacement Facility. LOL
It wouldn't appear so. STFLE is facility 7 and LDF is facility 18.
I went back and checked:
o Long-displacement
Displacement Facility (was: Fun with RXSBG)
"IBM Mainframe Assembler List" wrote on
03/03/2022 05:22:52 PM:
> Not counting any branch following the determination, I had
> previously managed to trim this down to three instructions. For
> example, to determine if a prospective insertion
: Re: Fun with RXSBG
I have used similar logic to "round up" a length or address value
with the same architecturally integral constraints. In this old
code fragment GPR 15 contains the initial value to be adjusted.
Yes, the code needs to be tweaked for 64-bit values.
I guess if I hu
There is another way to test facility bits:
We can use field FLCFACL on PSA+x'C8'.
Regards,
Philippe Leite
LAB Services - IBM
On 3/4/2022 9:31 AM, Dave Clark wrote:
It wouldn't appear so. STFLE is facility 7 and LDF is facility 18.
Thanks for the clarification.
For the record, I would never, Ever, EVER test the long-displacement
facility bit and code two different paths in my code.
Doing so would be ridiculous...
"IBM Mainframe Assembler List" wrote on
03/04/2022 12:19:51 PM:
> IIRC, STFLE is newer than the Long Displacement Facility. LOL
It wouldn't appear so. STFLE is facility 7 and LDF is facility
18.
Sincerely,
Dave Clark
--
int.ext: 91078
direct: (937) 531-6378
home: (937) 751-3300
IIRC, STFLE is newer than the Long Displacement Facility. LOL
On 3/4/2022 9:16 AM, Philippe Leite wrote:
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
https://www.phoenixsoftware.com/
"IBM Mainframe Assembler List" wrote on
03/04/2022 12:06:26 PM:
> Every other box (z800, z900 GA2, and beyond)
> has had this feature standard. There is no reasonable
> rationale for not using this 22 year-old facility.
Thank you.
Sincerely,
Dave Clark
--
int.ext: 91078
direct:
On 3/4/2022 9:01 AM, Dave Clark wrote:
So, I looked at the original email again and did some research
into the LAY instruction. That is when I read about the Long Displacement
Facility (LDF) having to be installed for this instruction to work
(otherwise: operation exception). So,
"IBM Mainframe Assembler List" wrote on
03/03/2022 05:22:52 PM:
> Not counting any branch following the determination, I had
> previously managed to trim this down to three instructions. For
> example, to determine if a prospective insertion crosses a 4 K-byte
boundary:
> 1. LAY S,-1(L,P)
I have used similar logic to "round up" a length or address value
with the same architecturally integral constraints. In this old
code fragment GPR 15 contains the initial value to be adjusted.
Yes, the code needs to be tweaked for 64-bit values.
I guess if I hurt my head a bit I could use the
Dan,
thanks for sharing this. It is not an obvious coding technique.
With the semantics of code fragment explained, it does make sense & speed!
Kind regards,
Abe
===
Op 03/03/2022 om 23:22 schreef Dan Greiner:
> At the risk of sounding pedantic, it's no secret that I think the ROTATE THEN
> *
2022 5:22 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Fun with RXSBG
At the risk of sounding pedantic, it's no secret that I think the ROTATE THEN *
SELECTED BITS instructions are the sexiest ops in the architecture. A former
colleague (thanks Tim) recently reminded me of a really co
At the risk of sounding pedantic, it's no secret that I think the ROTATE THEN *
SELECTED BITS instructions are the sexiest ops in the architecture. A former
colleague (thanks Tim) recently reminded me of a really cool feature of the
RXSBG instruction that I used to improve a code fragment I've
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