Re: [beagleboard] PRU to DMA DDR caching issues

This training material from free-electron explains the cache effects and how to deal with them. Starting at slide 440 http://free-electrons.com/doc/training/linux-kernel/linux-kernel-slides.pdf Regards, John > On

Re: [beagleboard] PRU to DMA DDR caching issues

On 1/3/2016 10:58 AM, Thomas Köhler wrote: > Hello and thank you for the fast help. Here my answers for your comments: > > Unless you carefully write kernel code to treat your DDR memory buffer >> as DMA memory, you are almost certainly encountering caching effects. > > I thought to have this d

Re: [beagleboard] PRU to DMA DDR caching issues

I tracked down the issue a bit more: If I insert something between two reads of the DDR memory in my kernel module (I inserted a pr_info("test")), the value is refreshed. Maybe there is a possiblity to invalidate the cache? I will investigate more. Thanks -- For more options, visit http://be

Re: [beagleboard] PRU to DMA DDR caching issues

Hello and thank you for the fast help. Here my answers for your comments: Unless you carefully write kernel code to treat your DDR memory buffer > as DMA memory, you are almost certainly encountering caching effects. > I thought to have this done by getting the memory space from dma_alloc_coh

Re: [beagleboard] PRU to DMA DDR caching issues

On 1/3/2016 7:53 AM, Thomas Köhler wrote: > > Any help? So many thanks... I hope the problem can be understood. Unless you carefully write kernel code to treat your DDR memory buffer as DMA memory, you are almost certainly encountering caching effects. The ARM core reads the memory location once