[bug #51974] multiline (define/endef) containing target-specific assignments causes errors in /bin/sh

Follow-up Comment #4, bug #51974 (project make): I can't dispute Anonymous's advice, which was what I first thought of too, but I don't think it's clearly documented, neither in the GNU make manual nor in this vein of bugs, how makefile fragments like these are being parsed. Perhaps this example

[bug #51974] multiline (define/endef) containing target-specific assignments causes errors in /bin/sh

Follow-up Comment #3, bug #51974 (project make): As the other poster points out here, $(eval) was required to parse the result of the $(call) reference. This resolves this issue. Many thanks for your patience and advice.

[bug #51972] target-specific assignments and target definitions in multi-line variable definitions not handled correctly

Follow-up Comment #2, bug #51972 (project make): As a posted pointed out in #51972, $(eval) was required to parse the result of the $(call) reference. This resolves this issue. ___ Reply to this item at:

[bug #51974] multiline (define/endef) containing target-specific assignments causes errors in /bin/sh

Follow-up Comment #2, bug #51974 (project make): case 4: Makefile: define EXELNK1 $(1): OBJ1=xOBJ1 endef define EXELNK2 $(1): OBJ2=xOBJ2 endef $(call EXELNK1, utl1) $(call EXELNK2, utl1) utl1:;@echo "jfh1:pt1:$(OBJ1):$(OBJ2):" result of invoking make : works as expected ___

[bug #51973] variable value set by target-specific assignment not available to reference in multi-line variable definition

Follow-up Comment #2, bug #51973 (project make): Anonymous: You are indeed correct. I did not take that first expansion into account. I think your explanation resolves this issue. Many Thanks for this. ___ Reply to this item at:

[bug #51972] target-specific assignments and target definitions in multi-line variable definitions not handled correctly

Follow-up Comment #1, bug #51972 (project make): as mentioned in but 51972 by another poster, I had neglected to account for the initial expansion of $(OBJ1) in the definition of EXELNK here is a corrected version with that (hopefully) taken into account: case 1 : Makefile: define EXELNK #$(1):

[bug #51974] multiline (define/endef) containing target-specific assignments causes errors in /bin/sh

Follow-up Comment #1, bug #51974 (project make): This is also not a bug but rather an example where you need to use $(eval). I suggest you email your question about how to do what you want to the help-make mailing list: https://lists.gnu.org/mailman/listinfo/help-make instead of filing bugs.

[bug #51973] variable value set by target-specific assignment not available to reference in multi-line variable definition

Follow-up Comment #1, bug #51973 (project make): This makefile is behaving as defined: when $(call) is used, make performs a round of variable expansion on the value of the variable that is called. So, when you say $(call EXELNK,utl1) make expands that to utl1:;@echo "jfh1:pt1::" This expansi

[bug #51974] multiline (define/endef) containing target-specific assignments causes errors in /bin/sh

URL: Summary: multiline (define/endef) containing target-specific assignments causes errors in /bin/sh Project: make Submitted by: oss542 Submitted on: Sat 09 Sep 2017 08:45:50 PM UTC

[bug #51973] variable value set by target-specific assignment not available to reference in multi-line variable definition

URL: Summary: variable value set by target-specific assignment not available to reference in multi-line variable definition Project: make Submitted by: oss542 Submitted on: Sat 09 Sep 2017 08:30:55 PM

[bug #51972] target-specific assignments and target definitions in multi-line variable definitions not handled correctly

URL: Summary: target-specific assignments and target definitions in multi-line variable definitions not handled correctly Project: make Submitted by: oss542 Submitted on: Sat 09 Sep 2017 07:09:29 PM U