Re: [casper] Paper featuring CASPER hardware

We should remind people using CASPER hardware and libraries to cite: @INPROCEEDINGS{parsons_et_al2006, author = {{Parsons}, A. and {Backer}, D. and {Chang}, C. and {Chapman}, D. and {Chen}, H. and {Crescini}, P. and {de Jes us}, C. and {Dick}, C. and {Droz}, P. and {MacMahon}, D. and {Meder}, K

Re: [casper] casper Digest, Vol 32, Issue 1

Thanks for the reference I'll be sure to include it next time. Ben > > > @INPROCEEDINGS{parsons_et_al2006, > author = {{Parsons}, A. and {Backer}, D. and {Chang}, C. and > {Chapman}, D. and {Chen}, H. and {Crescini}, P. and {de Jes > us}, C. and {Dick}, C. and {Droz}, P. and {MacMahon}, D. an

[casper] 16 ports of ADC

Dear all: I am developing the 5G adc board. I am feeding 16 ports with 4 bits from ADC block to PFB and FFT after finished the test of 8 ports with 8 bits. In my previous test of 8 ports with 8 bits, i have compiled the 2K channels , 8 taps model successfully under normal Windows without 3GB opti

Re: [casper] 16 ports of ADC

hi homin, the 16 input FFT takes twice as many resources as an 8 input FFT. (the 16 input FFT has 16 parallel inputs so it can compute fft's at 16 times the fpga clock rate). this factor of two expansion in fpga resources is largely independent of the input data bit width, because almost a

Re: [casper] 16 ports of ADC

On Jul 7, 2010, at 21:05 , Dan Werthimer wrote: a few years ago, dave macmahon developed a "bit growth" biplex FFT that grows the number of bits each butterfly stage. eg: if you start with 4 bit data, and do a 1K FFT, you need 10 stages - the first stage is done with 4 bit precision, the