[casper] Building a new romfs

Hi all. We are going to attempt to update the standard romfs file system to support some additional stuff, like ssh and ???. Can someone give me a hint where to start? Or is there a better way? John

Re: [casper] Building a new romfs

On Wed, Apr 3, 2013 at 1:30 PM, John Ford wrote: > Hi all. We are going to attempt to update the standard romfs file system > to support some additional stuff, like ssh and ???. Can someone give me a > hint where to start? Well, the current romfs is mainly busybox (unmodified) and the katcp too

Re: [casper] PPS Sync on Toolflow 14.2

Does anybody have tested the sync line (pps) on the iadc of the new toolflow? Cheers, Andrea 2013/3/27 Andrea Mattana : > Hi all, > > I have tested the PPS over the sync0-1-2-3 output port of the iADC on > the new libraries with a very simple design and it seems that the > simulated PPS in input

Re: [casper] Building a new romfs

> On Wed, Apr 3, 2013 at 1:30 PM, John Ford wrote: >> Hi all. We are going to attempt to update the standard romfs file >> system >> to support some additional stuff, like ssh and ???. Can someone give me >> a >> hint where to start? > > Well, the current romfs is mainly busybox (unmodified) and

Re: [casper] PPS Sync on Toolflow 14.2

Hi, Andrea, Are you seeing problems in simulation or on actual hardware? I just made a quick test model and the sync input was propagated fine in simulation. Can you please explain your symptoms in more detail? Which version of mlib_devel are you using? What hardware platform are you target

[casper] To disable the PAR timing check:

Hi CASPER team, I am working with the iBOB FPGA at 250 MHz and two iADCs at 1000 GHz in a correlator project. In the compilation I have a timing error ERROR: 1 constraint not met. PAR could not meet all timing constrain

Re: [casper] To disable the PAR timing check:

Hi, Isaac, On Apr 3, 2013, at 3:45 PM, isaac...@caltech.edu wrote: > ERROR: 1 constraint not met. > > PAR could not meet all timing constraints. A bitstream will not be generated. > > I have read lot of documents and everybody said that is better solve the > problem adding delays and no disabl

Re: [casper] To disable the PAR timing check:

Hi Isaac An alternative route might be to compile at 200 MHz, and then open the design with PlanAhead. In Planahead you can then bump it up to 250 MHz, and try to compile from there, with much more fine-grain control. As a bonus, you'll also be able to see where it's failing timing. I believe

[casper] Debian Sqeeze and BORPH

Hi All, I've been playing around in my spare time trying to get Debian squeeze as the OS for a ROACH board (possibly a bad/pointless idea but hey). The issue I'm facing is that I need a kernel with UDEV support in and so launched into cross-compiling one. The problem is finding a BORPH patch tha