Try this:
source /opt/xilinx/14.3/ISE_DS/settings64.sh
then run the Xilinx Licence Config Manager
xlcm
From here you can choose your license file.
Wesley New
South African SKA Project
+2721 506 7365
www.ska.ac.za
On Thu, Sep 11, 2014 at 6:01 PM, Andrea Giachero
Hi Jason,br/br/Thanks very much.br/br/From your experiences, it seems
that both the fiber cables(multimode and single mode) and copper cables work
without configuring the PHY chips.br/Now I am testing a 10Gbe PHY(broadcom
BCM8747) expansion board connected to a FPGA board. System
Thanks Wesley for your answer.
I've followed your instruction:
- I've sourced the file;
- I've launched xlcm;
- Within xlcm I've tried to import the file Xilinx.lic using the button
Copy License (maybe is it not the proper way to import the License?)
The problem remains.
I apologize, It' s the
You should go to the 2nd tab Manage Licenses and the click on the Load
license button. This will tell you if the license is up to date and what
features it supports.
Hope this helps.
Wesley New
South African SKA Project
+2721 506 7365
www.ska.ac.za
On Fri, Sep 12, 2014 at 2:26 PM, Andrea
Hi,
Here is some clarification.
To be precise it seems impossible to calibrate the ADC board connected to
ZDOK0. (the other one than Ricardo mentioned). We have a script which tries to
calibrate the 4 cores inside the ADC board considering phase,amplitude and
offsets.
So what we do is
Dear Wesley,
I've fixed the problem. The license I have is a floating license so I need
to start the server on the machine for which the license was generated in
order to use this it.
The right command is:
lmgrd -c directory_license_file/xilinx.lic -l debug.log file
Thanks a lot for your help,
Dear all,
Hope this email finds you well.
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fast approaching. We have issued a draft agenda for this conference, which
you can view here http://hpsp2014.com/programme/main.
We are currently accepting late abstract submission
Hi, Tom,
I suggest using an oscilloscope to probe the SPI signals on the ZDOK0 ADC card
while writing to it. Based on this schematic:
https://casper.berkeley.edu/wiki/images/d/d2/Schematic_ADC_A2_5G_DMUX11.pdf
...it looks like you can probe them at CN5 or CN2 since you know the cards
Hi, Katty,
It looks like something is going wrong accessing the filesystem. Maybe it's
because of the ñ (n with a tilde over it) character in the path? Maybe the
path is just too long? Is the filesystem full? Is there a permissions problem?
Hope this helps,
Dave
On Sep 10, 2014, at 12:54
Hi Katty,
We've already spoken about this, but I thought I'd reply to the maillist in
case others with the same problem land here -- I've had this problem once
before, after checking the potential things Dave mentioned, I tried
restarting Matlab and the problem disappeared. Not really a solution,
Hi Tom (and Ricardo),
Thanks for the clarification, there was initially some question here as to
whether the “calibration” you refer to is MMCM clock calibration (which sets up
the ADC to ZDOK interface), or the quad core calibration. Based on your
response you mean quad core calibration. In
Hi Jonathan,
Sorry for the confusion, describing a problem like this is more difficult than
I first anticipated.
In our code basically the first things we do are:
- Doing the MMCM calibration:
opt1, glitches1 = adc.calibrate_mmcm_phase(fpga, 1, ['snapshot1',])
- Clear the OGP registers:
Hi Tom,
I think you need to use rww_tools.set_zdok(1) if you want to adjust ZDOK1,
and of course set it back to 0 when you want to adjust ZDOK0.
Best,
Rurik
On Fri, Sep 12, 2014 at 3:22 PM, Geelen, T.F.G. t.f.g.gee...@student.tue.nl
wrote:
Hi Jonathan,
Sorry for the confusion, describing a
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