[casper] about tut3 input ports

2014-10-21 Thread Wang Jinqing
Hi, I have download the tut3.mdl. And I found than for the inports,such as [quant_gain], the sysgen always give out such error "The input ports on this block must be driven by other Xilinx blocks" during simulation,see the appendix. So then I have change a xilinx constant block,it seem good. But

Re: [casper] about tut3 input ports

2014-10-21 Thread Vertatschitsch, Laura E.
Hi Oliver, It is a bit tough to tell where your signals are coming from with the picture you have included. I see a few issues though. When connecting Xilinx blocks to Simulink/Matlab blocks, you need to go through a special block. Connecting your delay blocks directly to a scope will cause err

Re: [casper] about tut3 input ports

2014-10-21 Thread Jack Hickish
Hi Oliver, I've just grabbed the latest tut3.slx from the casper tutorials repository. It looks a little different from the screenshot you sent -- are you using the latest one? The quant_gain "from" tag should be driven by a yellow software register block (in the model I just checked out, it's in

Re: [casper] Problem with the overflow

2014-10-21 Thread peter
Hi Laura, Joe ,& all, Thanks for your help first! I have learned the tutorial 2 before.Well I also find a weird thing that when I run tutorial 2, we can see the 10Gbe ports on the PowerPc through ssh.Well when I run a bof file and configure 10Gb block by ruby scripts,it can transition data packe

Re: [casper] Problem with the overflow

2014-10-21 Thread peter
Hi Joe, Thanks for your suggestions and your delicate test model! Follow your suggestion,I connect the system in a simple way，well, I have installed wireshark and change the MTU to 9000. But it is still no data comes. I forgot one thing to tell you that I have a model modified the PAPER's model

Re: [casper] Problem with the overflow

2014-10-21 Thread Kujawski, Joseph
Peter, At one point during my testing of this system, I did run into the problem that the 10GBe did not output data. The problem ended up being related to flow control into the 10GBe model. Since you indicate that for a frame size of 4096 the system works, this may be your issue. My fully imple

[casper] ADC 5g Errors

2014-10-21 Thread Amit Bansod
Dear All, While testing the design from 5g ADC clock (adc0_clk) at 100 MHz, I am getting the following errors: Constructing platform-level connectivity ... ERROR:EDK:4072 - INSTANCE: opb_adc5g_controller_0, PORT: adc0_dcm_locked - port is driven by a sourceless connector - /.../.../.../pro

Re: [casper] ADC 5g Errors

2014-10-21 Thread Primiani, Rurik
What version of mlib_devel are you using? On Tue, Oct 21, 2014 at 4:56 PM, Amit Bansod wrote: > Dear All, > > While testing the design from 5g ADC clock (adc0_clk) at 100 MHz, I am > getting the following errors: > > Constructing platform-level connectivity ... > ERROR:EDK:4072 - INSTANCE: opb_a

Re: [casper] Problem with the overflow

2014-10-21 Thread peter
Hi Joe, These are the models I used.A little mess ,Let me have a instruduction:tl is short for our project: tian lai roach2_fengine_tl8511.mdl are the model that can send packets to PC.Attached bof file is I compiled on my PC. paperfengine.rar contains model and .v .m .vhd .config file .This