And if you're wondering why it's only ever toggling between -1 and 0, it's
because most ADCs are biased centred around -0.5, not 0. This is so that
they're symmetrical in positive and negative swing (remember two's complement
for an 8 bit number will be -128 to +127). Some will let you adjust
On 9/20/2016 3:55 PM, David MacMahon wrote:
Hi Adam,
A little bit of noise (a step or several rms) is a cure for many ADC
ills, and is widely practiced under
the term "dithering". It's usually nicest if the dithering waveform can
be arranged to fall outside the
signal band of interest (yet
Hi Heystek,
You can also just delete the simulation blocks inside the ADC for the time
being. You don't need them to compile the design, only to be able to
simulate the ADC analog inputs properly.
Cheers
Jack
On Tue, 20 Sep 2016 at 13:32 Heystek Grobler
wrote:
> Hi
Hi Michael
Thanks for your help. I will try to obtain a license for the DSP System
Toolbox.
Have a wonderful evening
Heystek
On Tue, Sep 20, 2016 at 10:28 PM, Michael D'Cruze <
michael.dcr...@postgrad.manchester.ac.uk> wrote:
> Hi Heystek,
>
>
>
> You need the DSP System Toolbox
Hi Heystek,
You need the DSP System Toolbox unfortunately, in order to compile the ADC
blocks. This is typically a paid-for toolbox, though my local IT Services were
helpful and had a few spare server licences.
BW
Michael
From: Heystek Grobler [mailto:heystekgrob...@gmail.com]
Sent: 20
Hi Michael
This is the toolboxes that I have:
MATLAB Version: 8.0.0.783 (R2012b)
MATLAB License Number: 724504
Operating System: Linux 3.19.0-68-generic #76~14.04.1-Ubuntu SMP Fri Aug 12
11:46:25 UTC 2016 x86_64
Java Version: Java 1.6.0_17-b04 with Sun Microsystems Inc. Java HotSpot(TM)
64-Bit
hi adam,
the effect you are seeing is visible on many adc's - some digital noise
gets into the analog input,
and is often easy to see when there is no signal input, especially when the
adc's DC offset
happens to lie near the boundry of two ADC steps (then any noise will cause
the ADC to toggle).
Hi, Adam,
I haven't looked at the spectral content of a terminated input before so I
don’t have any comparative results, but I think the spikes you are seeing are
caused by mismatched gains and/or offsets of the ADC’s interleaved cores (I
think there are a total of 8 cores, also called
Heystek,
Do you have the DSP System Toolbox installed in Matlab?
Michael
Good evening
I am trying to do the casper tutorial nr 3 on Ubuntu 14.04 LTS with ISE
14.7.
When I say update model in Simulink or run System generator I get the
following error:
Failed to load library 'dspsigops' referenced by 'tut3/adc/Downsamplei0'
Caused by:
Unable to load block diagram
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