[casper] Intel/Altera 64GSps DAC/ADC

Hi All, I know we are all using Xilinx devices, and CASPER is beginning to check out the RFSoC devices. Intel have just announced 64GSps converters on their new FPGAs http://www.intel.com/analogfpga I am sure this will be vaporware for a while, however, it is interesting to see that Intel tar

RE: [EXTERNAL] Re: [casper] Intel/Altera 64GSps DAC/ADC

, February 3, 2021 1:36 PM To: casper@lists.berkeley.edu Subject: [EXTERNAL] Re: [casper] Intel/Altera 64GSps DAC/ADC This is very interesting news, David. Thanks for sharing it. On Tue, Feb 2, 2021, 10:24 PM 'Hawkins, David W (US 334B)' via casper@lists.berkeley.edu<

RE: [EXTERNAL] [casper] Intel/Altera 64GSps DAC/ADC

r this great tip. Can Robert ask about ballpark pricing for this Intel SoC? Best wishes, Jonathan Weintroub On Feb 3, 2021, at 4:40 PM, 'Hawkins, David W (US 334B)' via casper@lists.berkeley.edu<mailto:casper@lists.berkeley.edu> mailto:casper@lists.berkeley.edu>> wrote:

RE: [casper] System Verilog

Hi All, Cliff Cummings still does training. We have had him come to JPL to give classes in UVM. He has a good teaching style. I have his contact details if anyone is interested. (His company is now part of Paradigm-Works, another company I have used). Once you dig into UVM, you’ll find that th

RE: [casper] System Verilog

Sorry, I missed the rest of a comment: >> there is “standard” way of doing things … The Mentor way, the Cadence way, the Aldec way, … you get the drift. Mentor’s Verification Academy has a lot of good resources for learning SystemVerilog, UVM, Code Coverage. On the subject of Code Coverage, Ra

RE: [EXTERNAL] Re: [casper] Inverting the Polyphase Filter Bank

Hi Nikhil, >> perfect reconstruction / inversion is not possible because the information >> in the Nyquist bin is thrown away? Correct, but imperfect reconstruction should work. A real-valued signal has a Hermitian spectrum, and an FFT has a cyclic response. That results in two things; *

RE: [EXTERNAL] Re: [casper] Inverting the Polyphase Filter Bank

grateful for the many helpful and prompt responses! Reconstructing imperfectly, Nikhil On Fri, 4 Feb 2022 at 11:26, 'Hawkins, David W (US 334B)' via casper@lists.berkeley.edu<mailto:casper@lists.berkeley.edu> mailto:casper@lists.berkeley.edu>> wrote: Hi Nikhil, >&

[casper] Electronics and FPGA Engineering positions at Caltech and JPL

Hi All, Caltech just contacted me about this newly opened Electronics Design Engineer position at LIGO lab at Caltech: https://phf.tbe.taleo.net/phf03/ats/careers/v2/viewRequisition?org=CALTECH&cws=37&rid=8530

RE: [EXTERNAL] [casper] Advice for radio astronomy components student project

Hi Colm, >> I am looking for components that easy to interface with via python In that case, I would recommend investing in: https://www.realdigital.org/hardware/rfsoc-4x2 Students can still learn about RF mixers, power amplifiers, and LNAs, and they would use the RFSoC board as a high-end sig

RE: [EXTERNAL] [casper] Re: Advice for radio astronomy components student project

Hi Colm, >> Maybe using the RF SoC for just generating/re-sampling the baseband signal >> might be straight forward enough for this project... Right. I was suggesting thinking of the RFSoC as “just” a piece of test equipment. If the PYNQ layer abstracts the fact that it is an FPGA, and the stu

RE: [EXTERNAL] [casper] Advice for radio astronomy components student project {External} {External}

n-boards-kits/adalm-pluto.html* > eb-buy__;Iw!!PvBDto6Hs4WbVuu7!N6uHI-iIm-d9M5Ld4KA5p-aexPfELTxCrE8PP6C2 > qpJHYYGKbC-F-iIZlizyL4CPkuhGqsdZ6p4AxFT7yqShIEE708sJgZanLS3i$ > > It would be great if someone could port the CASPER tools to this device. > > >> On Aug 16, 2023, a

RE: [EXTERNAL] [casper] state of the art single bit correlators

Hi Neil, For your 1-bit correlation, are you going to implement a lag correlator? If so, then your logic could be: * ISERDES operating at 1Gbps sampling the complex-valued baseband * 4-bits at 250MHz or 8-bits at 125MHz inside the FPGA * Logic to perform 4-bits or 8-bits digital dela

RE: [EXTERNAL] [casper] Low cost phase noise analysis

Hi Karl, >> Thanks in advance to anyone whose interest is piqued enough to respond. My interest in piqued ... I'm in the process of measuring phase noise using a Rhode&Swartz on some EVMs and custom designs: 1. Texas Instruments DAC39RF10 DAC (I have rev1 and rev2 of their space parts) 2. Tex

RE: [EXTERNAL] [casper] Low cost phase noise analysis

asper@lists.berkeley.edu On Behalf Of Karl Warnick Sent: Tuesday, August 20, 2024 2:10 PM To: 'Hawkins, David W (US 334B)' via casper@lists.berkeley.edu Subject: Re: [EXTERNAL] [casper] Low cost phase noise analysis Hi Dave, thanks for responding. I looked into the Wenzel referen