Re: [casper] PlanAhead to a working bof

There's also a UCF yellow block that lets you add ucf files to your design (much like the PCORE yellow block). I think there's also a method to inject ucf constraints via an environment variable (I think you could find this in the git log somewhere). Cheers, Jack On Wed, 3 Feb 2016 at 10:31

Re: [casper] PlanAhead to a working bof

Hi, Johnathon, > On Feb 3, 2016, at 2:26 AM, Gard, Johnathon D. > wrote: > > There are options in the PlanAhead bitfile generation and I could have those > wrong. This could be very likely. The bitgen options that the CASPER flow uses are in

Re: [casper] PlanAhead to a working bof

Thanks Jack and David Both of those are what I am looking for. The PlanAhead output a .bin not .bit and the ucf file yellow block. One other question that has come up while looking at the ucf file is that xilinx by default groups all of the clocks in the design into one clock group. This

[casper] PlanAhead to a working bof

Hello Casperites, ROACH2, MATLAB 2012a (I think), ISE 14.7, Ubuntu 14.04 LTS I am working on compiling firmware without timing errors. More like ignoring static configuration register timing errors. Any rate, I have been pulling my design into PlanAhead successfully and applying some DSP