Hi Ryan,
I could get rid of those errors but the tool had hard time in placing
with huge setup timing errors. How much utilization is good to set on
p-blocks ?
Currently, I had 60-70% for different components.
Cheers,
Amit
On 05-Nov-15 9:46 AM, Ryan Monroe wrote:
> Hi Amit,
>
> FYI, I am
Assuming that the pblock is not overlapping with any other pblocks, and
that you have not constrained any other resources in the pblock, I have
used 99% of the resources in a pblock (simply made it as small as
possible). The trouble comes into play when there are resources which
are not in
Hi Amit,
FYI, I am CC'ing the CASPER list on all of these emails, so that they
can be searchable for people in the future.
The placements I gave you were for my personal design, and may not work
for yours. When choosing pblock size, be sure to look at the pblock
utilization in planahead.
np! the 10gbe core wasn't really intended to run at fast clock rates.
Be sure to constrain it to the east-ish side of the chip, this is
probably either a
1. device utilization issue (you are trying to do too much stuff on the
chip), or
2. placement issue (probably this)-- the tools are
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