Re: [simh] RSTS processor identification

2021-03-08 Thread Johnny Billquist via cctalk
On 2021-03-08 15:40, Paul Koning wrote: On Mar 7, 2021, at 6:42 PM, Johnny Billquist wrote: On 2021-03-07 23:00, Paul Koning wrote: On Mar 5, 2021, at 9:02 PM, Johnny Billquist wrote: On 2021-03-06 02:33, Paul Koning wrote: ... Anyway, in RSX, when running DDCMP on the serial port,

Re: [simh] RSTS processor identification

2021-03-08 Thread Paul Koning via cctalk
> On Mar 5, 2021, at 9:02 PM, Johnny Billquist wrote: > > On 2021-03-06 02:33, Paul Koning wrote: > ... >> The explanation I heard for the slow J-11 clock is that the original J-11 >> spec called for it to operate at 20 MHz. When Harris failed to deliver and >> the max useable clock speed

Re: [simh] RSTS processor identification

2021-03-08 Thread Paul Koning via cctalk
> On Mar 5, 2021, at 9:15 PM, Chris Zach via cctalk > wrote: > >>> Can't run split I/D space on any version of P/OS. Neither does it support >>> supervisor mode. Also, the J11 on the Pro-380 is running a bit on the slow >>> side. Rather sad, but I guess they didn't want to improve the

Re: [simh] RSTS processor identification

2021-03-08 Thread Paul Koning via cctalk
> On Mar 7, 2021, at 6:42 PM, Johnny Billquist wrote: > > > > On 2021-03-07 23:00, Paul Koning wrote: >>> On Mar 5, 2021, at 9:02 PM, Johnny Billquist wrote: >>> >>> On 2021-03-06 02:33, Paul Koning wrote: > ... >>> I would have liked better comms. The USART has such a tiny

Re: [simh] RSTS processor identification

2021-03-07 Thread Johnny Billquist via cctalk
On 2021-03-07 23:00, Paul Koning wrote: On Mar 5, 2021, at 9:02 PM, Johnny Billquist wrote: On 2021-03-06 02:33, Paul Koning wrote: ... I would have liked better comms. The USART has such a tiny FIFO that you can't run it at higher than 9600 bps even with the J-11 CPU. At least

Re: [simh] RSTS processor identification

2021-03-07 Thread Paul Koning via cctalk
> On Mar 5, 2021, at 9:02 PM, Johnny Billquist wrote: > > On 2021-03-06 02:33, Paul Koning wrote: >>> ... > >> I would have liked better comms. The USART has such a tiny FIFO that you >> can't run it at higher than 9600 bps even with the J-11 CPU. At least not >> with RSTS; perhaps a

Re: [simh] RSTS processor identification

2021-03-06 Thread Peter Coghlan via cctalk
Johnny Billquist wrote: On 2021-03-06 02:33, Paul Koning wrote: The explanation I heard for the slow J-11 clock is that the original J-11 spec called for it to operate at 20 MHz. When Harris failed to deliver and the max useable clock speed ended up to be 18 MHz, most designs had no trouble.

Re: [simh] RSTS processor identification

2021-03-05 Thread Glen Slick via cctalk
On Fri, Mar 5, 2021 at 7:05 PM Chris Zach via cctalk wrote: > > > There seem to be a great many models of Unibus and Qbus multi-port async > > serial boards, which present different register-level interfaces, e.g. for > > Unibus, DH11, DHU11, DJ11, DM11, DZ11 . Which ones are considered "best", >

Re: [simh] RSTS processor identification

2021-03-05 Thread Johnny Billquist via cctalk
On 2021-03-06 03:22, Eric Smith wrote: On Fri, Mar 5, 2021 at 6:33 PM Paul Koning via cctalk mailto:cctalk@classiccmp.org>> wrote: I would have liked better comms.  The USART has such a tiny FIFO that you can't run it at higher than 9600 bps even with the J-11 CPU.  At least not

Re: [simh] RSTS processor identification

2021-03-05 Thread Chris Zach via cctalk
There seem to be a great many models of Unibus and Qbus multi-port async serial boards, which present different register-level interfaces, e.g. for Unibus, DH11, DHU11, DJ11, DM11, DZ11 . Which ones are considered "best", for each bus, for use with a multitasking OS like RSTS/E or RSX-11M+?

Re: [simh] RSTS processor identification

2021-03-05 Thread Eric Smith via cctalk
On Fri, Mar 5, 2021 at 6:33 PM Paul Koning via cctalk wrote: > I would have liked better comms. The USART has such a tiny FIFO that you > can't run it at higher than 9600 bps even with the J-11 CPU. At least not > with RSTS; perhaps a lighter weight OS can do better. The printer port is >

Re: [simh] RSTS processor identification

2021-03-05 Thread Chris Zach via cctalk
Can't run split I/D space on any version of P/OS. Neither does it support supervisor mode. Also, the J11 on the Pro-380 is running a bit on the slow side. Rather sad, but I guess they didn't want to improve the support chips on the Pro, which limited speed, and they didn't want to start having

Re: [simh] RSTS processor identification

2021-03-05 Thread Johnny Billquist via cctalk
On 2021-03-06 02:33, Paul Koning wrote: On Mar 5, 2021, at 7:22 PM, Johnny Billquist via cctalk wrote: ... Maybe this weekend I'll hack that SSD floppy thingie and load up the P/OS 3.2 disks to see how that works. Can't run split I/D space on any version of P/OS. Neither does it

Re: [simh] RSTS processor identification

2021-03-05 Thread Paul Koning via cctalk
> On Mar 5, 2021, at 7:22 PM, Johnny Billquist via cctalk > wrote: > > ... >> Maybe this weekend I'll hack that SSD floppy thingie and load up the P/OS >> 3.2 disks to see how that works. > > Can't run split I/D space on any version of P/OS. Neither does it support > supervisor mode.

Re: [simh] RSTS processor identification

2021-03-05 Thread Johnny Billquist via cctalk
On 2021-03-06 01:14, Chris Zach wrote: Ah ok. For some reason I always thought the 23 could only run M, which is still a fine platform. I'd be amazed if they got all the extra cool features like disk caching working without I/D. Officially, you need the 11/23+. The original 11/23 is not

Re: [simh] RSTS processor identification

2021-03-05 Thread Chris Zach via cctalk
Ah ok. For some reason I always thought the 23 could only run M, which is still a fine platform. I'd be amazed if they got all the extra cool features like disk caching working without I/D. But when I think about it, it makes sense: P/OS is basically M+ all the way and runs on the Pro/350.

Re: [simh] RSTS processor identification

2021-03-05 Thread Johnny Billquist via cctalk
The 11/23 is officially supported, and does indeed lack I/D space (also true of the 11/24). Which implies that split I/D space is not actually a requirement for RSX-11M-PLUS. That would also be clear by reading the SPD. However, officially, there is a requirement for 22-bit addressing. Which

Re: [simh] RSTS processor identification

2021-03-05 Thread Chris Zach via cctalk
How can you run m+ on an 11/23 or a 40? I thought it needed I/d space to run thus I can see it on a 45. On March 5, 2021 6:02:45 PM EST, Johnny Billquist via cctalk wrote: >Nice writeup, Paul. And very interesting. > >Just in case anyone wonder about RSX, here is how it's done in M+: > >1.

Re: [simh] RSTS processor identification

2021-03-05 Thread Johnny Billquist via cctalk
Nice writeup, Paul. And very interesting. Just in case anyone wonder about RSX, here is how it's done in M+: 1. Test if SYSID register exists If SYSID register exists: 2. Test if high bit of KISDR0 can be set and read back If high bit can be set and read back => 11/74 CPU If