dnpetrov-sc created this revision.
dnpetrov-sc added reviewers: craig.topper, anton-afanasyev, asi-sc.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck,
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craig.topper added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCV.td:637
+def : ProcessorModel<"scr1-min", SCR1Model,
+ [FeatureRV32E, FeatureStdExtC],
+ [TuneNoDefaultUnroll]>;
Shouldn't this also need Feature32B
craig.topper added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVSchedSCR1.td:208
+}
\ No newline at end of file
Add new line
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dnpetrov-sc added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCV.td:637
+def : ProcessorModel<"scr1-min", SCR1Model,
+ [FeatureRV32E, FeatureStdExtC],
+ [TuneNoDefaultUnroll]>;
craig.topper wrote:
> Shouldn't this
dnpetrov-sc updated this revision to Diff 480352.
dnpetrov-sc edited the summary of this revision.
dnpetrov-sc added a comment.
- fixed new line at end-of-file in RISCVSchedSCR1.td;
- dropped scr1-min (RV32E unsupported).
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craig.topper added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCV.td:637
+def : ProcessorModel<"scr1-min", SCR1Model,
+ [FeatureRV32E, FeatureStdExtC],
+ [TuneNoDefaultUnroll]>;
dnpetrov-sc wrote:
> craig.topper w
jrtc27 added inline comments.
Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:22
PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
+PROC(SCR1_BASE, {"scr1-base"}, FK_NONE, {"rv32ic"})
+PROC(SCR1_MAX, {"scr1-max"}, FK_NONE, {"rv32imc"})
Alphabeti
craig.topper added a comment.
Should the names be prefixed with "syntacore-". I assume there could be an
SCR2, etc. in the future?
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anton-afanasyev added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVSchedSCR1.td:14
+// This model covers SCR1_CFG_RV32IMC_MAX configuration (scr1-max).
+// SCR1_CFG_RV32EC_MIN (scr1-min) and SCR1_CFG_RV32IC_BASE (scr1-base)
+// configurations have essentially same sche
dnpetrov-sc updated this revision to Diff 482449.
dnpetrov-sc marked an inline comment as done.
dnpetrov-sc added a comment.
- Added syntacore prefix
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dnpetrov-sc updated this revision to Diff 482455.
dnpetrov-sc added a comment.
- Fixes
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clang/test/Driver/riscv-cpus.c
clang/test/Misc/target-inva
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.
LGTM
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___
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc86a878e8995: [RISCV] Add Syntacore SCR1 CPU model (authored
by dnpetrov-sc, committed by anton-afanasyev).
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