@@ -82,6 +88,13 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
return is64Bit() ? 2047 : 0;
}
+ bool isRegisterReserved(MCPhysReg PhysReg) const {
+if (PhysReg >= SP::G0 && PhysReg <= SP::O7)
+ return ReserveRegister[PhysReg - SP::G0];
https://github.com/s-barannikov approved this pull request.
https://github.com/llvm/llvm-project/pull/74927
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koachan wrote:
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https://github.com/llvm/llvm-project/pull/74927
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@@ -98,9 +96,34 @@ BitVector SparcRegisterInfo::getReservedRegs(const
MachineFunction ) const {
for (unsigned n = 0; n < 31; n++)
Reserved.set(SP::ASR1 + n);
+ for (size_t i = 0; i < SP::IntRegsRegClass.getNumRegs() / 4; ++i) {
+// Mark both single register and
@@ -29,6 +29,12 @@ namespace llvm {
class StringRef;
class SparcSubtarget : public SparcGenSubtargetInfo {
+ // Reserve*Register[i] - *#i is not available as a general purpose register.
+ BitVector ReserveGRegister;
koachan wrote:
It should be possible,
@@ -29,6 +29,12 @@ namespace llvm {
class StringRef;
class SparcSubtarget : public SparcGenSubtargetInfo {
+ // Reserve*Register[i] - *#i is not available as a general purpose register.
+ BitVector ReserveGRegister;
s-barannikov wrote:
Can this be a single
@@ -80,6 +86,11 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
return is64Bit() ? 2047 : 0;
}
+ bool isGRegisterReserved(size_t i) const { return ReserveGRegister[i]; }
+ bool isORegisterReserved(size_t i) const { return ReserveORegister[i]; }
+ bool
@@ -98,9 +96,34 @@ BitVector SparcRegisterInfo::getReservedRegs(const
MachineFunction ) const {
for (unsigned n = 0; n < 31; n++)
Reserved.set(SP::ASR1 + n);
+ for (size_t i = 0; i < SP::IntRegsRegClass.getNumRegs() / 4; ++i) {
+// Mark both single register and
@@ -1125,6 +1130,10 @@ Register SparcTargetLowering::getRegisterByName(const
char* RegName, LLT VT,
.Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7",
SP::G7)
.Default(0);
+ const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
+ if
@@ -1125,6 +1130,10 @@ Register SparcTargetLowering::getRegisterByName(const
char* RegName, LLT VT,
.Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7",
SP::G7)
.Default(0);
+ const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
+ if
https://github.com/koachan updated
https://github.com/llvm/llvm-project/pull/74927
>From 956ca7e210a438caac7c5dda8c9945305a53de39 Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Wed, 29 Nov 2023 08:08:29 +0700
Subject: [PATCH 1/3] [SPARC] Support reserving arbitrary general purpose
registers
@@ -1125,6 +1130,10 @@ Register SparcTargetLowering::getRegisterByName(const
char* RegName, LLT VT,
.Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7",
SP::G7)
.Default(0);
+ const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
+ if
@@ -1125,6 +1130,10 @@ Register SparcTargetLowering::getRegisterByName(const
char* RegName, LLT VT,
.Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7",
SP::G7)
.Default(0);
+ const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
+ if
https://github.com/koachan updated
https://github.com/llvm/llvm-project/pull/74927
>From 956ca7e210a438caac7c5dda8c9945305a53de39 Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Wed, 29 Nov 2023 08:08:29 +0700
Subject: [PATCH 1/2] [SPARC] Support reserving arbitrary general purpose
registers
@@ -98,9 +98,52 @@ BitVector SparcRegisterInfo::getReservedRegs(const
MachineFunction ) const {
for (unsigned n = 0; n < 31; n++)
Reserved.set(SP::ASR1 + n);
+ for (size_t i = 0; i < SP::IntRegsRegClass.getNumRegs() / 4; ++i) {
+// Mark both single register and
@@ -5730,6 +5730,18 @@ def mvis3 : Flag<["-"], "mvis3">,
Group;
def mno_vis3 : Flag<["-"], "mno-vis3">, Group;
def mhard_quad_float : Flag<["-"], "mhard-quad-float">,
Group;
def msoft_quad_float : Flag<["-"], "msoft-quad-float">,
Group;
+foreach i = {1-7} in
@@ -1125,6 +1130,19 @@ Register SparcTargetLowering::getRegisterByName(const
char* RegName, LLT VT,
.Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7",
SP::G7)
.Default(0);
+ const SparcRegisterInfo *MRI = Subtarget->getRegisterInfo();
@@ -1125,6 +1130,19 @@ Register SparcTargetLowering::getRegisterByName(const
char* RegName, LLT VT,
.Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7",
SP::G7)
.Default(0);
+ const SparcRegisterInfo *MRI = Subtarget->getRegisterInfo();
+ unsigned
koachan wrote:
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koachan wrote:
> Doesn’t the ABI require you to emit magic STT_REGISTER or whatever they are
> symbols to mark this?
Yeah, when targeting 64-bit and we're *not* reserving %g2, %g3, %g6, or %g7
then we should emit STT_SPARC_REGISTER entries for those registers.
However, currently we never emit
llvmbot wrote:
@llvm/pr-subscribers-clang
@llvm/pr-subscribers-clang-driver
Author: Koakuma (koachan)
Changes
This adds support for marking arbitrary general purpose registers - except for
those with special purpose (G0, I6-I7, O6-O7) - as reserved, as needed by some
software like the
https://github.com/koachan created
https://github.com/llvm/llvm-project/pull/74927
This adds support for marking arbitrary general purpose registers - except for
those with special purpose (G0, I6-I7, O6-O7) - as reserved, as needed by some
software like the Linux kernel.
>From
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