[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added a comment. @craig.topper Thanks! @asb Hi Alex, I'd like to get another approval from you. Are there any more concerns? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401 _

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added a comment. In D70401#4657101 , @jrtc27 wrote: > In D70401#4657098 , @jrtc27 wrote: > >> GCC only ever defines __riscv_32e > > Hm, seems the comments about __riscv_32e were from months ago, ignore them i

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added a comment. In D70401#4655408 , @asb wrote: > First of all, thank you to everyone who has been trying to nudge this forward > and apologies it must have been a frustrating experience. > > I appreciate there are users who want to see this and I

[PATCH] D122629: [RISCV] Add index check for vset/vget

pcwang-thead created this revision. pcwang-thead added reviewers: luismarques, asb, craig.topper, khchen. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, arphaman, the_o, bruceho

[PATCH] D122629: [RISCV] Add index check for vset/vget

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGcebbfd3d2555: [RISCV] Add index check for vset/vget (authored by pcwang-thead). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION h

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

pcwang-thead added a comment. In D129824#3699911 , @kito-cheng wrote: > Just realized the problem is trying to fixed the default value of `-mabi=`, > currently `clang -target riscv32-elf -march=rv64gc > -mabi=lp64d`/`riscv32-elf-clang -march=rv64gc -ma

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead commandeered this revision. pcwang-thead edited reviewers, added: zixuan-wu; removed: pcwang-thead. pcwang-thead added a comment. Herald added a subscriber: arichardson. Herald added a project: All. In D70401#3250049 , @khchen wrote: > 1. plea

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead added a comment. In D70401#3395340 , @kito-cheng wrote: > Last LLVM sync-up call @asb has raise the discussion about the ILP32E issue, > so here is note from my site: > > RISC-V psABI doc still say "we don't guarantee the stability of `ILP32

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead added a comment. Herald added a subscriber: StephenFan. In D70401#3391561 , @khchen wrote: > I found > https://github.com/llvm/llvm-test-suite/blob/main/SingleSource/UnitTests/2003-05-26-Shorts.c > result is mismatched with gcc's (-march=rv3

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

pcwang-thead updated this revision to Diff 423555. pcwang-thead added a comment. - Disable sized deallocation for Apple targets. - Update tests and don't use `-fno-sized-deallocation` any more. - With one exception: `clang/test/SemaCXX/builtin-operator-new-delete.cpp`, which will generate two n

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

pcwang-thead added a comment. In D112921#3453114 , @MaskRay wrote: > Beside the concern raised by platform maintainers: the cc1 default switch > part should be made separately from the patch. > This makes revert easy and leaves fewer churn to the test su

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

pcwang-thead added a comment. In D112921#3462592 , @Mordante wrote: > I didn't look at the code, but I have some hints how we can test libc++. Thanks! I ran tests with no error occurred on my local machine and I really want to know how to test it! Rep

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

pcwang-thead added inline comments. Comment at: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp:17 +// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}} #include Mordante wrote: >

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

pcwang-thead added a comment. In D112921#3473022 , @ldionne wrote: > (BTW I strongly support this patch, I just think we should do it properly on > all platforms from the start :-) I couldn't agree with you more, but I have no idea how to implement it.

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

pcwang-thead added a comment. In D112921#3474964 , @rjmccall wrote: > Hmm. Allowing a version on `-stdlib` is intuitively appealing, but I'm not > sure it actually gives us the information we need. As I recall, `-stdlib` > selects the high-level stdli

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

pcwang-thead updated this revision to Diff 425443. pcwang-thead added a comment. Herald added subscribers: dexonsmith, arichardson. - Add handling of Apple targets. - Update libc++ tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ ht

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

pcwang-thead created this revision. pcwang-thead added reviewers: asb, luismarques, kito-cheng, craig.topper. Herald added subscribers: sunshaoce, VincentWu, luke957, jeroen.dobbelaere, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, t

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

pcwang-thead updated this revision to Diff 430246. pcwang-thead added a comment. Herald added a subscriber: MaskRay. Add a test to check RVV type aliases. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125765/new/ https://reviews.llvm.org/D125765 F

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

pcwang-thead added a comment. Besides, should we add `vread_csr` and `vwrite_csr` like what in GCC ? These two functions doesn't exist in RVV intrinsics doc, is it a historical problem? R

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

pcwang-thead updated this revision to Diff 430285. pcwang-thead added a comment. Move to separate RVVHeader. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125765/new/ https://reviews.llvm.org/D125765 Files: clang/include/clang/Basic/riscv_vector

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

pcwang-thead created this revision. pcwang-thead added reviewers: asb, luismarques, kito-cheng, craig.topper. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, M

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

pcwang-thead added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1511 +__extension__ extern __inline +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +unsigned long vread_csr(enum RVV_CSR csr) { craig.topper wrote: > D

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

pcwang-thead added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1512 +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +unsigned long vread_csr(enum RVV_CSR csr) { + unsigned long rv = 0; craig.topper wrote: > pcwang-

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

pcwang-thead updated this revision to Diff 430567. pcwang-thead added a comment. Add double underscore to all variables. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125875/new/ https://reviews.llvm.org/D125875 Files: clang/include/clang/Basic/

[PATCH] D125947: [RISCV] Add default ABI for archs with only F extension

pcwang-thead created this revision. pcwang-thead added reviewers: asb, craig.topper, benshi001, luismarques, jrtc27. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, bruceh

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

pcwang-thead added a comment. In D125765#3524456 , @khchen wrote: > I think we have no consensus in > https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/18#issuecomment-817890161, > and most people disagree the current naming, > maybe we need to

[PATCH] D125947: [RISCV] Add default ABI for archs with only F extension

pcwang-thead added a comment. In D125947#3525537 , @jrtc27 wrote: > It's currently this way in order to be compatible with GCC. Changing this > requires consensus from both toolchains to ensure compatibility is preserved. > See https://github.com/riscv-

[PATCH] D125947: [RISCV] Add default ABI for archs with only F extension

pcwang-thead added a comment. In D125947#3525539 , @jrtc27 wrote: > Also, the tests where you have codegen changes rather than preserving a > soft-float ABI should probably be put up for review separately by adding an > explicit hard single-float ABI, a

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

pcwang-thead updated this revision to Diff 431654. pcwang-thead added a comment. - Rebase. - move tests to `test/CodeGen/RISCV/rvv-intrinsics`. - Update functions' attrs. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125875/new/ https://reviews.llv

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added a comment. @asb @kito-cheng @jrtc27 @craig.topper Can I commit this since the support of RVE is really of great importance for some downstreams? If there are some problems, I will be there to fix them. If we all agree with this, I will mark RVE as exprimental and commit it then. R

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead marked an inline comment as done. pcwang-thead added a comment. In D70401#3873347 , @luojia wrote: > Hello! Any further updates to this patch? It seems like all the inline > comments have been resolved. We have done some works in this patch

[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

pcwang-thead created this revision. pcwang-thead added reviewers: kito-cheng, craig.topper, asb. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosb

[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

pcwang-thead added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:2190 CmdArgs.push_back("-tune-cpu"); -CmdArgs.push_back(A->getValue()); +if (strcmp(A->getValue(), "native") == 0) + CmdArgs.push_back(Args.MakeArgString(llvm::sys::getHostCPUN

[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

pcwang-thead updated this revision to Diff 472228. pcwang-thead added a comment. - Add release note. - Add tests to `riscv-cpus.c`. - Add `getRISCVTargetCPU`. - Make diagnostic more exact for `native`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D1

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

pcwang-thead marked an inline comment as done. pcwang-thead added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:411 // implemented such that the stack will always be 16 byte aligned. unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * L

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

pcwang-thead added a comment. In D112921#4003939 , @Romain-Geissler-1A wrote: > Hi, > > Is there any update about this ? Currently, no. If someone is interesting in this, please feel free to commandeer. :-) Repository: rG LLVM Github Monorepo CHANG

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added a comment. In D137517#4009175 , @fpetrogalli wrote: > @pcwang-thead, I addressed some of your comments. > > The value of `EnumFeatures` is now computed dynamicaly from the > `Features` field of the `Processor` class. Thanks! That soun

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added a comment. In D137517#4012307 , @craig.topper wrote: > In D137517#4012298 , @pcwang-thead > wrote: > >> In D137517#4009175 , @fpetrogalli >> wrote: >

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added a comment. > @pcwang-thead, may I ask you to own these further optimisations of the > generative process, and submit a patch for it after the current patch lands? > I'd happily review it! > > The reason I am asking this is because the current patch is mostly dealing > with ma

[PATCH] D137838: [Support] Move TargetParsers to new component

pcwang-thead added inline comments. Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:10 +/// \file +/// This header is deprecated in favour of `llvm/Support/RISCVISAInfo.h`. +/// zixuan-wu wrote: > I think there is a typo that should be 'in favour of > `llvm

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:568 -def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>; -def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; +class RISCVProcessorModelPROCRISCVProcessorModel? RISCVP

[PATCH] D141032: [Clang][RISCV] Expose vlenb to vread_csr

pcwang-thead added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1559 __asm__ __volatile__ ("csrw\tvcsr, %z0" : : "rJ"(__value) : "memory"); break; } Should we report errors if `vwrite_csr(RVV_VLENB, some_value)`? Repos

[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

pcwang-thead added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1565 + unsigned long __rv = 0; + __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory"); + return __rv; Inline assembly may not be elegant since it can't be o

[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

pcwang-thead accepted this revision. pcwang-thead added a comment. This revision is now accepted and ready to land. The code is OK to me, except that a few small comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1579 + llvm::Function *F = +CGM.getIntr

[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

pcwang-thead added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1579 + llvm::Function *F = +CGM.getIntrinsic(llvm::Intrinsic::read_register, {Int64Ty}); + return Builder.CreateCall(F, Metadata); craig.topper wrote: > pc

[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

pcwang-thead added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c:33 +// RV32: !2 = !{i32 1, !"SmallDataLimit", i32 0} +// RV32: !3 = !{!"clang version 16.0.0 (g...@github.com:llvm/llvm-project.git e80f0cc0a318fe8473ba460d6a16166d81b303b1)"} +// RV3

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added a comment. Thanks! I think it's a great improvement! Comment at: llvm/lib/Target/RISCV/RISCV.td:509 -def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>; -def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; +class RISCVProcess

[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

pcwang-thead added a comment. Thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136930/new/ https://reviews.llvm.org/D136930 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm

[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

This revision was automatically updated to reflect the committed changes. Closed by commit rG7c50bcb44170: [RISCV] Support -mcpu/mtune=native (authored by pcwang-thead). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136930/new/ https://reviews.llvm.

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added a comment. A rough implementation just for your reference: diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp index 47e11b9a1eab..f91f969c2b17 100644 --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ b/llvm/

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

pcwang-thead added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125875/new/ https://reviews.llvm.org/D125875 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.o

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

This revision was automatically updated to reflect the committed changes. Closed by commit rGaebe24a856d2: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h (authored by pcwang-thead). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125875/new/ h

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

pcwang-thead updated this revision to Diff 436344. pcwang-thead added a comment. Add `REQUIRES` to tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125875/new/ https://reviews.llvm.org/D125875 Files: clang/include/clang/Basic/riscv_vector.td

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG93b4a41b5510: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h (authored by pcwang-thead). Repository: rG LLVM Github Monorepo CHANGES SINC

[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff destination isn't null

pcwang-thead added a comment. Ping. Any comments? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126461/new/ https://reviews.llvm.org/D126461 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https:

[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff destination isn't null

pcwang-thead added a comment. In D126461#3596769 , @khchen wrote: > Could you please purpose this implement in rvv-intrinsc-doc first? > I think this feature need to have discussion because store to nullptr is UB > but we are making it as defined behavio

[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff destination isn't null

pcwang-thead added a comment. In D126461#3597862 , @craig.topper wrote: > In D126461#3596761 , @reames wrote: > >> Despite the comments above, the purpose of this patch remains unclear. >> >> Per the draft spec,

[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff new_vl output pointer isn't null

pcwang-thead abandoned this revision. pcwang-thead added a comment. After discussion, we decide to not change anything right now. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126461/new/ https://reviews.llvm.org/D126461 __

[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

pcwang-thead created this revision. pcwang-thead added reviewers: khchen, kito-cheng, craig.topper, asb. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, bruce

[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

pcwang-thead added a comment. In D126461#3541577 , @craig.topper wrote: > What if it isn't known to be null at compile time but gets optimized to it. Thanks, I haven't thought it clearly and I just wanted to solve found bugs. :-) I changed it to generat

[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

pcwang-thead added a comment. Is there an easy way to update tests? Or we need to add passthru operands manually? I will appreciate it if you can tell me. :-) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125323/new/ https://reviews.llvm.org/D1253

[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

pcwang-thead added a comment. In D125323#3550307 , @khchen wrote: > In D125323#3549794 , @pcwang-thead > wrote: > >> Is there an easy way to update tests? Or we need to add passthru operands >> manually? I will

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

pcwang-thead added a comment. Gentle ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125875/new/ https://reviews.llvm.org/D125875 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists

[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

pcwang-thead added a comment. Ping. :-) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126461/new/ https://reviews.llvm.org/D126461 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.ll

[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

pcwang-thead added a comment. In D126461#3565305 , @khchen wrote: >> Store to null will be changed to unreachable, so all instructions after >> vleff intrinsic call will be deleted and it causes runtime errors. If >> destination to store is null, we won

[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

pcwang-thead added a comment. In D126461#3566626 , @khchen wrote: > IMO, if I'm an user, I would not expected intrinsic function will generate > the condition code to impact the performance, maybe we need to raise a issue > in rvv-intrinsic-doc. > maybe

[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

pcwang-thead updated this revision to Diff 435454. pcwang-thead edited the summary of this revision. pcwang-thead added a comment. Add null pointer checking for vlsegff. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126461/new/ https://reviews.llvm

[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff destination isn't null

pcwang-thead updated this revision to Diff 435466. pcwang-thead added a comment. Update test `rvv-intrinsics-overloaded/vlsegff.c`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126461/new/ https://reviews.llvm.org/D126461 Files: clang/include/c

[PATCH] D154576: [RISCV] RISCV vector calling convention (1/2)

wangpc added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVCallingConv.td:52 // Same as CSR_Interrupt, but including all 64-bit FP registers. def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, (sequence "F%u_D

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

wangpc updated this revision to Diff 541374. wangpc added a comment. Update ReleaseNotes. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155456/new/ https://reviews.llvm.org/D155456 Files: clang/docs/ReleaseNotes.rst clang/include/clang/Driver/

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 541415. wangpc added a comment. Rebase and fix libcxx tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/unittests/FindTargetTest

[PATCH] D155647: [RISCV] Add C intrinsics for scalar crypto

wangpc added a comment. Can we run mem2reg pass in RUNs just like RVV tests (maybe another cleanup patch)? I think there are a lot of noises in CHECKS. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155647/new/ https://reviews.llvm.org/D155647 ___

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

wangpc planned changes to this revision. wangpc added a comment. I don't have any thoughts on this patch now. In D125765#4511637 , @eopXD wrote: > Sorry for the late reply, I missed this in may mails. > > I see that the motivation start from where you sp

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

wangpc added inline comments. Comment at: clang/test/Driver/riscv-features.c:41 +// DEFAULT: "-target-feature" "-unaligned-scalar-mem" +// DEFAULT-NOT: "-target-feature" "+unaligned-scalar-mem" + arichardson wrote: > This looks a bit fragile, can we just check al

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 543828. wangpc added a comment. Rebase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/unittests/FindTargetTests.cpp clang-tools-e

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. In D112921#4529182 , @Mordante wrote: > I noticed some of the CI jobs are still failing with the patch, I didn't look > into them. I don't think they are related to this patch, so I rebased again. If still failed, I will try to

[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies

wangpc added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948 - // TODO: The 'q' extension requires rv64. - // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'. I think the comment is outdated here. `E` can be combined with all

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. In D112921#4532378 , @Mordante wrote: > In D112921#4530916 , @wangpc wrote: > >> In D112921#4529182 , @Mordante >> wrote: >> >>> I noticed some of

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 544640. wangpc added a comment. - Remove usages of `-fsized-deallocation` in some tests. - Rebase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. In D112921#4536088 , @Mordante wrote: > In D112921#4535716 , @wangpc wrote: > >> In D112921#4532378 , @Mordante >> wrote: >> >>> In D112921#453091

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 545006. wangpc added a comment. - Rebase. - Unsupport clang-18. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/unittests/FindTargetT

[PATCH] D149017: [RISCV] Rewrite all found class-based subroutines to functions

wangpc added a comment. In D149017#4579179 , @zixuan-wu wrote: > Is it going to commit? This patch is stuck since the patch to support function/lambda is WIP (I may not work on it recently). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST AC

[PATCH] D157680: [X86]Support options -mno-gather -mno-scatter

wangpc added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:7527 + // -mno-gather, -mno-scatter support + if (Args.hasArg(options::OPT_mno_gather)) { +CmdArgs.push_back("-target-feature"); Put these in `clang/lib/Driver/ToolChains/Arch/X

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 550983. wangpc marked 10 inline comments as done. wangpc added a comment. - Rebase. - Update tests, remove clang-17. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Fi

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. In D112921#4595918 , @Mordante wrote: > In D112921#4594092 , @wangpc wrote: > >> - Rebase. >> - Update tests, remove clang-17. > > The removal of the markers in the libc++ tests breaks thes

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 551367. wangpc added a comment. Rebase and fix failed tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/unittests/FindTargetTest

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 551702. wangpc added a comment. - Rebase. - Remove abilist changes. - Add clang-18. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/u

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 551890. wangpc added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/unittests/FindTargetTests.cpp clang-tools-ex

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc added a comment. @ldionne Sorry for bothering, what do you think about landing this patch? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 ___ cfe-commit

[PATCH] D155647: [RISCV] Add C intrinsics for scalar bitmanip and crypto

wangpc accepted this revision. wangpc added a comment. This revision is now accepted and ready to land. Herald added a subscriber: sunshaoce. LGTM if the proposal is merged. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155647/new/ https://reviews.

[PATCH] D142144: [RISCV][Driver] Add -mrvv-vector-bits= option similar to -msve-vector-bits=

wangpc added inline comments. Herald added subscribers: jobnoorman, sunshaoce. Comment at: clang/test/Driver/riscv-rvv-vector-bits.c:43 +// RUN: %clang -c %s -### --target=riscv64-linux-gnu -march=rv64gcv \ +// RUN: -mrvv-vector-bits=64 2>&1 | FileCheck --check-prefix=CHECK-BAD

[PATCH] D151730: [RISCV] Support target attribute for function

wangpc added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:376 + + if (AttrString.startswith("+") || AttrString.startswith("-")) { +// EXTENSION like arch=+v,+zbb,-c `-` is removed in https://github.com/riscv-non-isa/riscv-c-api-doc

[PATCH] D156693: [clang][ASTImporter]Skip check depth of friend template parameter

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG07ab5140080e: [clang][ASTImporter]Skip check depth of friend template parameter (authored by jcsxky, committed by wangpc). Repository: rG LLVM Git

[PATCH] D156779: [RISCV] Use correct LMUL!=1 types for __attribute__((riscv_rvv_vector_bits(N)))

wangpc created this revision. wangpc added a reviewer: craig.topper. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc2

[PATCH] D156779: [RISCV] Use correct LMUL!=1 types for __attribute__((riscv_rvv_vector_bits(N)))

This revision was automatically updated to reflect the committed changes. Closed by commit rGedb5056300bb: [RISCV] Use correct LMUL!=1 types for __attribute__((riscv_rvv_vector_bits(N))) (authored by wangpc). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

wangpc updated this revision to Diff 546760. wangpc added a comment. Rebase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 Files: clang-tools-extra/clangd/unittests/FindTargetTests.cpp clang-tools-e

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

wangpc added a comment. Thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155456/new/ https://reviews.llvm.org/D155456 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/c

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

wangpc updated this revision to Diff 546772. wangpc added a comment. Rebase since `ReleaseNotes.rst` is changed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155456/new/ https://reviews.llvm.org/D155456 Files: clang/docs/ReleaseNotes.rst clan

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG23ce5368409c: [RISCV] Support -m[no-]strict-align options (authored by wangpc). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION h

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