On Thu, Oct 9, 2008 at 11:23 PM, Ward Vandewege [EMAIL PROTECTED] wrote:
On Thu, Oct 09, 2008 at 10:20:29PM +0200, Peter Stuge wrote:
Roman Yeryomin wrote:
what could be the problem?
My 1c has the serial port on a superio chip. I recognize this
problem from other boards. I also have
On Fri, Oct 10, 2008 at 12:46 AM, Corey Osgood [EMAIL PROTECTED]wrote:
On Thu, Oct 9, 2008 at 9:57 PM, Corey Osgood [EMAIL PROTECTED]wrote:
On Thu, Oct 9, 2008 at 7:56 PM, ron minnich [EMAIL PROTECTED] wrote:
exciting! I am looking forward to this one!
Problems already:
[EMAIL
On 10.10.2008 09:25, Corey Osgood wrote:
On Fri, Oct 10, 2008 at 12:46 AM, Corey Osgood [EMAIL PROTECTED]wrote:
On Thu, Oct 9, 2008 at 9:57 PM, Corey Osgood [EMAIL PROTECTED]wrote:
On Thu, Oct 9, 2008 at 7:56 PM, ron minnich [EMAIL PROTECTED] wrote:
exciting! I am looking
On Fri, Oct 10, 2008 at 10:04 AM, Roman Yeryomin [EMAIL PROTECTED] wrote:
I don't understand - serial works fine for me on the 2c3. Getting serial to
work was in fact the 'hardest' part of doing the 2c3 port based on the .1c
code, because of the absense of the winbond superio chip. It required
On Fri, Oct 10, 2008 at 10:04:45AM +0300, Roman Yeryomin wrote:
On Thu, Oct 9, 2008 at 11:23 PM, Ward Vandewege [EMAIL PROTECTED] wrote:
On Thu, Oct 09, 2008 at 10:20:29PM +0200, Peter Stuge wrote:
Roman Yeryomin wrote:
what could be the problem?
My 1c has the serial port on a
On Fri, Oct 10, 2008 at 12:02:17PM +0300, Roman Yeryomin wrote:
On Fri, Oct 10, 2008 at 10:04 AM, Roman Yeryomin [EMAIL PROTECTED] wrote:
I don't understand - serial works fine for me on the 2c3. Getting serial to
work was in fact the 'hardest' part of doing the 2c3 port based on the .1c
On Thursday 09 October 2008 22:44:20 Roman Yeryomin wrote:
On Thu, Oct 9, 2008 at 10:33 PM, ron minnich [EMAIL PROTECTED] wrote:
lar z /tmp/d.bin
lar -z bios.bin
cool :)
I think it should be in --help also!
How about including -z option to lar --help?
I think it will be useful for users
The main reason I would like to use a custom BIOS in my laptop is so
that I could run a processor that I am not sure the stock BIOS would
support and so that I could set a custom clock frequency on it.
My laptop is an HP hdx9494. Its based on the Intel PM 965 chipset
(Socket 775) and runs higher
Hi,
I accidentally was sent the wrong board (MSI K9AG Neo2-Digital instead
of the ASUS M2A-MX I ordered), so I'm sending it back. But while I had
my hands on it I gathered some info:
- AMD RS690 / SB600 chipset
- Soldered SOIC/SPI ROM chip (MX25L8005)
- Fintek F71882FG Super I/O
Here's a
On Fri, Oct 10, 2008 at 4:14 AM, Roman Yeryomin [EMAIL PROTECTED]wrote:
On Thursday 09 October 2008 22:44:20 Roman Yeryomin wrote:
On Thu, Oct 9, 2008 at 10:33 PM, ron minnich [EMAIL PROTECTED] wrote:
lar z /tmp/d.bin
lar -z bios.bin
cool :)
I think it should be in --help also!
On 10.10.2008 06:46, Corey Osgood wrote:
On Thu, Oct 9, 2008 at 9:57 PM, Corey Osgood [EMAIL PROTECTED] wrote:
On Thu, Oct 9, 2008 at 7:56 PM, ron minnich [EMAIL PROTECTED] wrote:
exciting! I am looking forward to this one!
Problems already:
[EMAIL
if anybody wants to dash this off today, we need it.
The utillity would read the routing registers in k8 north and print
out what they mean. You get this info from config space.
I wrote one of these for the ultra 40 project and then lost it when I
shipped the machine back to xtreme data ...
I can easily read from the chip on the board.
But, hot plugging is not working out.
The basic part is a 49lf008a; putting in 49lf008 or 49lf080 just gets
reads back of ff.
Ideas welcome. Do BIos saviours exist any more?
ron
--
coreboot mailing list: coreboot@coreboot.org
On Fri, Oct 10, 2008 at 12:25 AM, Corey Osgood [EMAIL PROTECTED] wrote:
Sorry for the mailbox flooding, I'm slowly learning to step back and look at
things before jumping to conclusions. Geode and i586 also have ROM_CODE_SEG
defined, this didn't, that's why the jump was going to nowhere. Do
I can easily read from the chip on the board.
But, hot plugging is not working out.
The basic part is a 49lf008a; putting in 49lf008 or 49lf080 just gets
reads back of ff.
Is the difference FWH vs LPC?
from SST's site:
8 Mbit Firmware Hub SST49LF008A
8 Mbit LPC Flash SST49LF080A
On Friday 10 October 2008 15:47:22 Ward Vandewege wrote:
On Fri, Oct 10, 2008 at 10:04:45AM +0300, Roman Yeryomin wrote:
On Thu, Oct 9, 2008 at 11:23 PM, Ward Vandewege [EMAIL PROTECTED] wrote:
On Thu, Oct 09, 2008 at 10:20:29PM +0200, Peter Stuge wrote:
Roman Yeryomin wrote:
what
On Fri, Oct 10, 2008 at 07:17:48PM +0300, Roman Yeryomin wrote:
Yes, it does work for me. At 115200n8 of course. Note that the alix ships
with tinybios set to a (much) lower speed.
yes, I know, it's 38400, but I use 115200 for your image -- it's hard not to
notice this :)
OK, cool, just
On Friday 10 October 2008 15:51:13 Ward Vandewege wrote:
On Fri, Oct 10, 2008 at 12:02:17PM +0300, Roman Yeryomin wrote:
On Fri, Oct 10, 2008 at 10:04 AM, Roman Yeryomin [EMAIL PROTECTED]
wrote:
I don't understand - serial works fine for me on the 2c3. Getting
serial to work was in fact
On Fri, Oct 10, 2008 at 07:35:09PM +0300, Roman Yeryomin wrote:
Note that that image I gave you will not send out much on serial, I reduced
the coreboot log level because the alix.2c3 does not have a cmos battery
and thus will always default to the hardcoded log level when powered on -
and
On Friday 10 October 2008 19:33:39 Ward Vandewege wrote:
I use voyage linux (http://linux.voyage.hk), which is basically Debian
+ some specifics for embedded systems. It specifically supports alix,
and it really easy to install onto a CF card from your pc.
hmm... will look at it
I
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer uwe checked in revision 3645 to
the coreboot source repository and caused the following
changes:
Change Log:
Add Fintek F71882FG support (trivial).
Tested on actual hardware, the MSI K9AG Neo2-Digital
On Fri, Oct 10, 2008 at 9:52 AM, Ward Vandewege [EMAIL PROTECTED] wrote:
That is a bit odd. It's entirely possible that coreboot is not doing
something that busybox requires, but that is not required by init/(m)getty on
debian. I'm not sure what that would be though :/
interrupt setup?
ron
ron minnich wrote:
I can easily read from the chip on the board.
But, hot plugging is not working out.
The basic part is a 49lf008a; putting in 49lf008 or 49lf080 just gets
reads back of ff.
Ideas welcome. Do BIos saviours exist any more?
But you can read out the original ROM file? If you
Roman Yeryomin wrote:
T0:23:respawn:/sbin/getty -L ttyS0 115200
I should try getty from busybox (I use /bin/login now)...
Here's what I use:
s0:12345:respawn:/sbin/agetty -n -l /bin/bash 115200 ttyS0 ansi
(that way, no login prompt)
//Peter
--
coreboot mailing list:
On Fri, Oct 10, 2008 at 11:40 AM, ron minnich [EMAIL PROTECTED] wrote:
On Fri, Oct 10, 2008 at 12:25 AM, Corey Osgood [EMAIL PROTECTED]
wrote:
Sorry for the mailbox flooding, I'm slowly learning to step back and look
at
things before jumping to conclusions. Geode and i586 also have
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer uwe checked in revision 3645 to
the coreboot source repository and caused the following
changes:
Change Log:
Add Fintek F71882FG support (trivial).
Tested on actual hardware, the MSI K9AG Neo2-Digital
On Fri, Oct 10, 2008 at 9:00 AM, Corey Osgood [EMAIL PROTECTED] wrote:
Once CAR's running, the rest of initram should be a breeze (and I can
actually do it up right, too!). The hardest part after that will be the dts
given an lspci I can give you an initial dts.
how about we start committing
Author: ward
Date: 2008-10-10 20:06:56 +0200 (Fri, 10 Oct 2008)
New Revision: 3646
Modified:
trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb
Log:
Enable vga bios by default on Tyan s2881. The board has an onboard ati rage XL.
This is a trivial patch.
Signed-off-by: Ward Vandewege
Hello,
when the logo was announced this summer it came with a rather strict
license that made it difficult-to-impossible for many to use.
Everyone agreed that this was bad, and we've finally changed the
license to something that will hopefully be easier to work with.
The license is heavily
On Fri, Oct 10, 2008 at 5:18 PM, ron minnich [EMAIL PROTECTED] wrote:
if anybody wants to dash this off today, we need it.
The utillity would read the routing registers in k8 north and print
out what they mean. You get this info from config space.
Could you explain what you call routing
On Fri, Oct 10, 2008 at 8:16 PM, Peter Stuge [EMAIL PROTECTED] wrote:
Roman Yeryomin wrote:
T0:23:respawn:/sbin/getty -L ttyS0 115200
I should try getty from busybox (I use /bin/login now)...
Here's what I use:
s0:12345:respawn:/sbin/agetty -n -l /bin/bash 115200 ttyS0 ansi
(that way,
On Wed, Oct 01, 2008 at 02:57:03PM -0600, Marc Jones wrote:
Resubmitting this patch. I think I worked out all the corner cases and
made it a little easier to understand.
This will probably break the build on some boards, e.g.:
Processing mainboard/asus/a8v-e_se (i386: ok)
Creating config
On Thu, Oct 9, 2008 at 4:21 PM, Peter Stuge [EMAIL PROTECTED] wrote:
Corey Osgood wrote:
Worst part is that my stock BIOS chip doesn't write quite right, it
took at least a few dozen attempts to get the stock BIOS back on
it. Something wrong with the timing
Which flash part and chipset
Hi Folks,
I have an AMD LX800 custom board running coreboot v2 and linux just fine.
We may now want to use coreboot to boot a Windows2000/XP. I have traced
through the FAQ/lists and assembled this
1) ALDO embedded with CorebootV3
2) Merged in the LX VGA ROM file (64KB) into the blob/vsa
On Fri, Oct 10, 2008 at 11:37 AM, Vincent Legoll
[EMAIL PROTECTED] wrote:
On Fri, Oct 10, 2008 at 5:18 PM, ron minnich [EMAIL PROTECTED] wrote:
if anybody wants to dash this off today, we need it.
The utillity would read the routing registers in k8 north and print
out what they mean. You get
On Fri, Oct 10, 2008 at 9:36 PM, Roman Yeryomin [EMAIL PROTECTED] wrote:
On Fri, Oct 10, 2008 at 8:16 PM, Peter Stuge [EMAIL PROTECTED] wrote:
Roman Yeryomin wrote:
T0:23:respawn:/sbin/getty -L ttyS0 115200
I should try getty from busybox (I use /bin/login now)...
Here's what I use:
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer uwe checked in revision 3645 to
the coreboot source repository and caused the following
changes:
Change Log:
Add Fintek F71882FG support (trivial).
Tested on actual hardware, the MSI K9AG Neo2-Digital
Author: jcrouse
Date: 2008-10-10 21:54:41 +0200 (Fri, 10 Oct 2008)
New Revision: 246
Modified:
buildrom-devel/packages/filo/filo.mk
buildrom-devel/packages/libpayload/conf/defconfig
buildrom-devel/packages/libpayload/conf/defconfig.geode
Uwe Hermann wrote:
On Wed, Oct 01, 2008 at 02:57:03PM -0600, Marc Jones wrote:
Resubmitting this patch. I think I worked out all the corner cases and
made it a little easier to understand.
This will probably break the build on some boards, e.g.:
Processing mainboard/asus/a8v-e_se (i386: ok)
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer ward checked in revision 3646 to
the coreboot source repository and caused the following
changes:
Change Log:
Enable vga bios by default on Tyan s2881. The board has an onboard ati rage XL.
This is a
On Fri, Oct 10, 2008 at 1:10 PM, Steve Spano [EMAIL PROTECTED] wrote:
Hi Folks,
I have an AMD LX800 custom board running coreboot v2 and linux just fine.
We may now want to use coreboot to boot a Windows2000/XP. I have traced
through the FAQ/lists and assembled this
1) ALDO embedded with
Author: cozzie
Date: 2008-10-10 22:37:02 +0200 (Fri, 10 Oct 2008)
New Revision: 914
Modified:
coreboot-v3/superio/fintek/f71805f/f71805f.h
coreboot-v3/superio/fintek/f71805f/superio.c
Log:
Fix (read: hide) some warning on F71805F until the port gets completed
(trivial).
Signed-off-by:
Author: stuge
Date: 2008-10-10 22:43:17 +0200 (Fri, 10 Oct 2008)
New Revision: 3647
Modified:
trunk/util/flashrom/flashrom.c
Log:
flashrom: Check that a filename was specified also when using force read
Signed-off-by: Peter Stuge [EMAIL PROTECTED]
Acked-by: Peter Stuge [EMAIL PROTECTED]
Add ICH10 support to flashrom.
The ICH9 and ICH10 data sheets are identical regarding FWH/SPI flash
interfaces, so this just adds the required PCI IDs.
Signed-off-by: Carl-Daniel Hailfinger [EMAIL PROTECTED]
Acked-by: Peter Stuge [EMAIL PROTECTED]
Index: flashrom-ich10/chipset_enable.c
--
Ward Vandewege [EMAIL PROTECTED]
Free Software Foundation - Senior Systems Administrator
The Tyan s2881 ships with a 512KB rom chip. For LAB we require an 1MB chip, but
the VGA rom address is hardcoded assuming the 512KB chip.
This patch
a) bumps up the v2 revision to 3646 which actually
On 10.10.2008 22:54, Carl-Daniel Hailfinger wrote:
Add ICH10 support to flashrom.
The ICH9 and ICH10 data sheets are identical regarding FWH/SPI flash
interfaces, so this just adds the required PCI IDs.
Signed-off-by: Carl-Daniel Hailfinger [EMAIL PROTECTED]
Acked-by: Peter Stuge [EMAIL
On 10/10/08 17:12 -0400, Ward Vandewege wrote:
--
Ward Vandewege [EMAIL PROTECTED]
Free Software Foundation - Senior Systems Administrator
The Tyan s2881 ships with a 512KB rom chip. For LAB we require an 1MB chip,
but
the VGA rom address is hardcoded assuming the 512KB chip.
This
On Fri, Oct 10, 2008 at 03:22:13PM -0600, Jordan Crouse wrote:
On 10/10/08 17:12 -0400, Ward Vandewege wrote:
--
Ward Vandewege [EMAIL PROTECTED]
Free Software Foundation - Senior Systems Administrator
The Tyan s2881 ships with a 512KB rom chip. For LAB we require an 1MB chip,
Author: ward
Date: 2008-10-10 23:28:58 +0200 (Fri, 10 Oct 2008)
New Revision: 247
Added:
buildrom-devel/packages/coreboot-v2/patches/s2881-lab-vga-fix.patch
Modified:
buildrom-devel/config/platforms/tyan-s2881.conf
buildrom-devel/packages/coreboot-v2/coreboot.inc
Log:
The Tyan s2881
Author: ward
Date: 2008-10-10 23:43:25 +0200 (Fri, 10 Oct 2008)
New Revision: 249
Modified:
buildrom-devel/bin/construct-rom.sh
Log:
Remove unnecessary bash-ism.
This is a trivial patch.
Signed-off-by: Ward Vandewege [EMAIL PROTECTED]
Acked-by: Ward Vandewege [EMAIL PROTECTED]
Modified:
Author: ward
Date: 2008-10-10 23:38:45 +0200 (Fri, 10 Oct 2008)
New Revision: 248
Modified:
buildrom-devel/packages/coreboot-v2/coreboot.inc
Log:
Remove debug code that was accidentally committed in r247.
This is a trivial patch.
Signed-off-by: Ward Vandewege [EMAIL PROTECTED]
Acked-by:
On Fri, Oct 10, 2008 at 11:36 AM, Roman Yeryomin [EMAIL PROTECTED] wrote:
It's now obvious that somebody (coreboot or busybox's /bin/login) not
doing something...
Where this issue should be addressed?
OK, there was for some time a weird problem in linux w.r.t. com ports.
This was years ago.
Add support for Cache-as-RAM on VIA C7 processors in v3.
Finally.
Thanks to Jason Zhao we got a skeleton CAR code for VIA C7 based on
older v2 code.
I cleaned it up, modified the v3 stage0 code in lots of places as
preparation for this and believe this is mostly merge-ready.
Thanks to Bari Ari
On Fri, Oct 10, 2008 at 11:29 AM, Peter Stuge [EMAIL PROTECTED] wrote:
Everyone agreed that this was bad, and we've finally changed the
license to something that will hopefully be easier to work with.
Thank you.
I have shown the logo to many people and they all like the logo quite
a bit.
Acked-by: Ronald G. Minnich [EMAIL PROTECTED]
Note that it still won't build if CONFIG_XIP_ROM_{SIZE,BASE} are set
but I still don't know why we even have CONFIG_XIP in v3 :-)
We can fix this but I'd like to start getting via bits into v3 asap.
ron
--
coreboot mailing list:
Author: hailfinger
Date: 2008-10-11 02:07:36 +0200 (Sat, 11 Oct 2008)
New Revision: 915
Added:
coreboot-v3/arch/x86/via/
coreboot-v3/arch/x86/via/stage0.S
Modified:
coreboot-v3/arch/x86/Kconfig
coreboot-v3/arch/x86/Makefile
Log:
Add support for Cache-as-RAM on VIA C7 processors in v3.
Is that like what you had in mind:
~ # ./AMDK8MemMap.py
0x00: Ox1022 - Device ID
0x02: Ox1101 - Vendor ID
0x04: Ox - Status
0x06: Ox - Command
0x08: Ox00 - Base CLass Code
0x09: Ox00 - Subclass Code
0x0a: Ox00 - Program Interface
0x0b: Ox06 -
On the same machine:
~ # lspci -vvvxxx -s 0:0:18.1
00:18.1 Host bridge: Advanced Micro Devices [AMD] K8
[Athlon64/Opteron] Address Map
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr-
On Fri, Oct 10, 2008 at 5:06 PM, Vincent Legoll
[EMAIL PROTECTED] wrote:
Is that like what you had in mind:
This is 18:1 right?
~ # ./AMDK8MemMap.py
0x00: Ox1022 - Device ID
0x02: Ox1101 - Vendor ID
0x04: Ox - Status
0x06: Ox - Command
0x08: Ox00 - Base CLass
Author: hailfinger
Date: 2008-10-11 03:01:07 +0200 (Sat, 11 Oct 2008)
New Revision: 916
Modified:
coreboot-v3/arch/x86/Kconfig
coreboot-v3/arch/x86/i586/stage0.S
coreboot-v3/arch/x86/via/stage0.S
Log:
Whitespace fixes, readability improvements.
Signed-off-by: Carl-Daniel Hailfinger
On Fri, Oct 10, 2008 at 8:14 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
On 11.10.2008 01:03, ron minnich wrote:
Acked-by: Ronald G. Minnich [EMAIL PROTECTED]
Thanks, committed in r915.
Note that it still won't build if CONFIG_XIP_ROM_{SIZE,BASE} are set
but I still don't
On Fri, Oct 10, 2008 at 9:50 PM, Corey Osgood [EMAIL PROTECTED]wrote:
On Fri, Oct 10, 2008 at 8:14 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
On 11.10.2008 01:03, ron minnich wrote:
Acked-by: Ronald G. Minnich [EMAIL PROTECTED]
Thanks, committed in r915.
Note that it still
On 11.10.2008 03:51, Corey Osgood wrote:
On Fri, Oct 10, 2008 at 9:50 PM, Corey Osgood [EMAIL PROTECTED]wrote:
On Fri, Oct 10, 2008 at 8:14 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
On 11.10.2008 01:03, ron minnich wrote:
Acked-by: Ronald G. Minnich [EMAIL
Hi,
flashrom hasn't seen any major design changes in the last few months and
most chips still perform whole-chip erase instead of sector-based erase.
I'd like to introduce a function which takes a range and rounds the
start and the end of the range to the nearest block boundary.
void
On Fri, Oct 10, 2008 at 8:38 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
Hi,
flashrom hasn't seen any major design changes in the last few months and
most chips still perform whole-chip erase instead of sector-based erase.
I'd like to introduce a function which takes a range and
ron minnich wrote:
.. but I'd like to start getting via bits into v3 asap.
I would really like us to do a design review round before substantial
amounts of code supporting non-K8 systems are added to v3.
I realize everyone is eager to add as much as possible as quickly as
possible to v3, but I
Corey Osgood wrote:
And work it does:
Nice work Carl-Daniel!
//Peter
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Carl-Daniel Hailfinger wrote:
That XIP stuff needs a good explanation anyway. We may want to have
it cover the boot block only or the bootblock and initram. Either
way, reading the whole ROM to cache it may be less than useful and
a severe performance killer early on.
XIP could never perform
ron minnich wrote:
This is a good start but what you are missing is the interpretation
of the fields and shifting things so we know what they really are.
This is exactly what msrtool does. I must apologize for letting it
bitrot on my disk just because the two killer features weren't
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