On Monday 13 October 2008 03:01:35 Peter Stuge wrote:
Hi Roman,
Roman Yeryomin wrote:
on system with native bios (tinybios):
cat /proc/tty/driver/serial
serinfo:1.0 driver revision:
0: uart:16550A port:03F8 irq:4 tx:945 rx:15 RTS|CTS|DTR|DSR|CD
1: uart:16550A port:02F8
On Mon, Oct 13, 2008 at 5:17 AM, Peter Stuge [EMAIL PROTECTED] wrote:
ron minnich wrote:
I'm still puzzled as to what's going on with the dbm690t serial but
it doesn't work with any combination of things I normally do to get
rs232 to work. So it goes.
Set bit 6 in PCI register 44h of device
Darmawan Salihun wrote:
Anyway, how to set the baudrate?
Normal 16550 programming interface using io 3f8-3ff.
//Peter
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On Mon, Oct 13, 2008 at 03:05:54AM +0200, Peter Stuge wrote:
Acked-by: Peter Stuge [EMAIL PROTECTED]
Thanks, r3654.
Uwe.
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Uwe Hermann wrote:
See patch.
Uwe.
Index: src/mainboard/digitallogic/msm586seg/Config.lb
===
--- src/mainboard/digitallogic/msm586seg/Config.lb(Revision 3653)
+++ src/mainboard/digitallogic/msm586seg/Config.lb
On Mon, Oct 13, 2008 at 03:51:02PM +0200, Stefan Reinauer wrote:
Index: src/mainboard/digitallogic/msm586seg/Config.lb
===
--- src/mainboard/digitallogic/msm586seg/Config.lb (Revision 3653)
+++
Hi Kevin,
Thanks for the runthrough. I will redo with V2 coreboot and looks like I
will have to port in some low-level VGA startup according to your patches.
I will keep the list posted with my results and problems, my goal here is to
boot Windows 2000/XP/CE on the AMD Geode LX800.
Thanks
I used the it8718f dump code as a reference for how to do this.
There was one value that I wasn't sure about.
0x72 Watch Dog Timer Configuration Register
ldn idx def
0x7 0x720x20it8718f superiotool code
0x7 0x72001sh it8718f datasheet
0x7 0x72
On 11/10/08 07:13 +0200, Peter Stuge wrote:
ron minnich wrote:
I am not saying that we should stop working on v3 for two years. I'm
asking that we stick to the Hamburg plan, i.e. to step back and
evaluate (maybe tidy too) the code that is in v3 when simple
(geodelx) and complex (k8) are both
On Monday 13 October 2008 03:01:35 Peter Stuge wrote:
Hi Roman,
Roman Yeryomin wrote:
on system with native bios (tinybios):
cat /proc/tty/driver/serial
serinfo:1.0 driver revision:
0: uart:16550A port:03F8 irq:4 tx:945 rx:15 RTS|CTS|DTR|DSR|CD
1: uart:16550A port:02F8
On Thu, 09 Oct 2008, Uwe Hermann wrote:
Maybe, maybe not. Page 56 says 0x08, but on page 32 it says 0x00. The
datasheet contradicts itself here, and we don't know which one is
actually the correct default. We should probably document this in the
code, though.
The difference is that KBC
00:14.3 0601: 1002:438d
[EMAIL PROTECTED] rminnich]# /sbin/setpci -s 14.3 44.l
f7c3c043
It's set right? Seems set to me.
ron
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On 13.10.2008 05:30, Corey Osgood wrote:
On Sun, Oct 12, 2008 at 11:04 PM, Peter Stuge [EMAIL PROTECTED] wrote:
Carl-Daniel Hailfinger wrote:
I said in the past that we shouldn't send stuff to serial before
serial is set up, but my pleas have been ignored
Yes.
690G = RS690
690V is more or less like 690G but without digital video outputs, at least.
There is no 690 chipset AFAIK.
On Sun, Oct 12, 2008 at 6:57 PM, ron minnich [EMAIL PROTECTED] wrote:
What are those of you buying this going to do for serial? USB debug?
What's the current favorite usb
I'm working on vt8237 smbus in v3, and I had a quick question, mostly for
Rudolf Marek and Bari, but feel free to jump in with your 2 cents:
u8 smbus_read_byte(u16 dimm, u8 offset, u16 smbus_io_base)
{
u8 val;
printk(BIOS_SPEW, SMBus Read from DIMM %1x at address 0x%4x\n,
Author: rminnich
Date: 2008-10-13 20:38:50 +0200 (Mon, 13 Oct 2008)
New Revision: 919
Added:
coreboot-v3/util/mkdep
Modified:
coreboot-v3/arch/x86/Makefile
Log:
I need this to get my work done and there were no better proposals.
I did change the /bin/bash to /bin/sh per the comments.
ron minnich wrote:
00:14.3 0601: 1002:438d
[EMAIL PROTECTED] rminnich]# /sbin/setpci -s 14.3 44.l
f7c3c043
It's set right? Seems set to me.
0x43 = 0111 so yes it is.
What about setpci -s 14.0 64.l bit 20? It also defaults to 0. (Enable
LPC bridge.)
//Peter
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Steve Spano wrote:
I will keep the list posted with my results and problems, my goal here is to
boot Windows 2000/XP/CE on the AMD Geode LX800.
The Geode platform is not ideal for this exercise. The VSA used by
coreboot doesn't support the VGA BIOS (only the minimal set of pci
config space
I just commited the kscope patch. If you have not used kscope, try
make kscope and learn to use it. It is a HUGE time saver.
two hints:
on startup, it will ask to configure. Just hit the 'guess' button.
Hit CTRL-0 to start digging. Type in a name (e..g run_bios) and select
definition of usage.
On Mon, Oct 13, 2008 at 11:36 AM, Corey Osgood [EMAIL PROTECTED] wrote:
I'm working on vt8237 smbus in v3, and I had a quick question, mostly for
Rudolf Marek and Bari, but feel free to jump in with your 2 cents:
u8 smbus_read_byte(u16 dimm, u8 offset, u16 smbus_io_base)
{
u8 val;
On Mon, Oct 13, 2008 at 11:45 AM, Peter Stuge [EMAIL PROTECTED] wrote:
What about setpci -s 14.0 64.l bit 20? It also defaults to 0. (Enable
LPC bridge.)
Thanks to marc I found the problem. The connector as shown in the
manual is rotated 180. I have loopback and just need to do a bit of
cable
Corey Osgood wrote:
I'm working on vt8237 smbus in v3, and I had a quick question, mostly
for Rudolf Marek and Bari, but feel free to jump in with your 2 cents:
u8 smbus_read_byte(u16 dimm, u8 offset, u16 smbus_io_base)
{
u8 val;
printk(BIOS_SPEW, SMBus Read from DIMM
Myles, use this patch. Then send me output.
ron
Index: lib/console.c
===
--- lib/console.c (revision 920)
+++ lib/console.c (working copy)
@@ -136,8 +136,14 @@
return 0;
}
+
On Mon, Oct 13, 2008 at 10:53:27AM +0200, Darmawan Salihun wrote:
On Mon, Oct 13, 2008 at 5:17 AM, Peter Stuge [EMAIL PROTECTED] wrote:
ron minnich wrote:
I'm still puzzled as to what's going on with the dbm690t serial but
it doesn't work with any combination of things I normally do to get
I'd like to see this enabled by config option.
Signed-off-by: Myles Watson [EMAIL PROTECTED]
and/or
Acked-by: Myles Watson [EMAIL PROTECTED]
If you want to resend it since you wrote it.
Thanks,
Myles
On 10/13/08, ron minnich [EMAIL PROTECTED] wrote:
Myles, use this patch. Then send me
Hi,
0x50 is the actual address. 0xA0 is actual encoded address which starts from
bit1. bit0 indicates if it is R/W operation.
I would prefer to stick with 0x50.
Rudolf
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Hello
Well! That's a good thing to know...so this may be more of a research
project to boot Windows using coreboot on the Geode?
How would recommend attacking this if I want to boot Windows on the GeodeLX
using coreboot? Or should we just resort to those other bioses...
I would prefer not to
Corey Osgood wrote:
u8 smbus_read_byte(u16 dimm, u8 offset, u16 smbus_io_base)
..
dimm = (dimm 1) | 1;
..
With it, my spd addresses are 0x50, 0x51, etc, without it, they'd
be 0xa1, 0xa3, etc. Which would be preferred?
As others have said, the input to this function should be 0x50.
Do
Steve Spano wrote:
How would recommend attacking this if I want to boot Windows on the
GeodeLX using coreboot?
Maybe talk to AMD about licensing the VGA VSM.
//Peter
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See patch.
I've added the same license header as all the other sb600 files have
(copyright AMD, 2008, GPLv2). Ron has already added the same header
when porting the file to v3, but v2 doesn't have that header.
Uwe.
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ron minnich wrote:
Myles, use this patch. Then send me output.
Please send output to the list.
//Peter
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Myles Watson wrote:
I'd like to see this enabled by config option.
Add CONFIG_EXPERIMENTAL_HACKSTUFF_OR_SUCH to depends and I say
Acked-by: Peter Stuge [EMAIL PROTECTED]
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Hi
Licensing the VGA+VSM sounds reasonable. I see a few AMD folks on the list
here (Jordan/etc).
Who would I take this up with at AMD - can anyone from AMD chime in?
Thanks
Steve Spano, President
Finger Lakes Engineering
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL
On Mon, Oct 13, 2008 at 3:26 PM, Peter Stuge [EMAIL PROTECTED] wrote:
Corey Osgood wrote:
u8 smbus_read_byte(u16 dimm, u8 offset, u16 smbus_io_base)
..
dimm = (dimm 1) | 1;
..
With it, my spd addresses are 0x50, 0x51, etc, without it, they'd
be 0xa1, 0xa3, etc. Which would be
See patch.
Uwe.
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Fix various ITE IT8716F numbers in the dts. Some parts are incorrect,
some are just incomplete.
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Steve Spano wrote:
Who would I take this up with at AMD - can anyone from AMD chime in?
Through the embedded website/developer network is the place to contact
AMD about this.
http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_3364,00.html
If you have a problem or
On Mon, Oct 13, 2008 at 09:31:43PM +0200, Peter Stuge wrote:
Myles Watson wrote:
I'd like to see this enabled by config option.
Add CONFIG_EXPERIMENTAL_HACKSTUFF_OR_SUCH to depends and I say
Nothing really experimental here, I'd rather suggest EXPERT if you
want to hide it from normal
Author: myles
Date: 2008-10-13 22:15:56 +0200 (Mon, 13 Oct 2008)
New Revision: 921
Modified:
coreboot-v3/lib/Kconfig
coreboot-v3/lib/console.c
Log:
Add log levels to the output. In order to use this enable EXPERT and
CONSOLE_LOG_LEVEL.
EXPERT seemed like the best fit.
Signed-off-by:
Anyway, having such an option is a good idea, so:
Acked-by: Uwe Hermann [EMAIL PROTECTED]
Thanks Uwe and Peter.
Committed in 921.
Myles
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Uwe Hermann wrote:
Fix various ITE IT8716F numbers in the dts. Some parts are incorrect,
some are just incomplete.
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Acked-by: Peter Stuge [EMAIL PROTECTED]
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Attached please find a patch for flashrom which does the following:
Adds support for the EON EN29F040A flash chip.
Marks the AMIC A29040B flash chip as tested.
Adds support for the Bcom WinNET P680 motherboard to flashrom.
Unifies flash-enable for the winbond W83697 superio.
Signed-off-by: Alex
See patch.
Uwe.
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Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.
Build-tested with the AMD dbm690t board.
Signed-off-by: Uwe Hermann [EMAIL
See patch.
Uwe.
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Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.
Build-tested with the AMD dbm690t board.
Signed-off-by: Uwe Hermann [EMAIL
Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.
Build-tested with the AMD dbm690t board.
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Acked-by: Marc Jones [EMAIL PROTECTED]
--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:[EMAIL PROTECTED]
Uwe Hermann wrote:
Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.
Build-tested with the AMD dbm690t board.
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Acked-by: Marc Jones [EMAIL PROTECTED]
--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:[EMAIL
Hi to all,
I'm new in this mailing list. I have install, on my embedded system, a
minimal version of Debian and/or Ubuntu, but... I must have a very fast
boot, so I have see that my cpu and chipset are supported by LinuxBIOS.
I have a IB520 motherboard (http://www.ibase.com.tw/ib520.htm) with a
Hi Davide,
Davide Visconti wrote:
I'm new in this mailing list.
Welcome to the list!
I have install, on my embedded system, a minimal version of Debian
and/or Ubuntu, but... I must have a very fast boot, so I have see
that my cpu and chipset are supported by LinuxBIOS.
I have a IB520
Author: uwe
Date: 2008-10-13 23:41:03 +0200 (Mon, 13 Oct 2008)
New Revision: 922
Modified:
coreboot-v3/include/device/pci_ids.h
coreboot-v3/southbridge/amd/rs690/rs690.h
coreboot-v3/southbridge/amd/sb600/sb600.h
Log:
Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.
Author: uwe
Date: 2008-10-13 23:41:24 +0200 (Mon, 13 Oct 2008)
New Revision: 3655
Modified:
trunk/coreboot-v2/src/include/device/pci_ids.h
trunk/coreboot-v2/src/southbridge/amd/rs690/rs690.h
trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.h
Log:
Move AMD RS690 and SB600 PCI IDs to
On Mon, Oct 13, 2008 at 02:50:05PM -0600, Marc Jones wrote:
Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.
Build-tested with the AMD dbm690t board.
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Acked-by: Marc Jones [EMAIL PROTECTED]
Thanks, r3655.
Btw, should
On Mon, Oct 13, 2008 at 10:16:42PM +0200, Peter Stuge wrote:
Uwe Hermann wrote:
Fix various ITE IT8716F numbers in the dts. Some parts are incorrect,
some are just incomplete.
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Acked-by: Peter Stuge [EMAIL PROTECTED]
Thanks, r923.
Uwe.
--
Author: uwe
Date: 2008-10-13 23:47:56 +0200 (Mon, 13 Oct 2008)
New Revision: 923
Modified:
coreboot-v3/superio/ite/it8716f/dts
Log:
Fix various ITE IT8716F numbers in the dts. Some parts are incorrect,
some are just incomplete.
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Acked-by: Peter
Uwe Hermann wrote:
On Mon, Oct 13, 2008 at 02:50:05PM -0600, Marc Jones wrote:
Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.
Build-tested with the AMD dbm690t board.
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Acked-by: Marc Jones [EMAIL PROTECTED]
Thanks, r3655.
I have install, on my embedded system,
[...]
This platform (Geode LX + CS5536) is well supported by coreboot, and
several similar mainboards are already working well, but some code
and data files will still be needed to make this specific mainboard
work.
SST49LF004B is a FWH type flash chip,
At long last, here is a new version of the code for the EP80579
development mainboard (codename Truxton). It has been tested on real
hardware, booting a Linux kernel payload and running memtest86+ with
no errors. This is the final part of the EP80579 (Tolapai) patch set.
I tried to address all
patch for v3 would be appreciated.
ron
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Hi Ed,
thanks for the reworked patch.
One thing that caught my eye is the new romcc style which hasn't been
adopted in your code yet. Basically, we now build only one romcc copy
and use that for fallback and normal images.
On 14.10.2008 00:49, Ed Swierk wrote:
At long last, here is a new
Author: eswierk
Date: 2008-10-14 01:18:56 +0200 (Tue, 14 Oct 2008)
New Revision: 3656
Added:
trunk/coreboot-v2/src/mainboard/intel/truxton/
trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb
trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb
On Mon, Oct 13, 2008 at 4:01 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
With the romcc changes as indicated above and outlined below, this is
Acked-by: Carl-Daniel Hailfinger [EMAIL PROTECTED]
Thanks, r3656.
--Ed
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See patch.
Uwe.
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Make the ITE IT8712F support in v3 a bit more complete and fix the
incorrect and incomplete pnp_dev_info[] as we did in v2.
Signed-off-by: Uwe
Hi,
Sometimes, I got Invalid OPCODE 0x06 while running flashrom with -V (verbose)
on Supermicro X7DCL-3 / ICH9R / SST25VF016B.
After checking the codes, I found that OPCODE 0x06 (Write Enable) is not
available in OPMENU - Opcode Menu Configuration Register, but available in
PREOP - Prefix Opcode
2008/10/13 Uwe Hermann [EMAIL PROTECTED]
See patch.
Uwe.
Make the ITE IT8712F support in v3 a bit more complete and fix the
incorrect and incomplete pnp_dev_info[] as we did in v2.
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Acked-by: Corey Osgood [EMAIL PROTECTED]
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See patch.
Uwe.
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Fix incorrect and incomplete Fintek F71805F dts. Some LDNs got mixed
up in the dts, some LDNs were missing.
Signed-off-by: Uwe Hermann [EMAIL
2008/10/13 Uwe Hermann [EMAIL PROTECTED]
See patch.
Uwe.
Make the ITE IT8712F support in v3 a bit more complete and fix the
incorrect and incomplete pnp_dev_info[] as we did in v2.
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Acked-by: Corey Osgood [EMAIL PROTECTED]
Thanks!
--
coreboot
Hi,
I'm running flashrom to flash the BIOS on Supermicro X7DCL-3.
http://www.supermicro.com/products/motherboard/Xeon1333/5100/X7DCL-3.cfm
I found that flashrom -w (Write) does not work on ICH9R / SST25VF016B,
but -E (Erase) and -r (Read) options do work fine.
I once replaced the BIOS chip
See attached. Stage2 has to wait until CAR can be disabled on C7.
-Corey
Add stage1 support for vt8237[RS] to v3.
Signed-off-by: Corey Osgood [EMAIL PROTECTED]
Index: southbridge/via/vt8237/vt8237.h
===
---
Because the enable bit was masked off, checking for 0x didn't work.
This patch changes the place where the bit is masked. The other way to fix
it would be to check for 0xfffe.
V2 doesn't seem to have the problem.
Signed-off-by: Myles Watson [EMAIL PROTECTED]
Thanks,
Myles
Acked-by: Ronald G. Minnich [EMAIL PROTECTED]
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See attached. Thanks Carl-Daniel for the explanation on floats in CAR, hope
you don't mind that I've quoted you ;)
-Corey
Add ram init support for the Via CN700 to v3. Note that this isn't based on
current v2 support, but rather an older version I was working on that used too
many registers. It
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