Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
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On Wed, Nov 5, 2008 at 3:34 PM, Roman Yeryomin <[EMAIL PROTECTED]> wrote:
> cat /proc/interrupts
> CPU0
> 0: 541075XT-PIC-XTtimer
> 2: 0XT-PIC-XTcascade
> 4:403XT-PIC-XTserial
> 8: 0XT-PIC-XTrtc
> 10:
Is there any chance to get LEDs working on alix boards?
I suppose only GPIO lines/ports should be enabled in coreboot an
everything else is done in software.
Here is what documentation says about them:
Status LEDs are all turned on by the BIOS on power up. The BIOS will
turn off LEDs 2 and 3
befor
On Thu, Nov 6, 2008 at 1:28 AM, Roman Yeryomin <[EMAIL PROTECTED]> wrote:
> On Wed, Nov 5, 2008 at 11:35 PM, Roman Yeryomin <[EMAIL PROTECTED]> wrote:
>> On Wed, Nov 5, 2008 at 8:09 PM, Marc Jones <[EMAIL PROTECTED]> wrote:
>>> I see the problem. It is interesting that in some situations that it wo
On Wed, Nov 5, 2008 at 11:35 PM, Roman Yeryomin <[EMAIL PROTECTED]> wrote:
> On Wed, Nov 5, 2008 at 8:09 PM, Marc Jones <[EMAIL PROTECTED]> wrote:
>> I see the problem. It is interesting that in some situations that it works.
>>
>> Marc
>>
>>
>> --
>> Marc Jones
>> Senior Firmware Engineer
>> (970)
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer "hailfinger" checked in revision 3731 to
the coreboot source repository and caused the following
changes:
Change Log:
The ST M25P16 chip has been confirmed to work fine for probe, read,
erase and write b
Author: hailfinger
Date: 2008-11-05 23:54:36 +0100 (Wed, 05 Nov 2008)
New Revision: 3731
Modified:
trunk/util/flashrom/flashchips.c
Log:
The ST M25P16 chip has been confirmed to work fine for probe, read,
erase and write by St?\195?\169phan Guilloux.
Signed-off-by: Carl-Daniel Hailfinger <[EMA
Hi Stéphan,
On 28.10.2008 15:10, Stephan GUILLOUX wrote:
> Hello Carldani,
>
> You were right about the flash : this board is equipped with a ST
> flash and not with a Spansion...
>
> Now, I check the modifications we made yesterday night in flashrom.
> With them, flashrom is now working fine :
>
On 05.11.2008 22:50, [EMAIL PROTECTED] wrote:
> Author: myles
> Date: 2008-11-05 22:50:25 +0100 (Wed, 05 Nov 2008)
> New Revision: 981
>
> Modified:
>coreboot-v3/southbridge/amd/cs5536/cs5536.c
> Log:
> This patch removes a warning by making the struct pointer const.
>
Did you want to have
On Wed, Nov 5, 2008 at 4:14 PM, ron minnich <[EMAIL PROTECTED]> wrote:
> Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
>
Rev 982.
Thanks,
Myles
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Challenge: get via or k8 working by rev 1000. I used to think we'd make it :-)
ron
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On Wed, Nov 5, 2008 at 1:23 PM, ron minnich <[EMAIL PROTECTED]> wrote:
> looks good, not build or boot tested.
>
> Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Rev 983.
Thanks,
Myles
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Author: myles
Date: 2008-11-05 23:27:36 +0100 (Wed, 05 Nov 2008)
New Revision: 983
Modified:
coreboot-v3/device/Makefile
coreboot-v3/device/cardbus_device.c
coreboot-v3/device/device.c
coreboot-v3/device/pci_device.c
coreboot-v3/device/pcie_device.c
coreboot-v3/include/device/car
Author: myles
Date: 2008-11-05 23:18:53 +0100 (Wed, 05 Nov 2008)
New Revision: 982
Modified:
coreboot-v3/arch/x86/pci_ops_auto.c
coreboot-v3/include/arch/x86/pci_ops.h
coreboot-v3/northbridge/amd/geodelx/geodelx.c
Log:
This patch removes code related to PCI type 2 configuration cycles (go
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
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Author: myles
Date: 2008-11-05 22:50:25 +0100 (Wed, 05 Nov 2008)
New Revision: 981
Modified:
coreboot-v3/southbridge/amd/cs5536/cs5536.c
Log:
This patch removes a warning by making the struct pointer const.
Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
Acked-by: Myles Watson <[EMAIL PROTEC
On Wed, Nov 5, 2008 at 3:42 PM, ron minnich <[EMAIL PROTECTED]> wrote:
> >
> > /** Set the method to be used for PCI, type I or type II
> > */
> > void pci_set_method(struct device * dev)
> > {
> > printk(BIOS_INFO, "Finding PCI configuration type.\n");
> > dev->ops->ops_pci_bus = pci_che
>
> /** Set the method to be used for PCI, type I or type II
> */
> void pci_set_method(struct device * dev)
> {
> printk(BIOS_INFO, "Finding PCI configuration type.\n");
> dev->ops->ops_pci_bus = pci_check_direct();
> post_code(POST_STAGE2_PHASE2_PCI_SET_METHOD);
> }
>
yeah, just se
On Wed, Nov 5, 2008 at 8:09 PM, Marc Jones <[EMAIL PROTECTED]> wrote:
> I see the problem. It is interesting that in some situations that it works.
>
> Marc
>
>
> --
> Marc Jones
> Senior Firmware Engineer
> (970) 226-9684 Office
> mailto:[EMAIL PROTECTED]
> http://www.amd.com/embeddedprocessors
>
On Wed, Nov 5, 2008 at 1:24 PM, Myles Watson <[EMAIL PROTECTED]> wrote:
> > Are you testing these on qemu I assume?
>
> I can. I don't think I've made any functional changes, but it's probably
> good to check.
>
> Most of this patch isn't exercised by qemu, though. There are no bridges
> which a
Are you testing these on qemu I assume?
ron
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looks good, not build or boot tested.
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
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> Are you testing these on qemu I assume?
I can. I don't think I've made any functional changes, but it's probably
good to check.
Most of this patch isn't exercised by qemu, though. There are no bridges
which are not in the dts.
Thanks,
Myles
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h
On Wed, Nov 5, 2008 at 11:57 AM, ron minnich <[EMAIL PROTECTED]> wrote:
> great start. I will try to amend this as well.
Thanks.
> It belongs in the lyx doc but not yet.
A couple of iterations will do it good.
Thanks,
Myles
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great start. I will try to amend this as well.
It belongs in the lyx doc but not yet.
ron
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I couldn't see a great spot to put this on the wiki, so I decided to attach
it as a plain text file first. I didn't want to spend too much time on
formatting until we decide where it goes.
This text file explains how the pci_device code works.
Thanks,
Myles
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On Wed, Nov 5, 2008 at 12:27 PM, Myles Watson <[EMAIL PROTECTED]> wrote:
> This patch continues the device code cleanup.
I forgot the include/device/ changes in the first patch.
Thanks,
Myles
>
> The largest changes are to get_pci_bridge_ops, and related changes to make
> it
> compile and use
On Wed, Nov 5, 2008 at 12:35 PM, Myles Watson <[EMAIL PROTECTED]> wrote:
> I couldn't see a great spot to put this on the wiki, so I decided to attach
> it as a plain text file first. I didn't want to spend too much time on
> formatting until we decide where it goes.
>
> This text file explains h
This patch continues the device code cleanup.
The largest changes are to get_pci_bridge_ops, and related changes to make
it
compile and use correct declarations. I'd appreciate someone else checking
my const usage for sanity.
While I was doing that I moved the checks for CONFIG__PLUGIN_SUPPORT t
On Wed, Nov 5, 2008 at 8:32 AM, Jordan Crouse <[EMAIL PROTECTED]> wrote:
> On 05/11/08 08:24 -0800, ron minnich wrote:
>> We have a norwich which works (with v3, jordan?) with same chips as
>> alix. we have two kernels what work with norwich. Jordan, can you send
>> a boot log of these or at least
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
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I see the problem. It is interesting that in some situations that it works.
Marc
--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:[EMAIL PROTECTED]
http://www.amd.com/embeddedprocessors
LPC serial IRQs were being left enabled when there is no LPC serial device.
Signed-off-by
On Wednesday 05 November 2008 17:41:24 ron minnich wrote:
> On Wed, Nov 5, 2008 at 1:20 AM, Roman Yeryomin <[EMAIL PROTECTED]>
wrote:
> > Tried your image but no luck. Same behaviour. No serial console.
> > All it gave to serial console while booting is in attachment.
> > Does it have some ip addr
On 05/11/08 08:24 -0800, ron minnich wrote:
> We have a norwich which works (with v3, jordan?) with same chips as
> alix. we have two kernels what work with norwich. Jordan, can you send
> a boot log of these or at least tell us what irq they think is
> associated with com1?
v3 yes. And the IRQ i
On Wed, Nov 5, 2008 at 8:09 AM, Jordan Crouse <[EMAIL PROTECTED]> wrote:
> Not to rain on your parade, but the Norwich doesn't use a superio either. :)
The one thing I know for sure is that the way that alix1c connected
interrupts, and the way it set them up, was not a way that Marc
thought made
On 05/11/08 10:37 +0100, Uwe Hermann wrote:
> On Wed, Nov 05, 2008 at 02:39:11AM -0500, Corey Osgood wrote:
> > Build host is Ubuntu 8.04.1, gcc 4.2.4 (Ubuntu 4.2.4-1ubuntu3). I followed
> > the steps at coreboot.org/Filo, console output below. build.sh seems to work
> > fine.
>
> The wiki needed
On 05/11/08 10:04 +0100, Peter Stuge wrote:
> ron minnich wrote:
> > > It just occured to me, I use a busybox based image for my Geode... :)
> >
> > which geode is it? I am convinced there is something "different"
> > about the pcengines boards. I love those boards, but let's see.
>
> I think the
On 04/11/08 21:04 -0500, Gregg C Levine wrote:
> Hello!
> As always I am looking at new ideas.
> One that has occurred to me on numerous occasions is that of the idea of
> using Linux as a boot loader.
>
> I know it has been discussed on several occasions on this list, however I
> don't recall wha
On 04/11/08 20:17 -0800, ron minnich wrote:
> On Tue, Nov 4, 2008 at 5:24 PM, Jordan Crouse <[EMAIL PROTECTED]> wrote:
> > It just occured to me, I use a busybox based image for my Geode... :)
>
> which geode is it? I am convinced there is something "different" about
> the pcengines boards. I love
On Wed, Nov 5, 2008 at 1:20 AM, Roman Yeryomin <[EMAIL PROTECTED]> wrote:
> Tried your image but no luck. Same behaviour. No serial console.
> All it gave to serial console while booting is in attachment.
> Does it have some ip address and telnet/ssh server? So I could at
> least ping it and see i
thanks! this appears to be an i945-based system and might be a good candidate.
ron
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Hi,
About the additional (C) AMD thing:
Jordan Crouse wrote:
> If you are just copying the same API calls that all other motherboards
> use, then there is hardly anything to copyright in the first place.
...
> if there are some chunks of unmodified code that are unique to the
> db800 code (such a
I've written a rom file with 'flashrom -w romfile.rom' and verified
afterwards with 'flashrom -v romfile.rom'. The result was "VERIFIED"!
On the congatec board I just tried to erase and read again, have a look
at the attached output... I don't know if it's correct...
To the other systems i curren
On Wed, Nov 05, 2008 at 01:19:20PM +0100, Rogen, Mario wrote:
> Hi...
> I just tested flashrom on a bunch of mainboards:
>
> SST49LF008A congatec conga-x852 SBC
> (http://www.congatec.com/single_news+M5e8f9751886.html). Read, write and
> erase works out of the box. I also verified with the origina
Following uid313's instructions from
http://ubuntuforums.org/showthread.php?t=961975
/* This file was generated by getpir.c, do not modify!
* (but if you do, please run checkpir on it to verify)
*
* Contains the IRQ Routing Table dumped directly from your
* memory, which BIOS sets up.
*
* Doc
On 30.10.2008 15:59, Arne Georg Gleditsch wrote:
> Jordan Crouse <[EMAIL PROTECTED]> writes:
>
>> My bad - they are using a custom entry point (see i386/switch.S in filo).
>> So, they do need to call console_init() and lib_get_sysinfo(). Your
>> patch is correct.
>>
>
> Yes, I verified that
Hi...
I just tested flashrom on a bunch of mainboards:
SST49LF008A congatec conga-x852 SBC
(http://www.congatec.com/single_news+M5e8f9751886.html). Read, write and
erase works out of the box. I also verified with the original congatec
tool. It reports success!
SST49LF008A IEI PICOe-9452
(http://ww
On 05.11.2008 06:00, ron minnich wrote:
> Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
>
> and thanks to both of you. FIne work!
>
Corey? I'd appreciate if you could ack this patch as well since you did
the heavy lifting in the testing department.
Thanks,
Carl-Daniel
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On 05.11.2008 10:21, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>
>> @@ -64,6 +69,7 @@
>>
>> int total_size;
>> int page_size;
>> +struct eraseblock eraseblocks[4];
>>
>
> I don't know.. What about chips with more blocks than 4?
>
No problem. Let me quote another
Roman Yeryomin wrote:
> Maybe tinybios sources can help here?
Sure, can you find the assembly code that does serial init? Possibly
it's not all in once place but rather scattered out in a few places,
meaning that it's simpler to look at documentation than code.
Geode documentation is available b
On Wed, Nov 05, 2008 at 02:39:11AM -0500, Corey Osgood wrote:
> Build host is Ubuntu 8.04.1, gcc 4.2.4 (Ubuntu 4.2.4-1ubuntu3). I followed
> the steps at coreboot.org/Filo, console output below. build.sh seems to work
> fine.
The wiki needed a small fix (done).
After typing 'make' in libpayload,
On Wed, Nov 5, 2008 at 11:04 AM, Peter Stuge <[EMAIL PROTECTED]> wrote:
> ron minnich wrote:
>> > It just occured to me, I use a busybox based image for my Geode... :)
>>
>> which geode is it? I am convinced there is something "different"
>> about the pcengines boards. I love those boards, but let'
Carl-Daniel Hailfinger wrote:
> @@ -64,6 +69,7 @@
>
> int total_size;
> int page_size;
> + struct eraseblock eraseblocks[4];
I don't know.. What about chips with more blocks than 4?
//Peter
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On Wed, Nov 5, 2008 at 3:24 AM, Jordan Crouse <[EMAIL PROTECTED]> wrote:
> It just occured to me, I use a busybox based image for my Geode... :)
>
> I gzipped up the ext2 filesystem and put it here:
>
> http://www.infradead.org/~jcrouse/geode.rootfs.ext2.gz
>
> This uses busybox 1.9.2 and kernel 2.
ron minnich wrote:
> > It just occured to me, I use a busybox based image for my Geode... :)
>
> which geode is it? I am convinced there is something "different"
> about the pcengines boards. I love those boards, but let's see.
I think the main difference is that alix2 and alix3 have the serial
p
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