On 5/20/10 4:09 AM, ahmet alper parker wrote:
I know it is still not easy to support laptops, but is it possible to
support coreboot on my vaio vgn-fz21m now?
Best Regards...
Details:
Probably the motherboard is cited as: PCG-391M
Author: stepan
Date: Thu May 20 09:35:17 2010
New Revision: 5574
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5574
Log:
Add support for the Traverse Technologies Geos mainboard.
This board is similar to the AMD Norwich mainboard.
Signed-off-by: Nathan Williams nat...@traverse.com.au
On Thu, May 20, 2010 3:11 am, Joseph Smith wrote:
On 05/19/2010 05:56 PM, Myles Watson wrote:
On Wed, May 19, 2010 at 3:27 PM, xdrudisxdru...@tinet.cat wrote:
On Tue, May 18, 2010 at 07:45:18PM -0400, Kevin O'Connor wrote:
I think you're going to want SeaBIOS if you need to install Linux
On 20/05/2010 3:04 PM, Nathan Williams wrote:
1. On initial power-on, SeaBIOS doesn't get past Press F12 for boot menu.
...
3. Rev 5476 introduces a test for CS5536, which is failing
Peter Stuge has been helping me on IRC to investigate this issue. We think
the key is that for some reason
SeaBIOS is not slow - it is smaller than filo (both compressed and
uncompressed) and loads and initializes faster than filo. During one
of my tests, SeaBIOS was 1.5 seconds faster to the boot menu than
filo.
I didn't mean SeaBIOS is slow. I meant loading it from disk would be slower
than
On Thu, 20 May 2010 09:20:31 +0200, Joop Boonen joop_boo...@web.de
wrote:
On Thu, May 20, 2010 3:11 am, Joseph Smith wrote:
On 05/19/2010 05:56 PM, Myles Watson wrote:
On Wed, May 19, 2010 at 3:27 PM, xdrudisxdru...@tinet.cat wrote:
On Tue, May 18, 2010 at 07:45:18PM -0400, Kevin O'Connor
On Thu, May 20, 2010 at 11:07:51AM +0200, Xavi Drudis Ferran wrote:
SeaBIOS is not slow - it is smaller than filo (both compressed and
uncompressed) and loads and initializes faster than filo. During one
of my tests, SeaBIOS was 1.5 seconds faster to the boot menu than
filo.
I
On Thu, May 20, 2010 at 03:04:01PM +1000, Nathan Williams wrote:
On 20/05/2010 11:23 AM, Nathan Williams wrote:
This board is similar to the AMD Norwich mainboard.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Currently I'm having 4 issues with coreboot-v4 on this board:
attached patch moves the mptable entries for ISA bus interrupts (ie. the
legacy stuff) to generic code.
Instead of the hogde-podge in each board's mptable.c, it's relatively
clean code in arch/i386 now.
Thanks for doing this.
As this is quite a large patch, affecting lots of boards, I'd
Am 20.05.2010 17:00, schrieb Myles Watson:
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE |
MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb700, 0x0);
+
Hello all,
I am very interested in starting to play with coreboot and use it on
some of my systems. I have been interested in coreboot and following it
for a few years now.
I'll skip the chit chat and get straight to it. I got my hands on a few
Wyse S10 thinclients, and they work quite
Can the BIOS be swapped (is it socketed), do you have a spare (or one you fan
borrow from motherboard) .
Is the board using a supported or documented SuperIO (use superiotool, the
manual, the we or your eyes to see what chip you have).
Is the southbridg supported.
Is the northbridg supported.
On Wednesday, May 19, 2010 05:42:36 am Eric W. Biederman wrote:
The kernel initialization code as of boot protocol 2.10 is now reading the
kernel_alignment field. With the field left the kernel attempts to align
things to 4GB which is unlikely to work, so change the alignment to the
kernels
Use linked lists for resources instead of fixed arrays.
resources.diff - changes the definitions
resource_usage.diff - changes the functions where resources are used
sconfig.diff - changes the device tree
From the qemu boot log:
before:
malloc Enter, size 1092, free_mem_ptr 00118444
malloc
Troy Telford ttelford.gro...@gmail.com writes:
On Wednesday, May 19, 2010 05:42:36 am Eric W. Biederman wrote:
The kernel initialization code as of boot protocol 2.10 is now reading the
kernel_alignment field. With the field left the kernel attempts to align
things to 4GB which is unlikely
Heres a few lines to test erase and restore every thing.
sudo flashrom -r S10.rom
sudo rm ignoreme.txt
sudo flashrom -E -V flashrom-erase-SST49LF016C.txt
sudo flashrom -w S10.rom
But i think there might actually be more to testing erase, then just
erasing via the normal flashrom.
Take a full
On 05/20/2010 09:48 PM, Anders Jenbo wrote:
Heres a few lines to test erase and restore every thing.
sudo flashrom -r S10.rom
sudo rm ignoreme.txt
sudo flashrom -E -V flashrom-erase-SST49LF016C.txt
sudo flashrom -w S10.rom
But i think there might actually be more to testing erase, then just
On Thursday, May 20, 2010 12:56:48 pm Eric W. Biederman wrote:
Troy Telford ttelford.gro...@gmail.com writes:
On Wednesday, May 19, 2010 05:42:36 am Eric W. Biederman wrote:
The kernel initialization code as of boot protocol 2.10 is now reading
the kernel_alignment field. With the field
Try compiling the S50 code and flash the content to your bios. It seams
that there is no com port so you will need a USB debug device if you
want to debug the boot process.
Oh yeah, I forgot to ask; 'compile' how? Is there a good wiki page?
The links here:
On 05/20/2010 09:48 PM, Anders Jenbo wrote:
Heres a few lines to test erase and restore every thing.
sudo flashrom -r S10.rom
sudo rm ignoreme.txt
sudo flashrom -E -V flashrom-erase-SST49LF016C.txt
sudo flashrom -w S10.rom
But i think there might actually be more to testing erase, then just
Troy Telford ttelford.gro...@gmail.com writes:
On Thursday, May 20, 2010 12:56:48 pm Eric W. Biederman wrote:
Troy Telford ttelford.gro...@gmail.com writes:
On Wednesday, May 19, 2010 05:42:36 am Eric W. Biederman wrote:
The kernel initialization code as of boot protocol 2.10 is now reading
All,
I have a question for troubleshooting I need to sent kernel boot options
to the kernel.
Does anyone know if this is possible, if so what is the syntax?
Regards,
Joop.
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
All,
I have a question for troubleshooting I need to sent kernel boot options
to the kernel.
Does anyone know if this is possible, if so what is the syntax?
Regards,
Joop.
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Sorry. I guess you are using FILO boot loader. Maybe read this web page ?
http://www.coreboot.org/FILO
Regards,
Jiang
On Thu, May 20, 2010 at 6:10 PM, Jiang Wang jwang...@gmail.com wrote:
Which kernel, Linux? If so, are you using grub? There are many options
in the grub. Just google it.
Which kernel, Linux? If so, are you using grub? There are many options
in the grub. Just google it.
Regards,
Jiang
On Thu, May 20, 2010 at 5:51 PM, Joop Boonen joop_boo...@web.de wrote:
All,
I have a question for troubleshooting I need to sent kernel boot options
to the kernel.
Does
On Thu, May 20, 2010 at 1:16 PM, Myles Watson myle...@gmail.com wrote:
Use linked lists for resources instead of fixed arrays.
resource_usage.diff - changes the functions where resources are used
Here's an updated patch that doesn't hang :) I was in too much of a
hurry. We could add the
We could add the resources to the end of the list to maintain
the old order if anyone cares. Since we're using a list, the
resources are in reverse order.
Since it makes it easier to debug in case there's a problem, here it is.
Signed-off-by: Myles Watson myle...@gmail.com
Thanks,
Myles
I have a usb to serial device, but I think it will not be helpful
since I think I first need to make aware i965 about my device, right?
However, if it is ok, which steps do I need to follow? Is there a
link? (And say assume I will be pretty successful in low level
programming) :)
On Thu, May 20,
On Thursday, May 20, 2010 03:32:36 pm you wrote:
Ugh.
I can think of two things that might be useful.
1) Add a print statement into mkelfImage that prints the value of
kernel_alignment Most of the fields are already printed so this
just requires tweaking
Troy Telford ttelford.gro...@gmail.com writes:
On Thursday, May 20, 2010 03:32:36 pm you wrote:
Ugh.
I can think of two things that might be useful.
1) Add a print statement into mkelfImage that prints the value of
kernel_alignment Most of the fields are already printed so this
On 20/05/2010 10:56 PM, Kevin O'Connor wrote:
On Thu, May 20, 2010 at 03:04:01PM +1000, Nathan Williams wrote:
On 20/05/2010 11:23 AM, Nathan Williams wrote:
This board is similar to the AMD Norwich mainboard.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Currently I'm having 4
This patch improves the i82830 MBI SMI Handler. It is now able to load
Intel vbios VBT and Flexaim modules. Build and boot tested.
Signed-off-by: Joseph Smith j...@settoplinux.org
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
Index: src/northbridge/intel/i82830/i82830_smihandler.c
svn co svn://coreboot.org/coreboot/trunk coreboot
http://www.coreboot.org/Build_HOWTO
Mvh Anders
- Reply message -
Fra: Oliver Schinagl oli...@schinagl.nl
Dato: tor., maj 20, 2010 22:30
Emne: [coreboot] Indtast Bcc Wyse S10 and coreboot
Til: coreboot@coreboot.org
On 05/20/2010 09:48
Also check out the required tool chain here coreboot.org/Development_Guidelines
Mvh Anders
- Reply message -
Fra: Myles Watson myle...@gmail.com
Dato: tor., maj 20, 2010 22:45
Emne: [coreboot] Indtast Bcc Wyse S10 and coreboot
Til: 'Oliver Schinagl' oli...@schinagl.nl,
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