Tobias Diedrich wrote:
> This patch replaces the qword with a dword, which contains (TOM2 >> 20),
Could the name be changed to reflect this?
//Peter
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Ward Vandewege wrote:
> I'm not sure adding a post code to 'die' is a good idea. The
> problem with doing that is that it would clobber any previous post
> codes, which might be a better indicator for what's going wrong.
I think it is important to have a special POST code for use in die()
to posit
superiotool_fintek_f81865_id.patch
Description: superiotool_fintek_f81865_id.patch
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Peter Stuge wrote:
> Tobias Diedrich wrote:
> > This patch replaces the qword with a dword, which contains (TOM2 >> 20),
>
> Could the name be changed to reflect this?
Any suggestions?
Being limited to 4 characters there is not much you can do to convey this...
TM2S? (Top of memory 2 shifted)
-
Scott Duplichan wrote:
> With the unpatched code, the PCI resource allocation code finds bar
> 3 writable and assigns it a base address. In my case it assigned
> C000. This C00 range is unusable because it is not the
> range set aside for mmconf. I have mmconf at F800.
Do we need a par
"Scott Duplichan" writes:
> -- Disable the family 10h processor mmconf while the RS780 mmconf is in use.
I'm not sure I understand how this is supposed to work. Shouldn't we
just make sure the two mmconf regions don't overlap? (Or is the overlap
intended?) To be frank, I'm not sure what the RS
Hi, The SPI should be on 0x8, not 0x7, as that is the VID. I double checked the
datasheet and came across this while working on the coreboot port for my board.
This is a follow-up for the initial F71889 support for superiotool.
fix-SPI-VID.patch
Description: Binary data
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coreboot mai
Sorry, I forgot to sign-off.
Signed-off-by: Alec Ari
--- On Thu, 11/4/10, Neo The User wrote:
> From: Neo The User
> Subject: [superiotool] Fix VID / SPI registers for F71889
> To: coreboot@coreboot.org
> Date: Thursday, November 4, 2010, 3:17 PM
> Hi, The SPI should be on 0x8, not
> 0x7, as
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Arne Georg Gleditsch
Sent: Thursday, November 04, 2010 04:38 AM
To: Scott Duplichan
Cc: 'Peter Stuge'; 'Carl-Daniel Hailfinger'; coreboot@coreboot.org
Subject: Re: [coreboot] [PATCH]
>> > Loading stage image.
>> > Check CBFS header at
>> Normally a hang here means that the whole ROM isn't mapped, so trying
>> to read from the top of the ROM hangs, even though the bootblock
>> accesses work fine.
>
> Yup, sounds like that's the problem. Here's a quick patch to fix it
> by addin
"Scott Duplichan" writes:
> When I step through this pci_read_config32 call (on simnow) I see it using
> the cf8/cfc method for config access, not the mmio method.
Ok, that sounds like CONFIG_MMCONF_SUPPORT_DEFAULT is not set, is that
right? Presuming that's so, I'm worried that this code will b
Hello!
Yesterday I tried coreboot again, and it worked fine so far.
But I faced a nasty problem, like the last time I tried it with the MAC
address on MCP55. This is nothing serious as you can change it by editing the
romcache.inc from the southbridge, but it's nasty.
I was thinking about fixi
Hello readers,
after some while I tried to use coreboot again on my well supported Gigabyte
M57SLI and I was really happy, that the first built image booted the machine.
Last time I tried this, I stumbled across an error with the RAM, and had no
time to investigate this further.
With the recen
On Thu, Nov 04, 2010 at 10:09:14AM -0600, Myles Watson wrote:
> I just simplified the patch. TINYBOOTBLOCK can come later.
>
> It compiles.
>
> Signed-off-by: Myles Watson
True, go ahead.
Acked-by: Uwe Hermann
Uwe.
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-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Harald Gutmann
Sent: Thursday, November 04, 2010 12:46 PM
To: coreboot@coreboot.org
Subject: [coreboot] Gigabyte M57SLI - some troubles with recent corebootversion
]Hello readers,
]
Author: myles
Date: Thu Nov 4 19:33:42 2010
New Revision: 6018
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6018
Log:
Add a rom_enable() function to via/vt8231 and call it from via/epia/romstage.c
Signed-off-by: Uwe Hermann
Signed-off-by: Myles Watson
Acked-by: Uwe Hermann
Added
On Thu, Nov 4, 2010 at 10:03 AM, Scott Duplichan wrote:
> -Original Message-
> ]> + // disable processor pcie mmio, if enabled
> ]> + if (is_family10h()) {
> ]> + msr_t temp;
> ]> + pcie_mmio_save = temp = rdmsr (0xc0010058);
> ]> + temp.lo &= ~1;
>
-Original Message-
From: Marc Jones [mailto:marcj...@gmail.com]
Sent: Thursday, November 04, 2010 12:35 PM
To: Scott Duplichan
Cc: Arne Georg Gleditsch; Peter Stuge; Carl-Daniel Hailfinger;
coreboot@coreboot.org
Subject: Re: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7
"Scott Duplichan" writes:
> Yes, CONFIG_MMCONF_SUPPORT=y for my test.
This only indicates whether support for the mmconf facility should be
compiled in. If CONFIG_MMCONF_SUPPORT_DEFAULT isn't also set, you'll
only be using the mmconf facility if you explicitly do
pci_mmconf_read_config32 or simi
On Tue, Nov 2, 2010 at 12:45 PM, Uwe Hermann wrote:
> Hi,
>
> On Mon, Nov 01, 2010 at 01:02:53PM -0700, David Hendricks wrote:
> > The patch (attached) was tested by a user on IRC who had the F71889FG. I
> > wrote it using documentation from Fintek's website available here:
> > http://www.fintek.
Hello Scott,
thank you for your fast reply!
Your provided solution works fine to fix the MTRR problem on my board!
Just FYI, my CPU is the following:
model name : AMD Athlon(tm) 64 X2 Dual Core Processor 6000+
I'm just thinking if your suggested place for changing the KConfig is the right
-Original Message-
From: Arne Georg Gleditsch [mailto:a...@gledits.ch] On Behalf Of Arne Georg
Gleditsch
Sent: Thursday, November 04, 2010 02:25 PM
To: Scott Duplichan
Cc: 'Marc Jones'; 'Peter Stuge'; 'Carl-Daniel Hailfinger'; coreboot@coreboot.org
Subject: Re: [PATCH] Fix AMD HD 3200 uma
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Harald Gutmann
Sent: Thursday, November 04, 2010 02:47 PM
To: coreboot@coreboot.org
Subject: Re: [coreboot] Gigabyte M57SLI - some troubles with
recentcorebootversion
]Hello Scott,
"Scott Duplichan" writes:
> Hello Arne,
>
> That is a good point. Here are the relevant items from my config.h:
> #define CONFIG_MMCONF_BUS_NUMBER 16
> #define CONFIG_MMCONF_SUPPORT 1
> #define CONFIG_MMCONF_BASE_ADDRESS 0xf800
> #define CONFIG_MMCONF_SUPPORT_DEFAULT 1
My apologies, I went ba
Remove banner wrapper function and unify print(k).
Signed-off-by: Nils Jacobs
The banner part was requested by Uwe.
This is Abuild and boot tested.
V2:Also change Assymetirc into Asymmetric thanks to Idwer for spotting.
Thanks, Nils.
Index: src/northbridge/amd/gx2/raminit.c
===
someone I know from a Big telecom company just pushed an interesting
idea on me.
If coreboot+seabios would provide a bios service for serial console
over enet, it would improve their life a lot. They could stop building
cyclades boxes into their racks, and stop worrying about which
mainboards had
Author: uwe
Date: Fri Nov 5 01:07:13 2010
New Revision: 6020
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6020
Log:
Fintek and Intel i3100 Super I/O cleanups.
- Drop commented out "config chip.h" and a duplicate link to a datasheet.
- F71805F -> F71805F/FG, to mention all variant
Author: uwe
Date: Fri Nov 5 01:13:14 2010
New Revision: 6021
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6021
Log:
Remove banner wrapper function and unify print(k) usage.
- Drop banner(), use printk()s instead.
- Uncomment a few printk()s, if a users doesn't want to see them he
On Thu, Nov 04, 2010 at 11:35:56PM +0100, Nils wrote:
> Remove banner wrapper function and unify print(k).
>
> Signed-off-by: Nils Jacobs
Thanks, 6021.
Uwe.
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coreboot mailin
Author: uwe
Date: Fri Nov 5 01:19:21 2010
New Revision: 6022
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6022
Log:
GX2: Define the unused DIMM1 to 0xFF to make it obvious it is a bogus value.
This is Abuild and boot tested.
Signed-off-by: Nils Jacobs
Acked-by: Uwe Hermann
Modif
On Tue, Nov 02, 2010 at 10:33:22PM +0100, Nils wrote:
> This patch defines the unused DIMM1 to 0xFF to make it obvious it is a bogus
> value.
>
> Signed-off-by: Nils Jacobs
Thanks, r6022. I added some comments too to make it clearer why it's
0xFF, I hope the comments are correct and make sense.
Author: uwe
Date: Fri Nov 5 01:23:11 2010
New Revision: 6023
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6023
Log:
Add Kconfig CPU speed selection to Geode GX2 boards.
This is Abuild and boot tested.
Signed-off-by: Nils Jacobs
Acked-by: Uwe Hermann
Modified:
trunk/src/mainbo
On Tue, Nov 02, 2010 at 10:33:44PM +0100, Nils wrote:
> This patch adds Kconfig cpu speed selection to Geode GX2 boards as requested
> by
> Uwe.
>
> Signed-off-by: Nils Jacobs
Thanks, r6023.
Uwe.
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On Mon, Nov 01, 2010 at 08:28:27PM +0100, Nils wrote:
> >Shouldn't there be a "while (1)" around the hlt instruction?
> ?? i don't know should it?
> The code seems to work, but if it is preferred/needed i will add it.
As far as I know the "hlt" instruction on x86 does not really terminally
"halt"
Author: uwe
Date: Fri Nov 5 01:34:12 2010
New Revision: 6024
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6024
Log:
Add detection support for the Fintek F81865/F81865-I.
Signed-off-by: Zheng Bao
Acked-by: Uwe Hermann
Modified:
trunk/util/superiotool/fintek.c
Modified: trunk/u
Thanks, r6024.
Uwe.
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ron minnich wrote:
> I know that coreboot can now do console over enet; would be neat if
> seabios could provide a path for payloads to use it.
There's a problem; not very many ethernet adapters besides the old
RealTek 8029 (NE2000 PCI clone) have on-chip SRAM reachable via PIO.
:\
//Peter
--
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Rudolf Marek
Sent: Wednesday, November 03, 2010 06:07 PM
To: coreboot@coreboot.org
Subject: Re: [coreboot] [patch] fix unexpacted MTRR setup for UMA memory
]Hi,
]
]I just want to tel
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Rudolf Marek
Sent: Wednesday, November 03, 2010 04:34 PM
To: coreboot@coreboot.org
Subject: Re: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in Win7
(revised)
]Hi Scott,
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