Author: svens
Date: Thu Mar 3 09:29:03 2011
New Revision: 6427
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6427
Log:
add PC87384 SuperIO
Signed-off-by: Sven Schnelle sv...@stackframe.org
Acked-by: Peter Stuge pe...@stuge.se
Added:
trunk/src/superio/nsc/pc87384/
Peter Stuge pe...@stuge.se writes:
Sven Schnelle wrote:
Signed-off-by: Sven Schnelle sv...@stackframe.org
Acked-by: Peter Stuge pe...@stuge.se
r6427.
Thanks,
Sven.
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Hi Keith,
Keith Hui buu...@gmail.com writes:
Option C with GPLv2+ licensing.
A few quick things:
SUPERIO_FINTEK_F81865F_HAS_EARLY_SERIAL seems long-winded for a name.
I prefer to define CONFIG_SUPERIO_HAS_EARLY_SERIAL (or even just
CONFIG_HAS_EARLY_SERIAL) within the superio Kconfig and
On 03/03/2011 09:35 AM, Georgi, Patrick wrote:
The chipset components in Kconfig could be derived from the
devicetree.cb (statically, on config time or before) - this would
simplify board config a bit by reducing duplication.
Early serial could be managed with a new keyword there
(chip
On Sat, Feb 19 2011, Alex G. wrote:
On 02/19/2011 06:58 PM, sh4...@gmail.com wrote:
I wanted general purpose regular desktop for programming, internet,
GNU/Linux with common servers dovecote, tomcat, apache etc
Probably a socket AM2+ board will be best for you if you want to run
Hi,
I'm currently working on improving the support in Coreboot for the Intel
Truxton, which is an EVB for Intel EP80579 (codename Tolapai). I'm trying to
make it more agnostic with regards to which RAM modules can be used. Right now,
it supports only some ECC modules.
I was able to get the
I like this solution too. Just that it requires hacking sconfig, and
I'm not even close to qualified to actually do it. :)
And this requires sconfig to produce some other output for romstage as
well. The hardware tree it produces is currently only used during
ramstage.
While we're on sconfig,
On 03/03/2011 04:49 PM, Keith Hui wrote:
I like this solution too. Just that it requires hacking sconfig, and
I'm not even close to qualified to actually do it. :)
And this requires sconfig to produce some other output for romstage as
well. The hardware tree it produces is currently only
Author: jakllsch
Date: Thu Mar 3 16:36:08 2011
New Revision: 6428
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6428
Log:
Configure PCIe lanes on ms7135 as original BIOS does.
Signed-off-by: jakll...@kollasch.net
Acked-by: jakll...@kollasch.net
Modified:
When trying to make modifications to support other boards,
I got into similarly seemingly undeterministic failures
This was to be read When trying to make modification to
support other *RAM modules*.
After further testing, I can confirm that the random failure
problem has *not* been fixed by my
Improve ck804 IOAPIC and HPET resource handling.
Signed-off-by: Jonathan Kollasch jakll...@kollasch.net
-
Index: src/southbridge/nvidia/ck804/lpc.c
===
--- src/southbridge/nvidia/ck804/lpc.c (revision 6427)
+++
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer jakllsch checked in revision 6428 to
the coreboot repository. This caused the following
changes:
Change Log:
Configure PCIe lanes on ms7135 as original BIOS does.
Signed-off-by: jakll...@kollasch.net
Jonathan A. Kollasch wrote:
Improve ck804 IOAPIC and HPET resource handling.
Signed-off-by: Jonathan Kollasch jakll...@kollasch.net
Acked-by: Peter Stuge pe...@stuge.se
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Author: jakllsch
Date: Thu Mar 3 21:52:50 2011
New Revision: 6429
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6429
Log:
Improve ck804 IOAPIC and HPET resource handling.
Signed-off-by: Jonathan Kollasch jakll...@kollasch.net
Acked-by: Peter Stuge pe...@stuge.se
Modified:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer jakllsch checked in revision 6429 to
the coreboot repository. This caused the following
changes:
Change Log:
Improve ck804 IOAPIC and HPET resource handling.
Signed-off-by: Jonathan Kollasch
Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code.
With this change the last P-state entry of the last CPU in the table
is successfully conveyed into the SSDT.
Signed-off-by: Jonathan Kollasch jakll...@kollasch.net
Index: src/cpu/amd/model_fxx/powernow_acpi.c
Jonathan A. Kollasch wrote:
Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code.
With this change the last P-state entry of the last CPU in the table
is successfully conveyed into the SSDT.
Signed-off-by: Jonathan Kollasch jakll...@kollasch.net
Acked-by: Peter Stuge
Author: jakllsch
Date: Fri Mar 4 00:09:43 2011
New Revision: 6430
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6430
Log:
Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code.
With this change the last P-state entry of the last CPU in the table
is successfully conveyed
Hi Michael,
seems to me that the GPIO is accessed as you predicted. I attach the
output of superiorool -deV.
Regards,
Michal
2011/3/2 Michael Karcher flash...@mkarcher.dialup.fu-berlin.de:
Hello jankeso,
in the process of writing a board enable procedure for your mainboard I
stumbled upon
* Vitaly Chertovskih chert...@gmail.com [110303 20:08]:
Hi!
I'm experiencing some troubles with VGA on notebook Roda RF8. That
notebook's
motherboard and other specification is exact to Roda RK886EX, only the screen
is larger (17'' WXGA 1440x900).
On that week I installed coreboot on
* Michael Karcher flash...@mkarcher.dialup.fu-berlin.de [110302 23:30]:
Hello jankeso,
in the process of writing a board enable procedure for your mainboard I
stumbled upon the fact that the chip used to control the write enable
line is most likely your Super I/O chip, which is a NSC
sh4...@gmail.com wrote:
So I wanted to know if I have to purchase `GIGABYTE_GA-MA785GMT-US2H'
as `GIGABYTE_GA-MA785GMT-UD2H' is not available, Could it be easy
to get coreboot in it as `GIGABYTE_GA-MA785GMT-UD2H' have been already
supported, might be it is a newer version of
Hi
I think it's a issue about lvds setting in VGA rom.
You can get the vbios from Intel's web site, and you need to modify it to fit
your screen.
8086/27ae 8086/27a2 just different ID,because your have let the VGA rom run, so
it doesn't matter :-)
thanks!
2011-03-04
zxy__1127
*
On 3/3/11 9:46 PM, zxy__1127 wrote:
Hi
I think it's a issue about lvds setting in VGA rom.
You can get the vbios from Intel's web site, and you need to modify it
to fit your screen.
8086/27ae 8086/27a2 just different ID,because your have let the VGA
rom run, so it doesn't matter :-)
It
Then need to let it run correctlly first.
3 steps:
1) CONFIG_VGA_BIOS_ID=8086,27ae
2) modify VGA rom in hex, offset 46h =0xae
3）ignor the checksun error in payload(seabios).
may be there are better ways,let me know :-)
Thanks!
2011-03-04
zxy__1127
On 3/3/11 9:46 PM, zxy__1127
Am Freitag, den 18.02.2011, 12:28 +0100 schrieb Georgi, Patrick:
Am Freitag, den 18.02.2011, 12:15 +0100 schrieb Peter Stuge:
HAVE_CMOS_DEFAULT. Without this, cmos.default isn't put into CBFS
(by default), and without that file, no write happens.
But it's a mainboard knob, not a user
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