[coreboot] Re: System gcc requirements

2020-11-16 Thread Peter Stuge
Julius Werner wrote: > > > needed in cbfstool (e.g. for the --hash-algorithm parameter to add a > > > hash attribute to a file), and there is no Kconfig cbfstool so you > > > can't just configure it out if you don't need it. > > > > It is clear that I don't need that functionality when I build a >

[coreboot] Re: System gcc requirements

2020-11-16 Thread Julius Werner
> > vboot is used for more than just boot verification these days, we use > > it as a sort of generic crypto toolbox for all of coreboot's crypto > > needs (because it wouldn't make sense to implement, say, SHA-256 > > algorithms twice). For host utilities in particular, some of these are > > neede

[coreboot] Re: Memory initialisation error

2020-11-16 Thread Naresh G. Solanki
Don't know how to recover SPD from UEFI but Try to read memory part number written on chip and provide that. Look for SPD file with that name if it's already present in coreboot. Regards, Naresh solanki On Mon, 16 Nov, 2020, 11:46 pm Matt DeVillier, wrote: > > > src/soc/intel/cannonlake/romstag

[coreboot] Re: Feature request: add payload "Tianocore with SeaBIOS CSM"

2020-11-16 Thread Rafael Send
I'm also interested in this option & raised it sometime last year. As a user, I don't have the skills necessary to do it, and was informed of the same conclusion. However, I DID succeed in building a coreboot which contains both Tianocore & SeaBIOS separately, then using Grub to choose which paylo

[coreboot] Re: Memory initialisation error

2020-11-16 Thread Matt DeVillier
> src/soc/intel/cannonlake/romstage/fsp_params.c/mainboard_memory_init_params called means your board isn't overriding mainboard_memory_init_params() -- so all the defaults are being used, which I'm not sure will result in a bootable device. You might want to look at the CML/CFL reference boards,

[coreboot] Memory initialisation error

2020-11-16 Thread Andy Pont
Hello, I have some life out of my Comet Lake based board but the debug output ends with FMAP: area RW_MRC_CACHE found @ 42 (65536 bytes) MRC: no data in 'RW_MRC_CACHE' PRMRR disabled by config. WEAK: src/soc/intel/cannonlake/romstage/fsp_params.c/mainboard_memory_init_params called FspM

[coreboot] Re: Feature request: add payload "Tianocore with SeaBIOS CSM"

2020-11-16 Thread Patrick Georgi via coreboot
Am So., 15. Nov. 2020 um 19:43 Uhr schrieb Matt DeVillier < matt.devill...@gmail.com>: > if it were as simple as building Tianocore with SeaBIOS as the CSM, that > would be the default option offered, but unfortunately it's not. The > neither Tianocore package (the default CorebootPayloadPkg, nor